diff options
Diffstat (limited to 'drivers/gpu')
38 files changed, 280 insertions, 275 deletions
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index df8f92322865..f3a23a329f4e 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile | |||
@@ -12,7 +12,7 @@ drm-y := drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \ | |||
12 | drm_platform.o drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ | 12 | drm_platform.o drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \ |
13 | drm_crtc.o drm_modes.o drm_edid.o \ | 13 | drm_crtc.o drm_modes.o drm_edid.o \ |
14 | drm_info.o drm_debugfs.o drm_encoder_slave.o \ | 14 | drm_info.o drm_debugfs.o drm_encoder_slave.o \ |
15 | drm_trace_points.o | 15 | drm_trace_points.o drm_global.o |
16 | 16 | ||
17 | drm-$(CONFIG_COMPAT) += drm_ioc32.o | 17 | drm-$(CONFIG_COMPAT) += drm_ioc32.o |
18 | 18 | ||
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index b5a51686f492..d5b349d279f5 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c | |||
@@ -288,6 +288,7 @@ static int __init drm_core_init(void) | |||
288 | { | 288 | { |
289 | int ret = -ENOMEM; | 289 | int ret = -ENOMEM; |
290 | 290 | ||
291 | drm_global_init(); | ||
291 | idr_init(&drm_minors_idr); | 292 | idr_init(&drm_minors_idr); |
292 | 293 | ||
293 | if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops)) | 294 | if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops)) |
diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/drm_global.c index b17007178a36..c87dc96444de 100644 --- a/drivers/gpu/drm/ttm/ttm_global.c +++ b/drivers/gpu/drm/drm_global.c | |||
@@ -28,45 +28,45 @@ | |||
28 | * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com> | 28 | * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com> |
29 | */ | 29 | */ |
30 | 30 | ||
31 | #include "ttm/ttm_module.h" | ||
32 | #include <linux/mutex.h> | 31 | #include <linux/mutex.h> |
33 | #include <linux/slab.h> | 32 | #include <linux/slab.h> |
34 | #include <linux/module.h> | 33 | #include <linux/module.h> |
34 | #include "drm_global.h" | ||
35 | 35 | ||
36 | struct ttm_global_item { | 36 | struct drm_global_item { |
37 | struct mutex mutex; | 37 | struct mutex mutex; |
38 | void *object; | 38 | void *object; |
39 | int refcount; | 39 | int refcount; |
40 | }; | 40 | }; |
41 | 41 | ||
42 | static struct ttm_global_item glob[TTM_GLOBAL_NUM]; | 42 | static struct drm_global_item glob[DRM_GLOBAL_NUM]; |
43 | 43 | ||
44 | void ttm_global_init(void) | 44 | void drm_global_init(void) |
45 | { | 45 | { |
46 | int i; | 46 | int i; |
47 | 47 | ||
48 | for (i = 0; i < TTM_GLOBAL_NUM; ++i) { | 48 | for (i = 0; i < DRM_GLOBAL_NUM; ++i) { |
49 | struct ttm_global_item *item = &glob[i]; | 49 | struct drm_global_item *item = &glob[i]; |
50 | mutex_init(&item->mutex); | 50 | mutex_init(&item->mutex); |
51 | item->object = NULL; | 51 | item->object = NULL; |
52 | item->refcount = 0; | 52 | item->refcount = 0; |
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
56 | void ttm_global_release(void) | 56 | void drm_global_release(void) |
57 | { | 57 | { |
58 | int i; | 58 | int i; |
59 | for (i = 0; i < TTM_GLOBAL_NUM; ++i) { | 59 | for (i = 0; i < DRM_GLOBAL_NUM; ++i) { |
60 | struct ttm_global_item *item = &glob[i]; | 60 | struct drm_global_item *item = &glob[i]; |
61 | BUG_ON(item->object != NULL); | 61 | BUG_ON(item->object != NULL); |
62 | BUG_ON(item->refcount != 0); | 62 | BUG_ON(item->refcount != 0); |
63 | } | 63 | } |
64 | } | 64 | } |
65 | 65 | ||
66 | int ttm_global_item_ref(struct ttm_global_reference *ref) | 66 | int drm_global_item_ref(struct drm_global_reference *ref) |
67 | { | 67 | { |
68 | int ret; | 68 | int ret; |
69 | struct ttm_global_item *item = &glob[ref->global_type]; | 69 | struct drm_global_item *item = &glob[ref->global_type]; |
70 | void *object; | 70 | void *object; |
71 | 71 | ||
72 | mutex_lock(&item->mutex); | 72 | mutex_lock(&item->mutex); |
@@ -93,11 +93,11 @@ out_err: | |||
93 | item->object = NULL; | 93 | item->object = NULL; |
94 | return ret; | 94 | return ret; |
95 | } | 95 | } |
96 | EXPORT_SYMBOL(ttm_global_item_ref); | 96 | EXPORT_SYMBOL(drm_global_item_ref); |
97 | 97 | ||
98 | void ttm_global_item_unref(struct ttm_global_reference *ref) | 98 | void drm_global_item_unref(struct drm_global_reference *ref) |
99 | { | 99 | { |
100 | struct ttm_global_item *item = &glob[ref->global_type]; | 100 | struct drm_global_item *item = &glob[ref->global_type]; |
101 | 101 | ||
102 | mutex_lock(&item->mutex); | 102 | mutex_lock(&item->mutex); |
103 | BUG_ON(item->refcount == 0); | 103 | BUG_ON(item->refcount == 0); |
@@ -108,5 +108,5 @@ void ttm_global_item_unref(struct ttm_global_reference *ref) | |||
108 | } | 108 | } |
109 | mutex_unlock(&item->mutex); | 109 | mutex_unlock(&item->mutex); |
110 | } | 110 | } |
111 | EXPORT_SYMBOL(ttm_global_item_unref); | 111 | EXPORT_SYMBOL(drm_global_item_unref); |
112 | 112 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index d0a35d9ba522..e15db15dca77 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -533,7 +533,7 @@ struct drm_nouveau_private { | |||
533 | struct list_head vbl_waiting; | 533 | struct list_head vbl_waiting; |
534 | 534 | ||
535 | struct { | 535 | struct { |
536 | struct ttm_global_reference mem_global_ref; | 536 | struct drm_global_reference mem_global_ref; |
537 | struct ttm_bo_global_ref bo_global_ref; | 537 | struct ttm_bo_global_ref bo_global_ref; |
538 | struct ttm_bo_device bdev; | 538 | struct ttm_bo_device bdev; |
539 | spinlock_t bo_list_lock; | 539 | spinlock_t bo_list_lock; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index c385d50f041b..bd35f930568c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c | |||
@@ -42,13 +42,13 @@ nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma) | |||
42 | } | 42 | } |
43 | 43 | ||
44 | static int | 44 | static int |
45 | nouveau_ttm_mem_global_init(struct ttm_global_reference *ref) | 45 | nouveau_ttm_mem_global_init(struct drm_global_reference *ref) |
46 | { | 46 | { |
47 | return ttm_mem_global_init(ref->object); | 47 | return ttm_mem_global_init(ref->object); |
48 | } | 48 | } |
49 | 49 | ||
50 | static void | 50 | static void |
51 | nouveau_ttm_mem_global_release(struct ttm_global_reference *ref) | 51 | nouveau_ttm_mem_global_release(struct drm_global_reference *ref) |
52 | { | 52 | { |
53 | ttm_mem_global_release(ref->object); | 53 | ttm_mem_global_release(ref->object); |
54 | } | 54 | } |
@@ -56,16 +56,16 @@ nouveau_ttm_mem_global_release(struct ttm_global_reference *ref) | |||
56 | int | 56 | int |
57 | nouveau_ttm_global_init(struct drm_nouveau_private *dev_priv) | 57 | nouveau_ttm_global_init(struct drm_nouveau_private *dev_priv) |
58 | { | 58 | { |
59 | struct ttm_global_reference *global_ref; | 59 | struct drm_global_reference *global_ref; |
60 | int ret; | 60 | int ret; |
61 | 61 | ||
62 | global_ref = &dev_priv->ttm.mem_global_ref; | 62 | global_ref = &dev_priv->ttm.mem_global_ref; |
63 | global_ref->global_type = TTM_GLOBAL_TTM_MEM; | 63 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
64 | global_ref->size = sizeof(struct ttm_mem_global); | 64 | global_ref->size = sizeof(struct ttm_mem_global); |
65 | global_ref->init = &nouveau_ttm_mem_global_init; | 65 | global_ref->init = &nouveau_ttm_mem_global_init; |
66 | global_ref->release = &nouveau_ttm_mem_global_release; | 66 | global_ref->release = &nouveau_ttm_mem_global_release; |
67 | 67 | ||
68 | ret = ttm_global_item_ref(global_ref); | 68 | ret = drm_global_item_ref(global_ref); |
69 | if (unlikely(ret != 0)) { | 69 | if (unlikely(ret != 0)) { |
70 | DRM_ERROR("Failed setting up TTM memory accounting\n"); | 70 | DRM_ERROR("Failed setting up TTM memory accounting\n"); |
71 | dev_priv->ttm.mem_global_ref.release = NULL; | 71 | dev_priv->ttm.mem_global_ref.release = NULL; |
@@ -74,15 +74,15 @@ nouveau_ttm_global_init(struct drm_nouveau_private *dev_priv) | |||
74 | 74 | ||
75 | dev_priv->ttm.bo_global_ref.mem_glob = global_ref->object; | 75 | dev_priv->ttm.bo_global_ref.mem_glob = global_ref->object; |
76 | global_ref = &dev_priv->ttm.bo_global_ref.ref; | 76 | global_ref = &dev_priv->ttm.bo_global_ref.ref; |
77 | global_ref->global_type = TTM_GLOBAL_TTM_BO; | 77 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
78 | global_ref->size = sizeof(struct ttm_bo_global); | 78 | global_ref->size = sizeof(struct ttm_bo_global); |
79 | global_ref->init = &ttm_bo_global_init; | 79 | global_ref->init = &ttm_bo_global_init; |
80 | global_ref->release = &ttm_bo_global_release; | 80 | global_ref->release = &ttm_bo_global_release; |
81 | 81 | ||
82 | ret = ttm_global_item_ref(global_ref); | 82 | ret = drm_global_item_ref(global_ref); |
83 | if (unlikely(ret != 0)) { | 83 | if (unlikely(ret != 0)) { |
84 | DRM_ERROR("Failed setting up TTM BO subsystem\n"); | 84 | DRM_ERROR("Failed setting up TTM BO subsystem\n"); |
85 | ttm_global_item_unref(&dev_priv->ttm.mem_global_ref); | 85 | drm_global_item_unref(&dev_priv->ttm.mem_global_ref); |
86 | dev_priv->ttm.mem_global_ref.release = NULL; | 86 | dev_priv->ttm.mem_global_ref.release = NULL; |
87 | return ret; | 87 | return ret; |
88 | } | 88 | } |
@@ -96,8 +96,8 @@ nouveau_ttm_global_release(struct drm_nouveau_private *dev_priv) | |||
96 | if (dev_priv->ttm.mem_global_ref.release == NULL) | 96 | if (dev_priv->ttm.mem_global_ref.release == NULL) |
97 | return; | 97 | return; |
98 | 98 | ||
99 | ttm_global_item_unref(&dev_priv->ttm.bo_global_ref.ref); | 99 | drm_global_item_unref(&dev_priv->ttm.bo_global_ref.ref); |
100 | ttm_global_item_unref(&dev_priv->ttm.mem_global_ref); | 100 | drm_global_item_unref(&dev_priv->ttm.mem_global_ref); |
101 | dev_priv->ttm.mem_global_ref.release = NULL; | 101 | dev_priv->ttm.mem_global_ref.release = NULL; |
102 | } | 102 | } |
103 | 103 | ||
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index ec702345d70e..a2e65d9f2a1c 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -818,7 +818,7 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
818 | 818 | ||
819 | /* no fb bound */ | 819 | /* no fb bound */ |
820 | if (!crtc->fb) { | 820 | if (!crtc->fb) { |
821 | DRM_DEBUG("No FB bound\n"); | 821 | DRM_DEBUG_KMS("No FB bound\n"); |
822 | return 0; | 822 | return 0; |
823 | } | 823 | } |
824 | 824 | ||
@@ -957,7 +957,7 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
957 | 957 | ||
958 | /* no fb bound */ | 958 | /* no fb bound */ |
959 | if (!crtc->fb) { | 959 | if (!crtc->fb) { |
960 | DRM_DEBUG("No FB bound\n"); | 960 | DRM_DEBUG_KMS("No FB bound\n"); |
961 | return 0; | 961 | return 0; |
962 | } | 962 | } |
963 | 963 | ||
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index abffb1499e22..36e0d4b545e6 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c | |||
@@ -296,7 +296,7 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |||
296 | u8 this_v = dp_get_adjust_request_voltage(link_status, lane); | 296 | u8 this_v = dp_get_adjust_request_voltage(link_status, lane); |
297 | u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); | 297 | u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); |
298 | 298 | ||
299 | DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n", | 299 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
300 | lane, | 300 | lane, |
301 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | 301 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
302 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | 302 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
@@ -313,7 +313,7 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |||
313 | if (p >= dp_pre_emphasis_max(v)) | 313 | if (p >= dp_pre_emphasis_max(v)) |
314 | p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | 314 | p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
315 | 315 | ||
316 | DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n", | 316 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
317 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | 317 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
318 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | 318 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
319 | 319 | ||
@@ -358,7 +358,7 @@ retry: | |||
358 | if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { | 358 | if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { |
359 | if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) | 359 | if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) |
360 | goto retry; | 360 | goto retry; |
361 | DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n", | 361 | DRM_DEBUG_KMS("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n", |
362 | req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], | 362 | req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], |
363 | chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count); | 363 | chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count); |
364 | return false; | 364 | return false; |
@@ -461,10 +461,10 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) | |||
461 | memcpy(dig_connector->dpcd, msg, 8); | 461 | memcpy(dig_connector->dpcd, msg, 8); |
462 | { | 462 | { |
463 | int i; | 463 | int i; |
464 | DRM_DEBUG("DPCD: "); | 464 | DRM_DEBUG_KMS("DPCD: "); |
465 | for (i = 0; i < 8; i++) | 465 | for (i = 0; i < 8; i++) |
466 | DRM_DEBUG("%02x ", msg[i]); | 466 | DRM_DEBUG_KMS("%02x ", msg[i]); |
467 | DRM_DEBUG("\n"); | 467 | DRM_DEBUG_KMS("\n"); |
468 | } | 468 | } |
469 | return true; | 469 | return true; |
470 | } | 470 | } |
@@ -512,7 +512,7 @@ static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector, | |||
512 | return false; | 512 | return false; |
513 | } | 513 | } |
514 | 514 | ||
515 | DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n", | 515 | DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n", |
516 | link_status[0], link_status[1], link_status[2], | 516 | link_status[0], link_status[1], link_status[2], |
517 | link_status[3], link_status[4], link_status[5]); | 517 | link_status[3], link_status[4], link_status[5]); |
518 | return true; | 518 | return true; |
@@ -695,7 +695,7 @@ void dp_link_train(struct drm_encoder *encoder, | |||
695 | if (!clock_recovery) | 695 | if (!clock_recovery) |
696 | DRM_ERROR("clock recovery failed\n"); | 696 | DRM_ERROR("clock recovery failed\n"); |
697 | else | 697 | else |
698 | DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n", | 698 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
699 | train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, | 699 | train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
700 | (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> | 700 | (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
701 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | 701 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
@@ -739,7 +739,7 @@ void dp_link_train(struct drm_encoder *encoder, | |||
739 | if (!channel_eq) | 739 | if (!channel_eq) |
740 | DRM_ERROR("channel eq failed\n"); | 740 | DRM_ERROR("channel eq failed\n"); |
741 | else | 741 | else |
742 | DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n", | 742 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
743 | train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, | 743 | train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
744 | (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) | 744 | (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
745 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); | 745 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index e115583f84fb..e817a0bb5eb4 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -141,7 +141,7 @@ void r100_pm_get_dynpm_state(struct radeon_device *rdev) | |||
141 | /* only one clock mode per power state */ | 141 | /* only one clock mode per power state */ |
142 | rdev->pm.requested_clock_mode_index = 0; | 142 | rdev->pm.requested_clock_mode_index = 0; |
143 | 143 | ||
144 | DRM_DEBUG("Requested: e: %d m: %d p: %d\n", | 144 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
145 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 145 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
146 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | 146 | clock_info[rdev->pm.requested_clock_mode_index].sclk, |
147 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 147 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
@@ -276,7 +276,7 @@ void r100_pm_misc(struct radeon_device *rdev) | |||
276 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { | 276 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
277 | radeon_set_pcie_lanes(rdev, | 277 | radeon_set_pcie_lanes(rdev, |
278 | ps->pcie_lanes); | 278 | ps->pcie_lanes); |
279 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); | 279 | DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); |
280 | } | 280 | } |
281 | } | 281 | } |
282 | 282 | ||
@@ -849,7 +849,7 @@ static int r100_cp_init_microcode(struct radeon_device *rdev) | |||
849 | const char *fw_name = NULL; | 849 | const char *fw_name = NULL; |
850 | int err; | 850 | int err; |
851 | 851 | ||
852 | DRM_DEBUG("\n"); | 852 | DRM_DEBUG_KMS("\n"); |
853 | 853 | ||
854 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | 854 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
855 | err = IS_ERR(pdev); | 855 | err = IS_ERR(pdev); |
@@ -1803,6 +1803,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1803 | return r; | 1803 | return r; |
1804 | break; | 1804 | break; |
1805 | /* triggers drawing using indices to vertex buffer */ | 1805 | /* triggers drawing using indices to vertex buffer */ |
1806 | case PACKET3_3D_CLEAR_HIZ: | ||
1807 | case PACKET3_3D_CLEAR_ZMASK: | ||
1808 | if (p->rdev->hyperz_filp != p->filp) | ||
1809 | return -EINVAL; | ||
1810 | break; | ||
1806 | case PACKET3_NOP: | 1811 | case PACKET3_NOP: |
1807 | break; | 1812 | break; |
1808 | default: | 1813 | default: |
@@ -2642,7 +2647,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, | |||
2642 | flags |= pitch / 8; | 2647 | flags |= pitch / 8; |
2643 | 2648 | ||
2644 | 2649 | ||
2645 | DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); | 2650 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
2646 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); | 2651 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
2647 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); | 2652 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
2648 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); | 2653 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
@@ -3038,7 +3043,7 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
3038 | } | 3043 | } |
3039 | #endif | 3044 | #endif |
3040 | 3045 | ||
3041 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", | 3046 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
3042 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | 3047 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
3043 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | 3048 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
3044 | } | 3049 | } |
@@ -3134,7 +3139,7 @@ void r100_bandwidth_update(struct radeon_device *rdev) | |||
3134 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | 3139 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
3135 | } | 3140 | } |
3136 | 3141 | ||
3137 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", | 3142 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", |
3138 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | 3143 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
3139 | } | 3144 | } |
3140 | } | 3145 | } |
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h index d016b16fa116..b121b6c678d4 100644 --- a/drivers/gpu/drm/radeon/r100d.h +++ b/drivers/gpu/drm/radeon/r100d.h | |||
@@ -48,10 +48,12 @@ | |||
48 | #define PACKET3_3D_DRAW_IMMD 0x29 | 48 | #define PACKET3_3D_DRAW_IMMD 0x29 |
49 | #define PACKET3_3D_DRAW_INDX 0x2A | 49 | #define PACKET3_3D_DRAW_INDX 0x2A |
50 | #define PACKET3_3D_LOAD_VBPNTR 0x2F | 50 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
51 | #define PACKET3_3D_CLEAR_ZMASK 0x32 | ||
51 | #define PACKET3_INDX_BUFFER 0x33 | 52 | #define PACKET3_INDX_BUFFER 0x33 |
52 | #define PACKET3_3D_DRAW_VBUF_2 0x34 | 53 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
53 | #define PACKET3_3D_DRAW_IMMD_2 0x35 | 54 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
54 | #define PACKET3_3D_DRAW_INDX_2 0x36 | 55 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
56 | #define PACKET3_3D_CLEAR_HIZ 0x37 | ||
55 | #define PACKET3_BITBLT_MULTI 0x9B | 57 | #define PACKET3_BITBLT_MULTI 0x9B |
56 | 58 | ||
57 | #define PACKET0(reg, n) (CP_PACKET0 | \ | 59 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 58eab5d47305..c827738ad7dd 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -1048,14 +1048,47 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1048 | /* RB3D_COLOR_CHANNEL_MASK */ | 1048 | /* RB3D_COLOR_CHANNEL_MASK */ |
1049 | track->color_channel_mask = idx_value; | 1049 | track->color_channel_mask = idx_value; |
1050 | break; | 1050 | break; |
1051 | case 0x4d1c: | 1051 | case 0x43a4: |
1052 | /* SC_HYPERZ_EN */ | ||
1053 | /* r300c emits this register - we need to disable hyperz for it | ||
1054 | * without complaining */ | ||
1055 | if (p->rdev->hyperz_filp != p->filp) { | ||
1056 | if (idx_value & 0x1) | ||
1057 | ib[idx] = idx_value & ~1; | ||
1058 | } | ||
1059 | break; | ||
1060 | case 0x4f1c: | ||
1052 | /* ZB_BW_CNTL */ | 1061 | /* ZB_BW_CNTL */ |
1053 | track->zb_cb_clear = !!(idx_value & (1 << 5)); | 1062 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
1063 | if (p->rdev->hyperz_filp != p->filp) { | ||
1064 | if (idx_value & (R300_HIZ_ENABLE | | ||
1065 | R300_RD_COMP_ENABLE | | ||
1066 | R300_WR_COMP_ENABLE | | ||
1067 | R300_FAST_FILL_ENABLE)) | ||
1068 | goto fail; | ||
1069 | } | ||
1054 | break; | 1070 | break; |
1055 | case 0x4e04: | 1071 | case 0x4e04: |
1056 | /* RB3D_BLENDCNTL */ | 1072 | /* RB3D_BLENDCNTL */ |
1057 | track->blend_read_enable = !!(idx_value & (1 << 2)); | 1073 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
1058 | break; | 1074 | break; |
1075 | case 0x4f28: /* ZB_DEPTHCLEARVALUE */ | ||
1076 | break; | ||
1077 | case 0x4f30: /* ZB_MASK_OFFSET */ | ||
1078 | case 0x4f34: /* ZB_ZMASK_PITCH */ | ||
1079 | case 0x4f44: /* ZB_HIZ_OFFSET */ | ||
1080 | case 0x4f54: /* ZB_HIZ_PITCH */ | ||
1081 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | ||
1082 | goto fail; | ||
1083 | break; | ||
1084 | case 0x4028: | ||
1085 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | ||
1086 | goto fail; | ||
1087 | /* GB_Z_PEQ_CONFIG */ | ||
1088 | if (p->rdev->family >= CHIP_RV350) | ||
1089 | break; | ||
1090 | goto fail; | ||
1091 | break; | ||
1059 | case 0x4be8: | 1092 | case 0x4be8: |
1060 | /* valid register only on RV530 */ | 1093 | /* valid register only on RV530 */ |
1061 | if (p->rdev->family == CHIP_RV530) | 1094 | if (p->rdev->family == CHIP_RV530) |
@@ -1066,8 +1099,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1066 | } | 1099 | } |
1067 | return 0; | 1100 | return 0; |
1068 | fail: | 1101 | fail: |
1069 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | 1102 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
1070 | reg, idx); | 1103 | reg, idx, idx_value); |
1071 | return -EINVAL; | 1104 | return -EINVAL; |
1072 | } | 1105 | } |
1073 | 1106 | ||
@@ -1161,6 +1194,11 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1161 | return r; | 1194 | return r; |
1162 | } | 1195 | } |
1163 | break; | 1196 | break; |
1197 | case PACKET3_3D_CLEAR_HIZ: | ||
1198 | case PACKET3_3D_CLEAR_ZMASK: | ||
1199 | if (p->rdev->hyperz_filp != p->filp) | ||
1200 | return -EINVAL; | ||
1201 | break; | ||
1164 | case PACKET3_NOP: | 1202 | case PACKET3_NOP: |
1165 | break; | 1203 | break; |
1166 | default: | 1204 | default: |
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h index 968a33317fbf..0c036c60d9df 100644 --- a/drivers/gpu/drm/radeon/r300d.h +++ b/drivers/gpu/drm/radeon/r300d.h | |||
@@ -48,10 +48,12 @@ | |||
48 | #define PACKET3_3D_DRAW_IMMD 0x29 | 48 | #define PACKET3_3D_DRAW_IMMD 0x29 |
49 | #define PACKET3_3D_DRAW_INDX 0x2A | 49 | #define PACKET3_3D_DRAW_INDX 0x2A |
50 | #define PACKET3_3D_LOAD_VBPNTR 0x2F | 50 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
51 | #define PACKET3_3D_CLEAR_ZMASK 0x32 | ||
51 | #define PACKET3_INDX_BUFFER 0x33 | 52 | #define PACKET3_INDX_BUFFER 0x33 |
52 | #define PACKET3_3D_DRAW_VBUF_2 0x34 | 53 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
53 | #define PACKET3_3D_DRAW_IMMD_2 0x35 | 54 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
54 | #define PACKET3_3D_DRAW_INDX_2 0x36 | 55 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
56 | #define PACKET3_3D_CLEAR_HIZ 0x37 | ||
55 | #define PACKET3_BITBLT_MULTI 0x9B | 57 | #define PACKET3_BITBLT_MULTI 0x9B |
56 | 58 | ||
57 | #define PACKET0(reg, n) (CP_PACKET0 | \ | 59 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 28e39bc6768b..d0ebae9dde25 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -271,7 +271,7 @@ void r600_pm_get_dynpm_state(struct radeon_device *rdev) | |||
271 | } | 271 | } |
272 | } | 272 | } |
273 | 273 | ||
274 | DRM_DEBUG("Requested: e: %d m: %d p: %d\n", | 274 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
275 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 275 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
276 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | 276 | clock_info[rdev->pm.requested_clock_mode_index].sclk, |
277 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | 277 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
@@ -586,7 +586,7 @@ void r600_pm_misc(struct radeon_device *rdev) | |||
586 | if (voltage->voltage != rdev->pm.current_vddc) { | 586 | if (voltage->voltage != rdev->pm.current_vddc) { |
587 | radeon_atom_set_voltage(rdev, voltage->voltage); | 587 | radeon_atom_set_voltage(rdev, voltage->voltage); |
588 | rdev->pm.current_vddc = voltage->voltage; | 588 | rdev->pm.current_vddc = voltage->voltage; |
589 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); | 589 | DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); |
590 | } | 590 | } |
591 | } | 591 | } |
592 | } | 592 | } |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index c84f9a311550..3cd1c470b777 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -235,7 +235,7 @@ struct radeon_surface_reg { | |||
235 | */ | 235 | */ |
236 | struct radeon_mman { | 236 | struct radeon_mman { |
237 | struct ttm_bo_global_ref bo_global_ref; | 237 | struct ttm_bo_global_ref bo_global_ref; |
238 | struct ttm_global_reference mem_global_ref; | 238 | struct drm_global_reference mem_global_ref; |
239 | struct ttm_bo_device bdev; | 239 | struct ttm_bo_device bdev; |
240 | bool mem_global_referenced; | 240 | bool mem_global_referenced; |
241 | bool initialized; | 241 | bool initialized; |
@@ -1098,6 +1098,8 @@ struct radeon_device { | |||
1098 | 1098 | ||
1099 | bool powered_down; | 1099 | bool powered_down; |
1100 | struct notifier_block acpi_nb; | 1100 | struct notifier_block acpi_nb; |
1101 | /* only one userspace can use Hyperz features at a time */ | ||
1102 | struct drm_file *hyperz_filp; | ||
1101 | }; | 1103 | }; |
1102 | 1104 | ||
1103 | int radeon_device_init(struct radeon_device *rdev, | 1105 | int radeon_device_init(struct radeon_device *rdev, |
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 0a97aeb083dd..3bc2bcdf5308 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -723,7 +723,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct | |||
723 | } | 723 | } |
724 | 724 | ||
725 | if (i == ATOM_DEVICE_CV_INDEX) { | 725 | if (i == ATOM_DEVICE_CV_INDEX) { |
726 | DRM_DEBUG("Skipping Component Video\n"); | 726 | DRM_DEBUG_KMS("Skipping Component Video\n"); |
727 | continue; | 727 | continue; |
728 | } | 728 | } |
729 | 729 | ||
@@ -1032,21 +1032,18 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev) | |||
1032 | u8 frev, crev; | 1032 | u8 frev, crev; |
1033 | u16 data_offset; | 1033 | u16 data_offset; |
1034 | 1034 | ||
1035 | /* sideport is AMD only */ | ||
1036 | if (rdev->family == CHIP_RS600) | ||
1037 | return false; | ||
1038 | |||
1035 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, | 1039 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
1036 | &frev, &crev, &data_offset)) { | 1040 | &frev, &crev, &data_offset)) { |
1037 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | 1041 | igp_info = (union igp_info *)(mode_info->atom_context->bios + |
1038 | data_offset); | 1042 | data_offset); |
1039 | switch (crev) { | 1043 | switch (crev) { |
1040 | case 1: | 1044 | case 1: |
1041 | /* AMD IGPS */ | 1045 | if (igp_info->info.ulBootUpMemoryClock) |
1042 | if ((rdev->family == CHIP_RS690) || | 1046 | return true; |
1043 | (rdev->family == CHIP_RS740)) { | ||
1044 | if (igp_info->info.ulBootUpMemoryClock) | ||
1045 | return true; | ||
1046 | } else { | ||
1047 | if (igp_info->info.ucMemoryType & 0xf0) | ||
1048 | return true; | ||
1049 | } | ||
1050 | break; | 1047 | break; |
1051 | case 2: | 1048 | case 2: |
1052 | if (igp_info->info_2.ucMemoryType & 0x0f) | 1049 | if (igp_info->info_2.ucMemoryType & 0x0f) |
@@ -1095,7 +1092,7 @@ bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, | |||
1095 | (tmds_info->asMiscInfo[i]. | 1092 | (tmds_info->asMiscInfo[i]. |
1096 | ucPLL_VoltageSwing & 0xf) << 16; | 1093 | ucPLL_VoltageSwing & 0xf) << 16; |
1097 | 1094 | ||
1098 | DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", | 1095 | DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", |
1099 | tmds->tmds_pll[i].freq, | 1096 | tmds->tmds_pll[i].freq, |
1100 | tmds->tmds_pll[i].value); | 1097 | tmds->tmds_pll[i].value); |
1101 | 1098 | ||
@@ -2187,11 +2184,11 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2187 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && | 2184 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
2188 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { | 2185 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
2189 | if (connected) { | 2186 | if (connected) { |
2190 | DRM_DEBUG("TV1 connected\n"); | 2187 | DRM_DEBUG_KMS("TV1 connected\n"); |
2191 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; | 2188 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
2192 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; | 2189 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; |
2193 | } else { | 2190 | } else { |
2194 | DRM_DEBUG("TV1 disconnected\n"); | 2191 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
2195 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; | 2192 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
2196 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; | 2193 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; |
2197 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; | 2194 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; |
@@ -2200,11 +2197,11 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2200 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && | 2197 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && |
2201 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { | 2198 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { |
2202 | if (connected) { | 2199 | if (connected) { |
2203 | DRM_DEBUG("CV connected\n"); | 2200 | DRM_DEBUG_KMS("CV connected\n"); |
2204 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; | 2201 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
2205 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; | 2202 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; |
2206 | } else { | 2203 | } else { |
2207 | DRM_DEBUG("CV disconnected\n"); | 2204 | DRM_DEBUG_KMS("CV disconnected\n"); |
2208 | bios_0_scratch &= ~ATOM_S0_CV_MASK; | 2205 | bios_0_scratch &= ~ATOM_S0_CV_MASK; |
2209 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; | 2206 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; |
2210 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; | 2207 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; |
@@ -2213,12 +2210,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2213 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && | 2210 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
2214 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { | 2211 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
2215 | if (connected) { | 2212 | if (connected) { |
2216 | DRM_DEBUG("LCD1 connected\n"); | 2213 | DRM_DEBUG_KMS("LCD1 connected\n"); |
2217 | bios_0_scratch |= ATOM_S0_LCD1; | 2214 | bios_0_scratch |= ATOM_S0_LCD1; |
2218 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; | 2215 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; |
2219 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; | 2216 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; |
2220 | } else { | 2217 | } else { |
2221 | DRM_DEBUG("LCD1 disconnected\n"); | 2218 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
2222 | bios_0_scratch &= ~ATOM_S0_LCD1; | 2219 | bios_0_scratch &= ~ATOM_S0_LCD1; |
2223 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; | 2220 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; |
2224 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; | 2221 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; |
@@ -2227,12 +2224,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2227 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && | 2224 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
2228 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { | 2225 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
2229 | if (connected) { | 2226 | if (connected) { |
2230 | DRM_DEBUG("CRT1 connected\n"); | 2227 | DRM_DEBUG_KMS("CRT1 connected\n"); |
2231 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; | 2228 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
2232 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; | 2229 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; |
2233 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; | 2230 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; |
2234 | } else { | 2231 | } else { |
2235 | DRM_DEBUG("CRT1 disconnected\n"); | 2232 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
2236 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; | 2233 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
2237 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; | 2234 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; |
2238 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; | 2235 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; |
@@ -2241,12 +2238,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2241 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && | 2238 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
2242 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { | 2239 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
2243 | if (connected) { | 2240 | if (connected) { |
2244 | DRM_DEBUG("CRT2 connected\n"); | 2241 | DRM_DEBUG_KMS("CRT2 connected\n"); |
2245 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; | 2242 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
2246 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; | 2243 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; |
2247 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; | 2244 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; |
2248 | } else { | 2245 | } else { |
2249 | DRM_DEBUG("CRT2 disconnected\n"); | 2246 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
2250 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; | 2247 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
2251 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; | 2248 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; |
2252 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; | 2249 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; |
@@ -2255,12 +2252,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2255 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && | 2252 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
2256 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { | 2253 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
2257 | if (connected) { | 2254 | if (connected) { |
2258 | DRM_DEBUG("DFP1 connected\n"); | 2255 | DRM_DEBUG_KMS("DFP1 connected\n"); |
2259 | bios_0_scratch |= ATOM_S0_DFP1; | 2256 | bios_0_scratch |= ATOM_S0_DFP1; |
2260 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; | 2257 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; |
2261 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; | 2258 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; |
2262 | } else { | 2259 | } else { |
2263 | DRM_DEBUG("DFP1 disconnected\n"); | 2260 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
2264 | bios_0_scratch &= ~ATOM_S0_DFP1; | 2261 | bios_0_scratch &= ~ATOM_S0_DFP1; |
2265 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; | 2262 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; |
2266 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; | 2263 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; |
@@ -2269,12 +2266,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2269 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && | 2266 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
2270 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { | 2267 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
2271 | if (connected) { | 2268 | if (connected) { |
2272 | DRM_DEBUG("DFP2 connected\n"); | 2269 | DRM_DEBUG_KMS("DFP2 connected\n"); |
2273 | bios_0_scratch |= ATOM_S0_DFP2; | 2270 | bios_0_scratch |= ATOM_S0_DFP2; |
2274 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; | 2271 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; |
2275 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; | 2272 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; |
2276 | } else { | 2273 | } else { |
2277 | DRM_DEBUG("DFP2 disconnected\n"); | 2274 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
2278 | bios_0_scratch &= ~ATOM_S0_DFP2; | 2275 | bios_0_scratch &= ~ATOM_S0_DFP2; |
2279 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; | 2276 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; |
2280 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; | 2277 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; |
@@ -2283,12 +2280,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2283 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && | 2280 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && |
2284 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { | 2281 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { |
2285 | if (connected) { | 2282 | if (connected) { |
2286 | DRM_DEBUG("DFP3 connected\n"); | 2283 | DRM_DEBUG_KMS("DFP3 connected\n"); |
2287 | bios_0_scratch |= ATOM_S0_DFP3; | 2284 | bios_0_scratch |= ATOM_S0_DFP3; |
2288 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; | 2285 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; |
2289 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; | 2286 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; |
2290 | } else { | 2287 | } else { |
2291 | DRM_DEBUG("DFP3 disconnected\n"); | 2288 | DRM_DEBUG_KMS("DFP3 disconnected\n"); |
2292 | bios_0_scratch &= ~ATOM_S0_DFP3; | 2289 | bios_0_scratch &= ~ATOM_S0_DFP3; |
2293 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; | 2290 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; |
2294 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; | 2291 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; |
@@ -2297,12 +2294,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2297 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && | 2294 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && |
2298 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { | 2295 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { |
2299 | if (connected) { | 2296 | if (connected) { |
2300 | DRM_DEBUG("DFP4 connected\n"); | 2297 | DRM_DEBUG_KMS("DFP4 connected\n"); |
2301 | bios_0_scratch |= ATOM_S0_DFP4; | 2298 | bios_0_scratch |= ATOM_S0_DFP4; |
2302 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; | 2299 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; |
2303 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; | 2300 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; |
2304 | } else { | 2301 | } else { |
2305 | DRM_DEBUG("DFP4 disconnected\n"); | 2302 | DRM_DEBUG_KMS("DFP4 disconnected\n"); |
2306 | bios_0_scratch &= ~ATOM_S0_DFP4; | 2303 | bios_0_scratch &= ~ATOM_S0_DFP4; |
2307 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; | 2304 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; |
2308 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; | 2305 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; |
@@ -2311,12 +2308,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |||
2311 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && | 2308 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && |
2312 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { | 2309 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { |
2313 | if (connected) { | 2310 | if (connected) { |
2314 | DRM_DEBUG("DFP5 connected\n"); | 2311 | DRM_DEBUG_KMS("DFP5 connected\n"); |
2315 | bios_0_scratch |= ATOM_S0_DFP5; | 2312 | bios_0_scratch |= ATOM_S0_DFP5; |
2316 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; | 2313 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; |
2317 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; | 2314 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; |
2318 | } else { | 2315 | } else { |
2319 | DRM_DEBUG("DFP5 disconnected\n"); | 2316 | DRM_DEBUG_KMS("DFP5 disconnected\n"); |
2320 | bios_0_scratch &= ~ATOM_S0_DFP5; | 2317 | bios_0_scratch &= ~ATOM_S0_DFP5; |
2321 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; | 2318 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; |
2322 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; | 2319 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; |
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 5e45cb27eb98..5e1474cde4b4 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c | |||
@@ -693,6 +693,10 @@ bool radeon_combios_sideport_present(struct radeon_device *rdev) | |||
693 | struct drm_device *dev = rdev->ddev; | 693 | struct drm_device *dev = rdev->ddev; |
694 | u16 igp_info; | 694 | u16 igp_info; |
695 | 695 | ||
696 | /* sideport is AMD only */ | ||
697 | if (rdev->family == CHIP_RS400) | ||
698 | return false; | ||
699 | |||
696 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); | 700 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
697 | 701 | ||
698 | if (igp_info) { | 702 | if (igp_info) { |
@@ -1205,7 +1209,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |||
1205 | RBIOS32(tmds_info + i * 10 + 0x08); | 1209 | RBIOS32(tmds_info + i * 10 + 0x08); |
1206 | tmds->tmds_pll[i].freq = | 1210 | tmds->tmds_pll[i].freq = |
1207 | RBIOS16(tmds_info + i * 10 + 0x10); | 1211 | RBIOS16(tmds_info + i * 10 + 0x10); |
1208 | DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", | 1212 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1209 | tmds->tmds_pll[i].freq, | 1213 | tmds->tmds_pll[i].freq, |
1210 | tmds->tmds_pll[i].value); | 1214 | tmds->tmds_pll[i].value); |
1211 | } | 1215 | } |
@@ -1223,7 +1227,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, | |||
1223 | stride += 10; | 1227 | stride += 10; |
1224 | else | 1228 | else |
1225 | stride += 6; | 1229 | stride += 6; |
1226 | DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", | 1230 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
1227 | tmds->tmds_pll[i].freq, | 1231 | tmds->tmds_pll[i].freq, |
1228 | tmds->tmds_pll[i].value); | 1232 | tmds->tmds_pll[i].value); |
1229 | } | 1233 | } |
@@ -2208,7 +2212,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) | |||
2208 | uint16_t tmds_info = | 2212 | uint16_t tmds_info = |
2209 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); | 2213 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
2210 | if (tmds_info) { | 2214 | if (tmds_info) { |
2211 | DRM_DEBUG("Found DFP table, assuming DVI connector\n"); | 2215 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
2212 | 2216 | ||
2213 | radeon_add_legacy_encoder(dev, | 2217 | radeon_add_legacy_encoder(dev, |
2214 | radeon_get_encoder_id(dev, | 2218 | radeon_get_encoder_id(dev, |
@@ -2234,7 +2238,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) | |||
2234 | } else { | 2238 | } else { |
2235 | uint16_t crt_info = | 2239 | uint16_t crt_info = |
2236 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); | 2240 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
2237 | DRM_DEBUG("Found CRT table, assuming VGA connector\n"); | 2241 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
2238 | if (crt_info) { | 2242 | if (crt_info) { |
2239 | radeon_add_legacy_encoder(dev, | 2243 | radeon_add_legacy_encoder(dev, |
2240 | radeon_get_encoder_id(dev, | 2244 | radeon_get_encoder_id(dev, |
@@ -2251,7 +2255,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) | |||
2251 | CONNECTOR_OBJECT_ID_VGA, | 2255 | CONNECTOR_OBJECT_ID_VGA, |
2252 | &hpd); | 2256 | &hpd); |
2253 | } else { | 2257 | } else { |
2254 | DRM_DEBUG("No connector info found\n"); | 2258 | DRM_DEBUG_KMS("No connector info found\n"); |
2255 | return false; | 2259 | return false; |
2256 | } | 2260 | } |
2257 | } | 2261 | } |
@@ -2340,7 +2344,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) | |||
2340 | ddc_i2c.valid = false; | 2344 | ddc_i2c.valid = false; |
2341 | break; | 2345 | break; |
2342 | } | 2346 | } |
2343 | DRM_DEBUG("LCD DDC Info Table found!\n"); | 2347 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
2344 | } else | 2348 | } else |
2345 | ddc_i2c.valid = false; | 2349 | ddc_i2c.valid = false; |
2346 | 2350 | ||
@@ -3118,14 +3122,14 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |||
3118 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && | 3122 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
3119 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { | 3123 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
3120 | if (connected) { | 3124 | if (connected) { |
3121 | DRM_DEBUG("TV1 connected\n"); | 3125 | DRM_DEBUG_KMS("TV1 connected\n"); |
3122 | /* fix me */ | 3126 | /* fix me */ |
3123 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; | 3127 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
3124 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ | 3128 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3125 | bios_5_scratch |= RADEON_TV1_ON; | 3129 | bios_5_scratch |= RADEON_TV1_ON; |
3126 | bios_5_scratch |= RADEON_ACC_REQ_TV1; | 3130 | bios_5_scratch |= RADEON_ACC_REQ_TV1; |
3127 | } else { | 3131 | } else { |
3128 | DRM_DEBUG("TV1 disconnected\n"); | 3132 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
3129 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; | 3133 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
3130 | bios_5_scratch &= ~RADEON_TV1_ON; | 3134 | bios_5_scratch &= ~RADEON_TV1_ON; |
3131 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; | 3135 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
@@ -3134,12 +3138,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |||
3134 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && | 3138 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
3135 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { | 3139 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
3136 | if (connected) { | 3140 | if (connected) { |
3137 | DRM_DEBUG("LCD1 connected\n"); | 3141 | DRM_DEBUG_KMS("LCD1 connected\n"); |
3138 | bios_4_scratch |= RADEON_LCD1_ATTACHED; | 3142 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
3139 | bios_5_scratch |= RADEON_LCD1_ON; | 3143 | bios_5_scratch |= RADEON_LCD1_ON; |
3140 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; | 3144 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
3141 | } else { | 3145 | } else { |
3142 | DRM_DEBUG("LCD1 disconnected\n"); | 3146 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
3143 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; | 3147 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
3144 | bios_5_scratch &= ~RADEON_LCD1_ON; | 3148 | bios_5_scratch &= ~RADEON_LCD1_ON; |
3145 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; | 3149 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
@@ -3148,12 +3152,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |||
3148 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && | 3152 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
3149 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { | 3153 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
3150 | if (connected) { | 3154 | if (connected) { |
3151 | DRM_DEBUG("CRT1 connected\n"); | 3155 | DRM_DEBUG_KMS("CRT1 connected\n"); |
3152 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; | 3156 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
3153 | bios_5_scratch |= RADEON_CRT1_ON; | 3157 | bios_5_scratch |= RADEON_CRT1_ON; |
3154 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; | 3158 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
3155 | } else { | 3159 | } else { |
3156 | DRM_DEBUG("CRT1 disconnected\n"); | 3160 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
3157 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; | 3161 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
3158 | bios_5_scratch &= ~RADEON_CRT1_ON; | 3162 | bios_5_scratch &= ~RADEON_CRT1_ON; |
3159 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; | 3163 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
@@ -3162,12 +3166,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |||
3162 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && | 3166 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
3163 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { | 3167 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
3164 | if (connected) { | 3168 | if (connected) { |
3165 | DRM_DEBUG("CRT2 connected\n"); | 3169 | DRM_DEBUG_KMS("CRT2 connected\n"); |
3166 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; | 3170 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
3167 | bios_5_scratch |= RADEON_CRT2_ON; | 3171 | bios_5_scratch |= RADEON_CRT2_ON; |
3168 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; | 3172 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
3169 | } else { | 3173 | } else { |
3170 | DRM_DEBUG("CRT2 disconnected\n"); | 3174 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
3171 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; | 3175 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
3172 | bios_5_scratch &= ~RADEON_CRT2_ON; | 3176 | bios_5_scratch &= ~RADEON_CRT2_ON; |
3173 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; | 3177 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
@@ -3176,12 +3180,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |||
3176 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && | 3180 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
3177 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { | 3181 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
3178 | if (connected) { | 3182 | if (connected) { |
3179 | DRM_DEBUG("DFP1 connected\n"); | 3183 | DRM_DEBUG_KMS("DFP1 connected\n"); |
3180 | bios_4_scratch |= RADEON_DFP1_ATTACHED; | 3184 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
3181 | bios_5_scratch |= RADEON_DFP1_ON; | 3185 | bios_5_scratch |= RADEON_DFP1_ON; |
3182 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; | 3186 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
3183 | } else { | 3187 | } else { |
3184 | DRM_DEBUG("DFP1 disconnected\n"); | 3188 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
3185 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; | 3189 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
3186 | bios_5_scratch &= ~RADEON_DFP1_ON; | 3190 | bios_5_scratch &= ~RADEON_DFP1_ON; |
3187 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; | 3191 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
@@ -3190,12 +3194,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |||
3190 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && | 3194 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
3191 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { | 3195 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
3192 | if (connected) { | 3196 | if (connected) { |
3193 | DRM_DEBUG("DFP2 connected\n"); | 3197 | DRM_DEBUG_KMS("DFP2 connected\n"); |
3194 | bios_4_scratch |= RADEON_DFP2_ATTACHED; | 3198 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
3195 | bios_5_scratch |= RADEON_DFP2_ON; | 3199 | bios_5_scratch |= RADEON_DFP2_ON; |
3196 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; | 3200 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
3197 | } else { | 3201 | } else { |
3198 | DRM_DEBUG("DFP2 disconnected\n"); | 3202 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
3199 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; | 3203 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
3200 | bios_5_scratch &= ~RADEON_DFP2_ON; | 3204 | bios_5_scratch &= ~RADEON_DFP2_ON; |
3201 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; | 3205 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index adccbc2c202c..6b9aac754f10 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c | |||
@@ -214,7 +214,7 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode | |||
214 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; | 214 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; |
215 | drm_mode_set_name(mode); | 215 | drm_mode_set_name(mode); |
216 | 216 | ||
217 | DRM_DEBUG("Adding native panel mode %s\n", mode->name); | 217 | DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); |
218 | } else if (native_mode->hdisplay != 0 && | 218 | } else if (native_mode->hdisplay != 0 && |
219 | native_mode->vdisplay != 0) { | 219 | native_mode->vdisplay != 0) { |
220 | /* mac laptops without an edid */ | 220 | /* mac laptops without an edid */ |
@@ -226,7 +226,7 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode | |||
226 | */ | 226 | */ |
227 | mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); | 227 | mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); |
228 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; | 228 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; |
229 | DRM_DEBUG("Adding cvt approximation of native panel mode %s\n", mode->name); | 229 | DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); |
230 | } | 230 | } |
231 | return mode; | 231 | return mode; |
232 | } | 232 | } |
@@ -522,7 +522,7 @@ static int radeon_lvds_set_property(struct drm_connector *connector, | |||
522 | struct radeon_encoder *radeon_encoder; | 522 | struct radeon_encoder *radeon_encoder; |
523 | enum radeon_rmx_type rmx_type; | 523 | enum radeon_rmx_type rmx_type; |
524 | 524 | ||
525 | DRM_DEBUG("\n"); | 525 | DRM_DEBUG_KMS("\n"); |
526 | if (property != dev->mode_config.scaling_mode_property) | 526 | if (property != dev->mode_config.scaling_mode_property) |
527 | return 0; | 527 | return 0; |
528 | 528 | ||
@@ -1082,6 +1082,8 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
1082 | drm_connector_attach_property(&radeon_connector->base, | 1082 | drm_connector_attach_property(&radeon_connector->base, |
1083 | rdev->mode_info.load_detect_property, | 1083 | rdev->mode_info.load_detect_property, |
1084 | 1); | 1084 | 1); |
1085 | /* no HPD on analog connectors */ | ||
1086 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
1085 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | 1087 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
1086 | break; | 1088 | break; |
1087 | case DRM_MODE_CONNECTOR_DVIA: | 1089 | case DRM_MODE_CONNECTOR_DVIA: |
@@ -1096,6 +1098,8 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
1096 | drm_connector_attach_property(&radeon_connector->base, | 1098 | drm_connector_attach_property(&radeon_connector->base, |
1097 | rdev->mode_info.load_detect_property, | 1099 | rdev->mode_info.load_detect_property, |
1098 | 1); | 1100 | 1); |
1101 | /* no HPD on analog connectors */ | ||
1102 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
1099 | break; | 1103 | break; |
1100 | case DRM_MODE_CONNECTOR_DVII: | 1104 | case DRM_MODE_CONNECTOR_DVII: |
1101 | case DRM_MODE_CONNECTOR_DVID: | 1105 | case DRM_MODE_CONNECTOR_DVID: |
@@ -1186,6 +1190,8 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
1186 | drm_connector_attach_property(&radeon_connector->base, | 1190 | drm_connector_attach_property(&radeon_connector->base, |
1187 | rdev->mode_info.tv_std_property, | 1191 | rdev->mode_info.tv_std_property, |
1188 | radeon_atombios_get_tv_info(rdev)); | 1192 | radeon_atombios_get_tv_info(rdev)); |
1193 | /* no HPD on analog connectors */ | ||
1194 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
1189 | } | 1195 | } |
1190 | break; | 1196 | break; |
1191 | case DRM_MODE_CONNECTOR_LVDS: | 1197 | case DRM_MODE_CONNECTOR_LVDS: |
@@ -1209,7 +1215,7 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
1209 | break; | 1215 | break; |
1210 | } | 1216 | } |
1211 | 1217 | ||
1212 | if (hpd->hpd == RADEON_HPD_NONE) { | 1218 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { |
1213 | if (i2c_bus->valid) | 1219 | if (i2c_bus->valid) |
1214 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | 1220 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
1215 | } else | 1221 | } else |
@@ -1276,6 +1282,8 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
1276 | drm_connector_attach_property(&radeon_connector->base, | 1282 | drm_connector_attach_property(&radeon_connector->base, |
1277 | rdev->mode_info.load_detect_property, | 1283 | rdev->mode_info.load_detect_property, |
1278 | 1); | 1284 | 1); |
1285 | /* no HPD on analog connectors */ | ||
1286 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
1279 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | 1287 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
1280 | break; | 1288 | break; |
1281 | case DRM_MODE_CONNECTOR_DVIA: | 1289 | case DRM_MODE_CONNECTOR_DVIA: |
@@ -1290,6 +1298,8 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
1290 | drm_connector_attach_property(&radeon_connector->base, | 1298 | drm_connector_attach_property(&radeon_connector->base, |
1291 | rdev->mode_info.load_detect_property, | 1299 | rdev->mode_info.load_detect_property, |
1292 | 1); | 1300 | 1); |
1301 | /* no HPD on analog connectors */ | ||
1302 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
1293 | break; | 1303 | break; |
1294 | case DRM_MODE_CONNECTOR_DVII: | 1304 | case DRM_MODE_CONNECTOR_DVII: |
1295 | case DRM_MODE_CONNECTOR_DVID: | 1305 | case DRM_MODE_CONNECTOR_DVID: |
@@ -1328,6 +1338,8 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
1328 | drm_connector_attach_property(&radeon_connector->base, | 1338 | drm_connector_attach_property(&radeon_connector->base, |
1329 | rdev->mode_info.tv_std_property, | 1339 | rdev->mode_info.tv_std_property, |
1330 | radeon_combios_get_tv_info(rdev)); | 1340 | radeon_combios_get_tv_info(rdev)); |
1341 | /* no HPD on analog connectors */ | ||
1342 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | ||
1331 | } | 1343 | } |
1332 | break; | 1344 | break; |
1333 | case DRM_MODE_CONNECTOR_LVDS: | 1345 | case DRM_MODE_CONNECTOR_LVDS: |
@@ -1345,7 +1357,7 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
1345 | break; | 1357 | break; |
1346 | } | 1358 | } |
1347 | 1359 | ||
1348 | if (hpd->hpd == RADEON_HPD_NONE) { | 1360 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { |
1349 | if (i2c_bus->valid) | 1361 | if (i2c_bus->valid) |
1350 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | 1362 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
1351 | } else | 1363 | } else |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 0fea894fc127..a64811a94519 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -737,7 +737,8 @@ void radeon_device_fini(struct radeon_device *rdev) | |||
737 | destroy_workqueue(rdev->wq); | 737 | destroy_workqueue(rdev->wq); |
738 | vga_switcheroo_unregister_client(rdev->pdev); | 738 | vga_switcheroo_unregister_client(rdev->pdev); |
739 | vga_client_register(rdev->pdev, NULL, NULL, NULL); | 739 | vga_client_register(rdev->pdev, NULL, NULL, NULL); |
740 | pci_iounmap(rdev->pdev, rdev->rio_mem); | 740 | if (rdev->rio_mem) |
741 | pci_iounmap(rdev->pdev, rdev->rio_mem); | ||
741 | rdev->rio_mem = NULL; | 742 | rdev->rio_mem = NULL; |
742 | iounmap(rdev->rmmio); | 743 | iounmap(rdev->rmmio); |
743 | rdev->rmmio = NULL; | 744 | rdev->rmmio = NULL; |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index a68728dbd41d..283beedc2cbf 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
@@ -42,7 +42,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc) | |||
42 | struct radeon_device *rdev = dev->dev_private; | 42 | struct radeon_device *rdev = dev->dev_private; |
43 | int i; | 43 | int i; |
44 | 44 | ||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); | 45 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); | 46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
47 | 47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | 48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
@@ -75,7 +75,7 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc) | |||
75 | struct radeon_device *rdev = dev->dev_private; | 75 | struct radeon_device *rdev = dev->dev_private; |
76 | int i; | 76 | int i; |
77 | 77 | ||
78 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); | 78 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); | 79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
80 | 80 | ||
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); | 81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
@@ -469,7 +469,7 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll, | |||
469 | uint32_t post_div; | 469 | uint32_t post_div; |
470 | u32 pll_out_min, pll_out_max; | 470 | u32 pll_out_min, pll_out_max; |
471 | 471 | ||
472 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); | 472 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
473 | freq = freq * 1000; | 473 | freq = freq * 1000; |
474 | 474 | ||
475 | if (pll->flags & RADEON_PLL_IS_LCD) { | 475 | if (pll->flags & RADEON_PLL_IS_LCD) { |
@@ -805,7 +805,7 @@ done: | |||
805 | *ref_div_p = ref_div; | 805 | *ref_div_p = ref_div; |
806 | *post_div_p = post_div; | 806 | *post_div_p = post_div; |
807 | 807 | ||
808 | DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); | 808 | DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); |
809 | } | 809 | } |
810 | 810 | ||
811 | void radeon_compute_pll(struct radeon_pll *pll, | 811 | void radeon_compute_pll(struct radeon_pll *pll, |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 6f8a2e572878..795403b0e2cd 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -46,7 +46,7 @@ | |||
46 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs | 46 | * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs |
47 | * - 2.4.0 - add crtc id query | 47 | * - 2.4.0 - add crtc id query |
48 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen | 48 | * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen |
49 | * - 2.6.0 - add tiling config query (r6xx+) | 49 | * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) |
50 | */ | 50 | */ |
51 | #define KMS_DRIVER_MAJOR 2 | 51 | #define KMS_DRIVER_MAJOR 2 |
52 | #define KMS_DRIVER_MINOR 6 | 52 | #define KMS_DRIVER_MINOR 6 |
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index e0b30b264c28..5e7a0536c9c9 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -205,7 +205,7 @@ void radeon_encoder_set_active_device(struct drm_encoder *encoder) | |||
205 | if (connector->encoder == encoder) { | 205 | if (connector->encoder == encoder) { |
206 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 206 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
207 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; | 207 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
208 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", | 208 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
209 | radeon_encoder->active_device, radeon_encoder->devices, | 209 | radeon_encoder->active_device, radeon_encoder->devices, |
210 | radeon_connector->devices, encoder->encoder_type); | 210 | radeon_connector->devices, encoder->encoder_type); |
211 | } | 211 | } |
@@ -1021,7 +1021,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
1021 | 1021 | ||
1022 | memset(&args, 0, sizeof(args)); | 1022 | memset(&args, 0, sizeof(args)); |
1023 | 1023 | ||
1024 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", | 1024 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
1025 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | 1025 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1026 | radeon_encoder->active_device); | 1026 | radeon_encoder->active_device); |
1027 | switch (radeon_encoder->encoder_id) { | 1027 | switch (radeon_encoder->encoder_id) { |
@@ -1484,7 +1484,7 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec | |||
1484 | uint32_t bios_0_scratch; | 1484 | uint32_t bios_0_scratch; |
1485 | 1485 | ||
1486 | if (!atombios_dac_load_detect(encoder, connector)) { | 1486 | if (!atombios_dac_load_detect(encoder, connector)) { |
1487 | DRM_DEBUG("detect returned false \n"); | 1487 | DRM_DEBUG_KMS("detect returned false \n"); |
1488 | return connector_status_unknown; | 1488 | return connector_status_unknown; |
1489 | } | 1489 | } |
1490 | 1490 | ||
@@ -1493,7 +1493,7 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec | |||
1493 | else | 1493 | else |
1494 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | 1494 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1495 | 1495 | ||
1496 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); | 1496 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
1497 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | 1497 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
1498 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) | 1498 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1499 | return connector_status_connected; | 1499 | return connector_status_connected; |
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 8931c8e78101..e5b705427389 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -141,7 +141,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |||
141 | } | 141 | } |
142 | } | 142 | } |
143 | if (!found) { | 143 | if (!found) { |
144 | DRM_DEBUG("unknown crtc id %d\n", value); | 144 | DRM_DEBUG_KMS("unknown crtc id %d\n", value); |
145 | return -EINVAL; | 145 | return -EINVAL; |
146 | } | 146 | } |
147 | break; | 147 | break; |
@@ -156,12 +156,21 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |||
156 | else if (rdev->family >= CHIP_R600) | 156 | else if (rdev->family >= CHIP_R600) |
157 | value = rdev->config.r600.tile_config; | 157 | value = rdev->config.r600.tile_config; |
158 | else { | 158 | else { |
159 | DRM_DEBUG("tiling config is r6xx+ only!\n"); | 159 | DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); |
160 | return -EINVAL; | 160 | return -EINVAL; |
161 | } | 161 | } |
162 | case RADEON_INFO_WANT_HYPERZ: | ||
163 | mutex_lock(&dev->struct_mutex); | ||
164 | if (rdev->hyperz_filp) | ||
165 | value = 0; | ||
166 | else { | ||
167 | rdev->hyperz_filp = filp; | ||
168 | value = 1; | ||
169 | } | ||
170 | mutex_unlock(&dev->struct_mutex); | ||
162 | break; | 171 | break; |
163 | default: | 172 | default: |
164 | DRM_DEBUG("Invalid request %d\n", info->request); | 173 | DRM_DEBUG_KMS("Invalid request %d\n", info->request); |
165 | return -EINVAL; | 174 | return -EINVAL; |
166 | } | 175 | } |
167 | if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { | 176 | if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { |
@@ -199,9 +208,11 @@ void radeon_driver_postclose_kms(struct drm_device *dev, | |||
199 | void radeon_driver_preclose_kms(struct drm_device *dev, | 208 | void radeon_driver_preclose_kms(struct drm_device *dev, |
200 | struct drm_file *file_priv) | 209 | struct drm_file *file_priv) |
201 | { | 210 | { |
211 | struct radeon_device *rdev = dev->dev_private; | ||
212 | if (rdev->hyperz_filp == file_priv) | ||
213 | rdev->hyperz_filp = NULL; | ||
202 | } | 214 | } |
203 | 215 | ||
204 | |||
205 | /* | 216 | /* |
206 | * VBlank related functions. | 217 | * VBlank related functions. |
207 | */ | 218 | */ |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index e1e5255396ac..989df519a1e4 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |||
@@ -362,10 +362,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
362 | uint32_t gen_cntl_reg, gen_cntl_val; | 362 | uint32_t gen_cntl_reg, gen_cntl_val; |
363 | int r; | 363 | int r; |
364 | 364 | ||
365 | DRM_DEBUG("\n"); | 365 | DRM_DEBUG_KMS("\n"); |
366 | /* no fb bound */ | 366 | /* no fb bound */ |
367 | if (!crtc->fb) { | 367 | if (!crtc->fb) { |
368 | DRM_DEBUG("No FB bound\n"); | 368 | DRM_DEBUG_KMS("No FB bound\n"); |
369 | return 0; | 369 | return 0; |
370 | } | 370 | } |
371 | 371 | ||
@@ -528,7 +528,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod | |||
528 | uint32_t crtc_v_sync_strt_wid; | 528 | uint32_t crtc_v_sync_strt_wid; |
529 | bool is_tv = false; | 529 | bool is_tv = false; |
530 | 530 | ||
531 | DRM_DEBUG("\n"); | 531 | DRM_DEBUG_KMS("\n"); |
532 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 532 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
533 | if (encoder->crtc == crtc) { | 533 | if (encoder->crtc == crtc) { |
534 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 534 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
@@ -757,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |||
757 | } | 757 | } |
758 | } | 758 | } |
759 | 759 | ||
760 | DRM_DEBUG("\n"); | 760 | DRM_DEBUG_KMS("\n"); |
761 | 761 | ||
762 | if (!use_bios_divs) { | 762 | if (!use_bios_divs) { |
763 | radeon_compute_pll(pll, mode->clock, | 763 | radeon_compute_pll(pll, mode->clock, |
@@ -772,7 +772,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |||
772 | if (!post_div->divider) | 772 | if (!post_div->divider) |
773 | post_div = &post_divs[0]; | 773 | post_div = &post_divs[0]; |
774 | 774 | ||
775 | DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", | 775 | DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", |
776 | (unsigned)freq, | 776 | (unsigned)freq, |
777 | feedback_div, | 777 | feedback_div, |
778 | reference_div, | 778 | reference_div, |
@@ -841,12 +841,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |||
841 | | RADEON_P2PLL_SLEEP | 841 | | RADEON_P2PLL_SLEEP |
842 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); | 842 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
843 | 843 | ||
844 | DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", | 844 | DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
845 | (unsigned)pll_ref_div, | 845 | (unsigned)pll_ref_div, |
846 | (unsigned)pll_fb_post_div, | 846 | (unsigned)pll_fb_post_div, |
847 | (unsigned)htotal_cntl, | 847 | (unsigned)htotal_cntl, |
848 | RREG32_PLL(RADEON_P2PLL_CNTL)); | 848 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
849 | DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", | 849 | DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", |
850 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, | 850 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
851 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, | 851 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
852 | (unsigned)((pll_fb_post_div & | 852 | (unsigned)((pll_fb_post_div & |
@@ -947,12 +947,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |||
947 | | RADEON_PPLL_ATOMIC_UPDATE_EN | 947 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
948 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); | 948 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
949 | 949 | ||
950 | DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", | 950 | DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
951 | pll_ref_div, | 951 | pll_ref_div, |
952 | pll_fb_post_div, | 952 | pll_fb_post_div, |
953 | (unsigned)htotal_cntl, | 953 | (unsigned)htotal_cntl, |
954 | RREG32_PLL(RADEON_PPLL_CNTL)); | 954 | RREG32_PLL(RADEON_PPLL_CNTL)); |
955 | DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", | 955 | DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", |
956 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, | 956 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
957 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, | 957 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
958 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); | 958 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 5688a0cf6bbe..b8149cbc0c70 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c | |||
@@ -47,7 +47,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) | |||
47 | uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; | 47 | uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; |
48 | int panel_pwr_delay = 2000; | 48 | int panel_pwr_delay = 2000; |
49 | bool is_mac = false; | 49 | bool is_mac = false; |
50 | DRM_DEBUG("\n"); | 50 | DRM_DEBUG_KMS("\n"); |
51 | 51 | ||
52 | if (radeon_encoder->enc_priv) { | 52 | if (radeon_encoder->enc_priv) { |
53 | if (rdev->is_atom_bios) { | 53 | if (rdev->is_atom_bios) { |
@@ -151,7 +151,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, | |||
151 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 151 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
152 | uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; | 152 | uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; |
153 | 153 | ||
154 | DRM_DEBUG("\n"); | 154 | DRM_DEBUG_KMS("\n"); |
155 | 155 | ||
156 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); | 156 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
157 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; | 157 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; |
@@ -167,7 +167,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, | |||
167 | } else { | 167 | } else { |
168 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; | 168 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
169 | if (lvds) { | 169 | if (lvds) { |
170 | DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); | 170 | DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); |
171 | lvds_gen_cntl = lvds->lvds_gen_cntl; | 171 | lvds_gen_cntl = lvds->lvds_gen_cntl; |
172 | lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | | 172 | lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
173 | (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); | 173 | (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
@@ -250,7 +250,7 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode | |||
250 | uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); | 250 | uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); |
251 | uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); | 251 | uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
252 | 252 | ||
253 | DRM_DEBUG("\n"); | 253 | DRM_DEBUG_KMS("\n"); |
254 | 254 | ||
255 | switch (mode) { | 255 | switch (mode) { |
256 | case DRM_MODE_DPMS_ON: | 256 | case DRM_MODE_DPMS_ON: |
@@ -315,7 +315,7 @@ static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, | |||
315 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 315 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
316 | uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; | 316 | uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; |
317 | 317 | ||
318 | DRM_DEBUG("\n"); | 318 | DRM_DEBUG_KMS("\n"); |
319 | 319 | ||
320 | if (radeon_crtc->crtc_id == 0) { | 320 | if (radeon_crtc->crtc_id == 0) { |
321 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { | 321 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
@@ -446,7 +446,7 @@ static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) | |||
446 | struct drm_device *dev = encoder->dev; | 446 | struct drm_device *dev = encoder->dev; |
447 | struct radeon_device *rdev = dev->dev_private; | 447 | struct radeon_device *rdev = dev->dev_private; |
448 | uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); | 448 | uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); |
449 | DRM_DEBUG("\n"); | 449 | DRM_DEBUG_KMS("\n"); |
450 | 450 | ||
451 | switch (mode) { | 451 | switch (mode) { |
452 | case DRM_MODE_DPMS_ON: | 452 | case DRM_MODE_DPMS_ON: |
@@ -502,7 +502,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, | |||
502 | uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; | 502 | uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; |
503 | int i; | 503 | int i; |
504 | 504 | ||
505 | DRM_DEBUG("\n"); | 505 | DRM_DEBUG_KMS("\n"); |
506 | 506 | ||
507 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); | 507 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); |
508 | tmp &= 0xfffff; | 508 | tmp &= 0xfffff; |
@@ -610,7 +610,7 @@ static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) | |||
610 | struct drm_device *dev = encoder->dev; | 610 | struct drm_device *dev = encoder->dev; |
611 | struct radeon_device *rdev = dev->dev_private; | 611 | struct radeon_device *rdev = dev->dev_private; |
612 | uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); | 612 | uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
613 | DRM_DEBUG("\n"); | 613 | DRM_DEBUG_KMS("\n"); |
614 | 614 | ||
615 | switch (mode) { | 615 | switch (mode) { |
616 | case DRM_MODE_DPMS_ON: | 616 | case DRM_MODE_DPMS_ON: |
@@ -666,7 +666,7 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, | |||
666 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 666 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
667 | uint32_t fp2_gen_cntl; | 667 | uint32_t fp2_gen_cntl; |
668 | 668 | ||
669 | DRM_DEBUG("\n"); | 669 | DRM_DEBUG_KMS("\n"); |
670 | 670 | ||
671 | if (rdev->is_atom_bios) { | 671 | if (rdev->is_atom_bios) { |
672 | radeon_encoder->pixel_clock = adjusted_mode->clock; | 672 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
@@ -760,7 +760,7 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) | |||
760 | uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; | 760 | uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; |
761 | uint32_t tv_master_cntl = 0; | 761 | uint32_t tv_master_cntl = 0; |
762 | bool is_tv; | 762 | bool is_tv; |
763 | DRM_DEBUG("\n"); | 763 | DRM_DEBUG_KMS("\n"); |
764 | 764 | ||
765 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; | 765 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
766 | 766 | ||
@@ -878,7 +878,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, | |||
878 | uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; | 878 | uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; |
879 | bool is_tv = false; | 879 | bool is_tv = false; |
880 | 880 | ||
881 | DRM_DEBUG("\n"); | 881 | DRM_DEBUG_KMS("\n"); |
882 | 882 | ||
883 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; | 883 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
884 | 884 | ||
@@ -1075,10 +1075,10 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder, | |||
1075 | tmp = RREG32(RADEON_TV_DAC_CNTL); | 1075 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
1076 | if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { | 1076 | if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { |
1077 | found = true; | 1077 | found = true; |
1078 | DRM_DEBUG("S-video TV connection detected\n"); | 1078 | DRM_DEBUG_KMS("S-video TV connection detected\n"); |
1079 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { | 1079 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
1080 | found = true; | 1080 | found = true; |
1081 | DRM_DEBUG("Composite TV connection detected\n"); | 1081 | DRM_DEBUG_KMS("Composite TV connection detected\n"); |
1082 | } | 1082 | } |
1083 | 1083 | ||
1084 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); | 1084 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
@@ -1141,10 +1141,10 @@ static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, | |||
1141 | tmp = RREG32(RADEON_TV_DAC_CNTL); | 1141 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
1142 | if (tmp & RADEON_TV_DAC_GDACDET) { | 1142 | if (tmp & RADEON_TV_DAC_GDACDET) { |
1143 | found = true; | 1143 | found = true; |
1144 | DRM_DEBUG("S-video TV connection detected\n"); | 1144 | DRM_DEBUG_KMS("S-video TV connection detected\n"); |
1145 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { | 1145 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
1146 | found = true; | 1146 | found = true; |
1147 | DRM_DEBUG("Composite TV connection detected\n"); | 1147 | DRM_DEBUG_KMS("Composite TV connection detected\n"); |
1148 | } | 1148 | } |
1149 | 1149 | ||
1150 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); | 1150 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c index 032040397743..c7b6cb428d09 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c | |||
@@ -496,7 +496,7 @@ static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) | |||
496 | 496 | ||
497 | restart -= v_offset + h_offset; | 497 | restart -= v_offset + h_offset; |
498 | 498 | ||
499 | DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", | 499 | DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", |
500 | const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); | 500 | const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); |
501 | 501 | ||
502 | tv_dac->tv.hrestart = restart % h_total; | 502 | tv_dac->tv.hrestart = restart % h_total; |
@@ -505,7 +505,7 @@ static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) | |||
505 | restart /= v_total; | 505 | restart /= v_total; |
506 | tv_dac->tv.frestart = restart % f_total; | 506 | tv_dac->tv.frestart = restart % f_total; |
507 | 507 | ||
508 | DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n", | 508 | DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", |
509 | (unsigned)tv_dac->tv.frestart, | 509 | (unsigned)tv_dac->tv.frestart, |
510 | (unsigned)tv_dac->tv.vrestart, | 510 | (unsigned)tv_dac->tv.vrestart, |
511 | (unsigned)tv_dac->tv.hrestart); | 511 | (unsigned)tv_dac->tv.hrestart); |
@@ -523,7 +523,7 @@ static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) | |||
523 | tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | | 523 | tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | |
524 | ((u32)h_inc << RADEON_H_INC_SHIFT); | 524 | ((u32)h_inc << RADEON_H_INC_SHIFT); |
525 | 525 | ||
526 | DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); | 526 | DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); |
527 | 527 | ||
528 | return h_changed; | 528 | return h_changed; |
529 | } | 529 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 07579ae2ab68..95f8b3a3c43d 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c | |||
@@ -62,9 +62,9 @@ static int radeon_acpi_event(struct notifier_block *nb, | |||
62 | 62 | ||
63 | if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) { | 63 | if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) { |
64 | if (power_supply_is_system_supplied() > 0) | 64 | if (power_supply_is_system_supplied() > 0) |
65 | DRM_DEBUG("pm: AC\n"); | 65 | DRM_DEBUG_DRIVER("pm: AC\n"); |
66 | else | 66 | else |
67 | DRM_DEBUG("pm: DC\n"); | 67 | DRM_DEBUG_DRIVER("pm: DC\n"); |
68 | 68 | ||
69 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { | 69 | if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
70 | if (rdev->pm.profile == PM_PROFILE_AUTO) { | 70 | if (rdev->pm.profile == PM_PROFILE_AUTO) { |
@@ -198,7 +198,7 @@ static void radeon_set_power_state(struct radeon_device *rdev) | |||
198 | radeon_set_engine_clock(rdev, sclk); | 198 | radeon_set_engine_clock(rdev, sclk); |
199 | radeon_pm_debug_check_in_vbl(rdev, true); | 199 | radeon_pm_debug_check_in_vbl(rdev, true); |
200 | rdev->pm.current_sclk = sclk; | 200 | rdev->pm.current_sclk = sclk; |
201 | DRM_DEBUG("Setting: e: %d\n", sclk); | 201 | DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); |
202 | } | 202 | } |
203 | 203 | ||
204 | /* set memory clock */ | 204 | /* set memory clock */ |
@@ -207,7 +207,7 @@ static void radeon_set_power_state(struct radeon_device *rdev) | |||
207 | radeon_set_memory_clock(rdev, mclk); | 207 | radeon_set_memory_clock(rdev, mclk); |
208 | radeon_pm_debug_check_in_vbl(rdev, true); | 208 | radeon_pm_debug_check_in_vbl(rdev, true); |
209 | rdev->pm.current_mclk = mclk; | 209 | rdev->pm.current_mclk = mclk; |
210 | DRM_DEBUG("Setting: m: %d\n", mclk); | 210 | DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); |
211 | } | 211 | } |
212 | 212 | ||
213 | if (misc_after) | 213 | if (misc_after) |
@@ -219,7 +219,7 @@ static void radeon_set_power_state(struct radeon_device *rdev) | |||
219 | rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; | 219 | rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; |
220 | rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; | 220 | rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; |
221 | } else | 221 | } else |
222 | DRM_DEBUG("pm: GUI not idle!!!\n"); | 222 | DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); |
223 | } | 223 | } |
224 | 224 | ||
225 | static void radeon_pm_set_clocks(struct radeon_device *rdev) | 225 | static void radeon_pm_set_clocks(struct radeon_device *rdev) |
@@ -294,27 +294,27 @@ static void radeon_pm_print_states(struct radeon_device *rdev) | |||
294 | struct radeon_power_state *power_state; | 294 | struct radeon_power_state *power_state; |
295 | struct radeon_pm_clock_info *clock_info; | 295 | struct radeon_pm_clock_info *clock_info; |
296 | 296 | ||
297 | DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states); | 297 | DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); |
298 | for (i = 0; i < rdev->pm.num_power_states; i++) { | 298 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
299 | power_state = &rdev->pm.power_state[i]; | 299 | power_state = &rdev->pm.power_state[i]; |
300 | DRM_DEBUG("State %d: %s\n", i, | 300 | DRM_DEBUG_DRIVER("State %d: %s\n", i, |
301 | radeon_pm_state_type_name[power_state->type]); | 301 | radeon_pm_state_type_name[power_state->type]); |
302 | if (i == rdev->pm.default_power_state_index) | 302 | if (i == rdev->pm.default_power_state_index) |
303 | DRM_DEBUG("\tDefault"); | 303 | DRM_DEBUG_DRIVER("\tDefault"); |
304 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) | 304 | if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) |
305 | DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes); | 305 | DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); |
306 | if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) | 306 | if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
307 | DRM_DEBUG("\tSingle display only\n"); | 307 | DRM_DEBUG_DRIVER("\tSingle display only\n"); |
308 | DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes); | 308 | DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); |
309 | for (j = 0; j < power_state->num_clock_modes; j++) { | 309 | for (j = 0; j < power_state->num_clock_modes; j++) { |
310 | clock_info = &(power_state->clock_info[j]); | 310 | clock_info = &(power_state->clock_info[j]); |
311 | if (rdev->flags & RADEON_IS_IGP) | 311 | if (rdev->flags & RADEON_IS_IGP) |
312 | DRM_DEBUG("\t\t%d e: %d%s\n", | 312 | DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n", |
313 | j, | 313 | j, |
314 | clock_info->sclk * 10, | 314 | clock_info->sclk * 10, |
315 | clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); | 315 | clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); |
316 | else | 316 | else |
317 | DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n", | 317 | DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n", |
318 | j, | 318 | j, |
319 | clock_info->sclk * 10, | 319 | clock_info->sclk * 10, |
320 | clock_info->mclk * 10, | 320 | clock_info->mclk * 10, |
@@ -658,7 +658,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) | |||
658 | radeon_pm_get_dynpm_state(rdev); | 658 | radeon_pm_get_dynpm_state(rdev); |
659 | radeon_pm_set_clocks(rdev); | 659 | radeon_pm_set_clocks(rdev); |
660 | 660 | ||
661 | DRM_DEBUG("radeon: dynamic power management deactivated\n"); | 661 | DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); |
662 | } | 662 | } |
663 | } else if (rdev->pm.active_crtc_count == 1) { | 663 | } else if (rdev->pm.active_crtc_count == 1) { |
664 | /* TODO: Increase clocks if needed for current mode */ | 664 | /* TODO: Increase clocks if needed for current mode */ |
@@ -675,7 +675,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev) | |||
675 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; | 675 | rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
676 | queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work, | 676 | queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work, |
677 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); | 677 | msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); |
678 | DRM_DEBUG("radeon: dynamic power management activated\n"); | 678 | DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); |
679 | } | 679 | } |
680 | } else { /* count == 0 */ | 680 | } else { /* count == 0 */ |
681 | if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { | 681 | if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { |
@@ -771,7 +771,7 @@ static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish | |||
771 | bool in_vbl = radeon_pm_in_vbl(rdev); | 771 | bool in_vbl = radeon_pm_in_vbl(rdev); |
772 | 772 | ||
773 | if (in_vbl == false) | 773 | if (in_vbl == false) |
774 | DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc, | 774 | DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, |
775 | finish ? "exit" : "entry"); | 775 | finish ? "exit" : "entry"); |
776 | return in_vbl; | 776 | return in_vbl; |
777 | } | 777 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index e9918d88f5b0..84c53e41a88f 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -59,28 +59,28 @@ static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) | |||
59 | /* | 59 | /* |
60 | * Global memory. | 60 | * Global memory. |
61 | */ | 61 | */ |
62 | static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref) | 62 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
63 | { | 63 | { |
64 | return ttm_mem_global_init(ref->object); | 64 | return ttm_mem_global_init(ref->object); |
65 | } | 65 | } |
66 | 66 | ||
67 | static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref) | 67 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
68 | { | 68 | { |
69 | ttm_mem_global_release(ref->object); | 69 | ttm_mem_global_release(ref->object); |
70 | } | 70 | } |
71 | 71 | ||
72 | static int radeon_ttm_global_init(struct radeon_device *rdev) | 72 | static int radeon_ttm_global_init(struct radeon_device *rdev) |
73 | { | 73 | { |
74 | struct ttm_global_reference *global_ref; | 74 | struct drm_global_reference *global_ref; |
75 | int r; | 75 | int r; |
76 | 76 | ||
77 | rdev->mman.mem_global_referenced = false; | 77 | rdev->mman.mem_global_referenced = false; |
78 | global_ref = &rdev->mman.mem_global_ref; | 78 | global_ref = &rdev->mman.mem_global_ref; |
79 | global_ref->global_type = TTM_GLOBAL_TTM_MEM; | 79 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
80 | global_ref->size = sizeof(struct ttm_mem_global); | 80 | global_ref->size = sizeof(struct ttm_mem_global); |
81 | global_ref->init = &radeon_ttm_mem_global_init; | 81 | global_ref->init = &radeon_ttm_mem_global_init; |
82 | global_ref->release = &radeon_ttm_mem_global_release; | 82 | global_ref->release = &radeon_ttm_mem_global_release; |
83 | r = ttm_global_item_ref(global_ref); | 83 | r = drm_global_item_ref(global_ref); |
84 | if (r != 0) { | 84 | if (r != 0) { |
85 | DRM_ERROR("Failed setting up TTM memory accounting " | 85 | DRM_ERROR("Failed setting up TTM memory accounting " |
86 | "subsystem.\n"); | 86 | "subsystem.\n"); |
@@ -90,14 +90,14 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) | |||
90 | rdev->mman.bo_global_ref.mem_glob = | 90 | rdev->mman.bo_global_ref.mem_glob = |
91 | rdev->mman.mem_global_ref.object; | 91 | rdev->mman.mem_global_ref.object; |
92 | global_ref = &rdev->mman.bo_global_ref.ref; | 92 | global_ref = &rdev->mman.bo_global_ref.ref; |
93 | global_ref->global_type = TTM_GLOBAL_TTM_BO; | 93 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
94 | global_ref->size = sizeof(struct ttm_bo_global); | 94 | global_ref->size = sizeof(struct ttm_bo_global); |
95 | global_ref->init = &ttm_bo_global_init; | 95 | global_ref->init = &ttm_bo_global_init; |
96 | global_ref->release = &ttm_bo_global_release; | 96 | global_ref->release = &ttm_bo_global_release; |
97 | r = ttm_global_item_ref(global_ref); | 97 | r = drm_global_item_ref(global_ref); |
98 | if (r != 0) { | 98 | if (r != 0) { |
99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | 99 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
100 | ttm_global_item_unref(&rdev->mman.mem_global_ref); | 100 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
101 | return r; | 101 | return r; |
102 | } | 102 | } |
103 | 103 | ||
@@ -108,8 +108,8 @@ static int radeon_ttm_global_init(struct radeon_device *rdev) | |||
108 | static void radeon_ttm_global_fini(struct radeon_device *rdev) | 108 | static void radeon_ttm_global_fini(struct radeon_device *rdev) |
109 | { | 109 | { |
110 | if (rdev->mman.mem_global_referenced) { | 110 | if (rdev->mman.mem_global_referenced) { |
111 | ttm_global_item_unref(&rdev->mman.bo_global_ref.ref); | 111 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
112 | ttm_global_item_unref(&rdev->mman.mem_global_ref); | 112 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
113 | rdev->mman.mem_global_referenced = false; | 113 | rdev->mman.mem_global_referenced = false; |
114 | } | 114 | } |
115 | } | 115 | } |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 index 1e97b2d129fd..b506ec1cab4b 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r300 +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 | |||
@@ -187,7 +187,6 @@ r300 0x4f60 | |||
187 | 0x4364 RS_INST_13 | 187 | 0x4364 RS_INST_13 |
188 | 0x4368 RS_INST_14 | 188 | 0x4368 RS_INST_14 |
189 | 0x436C RS_INST_15 | 189 | 0x436C RS_INST_15 |
190 | 0x43A4 SC_HYPERZ_EN | ||
191 | 0x43A8 SC_EDGERULE | 190 | 0x43A8 SC_EDGERULE |
192 | 0x43B0 SC_CLIP_0_A | 191 | 0x43B0 SC_CLIP_0_A |
193 | 0x43B4 SC_CLIP_0_B | 192 | 0x43B4 SC_CLIP_0_B |
@@ -716,16 +715,4 @@ r300 0x4f60 | |||
716 | 0x4F08 ZB_STENCILREFMASK | 715 | 0x4F08 ZB_STENCILREFMASK |
717 | 0x4F14 ZB_ZTOP | 716 | 0x4F14 ZB_ZTOP |
718 | 0x4F18 ZB_ZCACHE_CTLSTAT | 717 | 0x4F18 ZB_ZCACHE_CTLSTAT |
719 | 0x4F1C ZB_BW_CNTL | ||
720 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
721 | 0x4F30 ZB_ZMASK_OFFSET | ||
722 | 0x4F34 ZB_ZMASK_PITCH | ||
723 | 0x4F38 ZB_ZMASK_WRINDEX | ||
724 | 0x4F3C ZB_ZMASK_DWORD | ||
725 | 0x4F40 ZB_ZMASK_RDINDEX | ||
726 | 0x4F44 ZB_HIZ_OFFSET | ||
727 | 0x4F48 ZB_HIZ_WRINDEX | ||
728 | 0x4F4C ZB_HIZ_DWORD | ||
729 | 0x4F50 ZB_HIZ_RDINDEX | ||
730 | 0x4F54 ZB_HIZ_PITCH | ||
731 | 0x4F58 ZB_ZPASS_DATA | 718 | 0x4F58 ZB_ZPASS_DATA |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420 index e958980d00f1..8c1214c2390f 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r420 +++ b/drivers/gpu/drm/radeon/reg_srcs/r420 | |||
@@ -130,6 +130,7 @@ r420 0x4f60 | |||
130 | 0x401C GB_SELECT | 130 | 0x401C GB_SELECT |
131 | 0x4020 GB_AA_CONFIG | 131 | 0x4020 GB_AA_CONFIG |
132 | 0x4024 GB_FIFO_SIZE | 132 | 0x4024 GB_FIFO_SIZE |
133 | 0x4028 GB_Z_PEQ_CONFIG | ||
133 | 0x4100 TX_INVALTAGS | 134 | 0x4100 TX_INVALTAGS |
134 | 0x4200 GA_POINT_S0 | 135 | 0x4200 GA_POINT_S0 |
135 | 0x4204 GA_POINT_T0 | 136 | 0x4204 GA_POINT_T0 |
@@ -187,7 +188,6 @@ r420 0x4f60 | |||
187 | 0x4364 RS_INST_13 | 188 | 0x4364 RS_INST_13 |
188 | 0x4368 RS_INST_14 | 189 | 0x4368 RS_INST_14 |
189 | 0x436C RS_INST_15 | 190 | 0x436C RS_INST_15 |
190 | 0x43A4 SC_HYPERZ_EN | ||
191 | 0x43A8 SC_EDGERULE | 191 | 0x43A8 SC_EDGERULE |
192 | 0x43B0 SC_CLIP_0_A | 192 | 0x43B0 SC_CLIP_0_A |
193 | 0x43B4 SC_CLIP_0_B | 193 | 0x43B4 SC_CLIP_0_B |
@@ -782,16 +782,4 @@ r420 0x4f60 | |||
782 | 0x4F08 ZB_STENCILREFMASK | 782 | 0x4F08 ZB_STENCILREFMASK |
783 | 0x4F14 ZB_ZTOP | 783 | 0x4F14 ZB_ZTOP |
784 | 0x4F18 ZB_ZCACHE_CTLSTAT | 784 | 0x4F18 ZB_ZCACHE_CTLSTAT |
785 | 0x4F1C ZB_BW_CNTL | ||
786 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
787 | 0x4F30 ZB_ZMASK_OFFSET | ||
788 | 0x4F34 ZB_ZMASK_PITCH | ||
789 | 0x4F38 ZB_ZMASK_WRINDEX | ||
790 | 0x4F3C ZB_ZMASK_DWORD | ||
791 | 0x4F40 ZB_ZMASK_RDINDEX | ||
792 | 0x4F44 ZB_HIZ_OFFSET | ||
793 | 0x4F48 ZB_HIZ_WRINDEX | ||
794 | 0x4F4C ZB_HIZ_DWORD | ||
795 | 0x4F50 ZB_HIZ_RDINDEX | ||
796 | 0x4F54 ZB_HIZ_PITCH | ||
797 | 0x4F58 ZB_ZPASS_DATA | 785 | 0x4F58 ZB_ZPASS_DATA |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 index 83e8bc0c2bb2..0828d80396f2 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rs600 +++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 | |||
@@ -187,7 +187,6 @@ rs600 0x6d40 | |||
187 | 0x4364 RS_INST_13 | 187 | 0x4364 RS_INST_13 |
188 | 0x4368 RS_INST_14 | 188 | 0x4368 RS_INST_14 |
189 | 0x436C RS_INST_15 | 189 | 0x436C RS_INST_15 |
190 | 0x43A4 SC_HYPERZ_EN | ||
191 | 0x43A8 SC_EDGERULE | 190 | 0x43A8 SC_EDGERULE |
192 | 0x43B0 SC_CLIP_0_A | 191 | 0x43B0 SC_CLIP_0_A |
193 | 0x43B4 SC_CLIP_0_B | 192 | 0x43B4 SC_CLIP_0_B |
@@ -782,16 +781,4 @@ rs600 0x6d40 | |||
782 | 0x4F08 ZB_STENCILREFMASK | 781 | 0x4F08 ZB_STENCILREFMASK |
783 | 0x4F14 ZB_ZTOP | 782 | 0x4F14 ZB_ZTOP |
784 | 0x4F18 ZB_ZCACHE_CTLSTAT | 783 | 0x4F18 ZB_ZCACHE_CTLSTAT |
785 | 0x4F1C ZB_BW_CNTL | ||
786 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
787 | 0x4F30 ZB_ZMASK_OFFSET | ||
788 | 0x4F34 ZB_ZMASK_PITCH | ||
789 | 0x4F38 ZB_ZMASK_WRINDEX | ||
790 | 0x4F3C ZB_ZMASK_DWORD | ||
791 | 0x4F40 ZB_ZMASK_RDINDEX | ||
792 | 0x4F44 ZB_HIZ_OFFSET | ||
793 | 0x4F48 ZB_HIZ_WRINDEX | ||
794 | 0x4F4C ZB_HIZ_DWORD | ||
795 | 0x4F50 ZB_HIZ_RDINDEX | ||
796 | 0x4F54 ZB_HIZ_PITCH | ||
797 | 0x4F58 ZB_ZPASS_DATA | 784 | 0x4F58 ZB_ZPASS_DATA |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 index 1e46233985eb..8293855f5f0d 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rv515 +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 | |||
@@ -235,7 +235,6 @@ rv515 0x6d40 | |||
235 | 0x4354 RS_INST_13 | 235 | 0x4354 RS_INST_13 |
236 | 0x4358 RS_INST_14 | 236 | 0x4358 RS_INST_14 |
237 | 0x435C RS_INST_15 | 237 | 0x435C RS_INST_15 |
238 | 0x43A4 SC_HYPERZ_EN | ||
239 | 0x43A8 SC_EDGERULE | 238 | 0x43A8 SC_EDGERULE |
240 | 0x43B0 SC_CLIP_0_A | 239 | 0x43B0 SC_CLIP_0_A |
241 | 0x43B4 SC_CLIP_0_B | 240 | 0x43B4 SC_CLIP_0_B |
@@ -479,17 +478,5 @@ rv515 0x6d40 | |||
479 | 0x4F08 ZB_STENCILREFMASK | 478 | 0x4F08 ZB_STENCILREFMASK |
480 | 0x4F14 ZB_ZTOP | 479 | 0x4F14 ZB_ZTOP |
481 | 0x4F18 ZB_ZCACHE_CTLSTAT | 480 | 0x4F18 ZB_ZCACHE_CTLSTAT |
482 | 0x4F1C ZB_BW_CNTL | ||
483 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
484 | 0x4F30 ZB_ZMASK_OFFSET | ||
485 | 0x4F34 ZB_ZMASK_PITCH | ||
486 | 0x4F38 ZB_ZMASK_WRINDEX | ||
487 | 0x4F3C ZB_ZMASK_DWORD | ||
488 | 0x4F40 ZB_ZMASK_RDINDEX | ||
489 | 0x4F44 ZB_HIZ_OFFSET | ||
490 | 0x4F48 ZB_HIZ_WRINDEX | ||
491 | 0x4F4C ZB_HIZ_DWORD | ||
492 | 0x4F50 ZB_HIZ_RDINDEX | ||
493 | 0x4F54 ZB_HIZ_PITCH | ||
494 | 0x4F58 ZB_ZPASS_DATA | 481 | 0x4F58 ZB_ZPASS_DATA |
495 | 0x4FD4 ZB_STENCILREFMASK_BF | 482 | 0x4FD4 ZB_STENCILREFMASK_BF |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 85cd911952c1..cc05b230d7ef 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -696,7 +696,6 @@ void rs600_mc_init(struct radeon_device *rdev) | |||
696 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | 696 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
697 | base = RREG32_MC(R_000004_MC_FB_LOCATION); | 697 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
698 | base = G_000004_MC_FB_START(base) << 16; | 698 | base = G_000004_MC_FB_START(base) << 16; |
699 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | ||
700 | radeon_vram_location(rdev, &rdev->mc, base); | 699 | radeon_vram_location(rdev, &rdev->mc, base); |
701 | rdev->mc.gtt_base_align = 0; | 700 | rdev->mc.gtt_base_align = 0; |
702 | radeon_gtt_location(rdev, &rdev->mc); | 701 | radeon_gtt_location(rdev, &rdev->mc); |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index f3a8c9344c64..3e3f75718be3 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -159,8 +159,8 @@ void rs690_mc_init(struct radeon_device *rdev) | |||
159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 159 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
160 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); | 160 | base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); |
161 | base = G_000100_MC_FB_START(base) << 16; | 161 | base = G_000100_MC_FB_START(base) << 16; |
162 | rs690_pm_info(rdev); | ||
163 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | 162 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
163 | rs690_pm_info(rdev); | ||
164 | radeon_vram_location(rdev, &rdev->mc, base); | 164 | radeon_vram_location(rdev, &rdev->mc, base); |
165 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; | 165 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
166 | radeon_gtt_location(rdev, &rdev->mc); | 166 | radeon_gtt_location(rdev, &rdev->mc); |
@@ -398,7 +398,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev) | |||
398 | struct drm_display_mode *mode1 = NULL; | 398 | struct drm_display_mode *mode1 = NULL; |
399 | struct rs690_watermark wm0; | 399 | struct rs690_watermark wm0; |
400 | struct rs690_watermark wm1; | 400 | struct rs690_watermark wm1; |
401 | u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; | 401 | u32 tmp; |
402 | u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); | ||
403 | u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); | ||
402 | fixed20_12 priority_mark02, priority_mark12, fill_rate; | 404 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
403 | fixed20_12 a, b; | 405 | fixed20_12 a, b; |
404 | 406 | ||
@@ -495,10 +497,6 @@ void rs690_bandwidth_update(struct radeon_device *rdev) | |||
495 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); | 497 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
496 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | 498 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
497 | } | 499 | } |
498 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | ||
499 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
500 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
501 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
502 | } else if (mode0) { | 500 | } else if (mode0) { |
503 | if (dfixed_trunc(wm0.dbpp) > 64) | 501 | if (dfixed_trunc(wm0.dbpp) > 64) |
504 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); | 502 | a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); |
@@ -528,13 +526,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev) | |||
528 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | 526 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
529 | if (rdev->disp_priority == 2) | 527 | if (rdev->disp_priority == 2) |
530 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); | 528 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
531 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | 529 | } else if (mode1) { |
532 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
533 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, | ||
534 | S_006D48_D2MODE_PRIORITY_A_OFF(1)); | ||
535 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, | ||
536 | S_006D4C_D2MODE_PRIORITY_B_OFF(1)); | ||
537 | } else { | ||
538 | if (dfixed_trunc(wm1.dbpp) > 64) | 530 | if (dfixed_trunc(wm1.dbpp) > 64) |
539 | a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); | 531 | a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); |
540 | else | 532 | else |
@@ -563,13 +555,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev) | |||
563 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | 555 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
564 | if (rdev->disp_priority == 2) | 556 | if (rdev->disp_priority == 2) |
565 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); | 557 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
566 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, | ||
567 | S_006548_D1MODE_PRIORITY_A_OFF(1)); | ||
568 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, | ||
569 | S_00654C_D1MODE_PRIORITY_B_OFF(1)); | ||
570 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
571 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
572 | } | 558 | } |
559 | |||
560 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | ||
561 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
562 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
563 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
573 | } | 564 | } |
574 | 565 | ||
575 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) | 566 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index b951b8790175..4d6e86041a9f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -927,7 +927,9 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
927 | struct drm_display_mode *mode1 = NULL; | 927 | struct drm_display_mode *mode1 = NULL; |
928 | struct rv515_watermark wm0; | 928 | struct rv515_watermark wm0; |
929 | struct rv515_watermark wm1; | 929 | struct rv515_watermark wm1; |
930 | u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; | 930 | u32 tmp; |
931 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; | ||
932 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; | ||
931 | fixed20_12 priority_mark02, priority_mark12, fill_rate; | 933 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
932 | fixed20_12 a, b; | 934 | fixed20_12 a, b; |
933 | 935 | ||
@@ -1001,10 +1003,6 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
1001 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1003 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1002 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1004 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1003 | } | 1005 | } |
1004 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | ||
1005 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
1006 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
1007 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
1008 | } else if (mode0) { | 1006 | } else if (mode0) { |
1009 | if (dfixed_trunc(wm0.dbpp) > 64) | 1007 | if (dfixed_trunc(wm0.dbpp) > 64) |
1010 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); | 1008 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
@@ -1034,11 +1032,7 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
1034 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | 1032 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1035 | if (rdev->disp_priority == 2) | 1033 | if (rdev->disp_priority == 2) |
1036 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1034 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1037 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | 1035 | } else if (mode1) { |
1038 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
1039 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
1040 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
1041 | } else { | ||
1042 | if (dfixed_trunc(wm1.dbpp) > 64) | 1036 | if (dfixed_trunc(wm1.dbpp) > 64) |
1043 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); | 1037 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
1044 | else | 1038 | else |
@@ -1067,11 +1061,12 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
1067 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | 1061 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1068 | if (rdev->disp_priority == 2) | 1062 | if (rdev->disp_priority == 2) |
1069 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1063 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1070 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
1071 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
1072 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
1073 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
1074 | } | 1064 | } |
1065 | |||
1066 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | ||
1067 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
1068 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
1069 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
1075 | } | 1070 | } |
1076 | 1071 | ||
1077 | void rv515_bandwidth_update(struct radeon_device *rdev) | 1072 | void rv515_bandwidth_update(struct radeon_device *rdev) |
diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index 4256e2006476..b256d4adfafe 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile | |||
@@ -3,7 +3,7 @@ | |||
3 | 3 | ||
4 | ccflags-y := -Iinclude/drm | 4 | ccflags-y := -Iinclude/drm |
5 | ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \ | 5 | ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \ |
6 | ttm_bo_util.o ttm_bo_vm.o ttm_module.o ttm_global.o \ | 6 | ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ |
7 | ttm_object.o ttm_lock.o ttm_execbuf_util.o ttm_page_alloc.o | 7 | ttm_object.o ttm_lock.o ttm_execbuf_util.o ttm_page_alloc.o |
8 | 8 | ||
9 | obj-$(CONFIG_DRM_TTM) += ttm.o | 9 | obj-$(CONFIG_DRM_TTM) += ttm.o |
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 9763288c6b2d..cb4cf7ef4d1e 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c | |||
@@ -1395,7 +1395,7 @@ static void ttm_bo_global_kobj_release(struct kobject *kobj) | |||
1395 | kfree(glob); | 1395 | kfree(glob); |
1396 | } | 1396 | } |
1397 | 1397 | ||
1398 | void ttm_bo_global_release(struct ttm_global_reference *ref) | 1398 | void ttm_bo_global_release(struct drm_global_reference *ref) |
1399 | { | 1399 | { |
1400 | struct ttm_bo_global *glob = ref->object; | 1400 | struct ttm_bo_global *glob = ref->object; |
1401 | 1401 | ||
@@ -1404,7 +1404,7 @@ void ttm_bo_global_release(struct ttm_global_reference *ref) | |||
1404 | } | 1404 | } |
1405 | EXPORT_SYMBOL(ttm_bo_global_release); | 1405 | EXPORT_SYMBOL(ttm_bo_global_release); |
1406 | 1406 | ||
1407 | int ttm_bo_global_init(struct ttm_global_reference *ref) | 1407 | int ttm_bo_global_init(struct drm_global_reference *ref) |
1408 | { | 1408 | { |
1409 | struct ttm_bo_global_ref *bo_ref = | 1409 | struct ttm_bo_global_ref *bo_ref = |
1410 | container_of(ref, struct ttm_bo_global_ref, ref); | 1410 | container_of(ref, struct ttm_bo_global_ref, ref); |
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index 9a6edbfeaa9e..902d7cf9fb4e 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c | |||
@@ -70,8 +70,6 @@ static int __init ttm_init(void) | |||
70 | if (unlikely(ret != 0)) | 70 | if (unlikely(ret != 0)) |
71 | return ret; | 71 | return ret; |
72 | 72 | ||
73 | ttm_global_init(); | ||
74 | |||
75 | atomic_set(&device_released, 0); | 73 | atomic_set(&device_released, 0); |
76 | ret = drm_class_device_register(&ttm_drm_class_device); | 74 | ret = drm_class_device_register(&ttm_drm_class_device); |
77 | if (unlikely(ret != 0)) | 75 | if (unlikely(ret != 0)) |
@@ -81,7 +79,6 @@ static int __init ttm_init(void) | |||
81 | out_no_dev_reg: | 79 | out_no_dev_reg: |
82 | atomic_set(&device_released, 1); | 80 | atomic_set(&device_released, 1); |
83 | wake_up_all(&exit_q); | 81 | wake_up_all(&exit_q); |
84 | ttm_global_release(); | ||
85 | return ret; | 82 | return ret; |
86 | } | 83 | } |
87 | 84 | ||
@@ -95,7 +92,6 @@ static void __exit ttm_exit(void) | |||
95 | */ | 92 | */ |
96 | 93 | ||
97 | wait_event(exit_q, atomic_read(&device_released) == 1); | 94 | wait_event(exit_q, atomic_read(&device_released) == 1); |
98 | ttm_global_release(); | ||
99 | } | 95 | } |
100 | 96 | ||
101 | module_init(ttm_init); | 97 | module_init(ttm_init); |
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index eaad52095339..429f917b60bf 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h | |||
@@ -164,7 +164,7 @@ struct vmw_vga_topology_state { | |||
164 | struct vmw_private { | 164 | struct vmw_private { |
165 | struct ttm_bo_device bdev; | 165 | struct ttm_bo_device bdev; |
166 | struct ttm_bo_global_ref bo_global_ref; | 166 | struct ttm_bo_global_ref bo_global_ref; |
167 | struct ttm_global_reference mem_global_ref; | 167 | struct drm_global_reference mem_global_ref; |
168 | 168 | ||
169 | struct vmw_fifo_state fifo; | 169 | struct vmw_fifo_state fifo; |
170 | 170 | ||
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c index e3df4adfb4d8..83123287c60c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c | |||
@@ -44,29 +44,29 @@ int vmw_mmap(struct file *filp, struct vm_area_struct *vma) | |||
44 | return ttm_bo_mmap(filp, vma, &dev_priv->bdev); | 44 | return ttm_bo_mmap(filp, vma, &dev_priv->bdev); |
45 | } | 45 | } |
46 | 46 | ||
47 | static int vmw_ttm_mem_global_init(struct ttm_global_reference *ref) | 47 | static int vmw_ttm_mem_global_init(struct drm_global_reference *ref) |
48 | { | 48 | { |
49 | DRM_INFO("global init.\n"); | 49 | DRM_INFO("global init.\n"); |
50 | return ttm_mem_global_init(ref->object); | 50 | return ttm_mem_global_init(ref->object); |
51 | } | 51 | } |
52 | 52 | ||
53 | static void vmw_ttm_mem_global_release(struct ttm_global_reference *ref) | 53 | static void vmw_ttm_mem_global_release(struct drm_global_reference *ref) |
54 | { | 54 | { |
55 | ttm_mem_global_release(ref->object); | 55 | ttm_mem_global_release(ref->object); |
56 | } | 56 | } |
57 | 57 | ||
58 | int vmw_ttm_global_init(struct vmw_private *dev_priv) | 58 | int vmw_ttm_global_init(struct vmw_private *dev_priv) |
59 | { | 59 | { |
60 | struct ttm_global_reference *global_ref; | 60 | struct drm_global_reference *global_ref; |
61 | int ret; | 61 | int ret; |
62 | 62 | ||
63 | global_ref = &dev_priv->mem_global_ref; | 63 | global_ref = &dev_priv->mem_global_ref; |
64 | global_ref->global_type = TTM_GLOBAL_TTM_MEM; | 64 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
65 | global_ref->size = sizeof(struct ttm_mem_global); | 65 | global_ref->size = sizeof(struct ttm_mem_global); |
66 | global_ref->init = &vmw_ttm_mem_global_init; | 66 | global_ref->init = &vmw_ttm_mem_global_init; |
67 | global_ref->release = &vmw_ttm_mem_global_release; | 67 | global_ref->release = &vmw_ttm_mem_global_release; |
68 | 68 | ||
69 | ret = ttm_global_item_ref(global_ref); | 69 | ret = drm_global_item_ref(global_ref); |
70 | if (unlikely(ret != 0)) { | 70 | if (unlikely(ret != 0)) { |
71 | DRM_ERROR("Failed setting up TTM memory accounting.\n"); | 71 | DRM_ERROR("Failed setting up TTM memory accounting.\n"); |
72 | return ret; | 72 | return ret; |
@@ -75,11 +75,11 @@ int vmw_ttm_global_init(struct vmw_private *dev_priv) | |||
75 | dev_priv->bo_global_ref.mem_glob = | 75 | dev_priv->bo_global_ref.mem_glob = |
76 | dev_priv->mem_global_ref.object; | 76 | dev_priv->mem_global_ref.object; |
77 | global_ref = &dev_priv->bo_global_ref.ref; | 77 | global_ref = &dev_priv->bo_global_ref.ref; |
78 | global_ref->global_type = TTM_GLOBAL_TTM_BO; | 78 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
79 | global_ref->size = sizeof(struct ttm_bo_global); | 79 | global_ref->size = sizeof(struct ttm_bo_global); |
80 | global_ref->init = &ttm_bo_global_init; | 80 | global_ref->init = &ttm_bo_global_init; |
81 | global_ref->release = &ttm_bo_global_release; | 81 | global_ref->release = &ttm_bo_global_release; |
82 | ret = ttm_global_item_ref(global_ref); | 82 | ret = drm_global_item_ref(global_ref); |
83 | 83 | ||
84 | if (unlikely(ret != 0)) { | 84 | if (unlikely(ret != 0)) { |
85 | DRM_ERROR("Failed setting up TTM buffer objects.\n"); | 85 | DRM_ERROR("Failed setting up TTM buffer objects.\n"); |
@@ -88,12 +88,12 @@ int vmw_ttm_global_init(struct vmw_private *dev_priv) | |||
88 | 88 | ||
89 | return 0; | 89 | return 0; |
90 | out_no_bo: | 90 | out_no_bo: |
91 | ttm_global_item_unref(&dev_priv->mem_global_ref); | 91 | drm_global_item_unref(&dev_priv->mem_global_ref); |
92 | return ret; | 92 | return ret; |
93 | } | 93 | } |
94 | 94 | ||
95 | void vmw_ttm_global_release(struct vmw_private *dev_priv) | 95 | void vmw_ttm_global_release(struct vmw_private *dev_priv) |
96 | { | 96 | { |
97 | ttm_global_item_unref(&dev_priv->bo_global_ref.ref); | 97 | drm_global_item_unref(&dev_priv->bo_global_ref.ref); |
98 | ttm_global_item_unref(&dev_priv->mem_global_ref); | 98 | drm_global_item_unref(&dev_priv->mem_global_ref); |
99 | } | 99 | } |