134 files changed, 8475 insertions, 1529 deletions

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 5b1cb7e73ee8..8e7fa4dbaed8 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -192,6 +192,8 @@ source "drivers/gpu/drm/tilcdc/Kconfig"
 
 source "drivers/gpu/drm/qxl/Kconfig"
 
+source "drivers/gpu/drm/bochs/Kconfig"
+
 source "drivers/gpu/drm/msm/Kconfig"
 
 source "drivers/gpu/drm/tegra/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index d1a5c7277678..292a79d64146 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
 obj-$(CONFIG_DRM_OMAP)  += omapdrm/
 obj-$(CONFIG_DRM_TILCDC)        += tilcdc/
 obj-$(CONFIG_DRM_QXL) += qxl/
+obj-$(CONFIG_DRM_BOCHS) += bochs/
 obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-y                   += i2c/
diff --git a/drivers/gpu/drm/bochs/Kconfig b/drivers/gpu/drm/bochs/Kconfig
new file mode 100644
index 000000000000..c8fcf12019f0
--- /dev/null
+++ b/drivers/gpu/drm/bochs/Kconfig
@@ -0,0 +1,11 @@
+config DRM_BOCHS
+        tristate "DRM Support for bochs dispi vga interface (qemu stdvga)"
+        depends on DRM && PCI
+        select DRM_KMS_HELPER
+        select FB_SYS_FILLRECT
+        select FB_SYS_COPYAREA
+        select FB_SYS_IMAGEBLIT
+        select DRM_TTM
+        help
+          Choose this option for qemu.
+          If M is selected the module will be called bochs-drm.
diff --git a/drivers/gpu/drm/bochs/Makefile b/drivers/gpu/drm/bochs/Makefile
new file mode 100644
index 000000000000..844a55614920
--- /dev/null
+++ b/drivers/gpu/drm/bochs/Makefile
@@ -0,0 +1,4 @@
+ccflags-y := -Iinclude/drm
+bochs-drm-y := bochs_drv.o bochs_mm.o bochs_kms.o bochs_fbdev.o bochs_hw.o
+
+obj-$(CONFIG_DRM_BOCHS) += bochs-drm.o
diff --git a/drivers/gpu/drm/bochs/bochs.h b/drivers/gpu/drm/bochs/bochs.h
new file mode 100644
index 000000000000..741965c001a6
--- /dev/null
+++ b/drivers/gpu/drm/bochs/bochs.h
@@ -0,0 +1,164 @@
+#include <linux/io.h>
+#include <linux/fb.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
+
+#include <ttm/ttm_bo_driver.h>
+#include <ttm/ttm_page_alloc.h>
+
+/* ---------------------------------------------------------------------- */
+
+#define VBE_DISPI_IOPORT_INDEX           0x01CE
+#define VBE_DISPI_IOPORT_DATA            0x01CF
+
+#define VBE_DISPI_INDEX_ID               0x0
+#define VBE_DISPI_INDEX_XRES             0x1
+#define VBE_DISPI_INDEX_YRES             0x2
+#define VBE_DISPI_INDEX_BPP              0x3
+#define VBE_DISPI_INDEX_ENABLE           0x4
+#define VBE_DISPI_INDEX_BANK             0x5
+#define VBE_DISPI_INDEX_VIRT_WIDTH       0x6
+#define VBE_DISPI_INDEX_VIRT_HEIGHT      0x7
+#define VBE_DISPI_INDEX_X_OFFSET         0x8
+#define VBE_DISPI_INDEX_Y_OFFSET         0x9
+#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa
+
+#define VBE_DISPI_ID0                    0xB0C0
+#define VBE_DISPI_ID1                    0xB0C1
+#define VBE_DISPI_ID2                    0xB0C2
+#define VBE_DISPI_ID3                    0xB0C3
+#define VBE_DISPI_ID4                    0xB0C4
+#define VBE_DISPI_ID5                    0xB0C5
+
+#define VBE_DISPI_DISABLED               0x00
+#define VBE_DISPI_ENABLED                0x01
+#define VBE_DISPI_GETCAPS                0x02
+#define VBE_DISPI_8BIT_DAC               0x20
+#define VBE_DISPI_LFB_ENABLED            0x40
+#define VBE_DISPI_NOCLEARMEM             0x80
+
+/* ---------------------------------------------------------------------- */
+
+enum bochs_types {
+        BOCHS_QEMU_STDVGA,
+        BOCHS_UNKNOWN,
+};
+
+struct bochs_framebuffer {
+        struct drm_framebuffer base;
+        struct drm_gem_object *obj;
+};
+
+struct bochs_device {
+        /* hw */
+        void __iomem   *mmio;
+        int            ioports;
+        void __iomem   *fb_map;
+        unsigned long  fb_base;
+        unsigned long  fb_size;
+
+        /* mode */
+        u16 xres;
+        u16 yres;
+        u16 yres_virtual;
+        u32 stride;
+        u32 bpp;
+
+        /* drm */
+        struct drm_device  *dev;
+        struct drm_crtc crtc;
+        struct drm_encoder encoder;
+        struct drm_connector connector;
+        bool mode_config_initialized;
+
+        /* ttm */
+        struct {
+                struct drm_global_reference mem_global_ref;
+                struct ttm_bo_global_ref bo_global_ref;
+                struct ttm_bo_device bdev;
+                bool initialized;
+        } ttm;
+
+        /* fbdev */
+        struct {
+                struct bochs_framebuffer gfb;
+                struct drm_fb_helper helper;
+                int size;
+                int x1, y1, x2, y2; /* dirty rect */
+                spinlock_t dirty_lock;
+                bool initialized;
+        } fb;
+};
+
+#define to_bochs_framebuffer(x) container_of(x, struct bochs_framebuffer, base)
+
+struct bochs_bo {
+        struct ttm_buffer_object bo;
+        struct ttm_placement placement;
+        struct ttm_bo_kmap_obj kmap;
+        struct drm_gem_object gem;
+        u32 placements[3];
+        int pin_count;
+};
+
+static inline struct bochs_bo *bochs_bo(struct ttm_buffer_object *bo)
+{
+        return container_of(bo, struct bochs_bo, bo);
+}
+
+static inline struct bochs_bo *gem_to_bochs_bo(struct drm_gem_object *gem)
+{
+        return container_of(gem, struct bochs_bo, gem);
+}
+
+#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
+
+static inline u64 bochs_bo_mmap_offset(struct bochs_bo *bo)
+{
+        return drm_vma_node_offset_addr(&bo->bo.vma_node);
+}
+
+/* ---------------------------------------------------------------------- */
+
+/* bochs_hw.c */
+int bochs_hw_init(struct drm_device *dev, uint32_t flags);
+void bochs_hw_fini(struct drm_device *dev);
+
+void bochs_hw_setmode(struct bochs_device *bochs,
+                      struct drm_display_mode *mode);
+void bochs_hw_setbase(struct bochs_device *bochs,
+                      int x, int y, u64 addr);
+
+/* bochs_mm.c */
+int bochs_mm_init(struct bochs_device *bochs);
+void bochs_mm_fini(struct bochs_device *bochs);
+int bochs_mmap(struct file *filp, struct vm_area_struct *vma);
+
+int bochs_gem_create(struct drm_device *dev, u32 size, bool iskernel,
+                     struct drm_gem_object **obj);
+int bochs_gem_init_object(struct drm_gem_object *obj);
+void bochs_gem_free_object(struct drm_gem_object *obj);
+int bochs_dumb_create(struct drm_file *file, struct drm_device *dev,
+                      struct drm_mode_create_dumb *args);
+int bochs_dumb_mmap_offset(struct drm_file *file, struct drm_device *dev,
+                           uint32_t handle, uint64_t *offset);
+
+int bochs_framebuffer_init(struct drm_device *dev,
+                           struct bochs_framebuffer *gfb,
+                           struct drm_mode_fb_cmd2 *mode_cmd,
+                           struct drm_gem_object *obj);
+int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr);
+int bochs_bo_unpin(struct bochs_bo *bo);
+
+extern const struct drm_mode_config_funcs bochs_mode_funcs;
+
+/* bochs_kms.c */
+int bochs_kms_init(struct bochs_device *bochs);
+void bochs_kms_fini(struct bochs_device *bochs);
+
+/* bochs_fbdev.c */
+int bochs_fbdev_init(struct bochs_device *bochs);
+void bochs_fbdev_fini(struct bochs_device *bochs);
diff --git a/drivers/gpu/drm/bochs/bochs_drv.c b/drivers/gpu/drm/bochs/bochs_drv.c
new file mode 100644
index 000000000000..395bba261c9a
--- /dev/null
+++ b/drivers/gpu/drm/bochs/bochs_drv.c
@@ -0,0 +1,178 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "bochs.h"
+
+static bool enable_fbdev = true;
+module_param_named(fbdev, enable_fbdev, bool, 0444);
+MODULE_PARM_DESC(fbdev, "register fbdev device");
+
+/* ---------------------------------------------------------------------- */
+/* drm interface                                                          */
+
+static int bochs_unload(struct drm_device *dev)
+{
+        struct bochs_device *bochs = dev->dev_private;
+
+        bochs_fbdev_fini(bochs);
+        bochs_kms_fini(bochs);
+        bochs_mm_fini(bochs);
+        bochs_hw_fini(dev);
+        kfree(bochs);
+        dev->dev_private = NULL;
+        return 0;
+}
+
+static int bochs_load(struct drm_device *dev, unsigned long flags)
+{
+        struct bochs_device *bochs;
+        int ret;
+
+        bochs = kzalloc(sizeof(*bochs), GFP_KERNEL);
+        if (bochs == NULL)
+                return -ENOMEM;
+        dev->dev_private = bochs;
+        bochs->dev = dev;
+
+        ret = bochs_hw_init(dev, flags);
+        if (ret)
+                goto err;
+
+        ret = bochs_mm_init(bochs);
+        if (ret)
+                goto err;
+
+        ret = bochs_kms_init(bochs);
+        if (ret)
+                goto err;
+
+        if (enable_fbdev)
+                bochs_fbdev_init(bochs);
+
+        return 0;
+
+err:
+        bochs_unload(dev);
+        return ret;
+}
+
+static const struct file_operations bochs_fops = {
+        .owner          = THIS_MODULE,
+        .open           = drm_open,
+        .release        = drm_release,
+        .unlocked_ioctl = drm_ioctl,
+#ifdef CONFIG_COMPAT
+        .compat_ioctl   = drm_compat_ioctl,
+#endif
+        .poll           = drm_poll,
+        .read           = drm_read,
+        .llseek         = no_llseek,
+        .mmap           = bochs_mmap,
+};
+
+static struct drm_driver bochs_driver = {
+        .driver_features        = DRIVER_GEM | DRIVER_MODESET,
+        .load                   = bochs_load,
+        .unload                 = bochs_unload,
+        .fops                   = &bochs_fops,
+        .name                   = "bochs-drm",
+        .desc                   = "bochs dispi vga interface (qemu stdvga)",
+        .date                   = "20130925",
+        .major                  = 1,
+        .minor                  = 0,
+        .gem_free_object        = bochs_gem_free_object,
+        .dumb_create            = bochs_dumb_create,
+        .dumb_map_offset        = bochs_dumb_mmap_offset,
+        .dumb_destroy           = drm_gem_dumb_destroy,
+};
+
+/* ---------------------------------------------------------------------- */
+/* pci interface                                                          */
+
+static int bochs_kick_out_firmware_fb(struct pci_dev *pdev)
+{
+        struct apertures_struct *ap;
+
+        ap = alloc_apertures(1);
+        if (!ap)
+                return -ENOMEM;
+
+        ap->ranges[0].base = pci_resource_start(pdev, 0);
+        ap->ranges[0].size = pci_resource_len(pdev, 0);
+        remove_conflicting_framebuffers(ap, "bochsdrmfb", false);
+        kfree(ap);
+
+        return 0;
+}
+
+static int bochs_pci_probe(struct pci_dev *pdev,
+                           const struct pci_device_id *ent)
+{
+        int ret;
+
+        ret = bochs_kick_out_firmware_fb(pdev);
+        if (ret)
+                return ret;
+
+        return drm_get_pci_dev(pdev, ent, &bochs_driver);
+}
+
+static void bochs_pci_remove(struct pci_dev *pdev)
+{
+        struct drm_device *dev = pci_get_drvdata(pdev);
+
+        drm_put_dev(dev);
+}
+
+static DEFINE_PCI_DEVICE_TABLE(bochs_pci_tbl) = {
+        {
+                .vendor      = 0x1234,
+                .device      = 0x1111,
+                .subvendor   = 0x1af4,
+                .subdevice   = 0x1100,
+                .driver_data = BOCHS_QEMU_STDVGA,
+        },
+        {
+                .vendor      = 0x1234,
+                .device      = 0x1111,
+                .subvendor   = PCI_ANY_ID,
+                .subdevice   = PCI_ANY_ID,
+                .driver_data = BOCHS_UNKNOWN,
+        },
+        { /* end of list */ }
+};
+
+static struct pci_driver bochs_pci_driver = {
+        .name =         "bochs-drm",
+        .id_table =     bochs_pci_tbl,
+        .probe =        bochs_pci_probe,
+        .remove =       bochs_pci_remove,
+};
+
+/* ---------------------------------------------------------------------- */
+/* module init/exit                                                       */
+
+static int __init bochs_init(void)
+{
+        return drm_pci_init(&bochs_driver, &bochs_pci_driver);
+}
+
+static void __exit bochs_exit(void)
+{
+        drm_pci_exit(&bochs_driver, &bochs_pci_driver);
+}
+
+module_init(bochs_init);
+module_exit(bochs_exit);
+
+MODULE_DEVICE_TABLE(pci, bochs_pci_tbl);
+MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/bochs/bochs_fbdev.c b/drivers/gpu/drm/bochs/bochs_fbdev.c
new file mode 100644
index 000000000000..4da5206b7cc9
--- /dev/null
+++ b/drivers/gpu/drm/bochs/bochs_fbdev.c
@@ -0,0 +1,215 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "bochs.h"
+
+/* ---------------------------------------------------------------------- */
+
+static struct fb_ops bochsfb_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = drm_fb_helper_check_var,
+        .fb_set_par = drm_fb_helper_set_par,
+        .fb_fillrect = sys_fillrect,
+        .fb_copyarea = sys_copyarea,
+        .fb_imageblit = sys_imageblit,
+        .fb_pan_display = drm_fb_helper_pan_display,
+        .fb_blank = drm_fb_helper_blank,
+        .fb_setcmap = drm_fb_helper_setcmap,
+};
+
+static int bochsfb_create_object(struct bochs_device *bochs,
+                                 struct drm_mode_fb_cmd2 *mode_cmd,
+                                 struct drm_gem_object **gobj_p)
+{
+        struct drm_device *dev = bochs->dev;
+        struct drm_gem_object *gobj;
+        u32 size;
+        int ret = 0;
+
+        size = mode_cmd->pitches[0] * mode_cmd->height;
+        ret = bochs_gem_create(dev, size, true, &gobj);
+        if (ret)
+                return ret;
+
+        *gobj_p = gobj;
+        return ret;
+}
+
+static int bochsfb_create(struct drm_fb_helper *helper,
+                          struct drm_fb_helper_surface_size *sizes)
+{
+        struct bochs_device *bochs =
+                container_of(helper, struct bochs_device, fb.helper);
+        struct drm_device *dev = bochs->dev;
+        struct fb_info *info;
+        struct drm_framebuffer *fb;
+        struct drm_mode_fb_cmd2 mode_cmd;
+        struct device *device = &dev->pdev->dev;
+        struct drm_gem_object *gobj = NULL;
+        struct bochs_bo *bo = NULL;
+        int size, ret;
+
+        if (sizes->surface_bpp != 32)
+                return -EINVAL;
+
+        mode_cmd.width = sizes->surface_width;
+        mode_cmd.height = sizes->surface_height;
+        mode_cmd.pitches[0] = mode_cmd.width * ((sizes->surface_bpp + 7) / 8);
+        mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
+                                                          sizes->surface_depth);
+        size = mode_cmd.pitches[0] * mode_cmd.height;
+
+        /* alloc, pin & map bo */
+        ret = bochsfb_create_object(bochs, &mode_cmd, &gobj);
+        if (ret) {
+                DRM_ERROR("failed to create fbcon backing object %d\n", ret);
+                return ret;
+        }
+
+        bo = gem_to_bochs_bo(gobj);
+
+        ret = ttm_bo_reserve(&bo->bo, true, false, false, 0);
+        if (ret)
+                return ret;
+
+        ret = bochs_bo_pin(bo, TTM_PL_FLAG_VRAM, NULL);
+        if (ret) {
+                DRM_ERROR("failed to pin fbcon\n");
+                ttm_bo_unreserve(&bo->bo);
+                return ret;
+        }
+
+        ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages,
+                          &bo->kmap);
+        if (ret) {
+                DRM_ERROR("failed to kmap fbcon\n");
+                ttm_bo_unreserve(&bo->bo);
+                return ret;
+        }
+
+        ttm_bo_unreserve(&bo->bo);
+
+        /* init fb device */
+        info = framebuffer_alloc(0, device);
+        if (info == NULL)
+                return -ENOMEM;
+
+        info->par = &bochs->fb.helper;
+
+        ret = bochs_framebuffer_init(bochs->dev, &bochs->fb.gfb, &mode_cmd, gobj);
+        if (ret)
+                return ret;
+
+        bochs->fb.size = size;
+
+        /* setup helper */
+        fb = &bochs->fb.gfb.base;
+        bochs->fb.helper.fb = fb;
+        bochs->fb.helper.fbdev = info;
+
+        strcpy(info->fix.id, "bochsdrmfb");
+
+        info->flags = FBINFO_DEFAULT;
+        info->fbops = &bochsfb_ops;
+
+        drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
+        drm_fb_helper_fill_var(info, &bochs->fb.helper, sizes->fb_width,
+                               sizes->fb_height);
+
+        info->screen_base = bo->kmap.virtual;
+        info->screen_size = size;
+
+#if 0
+        /* FIXME: get this right for mmap(/dev/fb0) */
+        info->fix.smem_start = bochs_bo_mmap_offset(bo);
+        info->fix.smem_len = size;
+#endif
+
+        ret = fb_alloc_cmap(&info->cmap, 256, 0);
+        if (ret) {
+                DRM_ERROR("%s: can't allocate color map\n", info->fix.id);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+static int bochs_fbdev_destroy(struct bochs_device *bochs)
+{
+        struct bochs_framebuffer *gfb = &bochs->fb.gfb;
+        struct fb_info *info;
+
+        DRM_DEBUG_DRIVER("\n");
+
+        if (bochs->fb.helper.fbdev) {
+                info = bochs->fb.helper.fbdev;
+
+                unregister_framebuffer(info);
+                if (info->cmap.len)
+                        fb_dealloc_cmap(&info->cmap);
+                framebuffer_release(info);
+        }
+
+        if (gfb->obj) {
+                drm_gem_object_unreference_unlocked(gfb->obj);
+                gfb->obj = NULL;
+        }
+
+        drm_fb_helper_fini(&bochs->fb.helper);
+        drm_framebuffer_unregister_private(&gfb->base);
+        drm_framebuffer_cleanup(&gfb->base);
+
+        return 0;
+}
+
+void bochs_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
+                        u16 blue, int regno)
+{
+}
+
+void bochs_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+                        u16 *blue, int regno)
+{
+        *red   = regno;
+        *green = regno;
+        *blue  = regno;
+}
+
+static struct drm_fb_helper_funcs bochs_fb_helper_funcs = {
+        .gamma_set = bochs_fb_gamma_set,
+        .gamma_get = bochs_fb_gamma_get,
+        .fb_probe = bochsfb_create,
+};
+
+int bochs_fbdev_init(struct bochs_device *bochs)
+{
+        int ret;
+
+        bochs->fb.helper.funcs = &bochs_fb_helper_funcs;
+        spin_lock_init(&bochs->fb.dirty_lock);
+
+        ret = drm_fb_helper_init(bochs->dev, &bochs->fb.helper,
+                                 1, 1);
+        if (ret)
+                return ret;
+
+        drm_fb_helper_single_add_all_connectors(&bochs->fb.helper);
+        drm_helper_disable_unused_functions(bochs->dev);
+        drm_fb_helper_initial_config(&bochs->fb.helper, 32);
+
+        bochs->fb.initialized = true;
+        return 0;
+}
+
+void bochs_fbdev_fini(struct bochs_device *bochs)
+{
+        if (!bochs->fb.initialized)
+                return;
+
+        bochs_fbdev_destroy(bochs);
+        bochs->fb.initialized = false;
+}
diff --git a/drivers/gpu/drm/bochs/bochs_hw.c b/drivers/gpu/drm/bochs/bochs_hw.c
new file mode 100644
index 000000000000..dbe619e6aab4
--- /dev/null
+++ b/drivers/gpu/drm/bochs/bochs_hw.c
@@ -0,0 +1,177 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "bochs.h"
+
+/* ---------------------------------------------------------------------- */
+
+static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
+{
+        if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
+                return;
+
+        if (bochs->mmio) {
+                int offset = ioport - 0x3c0 + 0x400;
+                writeb(val, bochs->mmio + offset);
+        } else {
+                outb(val, ioport);
+        }
+}
+
+static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
+{
+        u16 ret = 0;
+
+        if (bochs->mmio) {
+                int offset = 0x500 + (reg << 1);
+                ret = readw(bochs->mmio + offset);
+        } else {
+                outw(reg, VBE_DISPI_IOPORT_INDEX);
+                ret = inw(VBE_DISPI_IOPORT_DATA);
+        }
+        return ret;
+}
+
+static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
+{
+        if (bochs->mmio) {
+                int offset = 0x500 + (reg << 1);
+                writew(val, bochs->mmio + offset);
+        } else {
+                outw(reg, VBE_DISPI_IOPORT_INDEX);
+                outw(val, VBE_DISPI_IOPORT_DATA);
+        }
+}
+
+int bochs_hw_init(struct drm_device *dev, uint32_t flags)
+{
+        struct bochs_device *bochs = dev->dev_private;
+        struct pci_dev *pdev = dev->pdev;
+        unsigned long addr, size, mem, ioaddr, iosize;
+        u16 id;
+
+        if (/* (ent->driver_data == BOCHS_QEMU_STDVGA) && */
+            (pdev->resource[2].flags & IORESOURCE_MEM)) {
+                /* mmio bar with vga and bochs registers present */
+                if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
+                        DRM_ERROR("Cannot request mmio region\n");
+                        return -EBUSY;
+                }
+                ioaddr = pci_resource_start(pdev, 2);
+                iosize = pci_resource_len(pdev, 2);
+                bochs->mmio = ioremap(ioaddr, iosize);
+                if (bochs->mmio == NULL) {
+                        DRM_ERROR("Cannot map mmio region\n");
+                        return -ENOMEM;
+                }
+        } else {
+                ioaddr = VBE_DISPI_IOPORT_INDEX;
+                iosize = 2;
+                if (!request_region(ioaddr, iosize, "bochs-drm")) {
+                        DRM_ERROR("Cannot request ioports\n");
+                        return -EBUSY;
+                }
+                bochs->ioports = 1;
+        }
+
+        id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
+        mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
+                * 64 * 1024;
+        if ((id & 0xfff0) != VBE_DISPI_ID0) {
+                DRM_ERROR("ID mismatch\n");
+                return -ENODEV;
+        }
+
+        if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
+                return -ENODEV;
+        addr = pci_resource_start(pdev, 0);
+        size = pci_resource_len(pdev, 0);
+        if (addr == 0)
+                return -ENODEV;
+        if (size != mem) {
+                DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
+                        size, mem);
+                size = min(size, mem);
+        }
+
+        if (pci_request_region(pdev, 0, "bochs-drm") != 0) {
+                DRM_ERROR("Cannot request framebuffer\n");
+                return -EBUSY;
+        }
+
+        bochs->fb_map = ioremap(addr, size);
+        if (bochs->fb_map == NULL) {
+                DRM_ERROR("Cannot map framebuffer\n");
+                return -ENOMEM;
+        }
+        bochs->fb_base = addr;
+        bochs->fb_size = size;
+
+        DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
+        DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
+                 size / 1024, addr,
+                 bochs->ioports ? "ioports" : "mmio",
+                 ioaddr);
+        return 0;
+}
+
+void bochs_hw_fini(struct drm_device *dev)
+{
+        struct bochs_device *bochs = dev->dev_private;
+
+        if (bochs->mmio)
+                iounmap(bochs->mmio);
+        if (bochs->ioports)
+                release_region(VBE_DISPI_IOPORT_INDEX, 2);
+        if (bochs->fb_map)
+                iounmap(bochs->fb_map);
+        pci_release_regions(dev->pdev);
+}
+
+void bochs_hw_setmode(struct bochs_device *bochs,
+                      struct drm_display_mode *mode)
+{
+        bochs->xres = mode->hdisplay;
+        bochs->yres = mode->vdisplay;
+        bochs->bpp = 32;
+        bochs->stride = mode->hdisplay * (bochs->bpp / 8);
+        bochs->yres_virtual = bochs->fb_size / bochs->stride;
+
+        DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
+                         bochs->xres, bochs->yres, bochs->bpp,
+                         bochs->yres_virtual);
+
+        bochs_vga_writeb(bochs, 0x3c0, 0x20); /* unblank */
+
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP,         bochs->bpp);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES,        bochs->xres);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES,        bochs->yres);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK,        0);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH,  bochs->xres);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
+                          bochs->yres_virtual);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET,    0);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET,    0);
+
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
+                          VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
+}
+
+void bochs_hw_setbase(struct bochs_device *bochs,
+                      int x, int y, u64 addr)
+{
+        unsigned long offset = (unsigned long)addr +
+                y * bochs->stride +
+                x * (bochs->bpp / 8);
+        int vy = offset / bochs->stride;
+        int vx = (offset % bochs->stride) * 8 / bochs->bpp;
+
+        DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
+                         x, y, addr, offset, vx, vy);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
+        bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
+}
diff --git a/drivers/gpu/drm/bochs/bochs_kms.c b/drivers/gpu/drm/bochs/bochs_kms.c
new file mode 100644
index 000000000000..62ec7d4b3816
--- /dev/null
+++ b/drivers/gpu/drm/bochs/bochs_kms.c
@@ -0,0 +1,294 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "bochs.h"
+
+static int defx = 1024;
+static int defy = 768;
+
+module_param(defx, int, 0444);
+module_param(defy, int, 0444);
+MODULE_PARM_DESC(defx, "default x resolution");
+MODULE_PARM_DESC(defy, "default y resolution");
+
+/* ---------------------------------------------------------------------- */
+
+static void bochs_crtc_load_lut(struct drm_crtc *crtc)
+{
+}
+
+static void bochs_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+        default:
+                return;
+        }
+}
+
+static bool bochs_crtc_mode_fixup(struct drm_crtc *crtc,
+                                  const struct drm_display_mode *mode,
+                                  struct drm_display_mode *adjusted_mode)
+{
+        return true;
+}
+
+static int bochs_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
+                                    struct drm_framebuffer *old_fb)
+{
+        struct bochs_device *bochs =
+                container_of(crtc, struct bochs_device, crtc);
+        struct bochs_framebuffer *bochs_fb;
+        struct bochs_bo *bo;
+        u64 gpu_addr = 0;
+        int ret;
+
+        if (old_fb) {
+                bochs_fb = to_bochs_framebuffer(old_fb);
+                bo = gem_to_bochs_bo(bochs_fb->obj);
+                ret = ttm_bo_reserve(&bo->bo, true, false, false, 0);
+                if (ret) {
+                        DRM_ERROR("failed to reserve old_fb bo\n");
+                } else {
+                        bochs_bo_unpin(bo);
+                        ttm_bo_unreserve(&bo->bo);
+                }
+        }
+
+        if (WARN_ON(crtc->fb == NULL))
+                return -EINVAL;
+
+        bochs_fb = to_bochs_framebuffer(crtc->fb);
+        bo = gem_to_bochs_bo(bochs_fb->obj);
+        ret = ttm_bo_reserve(&bo->bo, true, false, false, 0);
+        if (ret)
+                return ret;
+
+        ret = bochs_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
+        if (ret) {
+                ttm_bo_unreserve(&bo->bo);
+                return ret;
+        }
+
+        ttm_bo_unreserve(&bo->bo);
+        bochs_hw_setbase(bochs, x, y, gpu_addr);
+        return 0;
+}
+
+static int bochs_crtc_mode_set(struct drm_crtc *crtc,
+                               struct drm_display_mode *mode,
+                               struct drm_display_mode *adjusted_mode,
+                               int x, int y, struct drm_framebuffer *old_fb)
+{
+        struct bochs_device *bochs =
+                container_of(crtc, struct bochs_device, crtc);
+
+        bochs_hw_setmode(bochs, mode);
+        bochs_crtc_mode_set_base(crtc, x, y, old_fb);
+        return 0;
+}
+
+static void bochs_crtc_prepare(struct drm_crtc *crtc)
+{
+}
+
+static void bochs_crtc_commit(struct drm_crtc *crtc)
+{
+}
+
+static void bochs_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+                                 u16 *blue, uint32_t start, uint32_t size)
+{
+}
+
+/* These provide the minimum set of functions required to handle a CRTC */
+static const struct drm_crtc_funcs bochs_crtc_funcs = {
+        .gamma_set = bochs_crtc_gamma_set,
+        .set_config = drm_crtc_helper_set_config,
+        .destroy = drm_crtc_cleanup,
+};
+
+static const struct drm_crtc_helper_funcs bochs_helper_funcs = {
+        .dpms = bochs_crtc_dpms,
+        .mode_fixup = bochs_crtc_mode_fixup,
+        .mode_set = bochs_crtc_mode_set,
+        .mode_set_base = bochs_crtc_mode_set_base,
+        .prepare = bochs_crtc_prepare,
+        .commit = bochs_crtc_commit,
+        .load_lut = bochs_crtc_load_lut,
+};
+
+static void bochs_crtc_init(struct drm_device *dev)
+{
+        struct bochs_device *bochs = dev->dev_private;
+        struct drm_crtc *crtc = &bochs->crtc;
+
+        drm_crtc_init(dev, crtc, &bochs_crtc_funcs);
+        drm_mode_crtc_set_gamma_size(crtc, 256);
+        drm_crtc_helper_add(crtc, &bochs_helper_funcs);
+}
+
+static bool bochs_encoder_mode_fixup(struct drm_encoder *encoder,
+                                     const struct drm_display_mode *mode,
+                                     struct drm_display_mode *adjusted_mode)
+{
+        return true;
+}
+
+static void bochs_encoder_mode_set(struct drm_encoder *encoder,
+                                   struct drm_display_mode *mode,
+                                   struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void bochs_encoder_dpms(struct drm_encoder *encoder, int state)
+{
+}
+
+static void bochs_encoder_prepare(struct drm_encoder *encoder)
+{
+}
+
+static void bochs_encoder_commit(struct drm_encoder *encoder)
+{
+}
+
+static const struct drm_encoder_helper_funcs bochs_encoder_helper_funcs = {
+        .dpms = bochs_encoder_dpms,
+        .mode_fixup = bochs_encoder_mode_fixup,
+        .mode_set = bochs_encoder_mode_set,
+        .prepare = bochs_encoder_prepare,
+        .commit = bochs_encoder_commit,
+};
+
+static const struct drm_encoder_funcs bochs_encoder_encoder_funcs = {
+        .destroy = drm_encoder_cleanup,
+};
+
+static void bochs_encoder_init(struct drm_device *dev)
+{
+        struct bochs_device *bochs = dev->dev_private;
+        struct drm_encoder *encoder = &bochs->encoder;
+
+        encoder->possible_crtcs = 0x1;
+        drm_encoder_init(dev, encoder, &bochs_encoder_encoder_funcs,
+                         DRM_MODE_ENCODER_DAC);
+        drm_encoder_helper_add(encoder, &bochs_encoder_helper_funcs);
+}
+
+
+int bochs_connector_get_modes(struct drm_connector *connector)
+{
+        int count;
+
+        count = drm_add_modes_noedid(connector, 8192, 8192);
+        drm_set_preferred_mode(connector, defx, defy);
+        return count;
+}
+
+static int bochs_connector_mode_valid(struct drm_connector *connector,
+                                      struct drm_display_mode *mode)
+{
+        struct bochs_device *bochs =
+                container_of(connector, struct bochs_device, connector);
+        unsigned long size = mode->hdisplay * mode->vdisplay * 4;
+
+        /*
+         * Make sure we can fit two framebuffers into video memory.
+         * This allows up to 1600x1200 with 16 MB (default size).
+         * If you want more try this:
+         *     'qemu -vga std -global VGA.vgamem_mb=32 $otherargs'
+         */
+        if (size * 2 > bochs->fb_size)
+                return MODE_BAD;
+
+        return MODE_OK;
+}
+
+static struct drm_encoder *
+bochs_connector_best_encoder(struct drm_connector *connector)
+{
+        int enc_id = connector->encoder_ids[0];
+        struct drm_mode_object *obj;
+        struct drm_encoder *encoder;
+
+        /* pick the encoder ids */
+        if (enc_id) {
+                obj = drm_mode_object_find(connector->dev, enc_id,
+                                           DRM_MODE_OBJECT_ENCODER);
+                if (!obj)
+                        return NULL;
+                encoder = obj_to_encoder(obj);
+                return encoder;
+        }
+        return NULL;
+}
+
+static enum drm_connector_status bochs_connector_detect(struct drm_connector
+                                                        *connector, bool force)
+{
+        return connector_status_connected;
+}
+
+struct drm_connector_helper_funcs bochs_connector_connector_helper_funcs = {
+        .get_modes = bochs_connector_get_modes,
+        .mode_valid = bochs_connector_mode_valid,
+        .best_encoder = bochs_connector_best_encoder,
+};
+
+struct drm_connector_funcs bochs_connector_connector_funcs = {
+        .dpms = drm_helper_connector_dpms,
+        .detect = bochs_connector_detect,
+        .fill_modes = drm_helper_probe_single_connector_modes,
+        .destroy = drm_connector_cleanup,
+};
+
+static void bochs_connector_init(struct drm_device *dev)
+{
+        struct bochs_device *bochs = dev->dev_private;
+        struct drm_connector *connector = &bochs->connector;
+
+        drm_connector_init(dev, connector, &bochs_connector_connector_funcs,
+                           DRM_MODE_CONNECTOR_VIRTUAL);
+        drm_connector_helper_add(connector,
+                                 &bochs_connector_connector_helper_funcs);
+}
+
+
+int bochs_kms_init(struct bochs_device *bochs)
+{
+        drm_mode_config_init(bochs->dev);
+        bochs->mode_config_initialized = true;
+
+        bochs->dev->mode_config.max_width = 8192;
+        bochs->dev->mode_config.max_height = 8192;
+
+        bochs->dev->mode_config.fb_base = bochs->fb_base;
+        bochs->dev->mode_config.preferred_depth = 24;
+        bochs->dev->mode_config.prefer_shadow = 0;
+
+        bochs->dev->mode_config.funcs = (void *)&bochs_mode_funcs;
+
+        bochs_crtc_init(bochs->dev);
+        bochs_encoder_init(bochs->dev);
+        bochs_connector_init(bochs->dev);
+        drm_mode_connector_attach_encoder(&bochs->connector,
+                                          &bochs->encoder);
+
+        return 0;
+}
+
+void bochs_kms_fini(struct bochs_device *bochs)
+{
+        if (bochs->mode_config_initialized) {
+                drm_mode_config_cleanup(bochs->dev);
+                bochs->mode_config_initialized = false;
+        }
+}
diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c
new file mode 100644
index 000000000000..ce6858765b37
--- /dev/null
+++ b/drivers/gpu/drm/bochs/bochs_mm.c
@@ -0,0 +1,546 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "bochs.h"
+
+static void bochs_ttm_placement(struct bochs_bo *bo, int domain);
+
+/* ---------------------------------------------------------------------- */
+
+static inline struct bochs_device *bochs_bdev(struct ttm_bo_device *bd)
+{
+        return container_of(bd, struct bochs_device, ttm.bdev);
+}
+
+static int bochs_ttm_mem_global_init(struct drm_global_reference *ref)
+{
+        return ttm_mem_global_init(ref->object);
+}
+
+static void bochs_ttm_mem_global_release(struct drm_global_reference *ref)
+{
+        ttm_mem_global_release(ref->object);
+}
+
+static int bochs_ttm_global_init(struct bochs_device *bochs)
+{
+        struct drm_global_reference *global_ref;
+        int r;
+
+        global_ref = &bochs->ttm.mem_global_ref;
+        global_ref->global_type = DRM_GLOBAL_TTM_MEM;
+        global_ref->size = sizeof(struct ttm_mem_global);
+        global_ref->init = &bochs_ttm_mem_global_init;
+        global_ref->release = &bochs_ttm_mem_global_release;
+        r = drm_global_item_ref(global_ref);
+        if (r != 0) {
+                DRM_ERROR("Failed setting up TTM memory accounting "
+                          "subsystem.\n");
+                return r;
+        }
+
+        bochs->ttm.bo_global_ref.mem_glob =
+                bochs->ttm.mem_global_ref.object;
+        global_ref = &bochs->ttm.bo_global_ref.ref;
+        global_ref->global_type = DRM_GLOBAL_TTM_BO;
+        global_ref->size = sizeof(struct ttm_bo_global);
+        global_ref->init = &ttm_bo_global_init;
+        global_ref->release = &ttm_bo_global_release;
+        r = drm_global_item_ref(global_ref);
+        if (r != 0) {
+                DRM_ERROR("Failed setting up TTM BO subsystem.\n");
+                drm_global_item_unref(&bochs->ttm.mem_global_ref);
+                return r;
+        }
+
+        return 0;
+}
+
+static void bochs_ttm_global_release(struct bochs_device *bochs)
+{
+        if (bochs->ttm.mem_global_ref.release == NULL)
+                return;
+
+        drm_global_item_unref(&bochs->ttm.bo_global_ref.ref);
+        drm_global_item_unref(&bochs->ttm.mem_global_ref);
+        bochs->ttm.mem_global_ref.release = NULL;
+}
+
+
+static void bochs_bo_ttm_destroy(struct ttm_buffer_object *tbo)
+{
+        struct bochs_bo *bo;
+
+        bo = container_of(tbo, struct bochs_bo, bo);
+        drm_gem_object_release(&bo->gem);
+        kfree(bo);
+}
+
+static bool bochs_ttm_bo_is_bochs_bo(struct ttm_buffer_object *bo)
+{
+        if (bo->destroy == &bochs_bo_ttm_destroy)
+                return true;
+        return false;
+}
+
+static int bochs_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
+                                  struct ttm_mem_type_manager *man)
+{
+        switch (type) {
+        case TTM_PL_SYSTEM:
+                man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
+                man->available_caching = TTM_PL_MASK_CACHING;
+                man->default_caching = TTM_PL_FLAG_CACHED;
+                break;
+        case TTM_PL_VRAM:
+                man->func = &ttm_bo_manager_func;
+                man->flags = TTM_MEMTYPE_FLAG_FIXED |
+                        TTM_MEMTYPE_FLAG_MAPPABLE;
+                man->available_caching = TTM_PL_FLAG_UNCACHED |
+                        TTM_PL_FLAG_WC;
+                man->default_caching = TTM_PL_FLAG_WC;
+                break;
+        default:
+                DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static void
+bochs_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
+{
+        struct bochs_bo *bochsbo = bochs_bo(bo);
+
+        if (!bochs_ttm_bo_is_bochs_bo(bo))
+                return;
+
+        bochs_ttm_placement(bochsbo, TTM_PL_FLAG_SYSTEM);
+        *pl = bochsbo->placement;
+}
+
+static int bochs_bo_verify_access(struct ttm_buffer_object *bo,
+                                  struct file *filp)
+{
+        struct bochs_bo *bochsbo = bochs_bo(bo);
+
+        return drm_vma_node_verify_access(&bochsbo->gem.vma_node, filp);
+}
+
+static int bochs_ttm_io_mem_reserve(struct ttm_bo_device *bdev,
+                                    struct ttm_mem_reg *mem)
+{
+        struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
+        struct bochs_device *bochs = bochs_bdev(bdev);
+
+        mem->bus.addr = NULL;
+        mem->bus.offset = 0;
+        mem->bus.size = mem->num_pages << PAGE_SHIFT;
+        mem->bus.base = 0;
+        mem->bus.is_iomem = false;
+        if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
+                return -EINVAL;
+        switch (mem->mem_type) {
+        case TTM_PL_SYSTEM:
+                /* system memory */
+                return 0;
+        case TTM_PL_VRAM:
+                mem->bus.offset = mem->start << PAGE_SHIFT;
+                mem->bus.base = bochs->fb_base;
+                mem->bus.is_iomem = true;
+                break;
+        default:
+                return -EINVAL;
+                break;
+        }
+        return 0;
+}
+
+static void bochs_ttm_io_mem_free(struct ttm_bo_device *bdev,
+                                  struct ttm_mem_reg *mem)
+{
+}
+
+static int bochs_bo_move(struct ttm_buffer_object *bo,
+                         bool evict, bool interruptible,
+                         bool no_wait_gpu,
+                         struct ttm_mem_reg *new_mem)
+{
+        return ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
+}
+
+
+static void bochs_ttm_backend_destroy(struct ttm_tt *tt)
+{
+        ttm_tt_fini(tt);
+        kfree(tt);
+}
+
+static struct ttm_backend_func bochs_tt_backend_func = {
+        .destroy = &bochs_ttm_backend_destroy,
+};
+
+static struct ttm_tt *bochs_ttm_tt_create(struct ttm_bo_device *bdev,
+                                          unsigned long size,
+                                          uint32_t page_flags,
+                                          struct page *dummy_read_page)
+{
+        struct ttm_tt *tt;
+
+        tt = kzalloc(sizeof(struct ttm_tt), GFP_KERNEL);
+        if (tt == NULL)
+                return NULL;
+        tt->func = &bochs_tt_backend_func;
+        if (ttm_tt_init(tt, bdev, size, page_flags, dummy_read_page)) {
+                kfree(tt);
+                return NULL;
+        }
+        return tt;
+}
+
+struct ttm_bo_driver bochs_bo_driver = {
+        .ttm_tt_create = bochs_ttm_tt_create,
+        .ttm_tt_populate = ttm_pool_populate,
+        .ttm_tt_unpopulate = ttm_pool_unpopulate,
+        .init_mem_type = bochs_bo_init_mem_type,
+        .evict_flags = bochs_bo_evict_flags,
+        .move = bochs_bo_move,
+        .verify_access = bochs_bo_verify_access,
+        .io_mem_reserve = &bochs_ttm_io_mem_reserve,
+        .io_mem_free = &bochs_ttm_io_mem_free,
+};
+
+int bochs_mm_init(struct bochs_device *bochs)
+{
+        struct ttm_bo_device *bdev = &bochs->ttm.bdev;
+        int ret;
+
+        ret = bochs_ttm_global_init(bochs);
+        if (ret)
+                return ret;
+
+        ret = ttm_bo_device_init(&bochs->ttm.bdev,
+                                 bochs->ttm.bo_global_ref.ref.object,
+                                 &bochs_bo_driver, DRM_FILE_PAGE_OFFSET,
+                                 true);
+        if (ret) {
+                DRM_ERROR("Error initialising bo driver; %d\n", ret);
+                return ret;
+        }
+
+        ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
+                             bochs->fb_size >> PAGE_SHIFT);
+        if (ret) {
+                DRM_ERROR("Failed ttm VRAM init: %d\n", ret);
+                return ret;
+        }
+
+        bochs->ttm.initialized = true;
+        return 0;
+}
+
+void bochs_mm_fini(struct bochs_device *bochs)
+{
+        if (!bochs->ttm.initialized)
+                return;
+
+        ttm_bo_device_release(&bochs->ttm.bdev);
+        bochs_ttm_global_release(bochs);
+        bochs->ttm.initialized = false;
+}
+
+static void bochs_ttm_placement(struct bochs_bo *bo, int domain)
+{
+        u32 c = 0;
+        bo->placement.fpfn = 0;
+        bo->placement.lpfn = 0;
+        bo->placement.placement = bo->placements;
+        bo->placement.busy_placement = bo->placements;
+        if (domain & TTM_PL_FLAG_VRAM) {
+                bo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED
+                        | TTM_PL_FLAG_VRAM;
+        }
+        if (domain & TTM_PL_FLAG_SYSTEM) {
+                bo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
+        }
+        if (!c) {
+                bo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
+        }
+        bo->placement.num_placement = c;
+        bo->placement.num_busy_placement = c;
+}
+
+static inline u64 bochs_bo_gpu_offset(struct bochs_bo *bo)
+{
+        return bo->bo.offset;
+}
+
+int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr)
+{
+        int i, ret;
+
+        if (bo->pin_count) {
+                bo->pin_count++;
+                if (gpu_addr)
+                        *gpu_addr = bochs_bo_gpu_offset(bo);
+                return 0;
+        }
+
+        bochs_ttm_placement(bo, pl_flag);
+        for (i = 0; i < bo->placement.num_placement; i++)
+                bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
+        ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+        if (ret)
+                return ret;
+
+        bo->pin_count = 1;
+        if (gpu_addr)
+                *gpu_addr = bochs_bo_gpu_offset(bo);
+        return 0;
+}
+
+int bochs_bo_unpin(struct bochs_bo *bo)
+{
+        int i, ret;
+
+        if (!bo->pin_count) {
+                DRM_ERROR("unpin bad %p\n", bo);
+                return 0;
+        }
+        bo->pin_count--;
+
+        if (bo->pin_count)
+                return 0;
+
+        for (i = 0; i < bo->placement.num_placement; i++)
+                bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
+        ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+int bochs_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+        struct drm_file *file_priv;
+        struct bochs_device *bochs;
+
+        if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
+                return drm_mmap(filp, vma);
+
+        file_priv = filp->private_data;
+        bochs = file_priv->minor->dev->dev_private;
+        return ttm_bo_mmap(filp, vma, &bochs->ttm.bdev);
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int bochs_bo_create(struct drm_device *dev, int size, int align,
+                           uint32_t flags, struct bochs_bo **pbochsbo)
+{
+        struct bochs_device *bochs = dev->dev_private;
+        struct bochs_bo *bochsbo;
+        size_t acc_size;
+        int ret;
+
+        bochsbo = kzalloc(sizeof(struct bochs_bo), GFP_KERNEL);
+        if (!bochsbo)
+                return -ENOMEM;
+
+        ret = drm_gem_object_init(dev, &bochsbo->gem, size);
+        if (ret) {
+                kfree(bochsbo);
+                return ret;
+        }
+
+        bochsbo->bo.bdev = &bochs->ttm.bdev;
+        bochsbo->bo.bdev->dev_mapping = dev->dev_mapping;
+
+        bochs_ttm_placement(bochsbo, TTM_PL_FLAG_VRAM | TTM_PL_FLAG_SYSTEM);
+
+        acc_size = ttm_bo_dma_acc_size(&bochs->ttm.bdev, size,
+                                       sizeof(struct bochs_bo));
+
+        ret = ttm_bo_init(&bochs->ttm.bdev, &bochsbo->bo, size,
+                          ttm_bo_type_device, &bochsbo->placement,
+                          align >> PAGE_SHIFT, false, NULL, acc_size,
+                          NULL, bochs_bo_ttm_destroy);
+        if (ret)
+                return ret;
+
+        *pbochsbo = bochsbo;
+        return 0;
+}
+
+int bochs_gem_create(struct drm_device *dev, u32 size, bool iskernel,
+                     struct drm_gem_object **obj)
+{
+        struct bochs_bo *bochsbo;
+        int ret;
+
+        *obj = NULL;
+
+        size = ALIGN(size, PAGE_SIZE);
+        if (size == 0)
+                return -EINVAL;
+
+        ret = bochs_bo_create(dev, size, 0, 0, &bochsbo);
+        if (ret) {
+                if (ret != -ERESTARTSYS)
+                        DRM_ERROR("failed to allocate GEM object\n");
+                return ret;
+        }
+        *obj = &bochsbo->gem;
+        return 0;
+}
+
+int bochs_dumb_create(struct drm_file *file, struct drm_device *dev,
+                      struct drm_mode_create_dumb *args)
+{
+        struct drm_gem_object *gobj;
+        u32 handle;
+        int ret;
+
+        args->pitch = args->width * ((args->bpp + 7) / 8);
+        args->size = args->pitch * args->height;
+
+        ret = bochs_gem_create(dev, args->size, false,
+                               &gobj);
+        if (ret)
+                return ret;
+
+        ret = drm_gem_handle_create(file, gobj, &handle);
+        drm_gem_object_unreference_unlocked(gobj);
+        if (ret)
+                return ret;
+
+        args->handle = handle;
+        return 0;
+}
+
+static void bochs_bo_unref(struct bochs_bo **bo)
+{
+        struct ttm_buffer_object *tbo;
+
+        if ((*bo) == NULL)
+                return;
+
+        tbo = &((*bo)->bo);
+        ttm_bo_unref(&tbo);
+        if (tbo == NULL)
+                *bo = NULL;
+
+}
+
+void bochs_gem_free_object(struct drm_gem_object *obj)
+{
+        struct bochs_bo *bochs_bo = gem_to_bochs_bo(obj);
+
+        if (!bochs_bo)
+                return;
+        bochs_bo_unref(&bochs_bo);
+}
+
+int bochs_dumb_mmap_offset(struct drm_file *file, struct drm_device *dev,
+                           uint32_t handle, uint64_t *offset)
+{
+        struct drm_gem_object *obj;
+        int ret;
+        struct bochs_bo *bo;
+
+        mutex_lock(&dev->struct_mutex);
+        obj = drm_gem_object_lookup(dev, file, handle);
+        if (obj == NULL) {
+                ret = -ENOENT;
+                goto out_unlock;
+        }
+
+        bo = gem_to_bochs_bo(obj);
+        *offset = bochs_bo_mmap_offset(bo);
+
+        drm_gem_object_unreference(obj);
+        ret = 0;
+out_unlock:
+        mutex_unlock(&dev->struct_mutex);
+        return ret;
+
+}
+
+/* ---------------------------------------------------------------------- */
+
+static void bochs_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
+        struct bochs_framebuffer *bochs_fb = to_bochs_framebuffer(fb);
+        if (bochs_fb->obj)
+                drm_gem_object_unreference_unlocked(bochs_fb->obj);
+        drm_framebuffer_cleanup(fb);
+        kfree(fb);
+}
+
+static const struct drm_framebuffer_funcs bochs_fb_funcs = {
+        .destroy = bochs_user_framebuffer_destroy,
+};
+
+int bochs_framebuffer_init(struct drm_device *dev,
+                           struct bochs_framebuffer *gfb,
+                           struct drm_mode_fb_cmd2 *mode_cmd,
+                           struct drm_gem_object *obj)
+{
+        int ret;
+
+        drm_helper_mode_fill_fb_struct(&gfb->base, mode_cmd);
+        gfb->obj = obj;
+        ret = drm_framebuffer_init(dev, &gfb->base, &bochs_fb_funcs);
+        if (ret) {
+                DRM_ERROR("drm_framebuffer_init failed: %d\n", ret);
+                return ret;
+        }
+        return 0;
+}
+
+static struct drm_framebuffer *
+bochs_user_framebuffer_create(struct drm_device *dev,
+                              struct drm_file *filp,
+                              struct drm_mode_fb_cmd2 *mode_cmd)
+{
+        struct drm_gem_object *obj;
+        struct bochs_framebuffer *bochs_fb;
+        int ret;
+
+        DRM_DEBUG_DRIVER("%dx%d, format %c%c%c%c\n",
+               mode_cmd->width, mode_cmd->height,
+               (mode_cmd->pixel_format)       & 0xff,
+               (mode_cmd->pixel_format >> 8)  & 0xff,
+               (mode_cmd->pixel_format >> 16) & 0xff,
+               (mode_cmd->pixel_format >> 24) & 0xff);
+
+        if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888)
+                return ERR_PTR(-ENOENT);
+
+        obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]);
+        if (obj == NULL)
+                return ERR_PTR(-ENOENT);
+
+        bochs_fb = kzalloc(sizeof(*bochs_fb), GFP_KERNEL);
+        if (!bochs_fb) {
+                drm_gem_object_unreference_unlocked(obj);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        ret = bochs_framebuffer_init(dev, bochs_fb, mode_cmd, obj);
+        if (ret) {
+                drm_gem_object_unreference_unlocked(obj);
+                kfree(bochs_fb);
+                return ERR_PTR(ret);
+        }
+        return &bochs_fb->base;
+}
+
+const struct drm_mode_config_funcs bochs_mode_funcs = {
+        .fb_create = bochs_user_framebuffer_create,
+};
diff --git a/drivers/gpu/drm/cirrus/cirrus_fbdev.c b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
index b27e95666fab..e63a7533f849 100644
--- a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
+++ b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
@@ -233,6 +233,9 @@ static int cirrusfb_create(struct drm_fb_helper *helper,
         info->apertures->ranges[0].base = cdev->dev->mode_config.fb_base;
         info->apertures->ranges[0].size = cdev->mc.vram_size;
 
+        info->fix.smem_start = cdev->dev->mode_config.fb_base;
+        info->fix.smem_len = cdev->mc.vram_size;
+
         info->screen_base = sysram;
         info->screen_size = size;
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 7e074a4d2848..9d096a0c5f8d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -14,6 +14,8 @@
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 
+#include <linux/anon_inodes.h>
+
 #include <drm/exynos_drm.h>
 
 #include "exynos_drm_drv.h"
@@ -152,9 +154,14 @@ static int exynos_drm_unload(struct drm_device *dev)
         return 0;
 }
 
+static const struct file_operations exynos_drm_gem_fops = {
+        .mmap = exynos_drm_gem_mmap_buffer,
+};
+
 static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
 {
         struct drm_exynos_file_private *file_priv;
+        struct file *anon_filp;
         int ret;
 
         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
@@ -169,6 +176,16 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
                 file->driver_priv = NULL;
         }
 
+        anon_filp = anon_inode_getfile("exynos_gem", &exynos_drm_gem_fops,
+                                        NULL, 0);
+        if (IS_ERR(anon_filp)) {
+                kfree(file_priv);
+                return PTR_ERR(anon_filp);
+        }
+
+        anon_filp->f_mode = FMODE_READ | FMODE_WRITE;
+        file_priv->anon_filp = anon_filp;
+
         return ret;
 }
 
@@ -181,6 +198,7 @@ static void exynos_drm_preclose(struct drm_device *dev,
 static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)
 {
         struct exynos_drm_private *private = dev->dev_private;
+        struct drm_exynos_file_private *file_priv;
         struct drm_pending_vblank_event *v, *vt;
         struct drm_pending_event *e, *et;
         unsigned long flags;
@@ -206,6 +224,9 @@ static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)
         }
         spin_unlock_irqrestore(&dev->event_lock, flags);
 
+        file_priv = file->driver_priv;
+        if (file_priv->anon_filp)
+                fput(file_priv->anon_filp);
 
         kfree(file->driver_priv);
         file->driver_priv = NULL;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index eaa19668bf00..0eaf5a27e120 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -226,6 +226,7 @@ struct exynos_drm_ipp_private {
 struct drm_exynos_file_private {
         struct exynos_drm_g2d_private   *g2d_priv;
         struct exynos_drm_ipp_private   *ipp_priv;
+        struct file                     *anon_filp;
 };
 
 /*
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 267aca91b70d..a20440ce32e6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -347,7 +347,7 @@ static void fimd_wait_for_vblank(struct device *dev)
          */
         if (!wait_event_timeout(ctx->wait_vsync_queue,
                                 !atomic_read(&ctx->wait_vsync_event),
-                                DRM_HZ/20))
+                                HZ/20))
                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 }
 
@@ -706,7 +706,7 @@ static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
         /* set wait vsync event to zero and wake up queue. */
         if (atomic_read(&ctx->wait_vsync_event)) {
                 atomic_set(&ctx->wait_vsync_event, 0);
-                DRM_WAKEUP(&ctx->wait_vsync_queue);
+                wake_up(&ctx->wait_vsync_queue);
         }
 out:
         return IRQ_HANDLED;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 1ade191d84f4..49b8c9b22902 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -338,46 +338,22 @@ int exynos_drm_gem_map_offset_ioctl(struct drm_device *dev, void *data,
                         &args->offset);
 }
 
-static struct drm_file *exynos_drm_find_drm_file(struct drm_device *drm_dev,
-                                                        struct file *filp)
-{
-        struct drm_file *file_priv;
-
-        /* find current process's drm_file from filelist. */
-        list_for_each_entry(file_priv, &drm_dev->filelist, lhead)
-                if (file_priv->filp == filp)
-                        return file_priv;
-
-        WARN_ON(1);
-
-        return ERR_PTR(-EFAULT);
-}
-
-static int exynos_drm_gem_mmap_buffer(struct file *filp,
+int exynos_drm_gem_mmap_buffer(struct file *filp,
                                       struct vm_area_struct *vma)
 {
         struct drm_gem_object *obj = filp->private_data;
         struct exynos_drm_gem_obj *exynos_gem_obj = to_exynos_gem_obj(obj);
         struct drm_device *drm_dev = obj->dev;
         struct exynos_drm_gem_buf *buffer;
-        struct drm_file *file_priv;
         unsigned long vm_size;
         int ret;
 
+        WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex));
+
         vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
         vma->vm_private_data = obj;
         vma->vm_ops = drm_dev->driver->gem_vm_ops;
 
-        /* restore it to driver's fops. */
-        filp->f_op = fops_get(drm_dev->driver->fops);
-
-        file_priv = exynos_drm_find_drm_file(drm_dev, filp);
-        if (IS_ERR(file_priv))
-                return PTR_ERR(file_priv);
-
-        /* restore it to drm_file. */
-        filp->private_data = file_priv;
-
         update_vm_cache_attr(exynos_gem_obj, vma);
 
         vm_size = vma->vm_end - vma->vm_start;
@@ -411,15 +387,13 @@ static int exynos_drm_gem_mmap_buffer(struct file *filp,
         return 0;
 }
 
-static const struct file_operations exynos_drm_gem_fops = {
-        .mmap = exynos_drm_gem_mmap_buffer,
-};
-
 int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data,
                               struct drm_file *file_priv)
 {
+        struct drm_exynos_file_private *exynos_file_priv;
         struct drm_exynos_gem_mmap *args = data;
         struct drm_gem_object *obj;
+        struct file *anon_filp;
         unsigned long addr;
 
         if (!(dev->driver->driver_features & DRIVER_GEM)) {
@@ -427,47 +401,25 @@ int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data,
                 return -ENODEV;
         }
 
+        mutex_lock(&dev->struct_mutex);
+
         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
         if (!obj) {
                 DRM_ERROR("failed to lookup gem object.\n");
+                mutex_unlock(&dev->struct_mutex);
                 return -EINVAL;
         }
 
-        /*
-         * We have to use gem object and its fops for specific mmaper,
-         * but vm_mmap() can deliver only filp. So we have to change
-         * filp->f_op and filp->private_data temporarily, then restore
-         * again. So it is important to keep lock until restoration the
-         * settings to prevent others from misuse of filp->f_op or
-         * filp->private_data.
-         */
-        mutex_lock(&dev->struct_mutex);
-
-        /*
-         * Set specific mmper's fops. And it will be restored by
-         * exynos_drm_gem_mmap_buffer to dev->driver->fops.
-         * This is used to call specific mapper temporarily.
-         */
-        file_priv->filp->f_op = &exynos_drm_gem_fops;
-
-        /*
-         * Set gem object to private_data so that specific mmaper
-         * can get the gem object. And it will be restored by
-         * exynos_drm_gem_mmap_buffer to drm_file.
-         */
-        file_priv->filp->private_data = obj;
+        exynos_file_priv = file_priv->driver_priv;
+        anon_filp = exynos_file_priv->anon_filp;
+        anon_filp->private_data = obj;
 
-        addr = vm_mmap(file_priv->filp, 0, args->size,
-                        PROT_READ | PROT_WRITE, MAP_SHARED, 0);
+        addr = vm_mmap(anon_filp, 0, args->size, PROT_READ | PROT_WRITE,
+                        MAP_SHARED, 0);
 
         drm_gem_object_unreference(obj);
 
         if (IS_ERR_VALUE(addr)) {
-                /* check filp->f_op, filp->private_data are restored */
-                if (file_priv->filp->f_op == &exynos_drm_gem_fops) {
-                        file_priv->filp->f_op = fops_get(dev->driver->fops);
-                        file_priv->filp->private_data = file_priv;
-                }
                 mutex_unlock(&dev->struct_mutex);
                 return (int)addr;
         }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h
index 702ec3abe85c..fde860c7eba3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
@@ -122,6 +122,9 @@ int exynos_drm_gem_map_offset_ioctl(struct drm_device *dev, void *data,
 int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data,
                               struct drm_file *file_priv);
 
+int exynos_drm_gem_mmap_buffer(struct file *filp,
+                                      struct vm_area_struct *vma);
+
 /* map user space allocated by malloc to pages. */
 int exynos_drm_gem_userptr_ioctl(struct drm_device *dev, void *data,
                                       struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index f39ab7554fc9..bb103fb4519e 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -2,8 +2,7 @@
 config DRM_MSM
         tristate "MSM DRM"
         depends on DRM
-        depends on ARCH_MSM
-        depends on ARCH_MSM8960
+        depends on (ARCH_MSM && ARCH_MSM8960) || (ARM && COMPILE_TEST)
         select DRM_KMS_HELPER
         select SHMEM
         select TMPFS
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index e5fa12b0d21e..4f977a593bea 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -12,18 +12,27 @@ msm-y := \
         hdmi/hdmi_i2c.o \
         hdmi/hdmi_phy_8960.o \
         hdmi/hdmi_phy_8x60.o \
-        mdp4/mdp4_crtc.o \
-        mdp4/mdp4_dtv_encoder.o \
-        mdp4/mdp4_format.o \
-        mdp4/mdp4_irq.o \
-        mdp4/mdp4_kms.o \
-        mdp4/mdp4_plane.o \
+        hdmi/hdmi_phy_8x74.o \
+        mdp/mdp_format.o \
+        mdp/mdp_kms.o \
+        mdp/mdp4/mdp4_crtc.o \
+        mdp/mdp4/mdp4_dtv_encoder.o \
+        mdp/mdp4/mdp4_irq.o \
+        mdp/mdp4/mdp4_kms.o \
+        mdp/mdp4/mdp4_plane.o \
+        mdp/mdp5/mdp5_crtc.o \
+        mdp/mdp5/mdp5_encoder.o \
+        mdp/mdp5/mdp5_irq.o \
+        mdp/mdp5/mdp5_kms.o \
+        mdp/mdp5/mdp5_plane.o \
+        mdp/mdp5/mdp5_smp.o \
         msm_drv.o \
         msm_fb.o \
         msm_gem.o \
         msm_gem_prime.o \
         msm_gem_submit.o \
         msm_gpu.o \
+        msm_iommu.o \
         msm_ringbuffer.o
 
 msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
diff --git a/drivers/gpu/drm/msm/NOTES b/drivers/gpu/drm/msm/NOTES
index e036f6c1db94..9c4255b98021 100644
--- a/drivers/gpu/drm/msm/NOTES
+++ b/drivers/gpu/drm/msm/NOTES
@@ -4,7 +4,7 @@ In the current snapdragon SoC's, we have (at least) 3 different
 display controller blocks at play:
  + MDP3 - ?? seems to be what is on geeksphone peak device
  + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
- + MDSS - snapdragon 800
+ + MDP5 - snapdragon 800
 
 (I don't have a completely clear picture on which display controller
 maps to which part #)
@@ -46,6 +46,24 @@ and treat the MDP4 block's irq as "the" irq.  Even though the connectors
 may have their own irqs which they install themselves.  For this reason
 the display controller is the "master" device.
 
+For MDP5, the mapping is:
+
+  plane   -> PIPE{RGBn,VIGn}             \
+  crtc    -> LM (layer mixer)            |-> MDP "device"
+  encoder -> INTF                        /
+  connector -> HDMI/DSI/eDP/etc          --> other device(s)
+
+Unlike MDP4, it appears we can get by with a single encoder, rather
+than needing a different implementation for DTV, DSI, etc.  (Ie. the
+register interface is same, just different bases.)
+
+Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
+etc) are routed through MDP.
+
+And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
+which blocks need to be allocated to the active pipes based on fetch
+stride.
+
 Each connector probably ends up being a separate device, just for the
 logistics of finding/mapping io region, irq, etc.  Idealy we would
 have a better way than just stashing the platform device in a global
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 9588098741b5..85d615e7d62f 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  31003 bytes, from 2013-09-19 18:50:16)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9759 bytes, from 2013-09-10 00:52:33)
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51983 bytes, from 2013-09-10 00:52:32)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -202,6 +203,12 @@ enum a2xx_rb_copy_sample_select {
         SAMPLE_0123 = 6,
 };
 
+enum adreno_mmu_clnt_beh {
+        BEH_NEVR = 0,
+        BEH_TRAN_RNG = 1,
+        BEH_TRAN_FLT = 2,
+};
+
 enum sq_tex_clamp {
         SQ_TEX_WRAP = 0,
         SQ_TEX_MIRROR = 1,
@@ -238,6 +245,92 @@ enum sq_tex_filter {
 
 #define REG_A2XX_CP_PFP_UCODE_DATA                              0x000000c1
 
+#define REG_A2XX_MH_MMU_CONFIG                                  0x00000040
+#define A2XX_MH_MMU_CONFIG_MMU_ENABLE                           0x00000001
+#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE                    0x00000002
+#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK             0x00000030
+#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT            4
+static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK             0x000000c0
+#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT            6
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK            0x00000300
+#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT           8
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK            0x00000c00
+#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT           10
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK            0x00003000
+#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT           12
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK            0x0000c000
+#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT           14
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK            0x00030000
+#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT           16
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK           0x000c0000
+#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT          18
+static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK           0x00300000
+#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT          20
+static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK             0x00c00000
+#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT            22
+static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK             0x03000000
+#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT            24
+static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
+}
+
+#define REG_A2XX_MH_MMU_VA_RANGE                                0x00000041
+
+#define REG_A2XX_MH_MMU_PT_BASE                                 0x00000042
+
+#define REG_A2XX_MH_MMU_PAGE_FAULT                              0x00000043
+
+#define REG_A2XX_MH_MMU_TRAN_ERROR                              0x00000044
+
+#define REG_A2XX_MH_MMU_INVALIDATE                              0x00000045
+
+#define REG_A2XX_MH_MMU_MPU_BASE                                0x00000046
+
+#define REG_A2XX_MH_MMU_MPU_END                                 0x00000047
+
+#define REG_A2XX_NQWAIT_UNTIL                                   0x00000394
+
 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT                       0x00000395
 
 #define REG_A2XX_RBBM_PERFCOUNTER1_LO                           0x00000397
@@ -276,20 +369,6 @@ enum sq_tex_filter {
 
 #define REG_A2XX_CP_PERFCOUNTER_HI                              0x00000447
 
-#define REG_A2XX_CP_ST_BASE                                     0x0000044d
-
-#define REG_A2XX_CP_ST_BUFSZ                                    0x0000044e
-
-#define REG_A2XX_CP_IB1_BASE                                    0x00000458
-
-#define REG_A2XX_CP_IB1_BUFSZ                                   0x00000459
-
-#define REG_A2XX_CP_IB2_BASE                                    0x0000045a
-
-#define REG_A2XX_CP_IB2_BUFSZ                                   0x0000045b
-
-#define REG_A2XX_CP_STAT                                        0x0000047f
-
 #define REG_A2XX_RBBM_STATUS                                    0x000005d0
 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK                    0x0000001f
 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT                   0
@@ -808,6 +887,12 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
 
 #define REG_A2XX_SQ_VS_PROGRAM                                  0x000021f7
 
+#define REG_A2XX_VGT_EVENT_INITIATOR                            0x000021f9
+
+#define REG_A2XX_VGT_DRAW_INITIATOR                             0x000021fc
+
+#define REG_A2XX_VGT_IMMED_DATA                                 0x000021fd
+
 #define REG_A2XX_RB_DEPTHCONTROL                                0x00002200
 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE                     0x00000001
 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE                           0x00000002
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index d4afdf657559..a7be56163d23 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  31003 bytes, from 2013-09-19 18:50:16)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9759 bytes, from 2013-09-10 00:52:33)
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51983 bytes, from 2013-09-10 00:52:32)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -292,6 +293,8 @@ enum a3xx_tex_type {
 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC                          0x40000000
 #define A3XX_RBBM_STATUS_GPU_BUSY                               0x80000000
 
+#define REG_A3XX_RBBM_NQWAIT_UNTIL                              0x00000040
+
 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL                      0x00000033
 
 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL                    0x00000050
@@ -304,6 +307,8 @@ enum a3xx_tex_type {
 
 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3                  0x0000005a
 
+#define REG_A3XX_RBBM_INT_SET_CMD                               0x00000060
+
 #define REG_A3XX_RBBM_INT_CLEAR_CMD                             0x00000061
 
 #define REG_A3XX_RBBM_INT_0_MASK                                0x00000063
@@ -937,13 +942,13 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
         return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
 }
 
-#define REG_A3XX_UNKNOWN_20E8                                   0x000020e8
+#define REG_A3XX_RB_CLEAR_COLOR_DW0                             0x000020e8
 
-#define REG_A3XX_UNKNOWN_20E9                                   0x000020e9
+#define REG_A3XX_RB_CLEAR_COLOR_DW1                             0x000020e9
 
-#define REG_A3XX_UNKNOWN_20EA                                   0x000020ea
+#define REG_A3XX_RB_CLEAR_COLOR_DW2                             0x000020ea
 
-#define REG_A3XX_UNKNOWN_20EB                                   0x000020eb
+#define REG_A3XX_RB_CLEAR_COLOR_DW3                             0x000020eb
 
 #define REG_A3XX_RB_COPY_CONTROL                                0x000020ec
 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK                 0x00000003
@@ -1026,7 +1031,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE                         0x00000080
 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE                     0x80000000
 
-#define REG_A3XX_UNKNOWN_2101                                   0x00002101
+#define REG_A3XX_RB_DEPTH_CLEAR                                 0x00002101
 
 #define REG_A3XX_RB_DEPTH_INFO                                  0x00002102
 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000001
@@ -1103,11 +1108,11 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
         return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
 }
 
-#define REG_A3XX_UNKNOWN_2105                                   0x00002105
+#define REG_A3XX_RB_STENCIL_CLEAR                               0x00002105
 
-#define REG_A3XX_UNKNOWN_2106                                   0x00002106
+#define REG_A3XX_RB_STENCIL_BUF_INFO                            0x00002106
 
-#define REG_A3XX_UNKNOWN_2107                                   0x00002107
+#define REG_A3XX_RB_STENCIL_BUF_PITCH                           0x00002107
 
 #define REG_A3XX_RB_STENCILREFMASK                              0x00002108
 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
@@ -1149,20 +1154,31 @@ static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
         return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
 }
 
-#define REG_A3XX_PA_SC_WINDOW_OFFSET                            0x0000210e
-#define A3XX_PA_SC_WINDOW_OFFSET_X__MASK                        0x0000ffff
-#define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT                       0
-static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val)
+#define REG_A3XX_RB_LRZ_VSC_CONTROL                             0x0000210c
+#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE                  0x00000002
+
+#define REG_A3XX_RB_WINDOW_OFFSET                               0x0000210e
+#define A3XX_RB_WINDOW_OFFSET_X__MASK                           0x0000ffff
+#define A3XX_RB_WINDOW_OFFSET_X__SHIFT                          0
+static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
 {
-        return ((val) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK;
+        return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
 }
-#define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK                        0xffff0000
-#define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT                       16
-static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val)
+#define A3XX_RB_WINDOW_OFFSET_Y__MASK                           0xffff0000
+#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT                          16
+static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
 {
-        return ((val) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK;
+        return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
 }
 
+#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL                        0x00002110
+
+#define REG_A3XX_RB_SAMPLE_COUNT_ADDR                           0x00002111
+
+#define REG_A3XX_RB_Z_CLAMP_MIN                                 0x00002114
+
+#define REG_A3XX_RB_Z_CLAMP_MAX                                 0x00002115
+
 #define REG_A3XX_PC_VSTREAM_CONTROL                             0x000021e4
 
 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL                     0x000021ea
@@ -1309,6 +1325,8 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
 
 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG                     0x00002215
 
+#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG                     0x00002216
+
 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG                     0x00002217
 
 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG                          0x0000221a
@@ -1491,12 +1509,13 @@ static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0
 
 #define REG_A3XX_SP_SP_CTRL_REG                                 0x000022c0
 #define A3XX_SP_SP_CTRL_REG_RESOLVE                             0x00010000
-#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK                     0x000c0000
+#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK                     0x00040000
 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT                    18
 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
 {
         return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
 }
+#define A3XX_SP_SP_CTRL_REG_BINNING                             0x00080000
 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK                     0x00300000
 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT                    20
 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
@@ -1669,7 +1688,7 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 
 #define REG_A3XX_SP_VS_OBJ_START_REG                            0x000022d5
 
-#define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG                         0x000022d6
+#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG                        0x000022d6
 
 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG                         0x000022d7
 
@@ -1772,7 +1791,7 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 
 #define REG_A3XX_SP_FS_OBJ_START_REG                            0x000022e3
 
-#define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG                         0x000022e4
+#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG                        0x000022e4
 
 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG                         0x000022e5
 
@@ -1943,6 +1962,9 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00
 
 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
 
+#define REG_A3XX_VSC_BIN_CONTROL                                0x00000c3c
+#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE                     0x00000001
+
 #define REG_A3XX_UNKNOWN_0C3D                                   0x00000c3d
 
 #define REG_A3XX_PC_PERFCOUNTER0_SELECT                         0x00000c48
@@ -1953,7 +1975,7 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000
 
 #define REG_A3XX_PC_PERFCOUNTER3_SELECT                         0x00000c4b
 
-#define REG_A3XX_UNKNOWN_0C81                                   0x00000c81
+#define REG_A3XX_GRAS_TSE_DEBUG_ECO                             0x00000c81
 
 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT                       0x00000c88
 
@@ -1975,22 +1997,24 @@ static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x000
 
 #define REG_A3XX_RB_GMEM_BASE_ADDR                              0x00000cc0
 
+#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR                     0x00000cc1
+
 #define REG_A3XX_RB_PERFCOUNTER0_SELECT                         0x00000cc6
 
 #define REG_A3XX_RB_PERFCOUNTER1_SELECT                         0x00000cc7
 
-#define REG_A3XX_RB_WINDOW_SIZE                                 0x00000ce0
-#define A3XX_RB_WINDOW_SIZE_WIDTH__MASK                         0x00003fff
-#define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT                        0
-static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val)
+#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION                      0x00000ce0
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK              0x00003fff
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT             0
+static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
 {
-        return ((val) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK;
+        return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
 }
-#define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK                        0x0fffc000
-#define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT                       14
-static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val)
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK             0x0fffc000
+#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT            14
+static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
 {
-        return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK;
+        return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
 }
 
 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT                       0x00000e00
@@ -2088,6 +2112,14 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
 
 #define REG_A3XX_TP_PERFCOUNTER5_SELECT                         0x00000f09
 
+#define REG_A3XX_VGT_CL_INITIATOR                               0x000021f0
+
+#define REG_A3XX_VGT_EVENT_INITIATOR                            0x000021f9
+
+#define REG_A3XX_VGT_DRAW_INITIATOR                             0x000021fc
+
+#define REG_A3XX_VGT_IMMED_DATA                                 0x000021fd
+
 #define REG_A3XX_TEX_SAMP_0                                     0x00000000
 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR                        0x00000002
 #define A3XX_TEX_SAMP_0_XY_MAG__MASK                            0x0000000c
@@ -2123,6 +2155,18 @@ static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
 #define A3XX_TEX_SAMP_0_UNNORM_COORDS                           0x80000000
 
 #define REG_A3XX_TEX_SAMP_1                                     0x00000001
+#define A3XX_TEX_SAMP_1_MAX_LOD__MASK                           0x003ff000
+#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT                          12
+static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
+{
+        return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
+}
+#define A3XX_TEX_SAMP_1_MIN_LOD__MASK                           0xffc00000
+#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT                          22
+static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
+{
+        return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
+}
 
 #define REG_A3XX_TEX_CONST_0                                    0x00000000
 #define A3XX_TEX_CONST_0_TILED                                  0x00000001
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 035bd13dc8bd..461df93e825e 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -15,6 +15,10 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifdef CONFIG_MSM_OCMEM
+#  include <mach/ocmem.h>
+#endif
+
 #include "a3xx_gpu.h"
 
 #define A3XX_INT0_MASK \
@@ -63,6 +67,7 @@ static void a3xx_me_init(struct msm_gpu *gpu)
 static int a3xx_hw_init(struct msm_gpu *gpu)
 {
         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+        struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(adreno_gpu);
         uint32_t *ptr, len;
         int i, ret;
 
@@ -105,6 +110,21 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
                 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
                 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
 
+        } else if (adreno_is_a330v2(adreno_gpu)) {
+                /*
+                 * Most of the VBIF registers on 8974v2 have the correct
+                 * values at power on, so we won't modify those if we don't
+                 * need to
+                 */
+                /* Enable 1k sort: */
+                gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
+                gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
+                /* Enable WR-REQ: */
+                gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
+                gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
+                /* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
+                gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
+
         } else if (adreno_is_a330(adreno_gpu)) {
                 /* Set up 16 deep read/write request queues: */
                 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
@@ -121,10 +141,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
                 /* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
                 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
                 /* Set up AOOO: */
-                gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000ffff);
-                gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0xffffffff);
+                gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);
+                gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);
                 /* Enable 1K sort: */
-                gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001ffff);
+                gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
                 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
                 /* Disable VBIF clock gating. This is to enable AXI running
                  * higher frequency than GPU:
@@ -162,14 +182,23 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
         gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
 
         /* Enable Clock gating: */
-        gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
-
-        /* Set the OCMEM base address for A330 */
-//TODO:
-//      if (adreno_is_a330(adreno_gpu)) {
-//              gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
-//                      (unsigned int)(a3xx_gpu->ocmem_base >> 14));
-//      }
+        if (adreno_is_a320(adreno_gpu))
+                gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
+        else if (adreno_is_a330v2(adreno_gpu))
+                gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
+        else if (adreno_is_a330(adreno_gpu))
+                gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);
+
+        if (adreno_is_a330v2(adreno_gpu))
+                gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);
+        else if (adreno_is_a330(adreno_gpu))
+                gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);
+
+        /* Set the OCMEM base address for A330, etc */
+        if (a3xx_gpu->ocmem_hdl) {
+                gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
+                        (unsigned int)(a3xx_gpu->ocmem_base >> 14));
+        }
 
         /* Turn on performance counters: */
         gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);
@@ -219,7 +248,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
         /* Load PM4: */
         ptr = (uint32_t *)(adreno_gpu->pm4->data);
         len = adreno_gpu->pm4->size / 4;
-        DBG("loading PM4 ucode version: %u", ptr[0]);
+        DBG("loading PM4 ucode version: %x", ptr[1]);
 
         gpu_write(gpu, REG_AXXX_CP_DEBUG,
                         AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE |
@@ -231,19 +260,26 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
         /* Load PFP: */
         ptr = (uint32_t *)(adreno_gpu->pfp->data);
         len = adreno_gpu->pfp->size / 4;
-        DBG("loading PFP ucode version: %u", ptr[0]);
+        DBG("loading PFP ucode version: %x", ptr[5]);
 
         gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
         for (i = 1; i < len; i++)
                 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
 
         /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
-        if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu))
+        if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu)) {
                 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
                                 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
                                 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
                                 AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
-
+        } else if (adreno_is_a330(adreno_gpu)) {
+                /* NOTE: this (value take from downstream android driver)
+                 * includes some bits outside of the known bitfields.  But
+                 * A330 has this "MERCIU queue" thing too, which might
+                 * explain a new bitfield or reshuffling:
+                 */
+                gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);
+        }
 
         /* clear ME_HALT to start micro engine */
         gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
@@ -253,6 +289,14 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
         return 0;
 }
 
+static void a3xx_recover(struct msm_gpu *gpu)
+{
+        gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);
+        gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD);
+        gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);
+        adreno_recover(gpu);
+}
+
 static void a3xx_destroy(struct msm_gpu *gpu)
 {
         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -261,6 +305,12 @@ static void a3xx_destroy(struct msm_gpu *gpu)
         DBG("%s", gpu->name);
 
         adreno_gpu_cleanup(adreno_gpu);
+
+#ifdef CONFIG_MSM_OCMEM
+        if (a3xx_gpu->ocmem_base)
+                ocmem_free(OCMEM_GRAPHICS, a3xx_gpu->ocmem_hdl);
+#endif
+
         put_device(&a3xx_gpu->pdev->dev);
         kfree(a3xx_gpu);
 }
@@ -371,7 +421,7 @@ static const struct adreno_gpu_funcs funcs = {
                 .hw_init = a3xx_hw_init,
                 .pm_suspend = msm_gpu_pm_suspend,
                 .pm_resume = msm_gpu_pm_resume,
-                .recover = adreno_recover,
+                .recover = a3xx_recover,
                 .last_fence = adreno_last_fence,
                 .submit = adreno_submit,
                 .flush = adreno_flush,
@@ -387,6 +437,7 @@ static const struct adreno_gpu_funcs funcs = {
 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
 {
         struct a3xx_gpu *a3xx_gpu = NULL;
+        struct adreno_gpu *adreno_gpu;
         struct msm_gpu *gpu;
         struct platform_device *pdev = a3xx_pdev;
         struct adreno_platform_config *config;
@@ -406,7 +457,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
                 goto fail;
         }
 
-        gpu = &a3xx_gpu->base.base;
+        adreno_gpu = &a3xx_gpu->base;
+        gpu = &adreno_gpu->base;
 
         get_device(&pdev->dev);
         a3xx_gpu->pdev = pdev;
@@ -414,16 +466,46 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
         gpu->fast_rate = config->fast_rate;
         gpu->slow_rate = config->slow_rate;
         gpu->bus_freq  = config->bus_freq;
+#ifdef CONFIG_MSM_BUS_SCALING
+        gpu->bus_scale_table = config->bus_scale_table;
+#endif
 
         DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
                         gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
 
-        ret = adreno_gpu_init(dev, pdev, &a3xx_gpu->base,
-                        &funcs, config->rev);
+        ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, config->rev);
         if (ret)
                 goto fail;
 
-        return &a3xx_gpu->base.base;
+        /* if needed, allocate gmem: */
+        if (adreno_is_a330(adreno_gpu)) {
+#ifdef CONFIG_MSM_OCMEM
+                /* TODO this is different/missing upstream: */
+                struct ocmem_buf *ocmem_hdl =
+                                ocmem_allocate(OCMEM_GRAPHICS, adreno_gpu->gmem);
+
+                a3xx_gpu->ocmem_hdl = ocmem_hdl;
+                a3xx_gpu->ocmem_base = ocmem_hdl->addr;
+                adreno_gpu->gmem = ocmem_hdl->len;
+                DBG("using %dK of OCMEM at 0x%08x", adreno_gpu->gmem / 1024,
+                                a3xx_gpu->ocmem_base);
+#endif
+        }
+
+        if (!gpu->mmu) {
+                /* TODO we think it is possible to configure the GPU to
+                 * restrict access to VRAM carveout.  But the required
+                 * registers are unknown.  For now just bail out and
+                 * limp along with just modesetting.  If it turns out
+                 * to not be possible to restrict access, then we must
+                 * implement a cmdstream validator.
+                 */
+                dev_err(dev->dev, "No memory protection without IOMMU\n");
+                ret = -ENXIO;
+                goto fail;
+        }
+
+        return gpu;
 
 fail:
         if (a3xx_gpu)
@@ -436,19 +518,59 @@ fail:
  * The a3xx device:
  */
 
+#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
+#  include <mach/kgsl.h>
+#endif
+
 static int a3xx_probe(struct platform_device *pdev)
 {
         static struct adreno_platform_config config = {};
 #ifdef CONFIG_OF
-        /* TODO */
+        struct device_node *child, *node = pdev->dev.of_node;
+        u32 val;
+        int ret;
+
+        ret = of_property_read_u32(node, "qcom,chipid", &val);
+        if (ret) {
+                dev_err(&pdev->dev, "could not find chipid: %d\n", ret);
+                return ret;
+        }
+
+        config.rev = ADRENO_REV((val >> 24) & 0xff,
+                        (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
+
+        /* find clock rates: */
+        config.fast_rate = 0;
+        config.slow_rate = ~0;
+        for_each_child_of_node(node, child) {
+                if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
+                        struct device_node *pwrlvl;
+                        for_each_child_of_node(child, pwrlvl) {
+                                ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
+                                if (ret) {
+                                        dev_err(&pdev->dev, "could not find gpu-freq: %d\n", ret);
+                                        return ret;
+                                }
+                                config.fast_rate = max(config.fast_rate, val);
+                                config.slow_rate = min(config.slow_rate, val);
+                        }
+                }
+        }
+
+        if (!config.fast_rate) {
+                dev_err(&pdev->dev, "could not find clk rates\n");
+                return -ENXIO;
+        }
+
 #else
+        struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
         uint32_t version = socinfo_get_version();
         if (cpu_is_apq8064ab()) {
                 config.fast_rate = 450000000;
                 config.slow_rate = 27000000;
                 config.bus_freq  = 4;
                 config.rev = ADRENO_REV(3, 2, 1, 0);
-        } else if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
+        } else if (cpu_is_apq8064()) {
                 config.fast_rate = 400000000;
                 config.slow_rate = 27000000;
                 config.bus_freq  = 4;
@@ -461,6 +583,16 @@ static int a3xx_probe(struct platform_device *pdev)
                 else
                         config.rev = ADRENO_REV(3, 2, 0, 0);
 
+        } else if (cpu_is_msm8960ab()) {
+                config.fast_rate = 400000000;
+                config.slow_rate = 320000000;
+                config.bus_freq  = 4;
+
+                if (SOCINFO_VERSION_MINOR(version) == 0)
+                        config.rev = ADRENO_REV(3, 2, 1, 0);
+                else
+                        config.rev = ADRENO_REV(3, 2, 1, 1);
+
         } else if (cpu_is_msm8930()) {
                 config.fast_rate = 400000000;
                 config.slow_rate = 27000000;
@@ -473,6 +605,9 @@ static int a3xx_probe(struct platform_device *pdev)
                         config.rev = ADRENO_REV(3, 0, 5, 0);
 
         }
+#  ifdef CONFIG_MSM_BUS_SCALING
+        config.bus_scale_table = pdata->bus_scale_table;
+#  endif
 #endif
         pdev->dev.platform_data = &config;
         a3xx_pdev = pdev;
@@ -485,10 +620,19 @@ static int a3xx_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id dt_match[] = {
+        { .compatible = "qcom,kgsl-3d0" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, dt_match);
+
 static struct platform_driver a3xx_driver = {
         .probe = a3xx_probe,
         .remove = a3xx_remove,
-        .driver.name = "kgsl-3d0",
+        .driver = {
+                .name = "kgsl-3d0",
+                .of_match_table = dt_match,
+        },
 };
 
 void __init a3xx_register(void)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h
index 32c398c2d00a..bb9a8ca0507b 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h
@@ -24,6 +24,10 @@
 struct a3xx_gpu {
         struct adreno_gpu base;
         struct platform_device *pdev;
+
+        /* if OCMEM is used for GMEM: */
+        uint32_t ocmem_base;
+        void *ocmem_hdl;
 };
 #define to_a3xx_gpu(x) container_of(x, struct a3xx_gpu, base)
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index 33dcc606c7c5..d6e6ce2d1abd 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  31003 bytes, from 2013-09-19 18:50:16)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9759 bytes, from 2013-09-10 00:52:33)
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51983 bytes, from 2013-09-10 00:52:32)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -115,96 +116,6 @@ enum adreno_rb_depth_format {
         DEPTHX_24_8 = 1,
 };
 
-enum adreno_mmu_clnt_beh {
-        BEH_NEVR = 0,
-        BEH_TRAN_RNG = 1,
-        BEH_TRAN_FLT = 2,
-};
-
-#define REG_AXXX_MH_MMU_CONFIG                                  0x00000040
-#define AXXX_MH_MMU_CONFIG_MMU_ENABLE                           0x00000001
-#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE                    0x00000002
-#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK             0x00000030
-#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT            4
-static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK             0x000000c0
-#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT            6
-static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK            0x00000300
-#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT           8
-static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK            0x00000c00
-#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT           10
-static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK            0x00003000
-#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT           12
-static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK            0x0000c000
-#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT           14
-static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK            0x00030000
-#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT           16
-static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK           0x000c0000
-#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT          18
-static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK           0x00300000
-#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT          20
-static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK             0x00c00000
-#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT            22
-static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
-}
-#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK             0x03000000
-#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT            24
-static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-        return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
-}
-
-#define REG_AXXX_MH_MMU_VA_RANGE                                0x00000041
-
-#define REG_AXXX_MH_MMU_PT_BASE                                 0x00000042
-
-#define REG_AXXX_MH_MMU_PAGE_FAULT                              0x00000043
-
-#define REG_AXXX_MH_MMU_TRAN_ERROR                              0x00000044
-
-#define REG_AXXX_MH_MMU_INVALIDATE                              0x00000045
-
-#define REG_AXXX_MH_MMU_MPU_BASE                                0x00000046
-
-#define REG_AXXX_MH_MMU_MPU_END                                 0x00000047
-
 #define REG_AXXX_CP_RB_BASE                                     0x000001c0
 
 #define REG_AXXX_CP_RB_CNTL                                     0x000001c1
@@ -275,6 +186,18 @@ static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
 }
 
 #define REG_AXXX_CP_MEQ_THRESHOLDS                              0x000001d6
+#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK                    0x001f0000
+#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT                   16
+static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
+{
+        return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
+}
+#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK                    0x1f000000
+#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT                   24
+static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
+{
+        return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
+}
 
 #define REG_AXXX_CP_CSQ_AVAIL                                   0x000001d7
 #define AXXX_CP_CSQ_AVAIL_RING__MASK                            0x0000007f
@@ -402,6 +325,36 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
         return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
 }
 
+#define REG_AXXX_CP_NON_PREFETCH_CNTRS                          0x00000440
+
+#define REG_AXXX_CP_STQ_ST_STAT                                 0x00000443
+
+#define REG_AXXX_CP_ST_BASE                                     0x0000044d
+
+#define REG_AXXX_CP_ST_BUFSZ                                    0x0000044e
+
+#define REG_AXXX_CP_MEQ_STAT                                    0x0000044f
+
+#define REG_AXXX_CP_MIU_TAG_STAT                                0x00000452
+
+#define REG_AXXX_CP_BIN_MASK_LO                                 0x00000454
+
+#define REG_AXXX_CP_BIN_MASK_HI                                 0x00000455
+
+#define REG_AXXX_CP_BIN_SELECT_LO                               0x00000456
+
+#define REG_AXXX_CP_BIN_SELECT_HI                               0x00000457
+
+#define REG_AXXX_CP_IB1_BASE                                    0x00000458
+
+#define REG_AXXX_CP_IB1_BUFSZ                                   0x00000459
+
+#define REG_AXXX_CP_IB2_BASE                                    0x0000045a
+
+#define REG_AXXX_CP_IB2_BUFSZ                                   0x0000045b
+
+#define REG_AXXX_CP_STAT                                        0x0000047f
+
 #define REG_AXXX_CP_SCRATCH_REG0                                0x00000578
 
 #define REG_AXXX_CP_SCRATCH_REG1                                0x00000579
@@ -418,6 +371,26 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
 
 #define REG_AXXX_CP_SCRATCH_REG7                                0x0000057f
 
+#define REG_AXXX_CP_ME_VS_EVENT_SRC                             0x00000600
+
+#define REG_AXXX_CP_ME_VS_EVENT_ADDR                            0x00000601
+
+#define REG_AXXX_CP_ME_VS_EVENT_DATA                            0x00000602
+
+#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM                        0x00000603
+
+#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM                        0x00000604
+
+#define REG_AXXX_CP_ME_PS_EVENT_SRC                             0x00000605
+
+#define REG_AXXX_CP_ME_PS_EVENT_ADDR                            0x00000606
+
+#define REG_AXXX_CP_ME_PS_EVENT_DATA                            0x00000607
+
+#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM                        0x00000608
+
+#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM                        0x00000609
+
 #define REG_AXXX_CP_ME_CF_EVENT_SRC                             0x0000060a
 
 #define REG_AXXX_CP_ME_CF_EVENT_ADDR                            0x0000060b
@@ -428,5 +401,11 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
 
 #define REG_AXXX_CP_ME_NRT_DATA                                 0x0000060e
 
+#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC                        0x00000612
+
+#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR                       0x00000613
+
+#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA                       0x00000614
+
 
 #endif /* ADRENO_COMMON_XML */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index a0b9d8a95b16..d321099abdd4 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -17,6 +17,7 @@
 
 #include "adreno_gpu.h"
 #include "msm_gem.h"
+#include "msm_mmu.h"
 
 struct adreno_info {
         struct adreno_rev rev;
@@ -44,7 +45,7 @@ static const struct adreno_info gpulist[] = {
                 .pfpfw = "a300_pfp.fw",
                 .gmem  = SZ_512K,
         }, {
-                .rev   = ADRENO_REV(3, 3, 0, 0),
+                .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
                 .revn  = 330,
                 .name  = "A330",
                 .pm4fw = "a330_pm4.fw",
@@ -53,6 +54,11 @@ static const struct adreno_info gpulist[] = {
         },
 };
 
+MODULE_FIRMWARE("a300_pm4.fw");
+MODULE_FIRMWARE("a300_pfp.fw");
+MODULE_FIRMWARE("a330_pm4.fw");
+MODULE_FIRMWARE("a330_pfp.fw");
+
 #define RB_SIZE    SZ_32K
 #define RB_BLKSIZE 16
 
@@ -65,7 +71,7 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
                 *value = adreno_gpu->info->revn;
                 return 0;
         case MSM_PARAM_GMEM_SIZE:
-                *value = adreno_gpu->info->gmem;
+                *value = adreno_gpu->gmem;
                 return 0;
         default:
                 DBG("%s: invalid param: %u", gpu->name, param);
@@ -86,7 +92,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
         gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
                         /* size is log2(quad-words): */
                         AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
-                        AXXX_CP_RB_CNTL_BLKSZ(RB_BLKSIZE));
+                        AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
 
         /* Setup ringbuffer address: */
         gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
@@ -286,6 +292,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
                 struct adreno_rev rev)
 {
+        struct msm_mmu *mmu;
         int i, ret;
 
         /* identify gpu: */
@@ -311,6 +318,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                         rev.core, rev.major, rev.minor, rev.patchid);
 
         gpu->funcs = funcs;
+        gpu->gmem = gpu->info->gmem;
         gpu->rev = rev;
 
         ret = request_firmware(&gpu->pm4, gpu->info->pm4fw, drm->dev);
@@ -333,10 +341,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
         if (ret)
                 return ret;
 
-        ret = msm_iommu_attach(drm, gpu->base.iommu,
-                        iommu_ports, ARRAY_SIZE(iommu_ports));
-        if (ret)
-                return ret;
+        mmu = gpu->base.mmu;
+        if (mmu) {
+                ret = mmu->funcs->attach(mmu, iommu_ports,
+                                ARRAY_SIZE(iommu_ports));
+                if (ret)
+                        return ret;
+        }
 
         gpu->memptrs_bo = msm_gem_new(drm, sizeof(*gpu->memptrs),
                         MSM_BO_UNCACHED);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index f73abfba7c22..ca11ea4da165 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -51,6 +51,7 @@ struct adreno_gpu {
         struct msm_gpu base;
         struct adreno_rev rev;
         const struct adreno_info *info;
+        uint32_t gmem;  /* actual gmem size */
         uint32_t revn;  /* numeric revision name */
         const struct adreno_gpu_funcs *funcs;
 
@@ -70,6 +71,9 @@ struct adreno_gpu {
 struct adreno_platform_config {
         struct adreno_rev rev;
         uint32_t fast_rate, slow_rate, bus_freq;
+#ifdef CONFIG_MSM_BUS_SCALING
+        struct msm_bus_scale_pdata *bus_scale_table;
+#endif
 };
 
 #define ADRENO_IDLE_TIMEOUT (20 * 1000)
@@ -94,6 +98,11 @@ static inline bool adreno_is_a330(struct adreno_gpu *gpu)
         return gpu->revn == 330;
 }
 
+static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
+{
+        return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
+}
+
 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
 int adreno_hw_init(struct msm_gpu *gpu);
 uint32_t adreno_last_fence(struct msm_gpu *gpu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index 259ad709b0cc..ae992c71703f 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  31003 bytes, from 2013-09-19 18:50:16)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9759 bytes, from 2013-09-10 00:52:33)
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51983 bytes, from 2013-09-10 00:52:32)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -66,13 +67,15 @@ enum vgt_event_type {
 
 enum pc_di_primtype {
         DI_PT_NONE = 0,
-        DI_PT_POINTLIST = 1,
+        DI_PT_POINTLIST_A2XX = 1,
         DI_PT_LINELIST = 2,
         DI_PT_LINESTRIP = 3,
         DI_PT_TRILIST = 4,
         DI_PT_TRIFAN = 5,
         DI_PT_TRISTRIP = 6,
+        DI_PT_LINELOOP = 7,
         DI_PT_RECTLIST = 8,
+        DI_PT_POINTLIST_A3XX = 9,
         DI_PT_QUADLIST = 13,
         DI_PT_QUADSTRIP = 14,
         DI_PT_POLYGON = 15,
@@ -119,7 +122,7 @@ enum adreno_pm4_type3_packets {
         CP_WAIT_FOR_IDLE = 38,
         CP_WAIT_REG_MEM = 60,
         CP_WAIT_REG_EQ = 82,
-        CP_WAT_REG_GTE = 83,
+        CP_WAIT_REG_GTE = 83,
         CP_WAIT_UNTIL_READ = 92,
         CP_WAIT_IB_PFD_COMPLETE = 93,
         CP_REG_RMW = 33,
@@ -151,7 +154,6 @@ enum adreno_pm4_type3_packets {
         CP_CONTEXT_UPDATE = 94,
         CP_INTERRUPT = 64,
         CP_IM_STORE = 44,
-        CP_SET_BIN_BASE_OFFSET = 75,
         CP_SET_DRAW_INIT_FLAGS = 75,
         CP_SET_PROTECTED_MODE = 95,
         CP_LOAD_STATE = 48,
@@ -159,6 +161,16 @@ enum adreno_pm4_type3_packets {
         CP_COND_INDIRECT_BUFFER_PFD = 50,
         CP_INDIRECT_BUFFER_PFE = 63,
         CP_SET_BIN = 76,
+        CP_TEST_TWO_MEMS = 113,
+        CP_WAIT_FOR_ME = 19,
+        IN_IB_PREFETCH_END = 23,
+        IN_SUBBLK_PREFETCH = 31,
+        IN_INSTR_PREFETCH = 32,
+        IN_INSTR_MATCH = 71,
+        IN_CONST_PREFETCH = 73,
+        IN_INCR_UPDT_STATE = 85,
+        IN_INCR_UPDT_CONST = 86,
+        IN_INCR_UPDT_INSTR = 87,
 };
 
 enum adreno_state_block {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 6d4c62bf70dc..87be647e3825 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
index d1df38bf5747..747a6ef4211f 100644
--- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
index 0030a111302d..48e03acf19bf 100644
--- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
+++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 50d11df35b21..6f1588aa9071 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -41,7 +41,7 @@ void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
                         power_on ? "Enable" : "Disable", ctrl);
 }
 
-static irqreturn_t hdmi_irq(int irq, void *dev_id)
+irqreturn_t hdmi_irq(int irq, void *dev_id)
 {
         struct hdmi *hdmi = dev_id;
 
@@ -71,13 +71,13 @@ void hdmi_destroy(struct kref *kref)
 }
 
 /* initialize connector */
-int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
+struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
 {
         struct hdmi *hdmi = NULL;
         struct msm_drm_private *priv = dev->dev_private;
         struct platform_device *pdev = hdmi_pdev;
         struct hdmi_platform_config *config;
-        int ret;
+        int i, ret;
 
         if (!pdev) {
                 dev_err(dev->dev, "no hdmi device\n");
@@ -99,6 +99,7 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
 
         hdmi->dev = dev;
         hdmi->pdev = pdev;
+        hdmi->config = config;
         hdmi->encoder = encoder;
 
         /* not sure about which phy maps to which msm.. probably I miss some */
@@ -114,44 +115,70 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
                 goto fail;
         }
 
-        hdmi->mmio = msm_ioremap(pdev, "hdmi_msm_hdmi_addr", "HDMI");
+        hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI");
         if (IS_ERR(hdmi->mmio)) {
                 ret = PTR_ERR(hdmi->mmio);
                 goto fail;
         }
 
-        hdmi->mvs = devm_regulator_get(&pdev->dev, "8901_hdmi_mvs");
-        if (IS_ERR(hdmi->mvs))
-                hdmi->mvs = devm_regulator_get(&pdev->dev, "hdmi_mvs");
-        if (IS_ERR(hdmi->mvs)) {
-                ret = PTR_ERR(hdmi->mvs);
-                dev_err(dev->dev, "failed to get mvs regulator: %d\n", ret);
-                goto fail;
+        BUG_ON(config->hpd_reg_cnt > ARRAY_SIZE(hdmi->hpd_regs));
+        for (i = 0; i < config->hpd_reg_cnt; i++) {
+                struct regulator *reg;
+
+                reg = devm_regulator_get(&pdev->dev, config->hpd_reg_names[i]);
+                if (IS_ERR(reg)) {
+                        ret = PTR_ERR(reg);
+                        dev_err(dev->dev, "failed to get hpd regulator: %s (%d)\n",
+                                        config->hpd_reg_names[i], ret);
+                        goto fail;
+                }
+
+                hdmi->hpd_regs[i] = reg;
         }
 
-        hdmi->mpp0 = devm_regulator_get(&pdev->dev, "8901_mpp0");
-        if (IS_ERR(hdmi->mpp0))
-                hdmi->mpp0 = NULL;
+        BUG_ON(config->pwr_reg_cnt > ARRAY_SIZE(hdmi->pwr_regs));
+        for (i = 0; i < config->pwr_reg_cnt; i++) {
+                struct regulator *reg;
 
-        hdmi->clk = devm_clk_get(&pdev->dev, "core_clk");
-        if (IS_ERR(hdmi->clk)) {
-                ret = PTR_ERR(hdmi->clk);
-                dev_err(dev->dev, "failed to get 'clk': %d\n", ret);
-                goto fail;
+                reg = devm_regulator_get(&pdev->dev, config->pwr_reg_names[i]);
+                if (IS_ERR(reg)) {
+                        ret = PTR_ERR(reg);
+                        dev_err(dev->dev, "failed to get pwr regulator: %s (%d)\n",
+                                        config->pwr_reg_names[i], ret);
+                        goto fail;
+                }
+
+                hdmi->pwr_regs[i] = reg;
         }
 
-        hdmi->m_pclk = devm_clk_get(&pdev->dev, "master_iface_clk");
-        if (IS_ERR(hdmi->m_pclk)) {
-                ret = PTR_ERR(hdmi->m_pclk);
-                dev_err(dev->dev, "failed to get 'm_pclk': %d\n", ret);
-                goto fail;
+        BUG_ON(config->hpd_clk_cnt > ARRAY_SIZE(hdmi->hpd_clks));
+        for (i = 0; i < config->hpd_clk_cnt; i++) {
+                struct clk *clk;
+
+                clk = devm_clk_get(&pdev->dev, config->hpd_clk_names[i]);
+                if (IS_ERR(clk)) {
+                        ret = PTR_ERR(clk);
+                        dev_err(dev->dev, "failed to get hpd clk: %s (%d)\n",
+                                        config->hpd_clk_names[i], ret);
+                        goto fail;
+                }
+
+                hdmi->hpd_clks[i] = clk;
         }
 
-        hdmi->s_pclk = devm_clk_get(&pdev->dev, "slave_iface_clk");
-        if (IS_ERR(hdmi->s_pclk)) {
-                ret = PTR_ERR(hdmi->s_pclk);
-                dev_err(dev->dev, "failed to get 's_pclk': %d\n", ret);
-                goto fail;
+        BUG_ON(config->pwr_clk_cnt > ARRAY_SIZE(hdmi->pwr_clks));
+        for (i = 0; i < config->pwr_clk_cnt; i++) {
+                struct clk *clk;
+
+                clk = devm_clk_get(&pdev->dev, config->pwr_clk_names[i]);
+                if (IS_ERR(clk)) {
+                        ret = PTR_ERR(clk);
+                        dev_err(dev->dev, "failed to get pwr clk: %s (%d)\n",
+                                        config->pwr_clk_names[i], ret);
+                        goto fail;
+                }
+
+                hdmi->pwr_clks[i] = clk;
         }
 
         hdmi->i2c = hdmi_i2c_init(hdmi);
@@ -178,20 +205,22 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
                 goto fail;
         }
 
-        hdmi->irq = platform_get_irq(pdev, 0);
-        if (hdmi->irq < 0) {
-                ret = hdmi->irq;
-                dev_err(dev->dev, "failed to get irq: %d\n", ret);
-                goto fail;
-        }
+        if (!config->shared_irq) {
+                hdmi->irq = platform_get_irq(pdev, 0);
+                if (hdmi->irq < 0) {
+                        ret = hdmi->irq;
+                        dev_err(dev->dev, "failed to get irq: %d\n", ret);
+                        goto fail;
+                }
 
-        ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq,
-                        NULL, hdmi_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-                        "hdmi_isr", hdmi);
-        if (ret < 0) {
-                dev_err(dev->dev, "failed to request IRQ%u: %d\n",
-                                hdmi->irq, ret);
-                goto fail;
+                ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq,
+                                NULL, hdmi_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+                                "hdmi_isr", hdmi);
+                if (ret < 0) {
+                        dev_err(dev->dev, "failed to request IRQ%u: %d\n",
+                                        hdmi->irq, ret);
+                        goto fail;
+                }
         }
 
         encoder->bridge = hdmi->bridge;
@@ -199,7 +228,7 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
         priv->bridges[priv->num_bridges++]       = hdmi->bridge;
         priv->connectors[priv->num_connectors++] = hdmi->connector;
 
-        return 0;
+        return hdmi;
 
 fail:
         if (hdmi) {
@@ -211,37 +240,100 @@ fail:
                 hdmi_destroy(&hdmi->refcount);
         }
 
-        return ret;
+        return ERR_PTR(ret);
 }
 
 /*
  * The hdmi device:
  */
 
+#include <linux/of_gpio.h>
+
 static int hdmi_dev_probe(struct platform_device *pdev)
 {
         static struct hdmi_platform_config config = {};
 #ifdef CONFIG_OF
-        /* TODO */
+        struct device_node *of_node = pdev->dev.of_node;
+
+        int get_gpio(const char *name)
+        {
+                int gpio = of_get_named_gpio(of_node, name, 0);
+                if (gpio < 0) {
+                        dev_err(&pdev->dev, "failed to get gpio: %s (%d)\n",
+                                        name, gpio);
+                        gpio = -1;
+                }
+                return gpio;
+        }
+
+        /* TODO actually use DT.. */
+        static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v"};
+        static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"};
+        static const char *hpd_clk_names[] = {"iface_clk", "core_clk", "mdp_core_clk"};
+        static const char *pwr_clk_names[] = {"extp_clk", "alt_iface_clk"};
+
+        config.phy_init      = hdmi_phy_8x74_init;
+        config.mmio_name     = "core_physical";
+        config.hpd_reg_names = hpd_reg_names;
+        config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);
+        config.pwr_reg_names = pwr_reg_names;
+        config.pwr_reg_cnt   = ARRAY_SIZE(pwr_reg_names);
+        config.hpd_clk_names = hpd_clk_names;
+        config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
+        config.pwr_clk_names = pwr_clk_names;
+        config.pwr_clk_cnt   = ARRAY_SIZE(pwr_clk_names);
+        config.ddc_clk_gpio  = get_gpio("qcom,hdmi-tx-ddc-clk");
+        config.ddc_data_gpio = get_gpio("qcom,hdmi-tx-ddc-data");
+        config.hpd_gpio      = get_gpio("qcom,hdmi-tx-hpd");
+        config.mux_en_gpio   = get_gpio("qcom,hdmi-tx-mux-en");
+        config.mux_sel_gpio  = get_gpio("qcom,hdmi-tx-mux-sel");
+        config.shared_irq    = true;
+
 #else
+        static const char *hpd_clk_names[] = {
+                        "core_clk", "master_iface_clk", "slave_iface_clk",
+        };
         if (cpu_is_apq8064()) {
+                static const char *hpd_reg_names[] = {"8921_hdmi_mvs"};
                 config.phy_init      = hdmi_phy_8960_init;
+                config.mmio_name     = "hdmi_msm_hdmi_addr";
+                config.hpd_reg_names = hpd_reg_names;
+                config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);
+                config.hpd_clk_names = hpd_clk_names;
+                config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
                 config.ddc_clk_gpio  = 70;
                 config.ddc_data_gpio = 71;
                 config.hpd_gpio      = 72;
-                config.pmic_gpio     = 13 + NR_GPIO_IRQS;
-        } else if (cpu_is_msm8960()) {
+                config.mux_en_gpio   = -1;
+                config.mux_sel_gpio  = 13 + NR_GPIO_IRQS;
+        } else if (cpu_is_msm8960() || cpu_is_msm8960ab()) {
+                static const char *hpd_reg_names[] = {"8921_hdmi_mvs"};
                 config.phy_init      = hdmi_phy_8960_init;
+                config.mmio_name     = "hdmi_msm_hdmi_addr";
+                config.hpd_reg_names = hpd_reg_names;
+                config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);
+                config.hpd_clk_names = hpd_clk_names;
+                config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
                 config.ddc_clk_gpio  = 100;
                 config.ddc_data_gpio = 101;
                 config.hpd_gpio      = 102;
-                config.pmic_gpio     = -1;
+                config.mux_en_gpio   = -1;
+                config.mux_sel_gpio  = -1;
         } else if (cpu_is_msm8x60()) {
+                static const char *hpd_reg_names[] = {
+                                "8901_hdmi_mvs", "8901_mpp0"
+                };
                 config.phy_init      = hdmi_phy_8x60_init;
+                config.mmio_name     = "hdmi_msm_hdmi_addr";
+                config.hpd_reg_names = hpd_reg_names;
+                config.hpd_reg_cnt   = ARRAY_SIZE(hpd_reg_names);
+                config.hpd_clk_names = hpd_clk_names;
+                config.hpd_clk_cnt   = ARRAY_SIZE(hpd_clk_names);
                 config.ddc_clk_gpio  = 170;
                 config.ddc_data_gpio = 171;
                 config.hpd_gpio      = 172;
-                config.pmic_gpio     = -1;
+                config.mux_en_gpio   = -1;
+                config.mux_sel_gpio  = -1;
         }
 #endif
         pdev->dev.platform_data = &config;
@@ -255,10 +347,19 @@ static int hdmi_dev_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id dt_match[] = {
+        { .compatible = "qcom,hdmi-tx" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, dt_match);
+
 static struct platform_driver hdmi_driver = {
         .probe = hdmi_dev_probe,
         .remove = hdmi_dev_remove,
-        .driver.name = "hdmi_msm",
+        .driver = {
+                .name = "hdmi_msm",
+                .of_match_table = dt_match,
+        },
 };
 
 void __init hdmi_register(void)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index 2c2ec566394c..41b29add70b1 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -28,6 +28,7 @@
 
 
 struct hdmi_phy;
+struct hdmi_platform_config;
 
 struct hdmi {
         struct kref refcount;
@@ -35,14 +36,14 @@ struct hdmi {
         struct drm_device *dev;
         struct platform_device *pdev;
 
-        void __iomem *mmio;
+        const struct hdmi_platform_config *config;
 
-        struct regulator *mvs;        /* HDMI_5V */
-        struct regulator *mpp0;       /* External 5V */
+        void __iomem *mmio;
 
-        struct clk *clk;
-        struct clk *m_pclk;
-        struct clk *s_pclk;
+        struct regulator *hpd_regs[2];
+        struct regulator *pwr_regs[2];
+        struct clk *hpd_clks[3];
+        struct clk *pwr_clks[2];
 
         struct hdmi_phy *phy;
         struct i2c_adapter *i2c;
@@ -60,7 +61,29 @@ struct hdmi {
 /* platform config data (ie. from DT, or pdata) */
 struct hdmi_platform_config {
         struct hdmi_phy *(*phy_init)(struct hdmi *hdmi);
-        int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, pmic_gpio;
+        const char *mmio_name;
+
+        /* regulators that need to be on for hpd: */
+        const char **hpd_reg_names;
+        int hpd_reg_cnt;
+
+        /* regulators that need to be on for screen pwr: */
+        const char **pwr_reg_names;
+        int pwr_reg_cnt;
+
+        /* clks that need to be on for hpd: */
+        const char **hpd_clk_names;
+        int hpd_clk_cnt;
+
+        /* clks that need to be on for screen pwr (ie pixel clk): */
+        const char **pwr_clk_names;
+        int pwr_clk_cnt;
+
+        /* gpio's: */
+        int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, mux_en_gpio, mux_sel_gpio;
+
+        /* older devices had their own irq, mdp5+ it is shared w/ mdp: */
+        bool shared_irq;
 };
 
 void hdmi_set_mode(struct hdmi *hdmi, bool power_on);
@@ -106,6 +129,7 @@ struct hdmi_phy {
 
 struct hdmi_phy *hdmi_phy_8960_init(struct hdmi *hdmi);
 struct hdmi_phy *hdmi_phy_8x60_init(struct hdmi *hdmi);
+struct hdmi_phy *hdmi_phy_8x74_init(struct hdmi *hdmi);
 
 /*
  * hdmi bridge:
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 4e939f82918c..e2636582cfd7 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -212,6 +214,20 @@ static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state
 #define REG_HDMI_HDCP_RESET                                     0x00000130
 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE                    0x00000001
 
+#define REG_HDMI_VENSPEC_INFO0                                  0x0000016c
+
+#define REG_HDMI_VENSPEC_INFO1                                  0x00000170
+
+#define REG_HDMI_VENSPEC_INFO2                                  0x00000174
+
+#define REG_HDMI_VENSPEC_INFO3                                  0x00000178
+
+#define REG_HDMI_VENSPEC_INFO4                                  0x0000017c
+
+#define REG_HDMI_VENSPEC_INFO5                                  0x00000180
+
+#define REG_HDMI_VENSPEC_INFO6                                  0x00000184
+
 #define REG_HDMI_AUDIO_CFG                                      0x000001d0
 #define HDMI_AUDIO_CFG_ENGINE_ENABLE                            0x00000001
 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK                     0x000000f0
@@ -235,6 +251,9 @@ static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
         return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
 }
 
+#define REG_HDMI_DDC_ARBITRATION                                0x00000210
+#define HDMI_DDC_ARBITRATION_HW_ARBITRATION                     0x00000010
+
 #define REG_HDMI_DDC_INT_CTRL                                   0x00000214
 #define HDMI_DDC_INT_CTRL_SW_DONE_INT                           0x00000001
 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK                           0x00000002
@@ -340,6 +359,20 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
         return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
 }
 
+#define REG_HDMI_CEC_STATUS                                     0x00000298
+
+#define REG_HDMI_CEC_INT                                        0x0000029c
+
+#define REG_HDMI_CEC_ADDR                                       0x000002a0
+
+#define REG_HDMI_CEC_TIME                                       0x000002a4
+
+#define REG_HDMI_CEC_REFTIMER                                   0x000002a8
+
+#define REG_HDMI_CEC_RD_DATA                                    0x000002ac
+
+#define REG_HDMI_CEC_RD_FILTER                                  0x000002b0
+
 #define REG_HDMI_ACTIVE_HSYNC                                   0x000002b4
 #define HDMI_ACTIVE_HSYNC_START__MASK                           0x00000fff
 #define HDMI_ACTIVE_HSYNC_START__SHIFT                          0
@@ -410,17 +443,33 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
 #define HDMI_FRAME_CTRL_HSYNC_LOW                               0x20000000
 #define HDMI_FRAME_CTRL_INTERLACED_EN                           0x80000000
 
+#define REG_HDMI_AUD_INT                                        0x000002cc
+#define HDMI_AUD_INT_AUD_FIFO_URUN_INT                          0x00000001
+#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK                         0x00000002
+#define HDMI_AUD_INT_AUD_SAM_DROP_INT                           0x00000004
+#define HDMI_AUD_INT_AUD_SAM_DROP_MASK                          0x00000008
+
 #define REG_HDMI_PHY_CTRL                                       0x000002d4
 #define HDMI_PHY_CTRL_SW_RESET_PLL                              0x00000001
 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW                          0x00000002
 #define HDMI_PHY_CTRL_SW_RESET                                  0x00000004
 #define HDMI_PHY_CTRL_SW_RESET_LOW                              0x00000008
 
-#define REG_HDMI_AUD_INT                                        0x000002cc
-#define HDMI_AUD_INT_AUD_FIFO_URUN_INT                          0x00000001
-#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK                         0x00000002
-#define HDMI_AUD_INT_AUD_SAM_DROP_INT                           0x00000004
-#define HDMI_AUD_INT_AUD_SAM_DROP_MASK                          0x00000008
+#define REG_HDMI_CEC_WR_RANGE                                   0x000002dc
+
+#define REG_HDMI_CEC_RD_RANGE                                   0x000002e0
+
+#define REG_HDMI_VERSION                                        0x000002e4
+
+#define REG_HDMI_CEC_COMPL_CTL                                  0x00000360
+
+#define REG_HDMI_CEC_RD_START_RANGE                             0x00000364
+
+#define REG_HDMI_CEC_RD_TOTAL_RANGE                             0x00000368
+
+#define REG_HDMI_CEC_RD_ERR_RESP_LO                             0x0000036c
+
+#define REG_HDMI_CEC_WR_CHECK_CONFIG                            0x00000370
 
 #define REG_HDMI_8x60_PHY_REG0                                  0x00000300
 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK                 0x0000001c
@@ -504,5 +553,23 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
 
 #define REG_HDMI_8960_PHY_REG12                                 0x00000430
 
+#define REG_HDMI_8x74_ANA_CFG0                                  0x00000000
+
+#define REG_HDMI_8x74_ANA_CFG1                                  0x00000004
+
+#define REG_HDMI_8x74_PD_CTRL0                                  0x00000010
+
+#define REG_HDMI_8x74_PD_CTRL1                                  0x00000014
+
+#define REG_HDMI_8x74_BIST_CFG0                                 0x00000034
+
+#define REG_HDMI_8x74_BIST_PATN0                                0x0000003c
+
+#define REG_HDMI_8x74_BIST_PATN1                                0x00000040
+
+#define REG_HDMI_8x74_BIST_PATN2                                0x00000044
+
+#define REG_HDMI_8x74_BIST_PATN3                                0x00000048
+
 
 #endif /* HDMI_XML */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 5a8ee3473cf5..7d10e55403c6 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -21,6 +21,7 @@ struct hdmi_bridge {
         struct drm_bridge base;
 
         struct hdmi *hdmi;
+        bool power_on;
 
         unsigned long int pixclock;
 };
@@ -34,6 +35,65 @@ static void hdmi_bridge_destroy(struct drm_bridge *bridge)
         kfree(hdmi_bridge);
 }
 
+static void power_on(struct drm_bridge *bridge)
+{
+        struct drm_device *dev = bridge->dev;
+        struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
+        struct hdmi *hdmi = hdmi_bridge->hdmi;
+        const struct hdmi_platform_config *config = hdmi->config;
+        int i, ret;
+
+        for (i = 0; i < config->pwr_reg_cnt; i++) {
+                ret = regulator_enable(hdmi->pwr_regs[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
+                                        config->pwr_reg_names[i], ret);
+                }
+        }
+
+        if (config->pwr_clk_cnt > 0) {
+                DBG("pixclock: %lu", hdmi_bridge->pixclock);
+                ret = clk_set_rate(hdmi->pwr_clks[0], hdmi_bridge->pixclock);
+                if (ret) {
+                        dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
+                                        config->pwr_clk_names[0], ret);
+                }
+        }
+
+        for (i = 0; i < config->pwr_clk_cnt; i++) {
+                ret = clk_prepare_enable(hdmi->pwr_clks[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
+                                        config->pwr_clk_names[i], ret);
+                }
+        }
+}
+
+static void power_off(struct drm_bridge *bridge)
+{
+        struct drm_device *dev = bridge->dev;
+        struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
+        struct hdmi *hdmi = hdmi_bridge->hdmi;
+        const struct hdmi_platform_config *config = hdmi->config;
+        int i, ret;
+
+        /* TODO do we need to wait for final vblank somewhere before
+         * cutting the clocks?
+         */
+        mdelay(16 + 4);
+
+        for (i = 0; i < config->pwr_clk_cnt; i++)
+                clk_disable_unprepare(hdmi->pwr_clks[i]);
+
+        for (i = 0; i < config->pwr_reg_cnt; i++) {
+                ret = regulator_disable(hdmi->pwr_regs[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
+                                        config->pwr_reg_names[i], ret);
+                }
+        }
+}
+
 static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
 {
         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
@@ -41,6 +101,12 @@ static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
         struct hdmi_phy *phy = hdmi->phy;
 
         DBG("power up");
+
+        if (!hdmi_bridge->power_on) {
+                power_on(bridge);
+                hdmi_bridge->power_on = true;
+        }
+
         phy->funcs->powerup(phy, hdmi_bridge->pixclock);
         hdmi_set_mode(hdmi, true);
 }
@@ -62,6 +128,11 @@ static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
         DBG("power down");
         hdmi_set_mode(hdmi, false);
         phy->funcs->powerdown(phy);
+
+        if (hdmi_bridge->power_on) {
+                power_off(bridge);
+                hdmi_bridge->power_on = false;
+        }
 }
 
 static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 823eee521a31..7dedfdd12075 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -17,19 +17,20 @@
 
 #include <linux/gpio.h>
 
+#include "msm_kms.h"
 #include "hdmi.h"
 
 struct hdmi_connector {
         struct drm_connector base;
         struct hdmi *hdmi;
+        struct work_struct hpd_work;
 };
 #define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base)
 
 static int gpio_config(struct hdmi *hdmi, bool on)
 {
         struct drm_device *dev = hdmi->dev;
-        struct hdmi_platform_config *config =
-                        hdmi->pdev->dev.platform_data;
+        const struct hdmi_platform_config *config = hdmi->config;
         int ret;
 
         if (on) {
@@ -39,26 +40,43 @@ static int gpio_config(struct hdmi *hdmi, bool on)
                                 "HDMI_DDC_CLK", config->ddc_clk_gpio, ret);
                         goto error1;
                 }
+                gpio_set_value_cansleep(config->ddc_clk_gpio, 1);
+
                 ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA");
                 if (ret) {
                         dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
                                 "HDMI_DDC_DATA", config->ddc_data_gpio, ret);
                         goto error2;
                 }
+                gpio_set_value_cansleep(config->ddc_data_gpio, 1);
+
                 ret = gpio_request(config->hpd_gpio, "HDMI_HPD");
                 if (ret) {
                         dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
                                 "HDMI_HPD", config->hpd_gpio, ret);
                         goto error3;
                 }
-                if (config->pmic_gpio != -1) {
-                        ret = gpio_request(config->pmic_gpio, "PMIC_HDMI_MUX_SEL");
+                gpio_direction_input(config->hpd_gpio);
+                gpio_set_value_cansleep(config->hpd_gpio, 1);
+
+                if (config->mux_en_gpio != -1) {
+                        ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN");
                         if (ret) {
                                 dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
-                                        "PMIC_HDMI_MUX_SEL", config->pmic_gpio, ret);
+                                        "HDMI_MUX_SEL", config->mux_en_gpio, ret);
                                 goto error4;
                         }
-                        gpio_set_value_cansleep(config->pmic_gpio, 0);
+                        gpio_set_value_cansleep(config->mux_en_gpio, 1);
+                }
+
+                if (config->mux_sel_gpio != -1) {
+                        ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL");
+                        if (ret) {
+                                dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n",
+                                        "HDMI_MUX_SEL", config->mux_sel_gpio, ret);
+                                goto error5;
+                        }
+                        gpio_set_value_cansleep(config->mux_sel_gpio, 0);
                 }
                 DBG("gpio on");
         } else {
@@ -66,15 +84,23 @@ static int gpio_config(struct hdmi *hdmi, bool on)
                 gpio_free(config->ddc_data_gpio);
                 gpio_free(config->hpd_gpio);
 
-                if (config->pmic_gpio != -1) {
-                        gpio_set_value_cansleep(config->pmic_gpio, 1);
-                        gpio_free(config->pmic_gpio);
+                if (config->mux_en_gpio != -1) {
+                        gpio_set_value_cansleep(config->mux_en_gpio, 0);
+                        gpio_free(config->mux_en_gpio);
+                }
+
+                if (config->mux_sel_gpio != -1) {
+                        gpio_set_value_cansleep(config->mux_sel_gpio, 1);
+                        gpio_free(config->mux_sel_gpio);
                 }
                 DBG("gpio off");
         }
 
         return 0;
 
+error5:
+        if (config->mux_en_gpio != -1)
+                gpio_free(config->mux_en_gpio);
 error4:
         gpio_free(config->hpd_gpio);
 error3:
@@ -88,10 +114,11 @@ error1:
 static int hpd_enable(struct hdmi_connector *hdmi_connector)
 {
         struct hdmi *hdmi = hdmi_connector->hdmi;
+        const struct hdmi_platform_config *config = hdmi->config;
         struct drm_device *dev = hdmi_connector->base.dev;
         struct hdmi_phy *phy = hdmi->phy;
         uint32_t hpd_ctrl;
-        int ret;
+        int i, ret;
 
         ret = gpio_config(hdmi, true);
         if (ret) {
@@ -99,31 +126,22 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
                 goto fail;
         }
 
-        ret = clk_prepare_enable(hdmi->clk);
-        if (ret) {
-                dev_err(dev->dev, "failed to enable 'clk': %d\n", ret);
-                goto fail;
-        }
-
-        ret = clk_prepare_enable(hdmi->m_pclk);
-        if (ret) {
-                dev_err(dev->dev, "failed to enable 'm_pclk': %d\n", ret);
-                goto fail;
-        }
-
-        ret = clk_prepare_enable(hdmi->s_pclk);
-        if (ret) {
-                dev_err(dev->dev, "failed to enable 's_pclk': %d\n", ret);
-                goto fail;
+        for (i = 0; i < config->hpd_clk_cnt; i++) {
+                ret = clk_prepare_enable(hdmi->hpd_clks[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to enable hpd clk: %s (%d)\n",
+                                        config->hpd_clk_names[i], ret);
+                        goto fail;
+                }
         }
 
-        if (hdmi->mpp0)
-                ret = regulator_enable(hdmi->mpp0);
-        if (!ret)
-                ret = regulator_enable(hdmi->mvs);
-        if (ret) {
-                dev_err(dev->dev, "failed to enable regulators: %d\n", ret);
-                goto fail;
+        for (i = 0; i < config->hpd_reg_cnt; i++) {
+                ret = regulator_enable(hdmi->hpd_regs[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to enable hpd regulator: %s (%d)\n",
+                                        config->hpd_reg_names[i], ret);
+                        goto fail;
+                }
         }
 
         hdmi_set_mode(hdmi, false);
@@ -156,26 +174,26 @@ fail:
 static int hdp_disable(struct hdmi_connector *hdmi_connector)
 {
         struct hdmi *hdmi = hdmi_connector->hdmi;
+        const struct hdmi_platform_config *config = hdmi->config;
         struct drm_device *dev = hdmi_connector->base.dev;
-        int ret = 0;
+        int i, ret = 0;
 
         /* Disable HPD interrupt */
         hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0);
 
         hdmi_set_mode(hdmi, false);
 
-        if (hdmi->mpp0)
-                ret = regulator_disable(hdmi->mpp0);
-        if (!ret)
-                ret = regulator_disable(hdmi->mvs);
-        if (ret) {
-                dev_err(dev->dev, "failed to enable regulators: %d\n", ret);
-                goto fail;
+        for (i = 0; i < config->hpd_reg_cnt; i++) {
+                ret = regulator_disable(hdmi->hpd_regs[i]);
+                if (ret) {
+                        dev_err(dev->dev, "failed to disable hpd regulator: %s (%d)\n",
+                                        config->hpd_reg_names[i], ret);
+                        goto fail;
+                }
         }
 
-        clk_disable_unprepare(hdmi->clk);
-        clk_disable_unprepare(hdmi->m_pclk);
-        clk_disable_unprepare(hdmi->s_pclk);
+        for (i = 0; i < config->hpd_clk_cnt; i++)
+                clk_disable_unprepare(hdmi->hpd_clks[i]);
 
         ret = gpio_config(hdmi, false);
         if (ret) {
@@ -189,9 +207,19 @@ fail:
         return ret;
 }
 
+static void
+hotplug_work(struct work_struct *work)
+{
+        struct hdmi_connector *hdmi_connector =
+                container_of(work, struct hdmi_connector, hpd_work);
+        struct drm_connector *connector = &hdmi_connector->base;
+        drm_helper_hpd_irq_event(connector->dev);
+}
+
 void hdmi_connector_irq(struct drm_connector *connector)
 {
         struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
+        struct msm_drm_private *priv = connector->dev->dev_private;
         struct hdmi *hdmi = hdmi_connector->hdmi;
         uint32_t hpd_int_status, hpd_int_ctrl;
 
@@ -209,13 +237,13 @@ void hdmi_connector_irq(struct drm_connector *connector)
                 hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL,
                                 hpd_int_ctrl | HDMI_HPD_INT_CTRL_INT_ACK);
 
-                drm_helper_hpd_irq_event(connector->dev);
-
                 /* detect disconnect if we are connected or visa versa: */
                 hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN;
                 if (!detected)
                         hpd_int_ctrl |= HDMI_HPD_INT_CTRL_INT_CONNECT;
                 hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, hpd_int_ctrl);
+
+                queue_work(priv->wq, &hdmi_connector->hpd_work);
         }
 }
 
@@ -224,6 +252,7 @@ static enum drm_connector_status hdmi_connector_detect(
 {
         struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
         struct hdmi *hdmi = hdmi_connector->hdmi;
+        const struct hdmi_platform_config *config = hdmi->config;
         uint32_t hpd_int_status;
         int retry = 20;
 
@@ -233,6 +262,14 @@ static enum drm_connector_status hdmi_connector_detect(
          * let that trick us into thinking the monitor is gone:
          */
         while (retry-- && !(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED)) {
+                /* hdmi debounce logic seems to get stuck sometimes,
+                 * read directly the gpio to get a second opinion:
+                 */
+                if (gpio_get_value(config->hpd_gpio)) {
+                        DBG("gpio tells us we are connected!");
+                        hpd_int_status |= HDMI_HPD_INT_STATUS_CABLE_DETECTED;
+                        break;
+                }
                 mdelay(10);
                 hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS);
                 DBG("status=%08x", hpd_int_status);
@@ -285,6 +322,8 @@ static int hdmi_connector_mode_valid(struct drm_connector *connector,
                                  struct drm_display_mode *mode)
 {
         struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
+        struct hdmi *hdmi = hdmi_connector->hdmi;
+        const struct hdmi_platform_config *config = hdmi->config;
         struct msm_drm_private *priv = connector->dev->dev_private;
         struct msm_kms *kms = priv->kms;
         long actual, requested;
@@ -293,6 +332,13 @@ static int hdmi_connector_mode_valid(struct drm_connector *connector,
         actual = kms->funcs->round_pixclk(kms,
                         requested, hdmi_connector->hdmi->encoder);
 
+        /* for mdp5/apq8074, we manage our own pixel clk (as opposed to
+         * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder
+         * instead):
+         */
+        if (config->pwr_clk_cnt > 0)
+                actual = clk_round_rate(hdmi->pwr_clks[0], actual);
+
         DBG("requested=%ld, actual=%ld", requested, actual);
 
         if (actual != requested)
@@ -335,6 +381,7 @@ struct drm_connector *hdmi_connector_init(struct hdmi *hdmi)
         }
 
         hdmi_connector->hdmi = hdmi_reference(hdmi);
+        INIT_WORK(&hdmi_connector->hpd_work, hotplug_work);
 
         connector = &hdmi_connector->base;
 
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c
new file mode 100644
index 000000000000..59fa6cdacb2a
--- /dev/null
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hdmi.h"
+
+struct hdmi_phy_8x74 {
+        struct hdmi_phy base;
+        struct hdmi *hdmi;
+        void __iomem *mmio;
+};
+#define to_hdmi_phy_8x74(x) container_of(x, struct hdmi_phy_8x74, base)
+
+
+static void phy_write(struct hdmi_phy_8x74 *phy, u32 reg, u32 data)
+{
+        msm_writel(data, phy->mmio + reg);
+}
+
+//static u32 phy_read(struct hdmi_phy_8x74 *phy, u32 reg)
+//{
+//      return msm_readl(phy->mmio + reg);
+//}
+
+static void hdmi_phy_8x74_destroy(struct hdmi_phy *phy)
+{
+        struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
+        kfree(phy_8x74);
+}
+
+static void hdmi_phy_8x74_reset(struct hdmi_phy *phy)
+{
+        struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
+        struct hdmi *hdmi = phy_8x74->hdmi;
+        unsigned int val;
+
+        /* NOTE that HDMI_PHY_CTL is in core mmio, not phy mmio: */
+
+        val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
+
+        if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
+                /* pull low */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val & ~HDMI_PHY_CTRL_SW_RESET);
+        } else {
+                /* pull high */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val | HDMI_PHY_CTRL_SW_RESET);
+        }
+
+        if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
+                /* pull low */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
+        } else {
+                /* pull high */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val | HDMI_PHY_CTRL_SW_RESET_PLL);
+        }
+
+        msleep(100);
+
+        if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
+                /* pull high */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val | HDMI_PHY_CTRL_SW_RESET);
+        } else {
+                /* pull low */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val & ~HDMI_PHY_CTRL_SW_RESET);
+        }
+
+        if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
+                /* pull high */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val | HDMI_PHY_CTRL_SW_RESET_PLL);
+        } else {
+                /* pull low */
+                hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
+                                val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
+        }
+}
+
+static void hdmi_phy_8x74_powerup(struct hdmi_phy *phy,
+                unsigned long int pixclock)
+{
+        struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
+
+        phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG0,   0x1b);
+        phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG1,   0xf2);
+        phy_write(phy_8x74, REG_HDMI_8x74_BIST_CFG0,  0x0);
+        phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN0, 0x0);
+        phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN1, 0x0);
+        phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN2, 0x0);
+        phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN3, 0x0);
+        phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL1,   0x20);
+}
+
+static void hdmi_phy_8x74_powerdown(struct hdmi_phy *phy)
+{
+        struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
+        phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL0, 0x7f);
+}
+
+static const struct hdmi_phy_funcs hdmi_phy_8x74_funcs = {
+                .destroy = hdmi_phy_8x74_destroy,
+                .reset = hdmi_phy_8x74_reset,
+                .powerup = hdmi_phy_8x74_powerup,
+                .powerdown = hdmi_phy_8x74_powerdown,
+};
+
+struct hdmi_phy *hdmi_phy_8x74_init(struct hdmi *hdmi)
+{
+        struct hdmi_phy_8x74 *phy_8x74;
+        struct hdmi_phy *phy = NULL;
+        int ret;
+
+        phy_8x74 = kzalloc(sizeof(*phy_8x74), GFP_KERNEL);
+        if (!phy_8x74) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+
+        phy = &phy_8x74->base;
+
+        phy->funcs = &hdmi_phy_8x74_funcs;
+
+        phy_8x74->hdmi = hdmi;
+
+        /* for 8x74, the phy mmio is mapped separately: */
+        phy_8x74->mmio = msm_ioremap(hdmi->pdev,
+                        "phy_physical", "HDMI_8x74");
+        if (IS_ERR(phy_8x74->mmio)) {
+                ret = PTR_ERR(phy_8x74->mmio);
+                goto fail;
+        }
+
+        return phy;
+
+fail:
+        if (phy)
+                hdmi_phy_8x74_destroy(phy);
+        return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
index dbde4f6339b9..d591567173c4 100644
--- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index 9908ffe1c3ad..416a26e1e58d 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -42,27 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
 
 
-enum mdp4_bpc {
-        BPC1 = 0,
-        BPC5 = 1,
-        BPC6 = 2,
-        BPC8 = 3,
-};
-
-enum mdp4_bpc_alpha {
-        BPC1A = 0,
-        BPC4A = 1,
-        BPC6A = 2,
-        BPC8A = 3,
-};
-
-enum mdp4_alpha_type {
-        FG_CONST = 0,
-        BG_CONST = 1,
-        FG_PIXEL = 2,
-        BG_PIXEL = 3,
-};
-
 enum mdp4_pipe {
         VG1 = 0,
         VG2 = 1,
@@ -79,15 +60,6 @@ enum mdp4_mixer {
         MIXER2 = 2,
 };
 
-enum mdp4_mixer_stage_id {
-        STAGE_UNUSED = 0,
-        STAGE_BASE = 1,
-        STAGE0 = 2,
-        STAGE1 = 3,
-        STAGE2 = 4,
-        STAGE3 = 5,
-};
-
 enum mdp4_intf {
         INTF_LCDC_DTV = 0,
         INTF_DSI_VIDEO = 1,
@@ -194,56 +166,56 @@ static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
 #define REG_MDP4_LAYERMIXER2_IN_CFG                             0x000100f0
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK                     0x00000007
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT                    0
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1                    0x00000008
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK                     0x00000070
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT                    4
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1                    0x00000080
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK                     0x00000700
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT                    8
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1                    0x00000800
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK                     0x00007000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT                    12
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1                    0x00008000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK                     0x00070000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT                    16
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1                    0x00080000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK                     0x00700000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT                    20
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1                    0x00800000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK                     0x07000000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT                    24
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
 }
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1                    0x08000000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK                     0x70000000
 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT                    28
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
 }
@@ -254,56 +226,56 @@ static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id va
 #define REG_MDP4_LAYERMIXER_IN_CFG                              0x00010100
 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK                      0x00000007
 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT                     0
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1                     0x00000008
 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK                      0x00000070
 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT                     4
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1                     0x00000080
 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK                      0x00000700
 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT                     8
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1                     0x00000800
 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK                      0x00007000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT                     12
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1                     0x00008000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK                      0x00070000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT                     16
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1                     0x00080000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK                      0x00700000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT                     20
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1                     0x00800000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK                      0x07000000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT                     24
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
 }
 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1                     0x08000000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK                      0x70000000
 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT                     28
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
 {
         return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
 }
@@ -369,7 +341,7 @@ static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x
 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK                       0x00000003
 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT                      0
-static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
+static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
 {
         return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
 }
@@ -377,7 +349,7 @@ static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA                         0x00000008
 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK                       0x00000030
 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT                      4
-static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val)
+static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
 {
         return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
 }
@@ -472,19 +444,19 @@ static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __of
 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
 #define MDP4_DMA_CONFIG_G_BPC__MASK                             0x00000003
 #define MDP4_DMA_CONFIG_G_BPC__SHIFT                            0
-static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val)
+static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
 {
         return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
 }
 #define MDP4_DMA_CONFIG_B_BPC__MASK                             0x0000000c
 #define MDP4_DMA_CONFIG_B_BPC__SHIFT                            2
-static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val)
+static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
 {
         return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
 }
 #define MDP4_DMA_CONFIG_R_BPC__MASK                             0x00000030
 #define MDP4_DMA_CONFIG_R_BPC__SHIFT                            4
-static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val)
+static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
 {
         return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
 }
@@ -710,25 +682,25 @@ static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK                        0x00000003
 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT                       0
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val)
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
 {
         return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
 }
 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK                        0x0000000c
 #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT                       2
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val)
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
 {
         return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
 }
 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK                        0x00000030
 #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT                       4
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val)
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
 {
         return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
 }
 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK                        0x000000c0
 #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT                       6
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val)
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
 {
         return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
 }
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index 019d530187ff..1964f4f0d452 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -66,15 +66,15 @@ struct mdp4_crtc {
         /* for unref'ing cursor bo's after scanout completes: */
         struct drm_flip_work unref_cursor_work;
 
-        struct mdp4_irq vblank;
-        struct mdp4_irq err;
+        struct mdp_irq vblank;
+        struct mdp_irq err;
 };
 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
 
 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
 {
         struct msm_drm_private *priv = crtc->dev->dev_private;
-        return to_mdp4_kms(priv->kms);
+        return to_mdp4_kms(to_mdp_kms(priv->kms));
 }
 
 static void update_fb(struct drm_crtc *crtc, bool async,
@@ -93,7 +93,7 @@ static void update_fb(struct drm_crtc *crtc, bool async,
 
         if (!async) {
                 /* enable vblank to pick up the old_fb */
-                mdp4_irq_register(get_kms(crtc), &mdp4_crtc->vblank);
+                mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
         }
 }
 
@@ -145,7 +145,7 @@ static void request_pending(struct drm_crtc *crtc, uint32_t pending)
         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 
         atomic_or(pending, &mdp4_crtc->pending);
-        mdp4_irq_register(get_kms(crtc), &mdp4_crtc->vblank);
+        mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
 }
 
 static void pageflip_cb(struct msm_fence_cb *cb)
@@ -210,9 +210,9 @@ static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
         if (enabled != mdp4_crtc->enabled) {
                 if (enabled) {
                         mdp4_enable(mdp4_kms);
-                        mdp4_irq_register(mdp4_kms, &mdp4_crtc->err);
+                        mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
                 } else {
-                        mdp4_irq_unregister(mdp4_kms, &mdp4_crtc->err);
+                        mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
                         mdp4_disable(mdp4_kms);
                 }
                 mdp4_crtc->enabled = enabled;
@@ -232,7 +232,7 @@ static void blend_setup(struct drm_crtc *crtc)
         struct mdp4_kms *mdp4_kms = get_kms(crtc);
         int i, ovlp = mdp4_crtc->ovlp;
         uint32_t mixer_cfg = 0;
-        static const enum mdp4_mixer_stage_id stages[] = {
+        static const enum mdp_mixer_stage_id stages[] = {
                         STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
         };
         /* statically (for now) map planes to mixer stage (z-order): */
@@ -262,8 +262,8 @@ static void blend_setup(struct drm_crtc *crtc)
                         enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
                         int idx = idxs[pipe_id];
                         if (idx > 0) {
-                                const struct mdp4_format *format =
-                                        to_mdp4_format(msm_framebuffer_format(plane->fb));
+                                const struct mdp_format *format =
+                                        to_mdp_format(msm_framebuffer_format(plane->fb));
                                 alpha[idx-1] = format->alpha_enable;
                         }
                         mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, stages[idx]);
@@ -571,14 +571,14 @@ static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
         .load_lut = mdp4_crtc_load_lut,
 };
 
-static void mdp4_crtc_vblank_irq(struct mdp4_irq *irq, uint32_t irqstatus)
+static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 {
         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
         struct drm_crtc *crtc = &mdp4_crtc->base;
         struct msm_drm_private *priv = crtc->dev->dev_private;
         unsigned pending;
 
-        mdp4_irq_unregister(get_kms(crtc), &mdp4_crtc->vblank);
+        mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
 
         pending = atomic_xchg(&mdp4_crtc->pending, 0);
 
@@ -593,7 +593,7 @@ static void mdp4_crtc_vblank_irq(struct mdp4_irq *irq, uint32_t irqstatus)
         }
 }
 
-static void mdp4_crtc_err_irq(struct mdp4_irq *irq, uint32_t irqstatus)
+static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 {
         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
         struct drm_crtc *crtc = &mdp4_crtc->base;
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c
index 5e0dcae70ab5..067ed03b35fe 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c
@@ -15,8 +15,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <mach/clk.h>
-
 #include "mdp4_kms.h"
 
 #include "drm_crtc.h"
@@ -37,7 +35,7 @@ struct mdp4_dtv_encoder {
 static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
 {
         struct msm_drm_private *priv = encoder->dev->dev_private;
-        return to_mdp4_kms(priv->kms);
+        return to_mdp4_kms(to_mdp_kms(priv->kms));
 }
 
 #ifdef CONFIG_MSM_BUS_SCALING
@@ -139,7 +137,7 @@ static void mdp4_dtv_encoder_dpms(struct drm_encoder *encoder, int mode)
                  * the settings changes for the new modeset (like new
                  * scanout buffer) don't latch properly..
                  */
-                mdp4_irq_wait(mdp4_kms, MDP4_IRQ_EXTERNAL_VSYNC);
+                mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC);
 
                 clk_disable_unprepare(mdp4_dtv_encoder->src_clk);
                 clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk);
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c
new file mode 100644
index 000000000000..c740ccd1cc67
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "msm_drv.h"
+#include "mdp4_kms.h"
+
+void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
+{
+        mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask);
+}
+
+static void mdp4_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
+{
+        DRM_ERROR("errors: %08x\n", irqstatus);
+}
+
+void mdp4_irq_preinstall(struct msm_kms *kms)
+{
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
+        mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff);
+}
+
+int mdp4_irq_postinstall(struct msm_kms *kms)
+{
+        struct mdp_kms *mdp_kms = to_mdp_kms(kms);
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms);
+        struct mdp_irq *error_handler = &mdp4_kms->error_handler;
+
+        error_handler->irq = mdp4_irq_error_handler;
+        error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN |
+                        MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
+
+        mdp_irq_register(mdp_kms, error_handler);
+
+        return 0;
+}
+
+void mdp4_irq_uninstall(struct msm_kms *kms)
+{
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
+        mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000);
+}
+
+irqreturn_t mdp4_irq(struct msm_kms *kms)
+{
+        struct mdp_kms *mdp_kms = to_mdp_kms(kms);
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms);
+        struct drm_device *dev = mdp4_kms->dev;
+        struct msm_drm_private *priv = dev->dev_private;
+        unsigned int id;
+        uint32_t status;
+
+        status = mdp4_read(mdp4_kms, REG_MDP4_INTR_STATUS);
+        mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status);
+
+        VERB("status=%08x", status);
+
+        for (id = 0; id < priv->num_crtcs; id++)
+                if (status & mdp4_crtc_vblank(priv->crtcs[id]))
+                        drm_handle_vblank(dev, id);
+
+        mdp_dispatch_irqs(mdp_kms, status);
+
+        return IRQ_HANDLED;
+}
+
+int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
+{
+        mdp_update_vblank_mask(to_mdp_kms(kms),
+                        mdp4_crtc_vblank(crtc), true);
+        return 0;
+}
+
+void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
+{
+        mdp_update_vblank_mask(to_mdp_kms(kms),
+                        mdp4_crtc_vblank(crtc), false);
+}
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
index 8972ac35a43d..272e707c9487 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
@@ -17,13 +17,14 @@
 
 
 #include "msm_drv.h"
+#include "msm_mmu.h"
 #include "mdp4_kms.h"
 
 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
 
 static int mdp4_hw_init(struct msm_kms *kms)
 {
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
         struct drm_device *dev = mdp4_kms->dev;
         uint32_t version, major, minor, dmap_cfg, vg_cfg;
         unsigned long clk;
@@ -31,12 +32,14 @@ static int mdp4_hw_init(struct msm_kms *kms)
 
         pm_runtime_get_sync(dev->dev);
 
+        mdp4_enable(mdp4_kms);
         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
+        mdp4_disable(mdp4_kms);
 
         major = FIELD(version, MDP4_VERSION_MAJOR);
         minor = FIELD(version, MDP4_VERSION_MINOR);
 
-        DBG("found MDP version v%d.%d", major, minor);
+        DBG("found MDP4 version v%d.%d", major, minor);
 
         if (major != 4) {
                 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
@@ -130,7 +133,7 @@ static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 
 static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 {
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
         struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
         unsigned i;
 
@@ -140,11 +143,12 @@ static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 
 static void mdp4_destroy(struct msm_kms *kms)
 {
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
+        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
         kfree(mdp4_kms);
 }
 
-static const struct msm_kms_funcs kms_funcs = {
+static const struct mdp_kms_funcs kms_funcs = {
+        .base = {
                 .hw_init         = mdp4_hw_init,
                 .irq_preinstall  = mdp4_irq_preinstall,
                 .irq_postinstall = mdp4_irq_postinstall,
@@ -152,10 +156,12 @@ static const struct msm_kms_funcs kms_funcs = {
                 .irq             = mdp4_irq,
                 .enable_vblank   = mdp4_enable_vblank,
                 .disable_vblank  = mdp4_disable_vblank,
-                .get_format      = mdp4_get_format,
+                .get_format      = mdp_get_format,
                 .round_pixclk    = mdp4_round_pixclk,
                 .preclose        = mdp4_preclose,
                 .destroy         = mdp4_destroy,
+        },
+        .set_irqmask         = mdp4_set_irqmask,
 };
 
 int mdp4_disable(struct mdp4_kms *mdp4_kms)
@@ -189,6 +195,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms)
         struct drm_plane *plane;
         struct drm_crtc *crtc;
         struct drm_encoder *encoder;
+        struct hdmi *hdmi;
         int ret;
 
         /*
@@ -238,9 +245,10 @@ static int modeset_init(struct mdp4_kms *mdp4_kms)
         encoder->possible_crtcs = 0x1;     /* DTV can be hooked to DMA_E */
         priv->encoders[priv->num_encoders++] = encoder;
 
-        ret = hdmi_init(dev, encoder);
-        if (ret) {
-                dev_err(dev->dev, "failed to initialize HDMI\n");
+        hdmi = hdmi_init(dev, encoder);
+        if (IS_ERR(hdmi)) {
+                ret = PTR_ERR(hdmi);
+                dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
                 goto fail;
         }
 
@@ -260,6 +268,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
         struct mdp4_platform_config *config = mdp4_get_config(pdev);
         struct mdp4_kms *mdp4_kms;
         struct msm_kms *kms = NULL;
+        struct msm_mmu *mmu;
         int ret;
 
         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
@@ -269,8 +278,9 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
                 goto fail;
         }
 
-        kms = &mdp4_kms->base;
-        kms->funcs = &kms_funcs;
+        mdp_kms_init(&mdp4_kms->base, &kms_funcs);
+
+        kms = &mdp4_kms->base.base;
 
         mdp4_kms->dev = dev;
 
@@ -322,27 +332,34 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
         clk_set_rate(mdp4_kms->clk, config->max_clk);
         clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 
-        if (!config->iommu) {
-                dev_err(dev->dev, "no iommu\n");
-                ret = -ENXIO;
-                goto fail;
-        }
-
         /* make sure things are off before attaching iommu (bootloader could
          * have left things on, in which case we'll start getting faults if
          * we don't disable):
          */
+        mdp4_enable(mdp4_kms);
         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
+        mdp4_disable(mdp4_kms);
         mdelay(16);
 
-        ret = msm_iommu_attach(dev, config->iommu,
-                        iommu_ports, ARRAY_SIZE(iommu_ports));
-        if (ret)
-                goto fail;
+        if (config->iommu) {
+                mmu = msm_iommu_new(dev, config->iommu);
+                if (IS_ERR(mmu)) {
+                        ret = PTR_ERR(mmu);
+                        goto fail;
+                }
+                ret = mmu->funcs->attach(mmu, iommu_ports,
+                                ARRAY_SIZE(iommu_ports));
+                if (ret)
+                        goto fail;
+        } else {
+                dev_info(dev->dev, "no iommu, fallback to phys "
+                                "contig buffers for scanout\n");
+                mmu = NULL;
+        }
 
-        mdp4_kms->id = msm_register_iommu(dev, config->iommu);
+        mdp4_kms->id = msm_register_mmu(dev, mmu);
         if (mdp4_kms->id < 0) {
                 ret = mdp4_kms->id;
                 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
index eb015c834087..66a4d31aec80 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
@@ -18,29 +18,13 @@
 #ifndef __MDP4_KMS_H__
 #define __MDP4_KMS_H__
 
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/consumer.h>
-
 #include "msm_drv.h"
+#include "msm_kms.h"
+#include "mdp/mdp_kms.h"
 #include "mdp4.xml.h"
 
-
-/* For transiently registering for different MDP4 irqs that various parts
- * of the KMS code need during setup/configuration.  We these are not
- * necessarily the same as what drm_vblank_get/put() are requesting, and
- * the hysteresis in drm_vblank_put() is not necessarily desirable for
- * internal housekeeping related irq usage.
- */
-struct mdp4_irq {
-        struct list_head node;
-        uint32_t irqmask;
-        bool registered;
-        void (*irq)(struct mdp4_irq *irq, uint32_t irqstatus);
-};
-
 struct mdp4_kms {
-        struct msm_kms base;
+        struct mdp_kms base;
 
         struct drm_device *dev;
 
@@ -59,11 +43,7 @@ struct mdp4_kms {
         struct clk *pclk;
         struct clk *lut_clk;
 
-        /* irq handling: */
-        bool in_irq;
-        struct list_head irq_list;    /* list of mdp4_irq */
-        uint32_t vblank_mask;         /* irq bits set for userspace vblank */
-        struct mdp4_irq error_handler;
+        struct mdp_irq error_handler;
 };
 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
 
@@ -73,16 +53,6 @@ struct mdp4_platform_config {
         uint32_t max_clk;
 };
 
-struct mdp4_format {
-        struct msm_format base;
-        enum mdp4_bpc bpc_r, bpc_g, bpc_b;
-        enum mdp4_bpc_alpha bpc_a;
-        uint8_t unpack[4];
-        bool alpha_enable, unpack_tight;
-        uint8_t cpp, unpack_count;
-};
-#define to_mdp4_format(x) container_of(x, struct mdp4_format, base)
-
 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
 {
         msm_writel(data, mdp4_kms->mmio + reg);
@@ -134,7 +104,7 @@ static inline uint32_t dma2err(enum mdp4_dma dma)
 }
 
 static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
-                enum mdp4_mixer_stage_id stage)
+                enum mdp_mixer_stage_id stage)
 {
         uint32_t mixer_cfg = 0;
 
@@ -178,19 +148,23 @@ static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
 int mdp4_disable(struct mdp4_kms *mdp4_kms);
 int mdp4_enable(struct mdp4_kms *mdp4_kms);
 
+void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
 void mdp4_irq_preinstall(struct msm_kms *kms);
 int mdp4_irq_postinstall(struct msm_kms *kms);
 void mdp4_irq_uninstall(struct msm_kms *kms);
 irqreturn_t mdp4_irq(struct msm_kms *kms);
-void mdp4_irq_wait(struct mdp4_kms *mdp4_kms, uint32_t irqmask);
-void mdp4_irq_register(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
-void mdp4_irq_unregister(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq);
 int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 
-uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *formats,
-                uint32_t max_formats);
-const struct msm_format *mdp4_get_format(struct msm_kms *kms, uint32_t format);
+static inline
+uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
+                uint32_t max_formats)
+{
+        /* TODO when we have YUV, we need to filter supported formats
+         * based on pipe_id..
+         */
+        return mdp_get_formats(pixel_formats, max_formats);
+}
 
 void mdp4_plane_install_properties(struct drm_plane *plane,
                 struct drm_mode_object *obj);
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
index 0f0af243f6fc..2406027200ec 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
@@ -34,7 +34,7 @@ struct mdp4_plane {
 static struct mdp4_kms *get_kms(struct drm_plane *plane)
 {
         struct msm_drm_private *priv = plane->dev->dev_private;
-        return to_mdp4_kms(priv->kms);
+        return to_mdp4_kms(to_mdp_kms(priv->kms));
 }
 
 static int mdp4_plane_update(struct drm_plane *plane,
@@ -132,7 +132,7 @@ int mdp4_plane_mode_set(struct drm_plane *plane,
         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
         struct mdp4_kms *mdp4_kms = get_kms(plane);
         enum mdp4_pipe pipe = mdp4_plane->pipe;
-        const struct mdp4_format *format;
+        const struct mdp_format *format;
         uint32_t op_mode = 0;
         uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
         uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
@@ -175,7 +175,7 @@ int mdp4_plane_mode_set(struct drm_plane *plane,
 
         mdp4_plane_set_scanout(plane, fb);
 
-        format = to_mdp4_format(msm_framebuffer_format(fb));
+        format = to_mdp_format(msm_framebuffer_format(fb));
 
         mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
                         MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
new file mode 100644
index 000000000000..0aa51517f826
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -0,0 +1,1036 @@
+#ifndef MDP5_XML
+#define MDP5_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/freedreno/envytools/
+git clone https://github.com/freedreno/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum mdp5_intf {
+        INTF_DSI = 1,
+        INTF_HDMI = 3,
+        INTF_LCDC = 5,
+        INTF_eDP = 9,
+};
+
+enum mdp5_intfnum {
+        NO_INTF = 0,
+        INTF0 = 1,
+        INTF1 = 2,
+        INTF2 = 3,
+        INTF3 = 4,
+};
+
+enum mdp5_pipe {
+        SSPP_VIG0 = 0,
+        SSPP_VIG1 = 1,
+        SSPP_VIG2 = 2,
+        SSPP_RGB0 = 3,
+        SSPP_RGB1 = 4,
+        SSPP_RGB2 = 5,
+        SSPP_DMA0 = 6,
+        SSPP_DMA1 = 7,
+};
+
+enum mdp5_ctl_mode {
+        MODE_NONE = 0,
+        MODE_ROT0 = 1,
+        MODE_ROT1 = 2,
+        MODE_WB0 = 3,
+        MODE_WB1 = 4,
+        MODE_WFD = 5,
+};
+
+enum mdp5_pack_3d {
+        PACK_3D_FRAME_INT = 0,
+        PACK_3D_H_ROW_INT = 1,
+        PACK_3D_V_ROW_INT = 2,
+        PACK_3D_COL_INT = 3,
+};
+
+enum mdp5_chroma_samp_type {
+        CHROMA_RGB = 0,
+        CHROMA_H2V1 = 1,
+        CHROMA_H1V2 = 2,
+        CHROMA_420 = 3,
+};
+
+enum mdp5_scale_filter {
+        SCALE_FILTER_NEAREST = 0,
+        SCALE_FILTER_BIL = 1,
+        SCALE_FILTER_PCMN = 2,
+        SCALE_FILTER_CA = 3,
+};
+
+enum mdp5_pipe_bwc {
+        BWC_LOSSLESS = 0,
+        BWC_Q_HIGH = 1,
+        BWC_Q_MED = 2,
+};
+
+enum mdp5_client_id {
+        CID_UNUSED = 0,
+        CID_VIG0_Y = 1,
+        CID_VIG0_CR = 2,
+        CID_VIG0_CB = 3,
+        CID_VIG1_Y = 4,
+        CID_VIG1_CR = 5,
+        CID_VIG1_CB = 6,
+        CID_VIG2_Y = 7,
+        CID_VIG2_CR = 8,
+        CID_VIG2_CB = 9,
+        CID_DMA0_Y = 10,
+        CID_DMA0_CR = 11,
+        CID_DMA0_CB = 12,
+        CID_DMA1_Y = 13,
+        CID_DMA1_CR = 14,
+        CID_DMA1_CB = 15,
+        CID_RGB0 = 16,
+        CID_RGB1 = 17,
+        CID_RGB2 = 18,
+        CID_MAX = 19,
+};
+
+enum mdp5_igc_type {
+        IGC_VIG = 0,
+        IGC_RGB = 1,
+        IGC_DMA = 2,
+        IGC_DSPP = 3,
+};
+
+#define MDP5_IRQ_INTF0_WB_ROT_COMP                              0x00000001
+#define MDP5_IRQ_INTF1_WB_ROT_COMP                              0x00000002
+#define MDP5_IRQ_INTF2_WB_ROT_COMP                              0x00000004
+#define MDP5_IRQ_INTF3_WB_ROT_COMP                              0x00000008
+#define MDP5_IRQ_INTF0_WB_WFD                                   0x00000010
+#define MDP5_IRQ_INTF1_WB_WFD                                   0x00000020
+#define MDP5_IRQ_INTF2_WB_WFD                                   0x00000040
+#define MDP5_IRQ_INTF3_WB_WFD                                   0x00000080
+#define MDP5_IRQ_INTF0_PING_PONG_COMP                           0x00000100
+#define MDP5_IRQ_INTF1_PING_PONG_COMP                           0x00000200
+#define MDP5_IRQ_INTF2_PING_PONG_COMP                           0x00000400
+#define MDP5_IRQ_INTF3_PING_PONG_COMP                           0x00000800
+#define MDP5_IRQ_INTF0_PING_PONG_RD_PTR                         0x00001000
+#define MDP5_IRQ_INTF1_PING_PONG_RD_PTR                         0x00002000
+#define MDP5_IRQ_INTF2_PING_PONG_RD_PTR                         0x00004000
+#define MDP5_IRQ_INTF3_PING_PONG_RD_PTR                         0x00008000
+#define MDP5_IRQ_INTF0_PING_PONG_WR_PTR                         0x00010000
+#define MDP5_IRQ_INTF1_PING_PONG_WR_PTR                         0x00020000
+#define MDP5_IRQ_INTF2_PING_PONG_WR_PTR                         0x00040000
+#define MDP5_IRQ_INTF3_PING_PONG_WR_PTR                         0x00080000
+#define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF                       0x00100000
+#define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF                       0x00200000
+#define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF                       0x00400000
+#define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF                       0x00800000
+#define MDP5_IRQ_INTF0_UNDER_RUN                                0x01000000
+#define MDP5_IRQ_INTF0_VSYNC                                    0x02000000
+#define MDP5_IRQ_INTF1_UNDER_RUN                                0x04000000
+#define MDP5_IRQ_INTF1_VSYNC                                    0x08000000
+#define MDP5_IRQ_INTF2_UNDER_RUN                                0x10000000
+#define MDP5_IRQ_INTF2_VSYNC                                    0x20000000
+#define MDP5_IRQ_INTF3_UNDER_RUN                                0x40000000
+#define MDP5_IRQ_INTF3_VSYNC                                    0x80000000
+#define REG_MDP5_HW_VERSION                                     0x00000000
+
+#define REG_MDP5_HW_INTR_STATUS                                 0x00000010
+#define MDP5_HW_INTR_STATUS_INTR_MDP                            0x00000001
+#define MDP5_HW_INTR_STATUS_INTR_DSI0                           0x00000010
+#define MDP5_HW_INTR_STATUS_INTR_DSI1                           0x00000020
+#define MDP5_HW_INTR_STATUS_INTR_HDMI                           0x00000100
+#define MDP5_HW_INTR_STATUS_INTR_EDP                            0x00001000
+
+#define REG_MDP5_MDP_VERSION                                    0x00000100
+#define MDP5_MDP_VERSION_MINOR__MASK                            0x00ff0000
+#define MDP5_MDP_VERSION_MINOR__SHIFT                           16
+static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
+{
+        return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & MDP5_MDP_VERSION_MINOR__MASK;
+}
+#define MDP5_MDP_VERSION_MAJOR__MASK                            0xf0000000
+#define MDP5_MDP_VERSION_MAJOR__SHIFT                           28
+static inline uint32_t MDP5_MDP_VERSION_MAJOR(uint32_t val)
+{
+        return ((val) << MDP5_MDP_VERSION_MAJOR__SHIFT) & MDP5_MDP_VERSION_MAJOR__MASK;
+}
+
+#define REG_MDP5_DISP_INTF_SEL                                  0x00000104
+#define MDP5_DISP_INTF_SEL_INTF0__MASK                          0x000000ff
+#define MDP5_DISP_INTF_SEL_INTF0__SHIFT                         0
+static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val)
+{
+        return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
+}
+#define MDP5_DISP_INTF_SEL_INTF1__MASK                          0x0000ff00
+#define MDP5_DISP_INTF_SEL_INTF1__SHIFT                         8
+static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val)
+{
+        return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
+}
+#define MDP5_DISP_INTF_SEL_INTF2__MASK                          0x00ff0000
+#define MDP5_DISP_INTF_SEL_INTF2__SHIFT                         16
+static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val)
+{
+        return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
+}
+#define MDP5_DISP_INTF_SEL_INTF3__MASK                          0xff000000
+#define MDP5_DISP_INTF_SEL_INTF3__SHIFT                         24
+static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val)
+{
+        return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
+}
+
+#define REG_MDP5_INTR_EN                                        0x00000110
+
+#define REG_MDP5_INTR_STATUS                                    0x00000114
+
+#define REG_MDP5_INTR_CLEAR                                     0x00000118
+
+#define REG_MDP5_HIST_INTR_EN                                   0x0000011c
+
+#define REG_MDP5_HIST_INTR_STATUS                               0x00000120
+
+#define REG_MDP5_HIST_INTR_CLEAR                                0x00000124
+
+static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; }
+
+static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; }
+#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK                      0x000000ff
+#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT                     0
+static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)
+{
+        return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
+}
+#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK                      0x0000ff00
+#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT                     8
+static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)
+{
+        return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
+}
+#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK                      0x00ff0000
+#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT                     16
+static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)
+{
+        return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
+}
+
+static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; }
+
+static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; }
+#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK                      0x000000ff
+#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT                     0
+static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)
+{
+        return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
+}
+#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK                      0x0000ff00
+#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT                     8
+static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)
+{
+        return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
+}
+#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK                      0x00ff0000
+#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT                     16
+static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)
+{
+        return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
+}
+
+static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
+{
+        switch (idx) {
+                case IGC_VIG: return 0x00000300;
+                case IGC_RGB: return 0x00000310;
+                case IGC_DMA: return 0x00000320;
+                case IGC_DSPP: return 0x00000400;
+                default: return INVALID_IDX(idx);
+        }
+}
+static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
+
+static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
+#define MDP5_IGC_LUT_REG_VAL__MASK                              0x00000fff
+#define MDP5_IGC_LUT_REG_VAL__SHIFT                             0
+static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
+{
+        return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
+}
+#define MDP5_IGC_LUT_REG_INDEX_UPDATE                           0x02000000
+#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0                         0x10000000
+#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1                         0x20000000
+#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2                         0x40000000
+
+static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000600 + 0x100*i0; }
+
+static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; }
+#define MDP5_CTL_LAYER_REG_VIG0__MASK                           0x00000007
+#define MDP5_CTL_LAYER_REG_VIG0__SHIFT                          0
+static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
+}
+#define MDP5_CTL_LAYER_REG_VIG1__MASK                           0x00000038
+#define MDP5_CTL_LAYER_REG_VIG1__SHIFT                          3
+static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
+}
+#define MDP5_CTL_LAYER_REG_VIG2__MASK                           0x000001c0
+#define MDP5_CTL_LAYER_REG_VIG2__SHIFT                          6
+static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
+}
+#define MDP5_CTL_LAYER_REG_RGB0__MASK                           0x00000e00
+#define MDP5_CTL_LAYER_REG_RGB0__SHIFT                          9
+static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
+}
+#define MDP5_CTL_LAYER_REG_RGB1__MASK                           0x00007000
+#define MDP5_CTL_LAYER_REG_RGB1__SHIFT                          12
+static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
+}
+#define MDP5_CTL_LAYER_REG_RGB2__MASK                           0x00038000
+#define MDP5_CTL_LAYER_REG_RGB2__SHIFT                          15
+static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
+}
+#define MDP5_CTL_LAYER_REG_DMA0__MASK                           0x001c0000
+#define MDP5_CTL_LAYER_REG_DMA0__SHIFT                          18
+static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
+}
+#define MDP5_CTL_LAYER_REG_DMA1__MASK                           0x00e00000
+#define MDP5_CTL_LAYER_REG_DMA1__SHIFT                          21
+static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
+{
+        return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
+}
+#define MDP5_CTL_LAYER_REG_BORDER_COLOR                         0x01000000
+#define MDP5_CTL_LAYER_REG_CURSOR_OUT                           0x02000000
+
+static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000614 + 0x100*i0; }
+#define MDP5_CTL_OP_MODE__MASK                                  0x0000000f
+#define MDP5_CTL_OP_MODE__SHIFT                                 0
+static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
+{
+        return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
+}
+#define MDP5_CTL_OP_INTF_NUM__MASK                              0x00000070
+#define MDP5_CTL_OP_INTF_NUM__SHIFT                             4
+static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
+{
+        return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
+}
+#define MDP5_CTL_OP_CMD_MODE                                    0x00020000
+#define MDP5_CTL_OP_PACK_3D_ENABLE                              0x00080000
+#define MDP5_CTL_OP_PACK_3D__MASK                               0x00300000
+#define MDP5_CTL_OP_PACK_3D__SHIFT                              20
+static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
+{
+        return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
+}
+
+static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000618 + 0x100*i0; }
+#define MDP5_CTL_FLUSH_VIG0                                     0x00000001
+#define MDP5_CTL_FLUSH_VIG1                                     0x00000002
+#define MDP5_CTL_FLUSH_VIG2                                     0x00000004
+#define MDP5_CTL_FLUSH_RGB0                                     0x00000008
+#define MDP5_CTL_FLUSH_RGB1                                     0x00000010
+#define MDP5_CTL_FLUSH_RGB2                                     0x00000020
+#define MDP5_CTL_FLUSH_LM0                                      0x00000040
+#define MDP5_CTL_FLUSH_LM1                                      0x00000080
+#define MDP5_CTL_FLUSH_LM2                                      0x00000100
+#define MDP5_CTL_FLUSH_DMA0                                     0x00000800
+#define MDP5_CTL_FLUSH_DMA1                                     0x00001000
+#define MDP5_CTL_FLUSH_DSPP0                                    0x00002000
+#define MDP5_CTL_FLUSH_DSPP1                                    0x00004000
+#define MDP5_CTL_FLUSH_DSPP2                                    0x00008000
+#define MDP5_CTL_FLUSH_CTL                                      0x00020000
+
+static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000061c + 0x100*i0; }
+
+static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000620 + 0x100*i0; }
+
+static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000014c4 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000014f0 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00001500 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; }
+#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK                         0xffff0000
+#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT                        16
+static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
+}
+#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK                          0x0000ffff
+#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT                         0
+static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00001204 + 0x400*i0; }
+#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK                     0xffff0000
+#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT                    16
+static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
+}
+#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK                      0x0000ffff
+#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT                     0
+static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00001208 + 0x400*i0; }
+#define MDP5_PIPE_SRC_XY_Y__MASK                                0xffff0000
+#define MDP5_PIPE_SRC_XY_Y__SHIFT                               16
+static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
+}
+#define MDP5_PIPE_SRC_XY_X__MASK                                0x0000ffff
+#define MDP5_PIPE_SRC_XY_X__SHIFT                               0
+static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000120c + 0x400*i0; }
+#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK                         0xffff0000
+#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT                        16
+static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
+}
+#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK                          0x0000ffff
+#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT                         0
+static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00001210 + 0x400*i0; }
+#define MDP5_PIPE_OUT_XY_Y__MASK                                0xffff0000
+#define MDP5_PIPE_OUT_XY_Y__SHIFT                               16
+static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
+}
+#define MDP5_PIPE_OUT_XY_X__MASK                                0x0000ffff
+#define MDP5_PIPE_OUT_XY_X__SHIFT                               0
+static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00001214 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00001218 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000121c + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00001220 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00001224 + 0x400*i0; }
+#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK                         0x0000ffff
+#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT                        0
+static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
+}
+#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK                         0xffff0000
+#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT                        16
+static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00001228 + 0x400*i0; }
+#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK                         0x0000ffff
+#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT                        0
+static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
+}
+#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK                         0xffff0000
+#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT                        16
+static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000122c + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00001230 + 0x400*i0; }
+#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK                        0x00000003
+#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT                       0
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK                        0x0000000c
+#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT                       2
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK                        0x00000030
+#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT                       4
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK                        0x000000c0
+#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT                       6
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE                       0x00000100
+#define MDP5_PIPE_SRC_FORMAT_CPP__MASK                          0x00000600
+#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT                         9
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_ROT90                              0x00000800
+#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK                 0x00003000
+#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT                12
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT                       0x00020000
+#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB                   0x00040000
+#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK                   0x00780000
+#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT                  19
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
+}
+#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK                  0x01800000
+#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT                 23
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_type val)
+{
+        return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00001234 + 0x400*i0; }
+#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK                        0x000000ff
+#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT                       0
+static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
+}
+#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK                        0x0000ff00
+#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT                       8
+static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
+}
+#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK                        0x00ff0000
+#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT                       16
+static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
+}
+#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK                        0xff000000
+#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT                       24
+static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00001238 + 0x400*i0; }
+#define MDP5_PIPE_SRC_OP_MODE_BWC_EN                            0x00000001
+#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK                         0x00000006
+#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT                        1
+static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
+{
+        return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
+}
+#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR                           0x00002000
+#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD                           0x00004000
+#define MDP5_PIPE_SRC_OP_MODE_IGC_EN                            0x00010000
+#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0                         0x00020000
+#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1                         0x00040000
+#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE                       0x00400000
+#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD                   0x00800000
+
+static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000123c + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00001248 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000124c + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00001250 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00001254 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00001258 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00001270 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000012a4 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000012a8 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000012ac + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000012b0 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000012b4 + 0x400*i0; }
+#define MDP5_PIPE_DECIMATION_VERT__MASK                         0x000000ff
+#define MDP5_PIPE_DECIMATION_VERT__SHIFT                        0
+static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
+}
+#define MDP5_PIPE_DECIMATION_HORZ__MASK                         0x0000ff00
+#define MDP5_PIPE_DECIMATION_HORZ__SHIFT                        8
+static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
+{
+        return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00001404 + 0x400*i0; }
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN                        0x00000001
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN                        0x00000002
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK          0x00000300
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT         8
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
+{
+        return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
+}
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK          0x00000c00
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT         10
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
+{
+        return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
+}
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK           0x00003000
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT          12
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
+{
+        return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
+}
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK           0x0000c000
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT          14
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
+{
+        return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
+}
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK          0x00030000
+#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT         16
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
+{
+        return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
+}
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK          0x000c0000
+#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT         18
+static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
+{
+        return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
+}
+
+static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00001410 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00001414 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00001420 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00001424 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00003200 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00003200 + 0x400*i0; }
+#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA                 0x00000002
+#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA                 0x00000004
+#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA                 0x00000008
+#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA                 0x00000010
+
+static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00003204 + 0x400*i0; }
+#define MDP5_LM_OUT_SIZE_HEIGHT__MASK                           0xffff0000
+#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT                          16
+static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
+}
+#define MDP5_LM_OUT_SIZE_WIDTH__MASK                            0x0000ffff
+#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT                           0
+static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00003208 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00003210 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; }
+#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK                    0x00000003
+#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT                   0
+static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
+{
+        return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
+}
+#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA                      0x00000004
+#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA                      0x00000008
+#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA                  0x00000010
+#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN                      0x00000020
+#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK                    0x00000300
+#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT                   8
+static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
+{
+        return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
+}
+#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA                      0x00000400
+#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA                      0x00000800
+#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA                  0x00001000
+#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN                      0x00002000
+
+static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003224 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003228 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000322c + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003230 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003234 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003238 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000323c + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003240 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003244 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003248 + 0x400*i0 + 0x30*i1; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000032e0 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000032e4 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000032e8 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000032dc + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000032ec + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000032f0 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000032f4 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000032f8 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000032fc + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00003300 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00003304 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00003308 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000330c + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00003310 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00004600 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00004600 + 0x400*i0; }
+#define MDP5_DSPP_OP_MODE_IGC_LUT_EN                            0x00000001
+#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK                     0x0000000e
+#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT                    1
+static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
+{
+        return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
+}
+#define MDP5_DSPP_OP_MODE_PCC_EN                                0x00000010
+#define MDP5_DSPP_OP_MODE_DITHER_EN                             0x00000100
+#define MDP5_DSPP_OP_MODE_HIST_EN                               0x00010000
+#define MDP5_DSPP_OP_MODE_AUTO_CLEAR                            0x00020000
+#define MDP5_DSPP_OP_MODE_HIST_LUT_EN                           0x00080000
+#define MDP5_DSPP_OP_MODE_PA_EN                                 0x00100000
+#define MDP5_DSPP_OP_MODE_GAMUT_EN                              0x00800000
+#define MDP5_DSPP_OP_MODE_GAMUT_ORDER                           0x01000000
+
+static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00004630 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00004750 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00004810 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00004830 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00004834 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00004838 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000048dc + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000048b0 + 0x400*i0; }
+
+static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00012500 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00012500 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00012504 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00012508 + 0x200*i0; }
+#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK                        0x0000ffff
+#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT                       0
+static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
+{
+        return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
+}
+#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK                        0xffff0000
+#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT                       16
+static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
+{
+        return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
+}
+
+static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0001250c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00012510 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00012514 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00012518 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0001251c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00012520 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00012524 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00012528 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0001252c + 0x200*i0; }
+#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK                    0x7fffffff
+#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT                   0
+static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
+{
+        return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
+}
+#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE              0x80000000
+
+static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00012530 + 0x200*i0; }
+#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK                    0x7fffffff
+#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT                   0
+static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
+{
+        return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
+}
+
+static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00012534 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00012538 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0001253c + 0x200*i0; }
+#define MDP5_INTF_DISPLAY_HCTL_START__MASK                      0x0000ffff
+#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT                     0
+static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
+{
+        return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
+}
+#define MDP5_INTF_DISPLAY_HCTL_END__MASK                        0xffff0000
+#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT                       16
+static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
+{
+        return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
+}
+
+static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00012540 + 0x200*i0; }
+#define MDP5_INTF_ACTIVE_HCTL_START__MASK                       0x00007fff
+#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT                      0
+static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
+{
+        return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
+}
+#define MDP5_INTF_ACTIVE_HCTL_END__MASK                         0x7fff0000
+#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT                        16
+static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
+{
+        return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
+}
+#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE                   0x80000000
+
+static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00012544 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00012548 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0001254c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00012550 + 0x200*i0; }
+#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW                        0x00000001
+#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW                        0x00000002
+#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW                      0x00000004
+
+static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00012554 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00012558 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0001255c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00012584 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00012590 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000125a8 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000125ac + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000125b0 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000125f0 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000125f4 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000125f8 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00012600 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00012604 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00012608 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0001260c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00012610 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00012614 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00012618 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0001261c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00013100 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00013100 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00013104 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00013108 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0001310c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00013110 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00013114 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00013118 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0001311c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00013120 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00013124 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00013128 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0001312c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00013130 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00013134 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00013138 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0001317c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000131c8 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000131cc + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000131d0 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000131d4 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000131d8 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000131dc + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000131e0 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000131e8 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000131ec + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000131f0 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000131f4 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000131f8 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00013200 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00013244 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00013248 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0001324c + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00013254 + 0x200*i0; }
+
+static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00013258 + 0x200*i0; }
+
+
+#endif /* MDP5_XML */
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
new file mode 100644
index 000000000000..71a3b2345eb3
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mdp5_kms.h"
+
+#include <drm/drm_mode.h>
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+#include "drm_flip_work.h"
+
+struct mdp5_crtc {
+        struct drm_crtc base;
+        char name[8];
+        struct drm_plane *plane;
+        struct drm_plane *planes[8];
+        int id;
+        bool enabled;
+
+        /* which mixer/encoder we route output to: */
+        int mixer;
+
+        /* if there is a pending flip, these will be non-null: */
+        struct drm_pending_vblank_event *event;
+        struct msm_fence_cb pageflip_cb;
+
+#define PENDING_CURSOR 0x1
+#define PENDING_FLIP   0x2
+        atomic_t pending;
+
+        /* the fb that we logically (from PoV of KMS API) hold a ref
+         * to.  Which we may not yet be scanning out (we may still
+         * be scanning out previous in case of page_flip while waiting
+         * for gpu rendering to complete:
+         */
+        struct drm_framebuffer *fb;
+
+        /* the fb that we currently hold a scanout ref to: */
+        struct drm_framebuffer *scanout_fb;
+
+        /* for unref'ing framebuffers after scanout completes: */
+        struct drm_flip_work unref_fb_work;
+
+        struct mdp_irq vblank;
+        struct mdp_irq err;
+};
+#define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
+
+static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
+{
+        struct msm_drm_private *priv = crtc->dev->dev_private;
+        return to_mdp5_kms(to_mdp_kms(priv->kms));
+}
+
+static void request_pending(struct drm_crtc *crtc, uint32_t pending)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+
+        atomic_or(pending, &mdp5_crtc->pending);
+        mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
+}
+
+static void crtc_flush(struct drm_crtc *crtc)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct mdp5_kms *mdp5_kms = get_kms(crtc);
+        int id = mdp5_crtc->id;
+        uint32_t i, flush = 0;
+
+        for (i = 0; i < ARRAY_SIZE(mdp5_crtc->planes); i++) {
+                struct drm_plane *plane = mdp5_crtc->planes[i];
+                if (plane) {
+                        enum mdp5_pipe pipe = mdp5_plane_pipe(plane);
+                        flush |= pipe2flush(pipe);
+                }
+        }
+        flush |= mixer2flush(mdp5_crtc->id);
+        flush |= MDP5_CTL_FLUSH_CTL;
+
+        DBG("%s: flush=%08x", mdp5_crtc->name, flush);
+
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_FLUSH(id), flush);
+}
+
+static void update_fb(struct drm_crtc *crtc, struct drm_framebuffer *new_fb)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct drm_framebuffer *old_fb = mdp5_crtc->fb;
+
+        /* grab reference to incoming scanout fb: */
+        drm_framebuffer_reference(new_fb);
+        mdp5_crtc->base.fb = new_fb;
+        mdp5_crtc->fb = new_fb;
+
+        if (old_fb)
+                drm_flip_work_queue(&mdp5_crtc->unref_fb_work, old_fb);
+}
+
+/* unlike update_fb(), take a ref to the new scanout fb *before* updating
+ * plane, then call this.  Needed to ensure we don't unref the buffer that
+ * is actually still being scanned out.
+ *
+ * Note that this whole thing goes away with atomic.. since we can defer
+ * calling into driver until rendering is done.
+ */
+static void update_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+
+        /* flush updates, to make sure hw is updated to new scanout fb,
+         * so that we can safely queue unref to current fb (ie. next
+         * vblank we know hw is done w/ previous scanout_fb).
+         */
+        crtc_flush(crtc);
+
+        if (mdp5_crtc->scanout_fb)
+                drm_flip_work_queue(&mdp5_crtc->unref_fb_work,
+                                mdp5_crtc->scanout_fb);
+
+        mdp5_crtc->scanout_fb = fb;
+
+        /* enable vblank to complete flip: */
+        request_pending(crtc, PENDING_FLIP);
+}
+
+/* if file!=NULL, this is preclose potential cancel-flip path */
+static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct drm_pending_vblank_event *event;
+        unsigned long flags, i;
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        event = mdp5_crtc->event;
+        if (event) {
+                /* if regular vblank case (!file) or if cancel-flip from
+                 * preclose on file that requested flip, then send the
+                 * event:
+                 */
+                if (!file || (event->base.file_priv == file)) {
+                        mdp5_crtc->event = NULL;
+                        drm_send_vblank_event(dev, mdp5_crtc->id, event);
+                }
+        }
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        for (i = 0; i < ARRAY_SIZE(mdp5_crtc->planes); i++) {
+                struct drm_plane *plane = mdp5_crtc->planes[i];
+                if (plane)
+                        mdp5_plane_complete_flip(plane);
+        }
+}
+
+static void pageflip_cb(struct msm_fence_cb *cb)
+{
+        struct mdp5_crtc *mdp5_crtc =
+                container_of(cb, struct mdp5_crtc, pageflip_cb);
+        struct drm_crtc *crtc = &mdp5_crtc->base;
+        struct drm_framebuffer *fb = mdp5_crtc->fb;
+
+        if (!fb)
+                return;
+
+        drm_framebuffer_reference(fb);
+        mdp5_plane_set_scanout(mdp5_crtc->plane, fb);
+        update_scanout(crtc, fb);
+}
+
+static void unref_fb_worker(struct drm_flip_work *work, void *val)
+{
+        struct mdp5_crtc *mdp5_crtc =
+                container_of(work, struct mdp5_crtc, unref_fb_work);
+        struct drm_device *dev = mdp5_crtc->base.dev;
+
+        mutex_lock(&dev->mode_config.mutex);
+        drm_framebuffer_unreference(val);
+        mutex_unlock(&dev->mode_config.mutex);
+}
+
+static void mdp5_crtc_destroy(struct drm_crtc *crtc)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+
+        mdp5_crtc->plane->funcs->destroy(mdp5_crtc->plane);
+
+        drm_crtc_cleanup(crtc);
+        drm_flip_work_cleanup(&mdp5_crtc->unref_fb_work);
+
+        kfree(mdp5_crtc);
+}
+
+static void mdp5_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct mdp5_kms *mdp5_kms = get_kms(crtc);
+        bool enabled = (mode == DRM_MODE_DPMS_ON);
+
+        DBG("%s: mode=%d", mdp5_crtc->name, mode);
+
+        if (enabled != mdp5_crtc->enabled) {
+                if (enabled) {
+                        mdp5_enable(mdp5_kms);
+                        mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
+                } else {
+                        mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
+                        mdp5_disable(mdp5_kms);
+                }
+                mdp5_crtc->enabled = enabled;
+        }
+}
+
+static bool mdp5_crtc_mode_fixup(struct drm_crtc *crtc,
+                const struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode)
+{
+        return true;
+}
+
+static void blend_setup(struct drm_crtc *crtc)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct mdp5_kms *mdp5_kms = get_kms(crtc);
+        int id = mdp5_crtc->id;
+
+        /*
+         * Hard-coded setup for now until I figure out how the
+         * layer-mixer works
+         */
+
+        /* LM[id]: */
+        mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(id),
+                        MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA);
+        mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(id, 0),
+                        MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
+                        MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL) |
+                        MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA);
+        mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(id, 0), 0xff);
+        mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(id, 0), 0x00);
+
+        /* NOTE: seems that LM[n] and CTL[m], we do not need n==m.. but
+         * we want to be setting CTL[m].LAYER[n].  Not sure what the
+         * point of having CTL[m].LAYER[o] (for o!=n).. maybe that is
+         * used when chaining up mixers for high resolution displays?
+         */
+
+        /* CTL[id]: */
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_LAYER_REG(id, 0),
+                        MDP5_CTL_LAYER_REG_RGB0(STAGE0) |
+                        MDP5_CTL_LAYER_REG_BORDER_COLOR);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_LAYER_REG(id, 1), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_LAYER_REG(id, 2), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_LAYER_REG(id, 3), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_LAYER_REG(id, 4), 0);
+}
+
+static int mdp5_crtc_mode_set(struct drm_crtc *crtc,
+                struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode,
+                int x, int y,
+                struct drm_framebuffer *old_fb)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct mdp5_kms *mdp5_kms = get_kms(crtc);
+        int ret;
+
+        mode = adjusted_mode;
+
+        DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
+                        mdp5_crtc->name, mode->base.id, mode->name,
+                        mode->vrefresh, mode->clock,
+                        mode->hdisplay, mode->hsync_start,
+                        mode->hsync_end, mode->htotal,
+                        mode->vdisplay, mode->vsync_start,
+                        mode->vsync_end, mode->vtotal,
+                        mode->type, mode->flags);
+
+        /* grab extra ref for update_scanout() */
+        drm_framebuffer_reference(crtc->fb);
+
+        ret = mdp5_plane_mode_set(mdp5_crtc->plane, crtc, crtc->fb,
+                        0, 0, mode->hdisplay, mode->vdisplay,
+                        x << 16, y << 16,
+                        mode->hdisplay << 16, mode->vdisplay << 16);
+        if (ret) {
+                dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n",
+                                mdp5_crtc->name, ret);
+                return ret;
+        }
+
+        mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->id),
+                        MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
+                        MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
+
+        update_fb(crtc, crtc->fb);
+        update_scanout(crtc, crtc->fb);
+
+        return 0;
+}
+
+static void mdp5_crtc_prepare(struct drm_crtc *crtc)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        DBG("%s", mdp5_crtc->name);
+        /* make sure we hold a ref to mdp clks while setting up mode: */
+        mdp5_enable(get_kms(crtc));
+        mdp5_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+}
+
+static void mdp5_crtc_commit(struct drm_crtc *crtc)
+{
+        mdp5_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
+        crtc_flush(crtc);
+        /* drop the ref to mdp clk's that we got in prepare: */
+        mdp5_disable(get_kms(crtc));
+}
+
+static int mdp5_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
+                struct drm_framebuffer *old_fb)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct drm_plane *plane = mdp5_crtc->plane;
+        struct drm_display_mode *mode = &crtc->mode;
+        int ret;
+
+        /* grab extra ref for update_scanout() */
+        drm_framebuffer_reference(crtc->fb);
+
+        ret = mdp5_plane_mode_set(plane, crtc, crtc->fb,
+                        0, 0, mode->hdisplay, mode->vdisplay,
+                        x << 16, y << 16,
+                        mode->hdisplay << 16, mode->vdisplay << 16);
+
+        update_fb(crtc, crtc->fb);
+        update_scanout(crtc, crtc->fb);
+
+        return ret;
+}
+
+static void mdp5_crtc_load_lut(struct drm_crtc *crtc)
+{
+}
+
+static int mdp5_crtc_page_flip(struct drm_crtc *crtc,
+                struct drm_framebuffer *new_fb,
+                struct drm_pending_vblank_event *event,
+                uint32_t page_flip_flags)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct drm_gem_object *obj;
+        unsigned long flags;
+
+        if (mdp5_crtc->event) {
+                dev_err(dev->dev, "already pending flip!\n");
+                return -EBUSY;
+        }
+
+        obj = msm_framebuffer_bo(new_fb, 0);
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        mdp5_crtc->event = event;
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        update_fb(crtc, new_fb);
+
+        return msm_gem_queue_inactive_cb(obj, &mdp5_crtc->pageflip_cb);
+}
+
+static int mdp5_crtc_set_property(struct drm_crtc *crtc,
+                struct drm_property *property, uint64_t val)
+{
+        // XXX
+        return -EINVAL;
+}
+
+static const struct drm_crtc_funcs mdp5_crtc_funcs = {
+        .set_config = drm_crtc_helper_set_config,
+        .destroy = mdp5_crtc_destroy,
+        .page_flip = mdp5_crtc_page_flip,
+        .set_property = mdp5_crtc_set_property,
+};
+
+static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
+        .dpms = mdp5_crtc_dpms,
+        .mode_fixup = mdp5_crtc_mode_fixup,
+        .mode_set = mdp5_crtc_mode_set,
+        .prepare = mdp5_crtc_prepare,
+        .commit = mdp5_crtc_commit,
+        .mode_set_base = mdp5_crtc_mode_set_base,
+        .load_lut = mdp5_crtc_load_lut,
+};
+
+static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
+{
+        struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
+        struct drm_crtc *crtc = &mdp5_crtc->base;
+        struct msm_drm_private *priv = crtc->dev->dev_private;
+        unsigned pending;
+
+        mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
+
+        pending = atomic_xchg(&mdp5_crtc->pending, 0);
+
+        if (pending & PENDING_FLIP) {
+                complete_flip(crtc, NULL);
+                drm_flip_work_commit(&mdp5_crtc->unref_fb_work, priv->wq);
+        }
+}
+
+static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
+{
+        struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
+        struct drm_crtc *crtc = &mdp5_crtc->base;
+        DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
+        crtc_flush(crtc);
+}
+
+uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        return mdp5_crtc->vblank.irqmask;
+}
+
+void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
+{
+        DBG("cancel: %p", file);
+        complete_flip(crtc, file);
+}
+
+/* set interface for routing crtc->encoder: */
+void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
+                enum mdp5_intf intf_id)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+        struct mdp5_kms *mdp5_kms = get_kms(crtc);
+        static const enum mdp5_intfnum intfnum[] = {
+                        INTF0, INTF1, INTF2, INTF3,
+        };
+        uint32_t intf_sel;
+
+        /* now that we know what irq's we want: */
+        mdp5_crtc->err.irqmask = intf2err(intf);
+        mdp5_crtc->vblank.irqmask = intf2vblank(intf);
+
+        /* when called from modeset_init(), skip the rest until later: */
+        if (!mdp5_kms)
+                return;
+
+        intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
+
+        switch (intf) {
+        case 0:
+                intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
+                intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf_id);
+                break;
+        case 1:
+                intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
+                intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf_id);
+                break;
+        case 2:
+                intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
+                intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf_id);
+                break;
+        case 3:
+                intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
+                intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf_id);
+                break;
+        default:
+                BUG();
+                break;
+        }
+
+        blend_setup(crtc);
+
+        DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
+
+        mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(mdp5_crtc->id),
+                        MDP5_CTL_OP_MODE(MODE_NONE) |
+                        MDP5_CTL_OP_INTF_NUM(intfnum[intf]));
+
+        crtc_flush(crtc);
+}
+
+static void set_attach(struct drm_crtc *crtc, enum mdp5_pipe pipe_id,
+                struct drm_plane *plane)
+{
+        struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
+
+        BUG_ON(pipe_id >= ARRAY_SIZE(mdp5_crtc->planes));
+
+        if (mdp5_crtc->planes[pipe_id] == plane)
+                return;
+
+        mdp5_crtc->planes[pipe_id] = plane;
+        blend_setup(crtc);
+        if (mdp5_crtc->enabled && (plane != mdp5_crtc->plane))
+                crtc_flush(crtc);
+}
+
+void mdp5_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane)
+{
+        set_attach(crtc, mdp5_plane_pipe(plane), plane);
+}
+
+void mdp5_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane)
+{
+        set_attach(crtc, mdp5_plane_pipe(plane), NULL);
+}
+
+/* initialize crtc */
+struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
+                struct drm_plane *plane, int id)
+{
+        struct drm_crtc *crtc = NULL;
+        struct mdp5_crtc *mdp5_crtc;
+        int ret;
+
+        mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
+        if (!mdp5_crtc) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+
+        crtc = &mdp5_crtc->base;
+
+        mdp5_crtc->plane = plane;
+        mdp5_crtc->id = id;
+
+        mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
+        mdp5_crtc->err.irq = mdp5_crtc_err_irq;
+
+        snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
+                        pipe2name(mdp5_plane_pipe(plane)), id);
+
+        ret = drm_flip_work_init(&mdp5_crtc->unref_fb_work, 16,
+                        "unref fb", unref_fb_worker);
+        if (ret)
+                goto fail;
+
+        INIT_FENCE_CB(&mdp5_crtc->pageflip_cb, pageflip_cb);
+
+        drm_crtc_init(dev, crtc, &mdp5_crtc_funcs);
+        drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
+
+        mdp5_plane_install_properties(mdp5_crtc->plane, &crtc->base);
+
+        return crtc;
+
+fail:
+        if (crtc)
+                mdp5_crtc_destroy(crtc);
+
+        return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
new file mode 100644
index 000000000000..edec7bfaa952
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mdp5_kms.h"
+
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+
+struct mdp5_encoder {
+        struct drm_encoder base;
+        int intf;
+        enum mdp5_intf intf_id;
+        bool enabled;
+        uint32_t bsc;
+};
+#define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
+
+static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
+{
+        struct msm_drm_private *priv = encoder->dev->dev_private;
+        return to_mdp5_kms(to_mdp_kms(priv->kms));
+}
+
+#ifdef CONFIG_MSM_BUS_SCALING
+#include <mach/board.h>
+#include <mach/msm_bus.h>
+#include <mach/msm_bus_board.h>
+#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val)            \
+        {                                               \
+                .src = MSM_BUS_MASTER_MDP_PORT0,        \
+                .dst = MSM_BUS_SLAVE_EBI_CH0,           \
+                .ab = (ab_val),                         \
+                .ib = (ib_val),                         \
+        }
+
+static struct msm_bus_vectors mdp_bus_vectors[] = {
+        MDP_BUS_VECTOR_ENTRY(0, 0),
+        MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000),
+};
+static struct msm_bus_paths mdp_bus_usecases[] = { {
+                .num_paths = 1,
+                .vectors = &mdp_bus_vectors[0],
+}, {
+                .num_paths = 1,
+                .vectors = &mdp_bus_vectors[1],
+} };
+static struct msm_bus_scale_pdata mdp_bus_scale_table = {
+        .usecase = mdp_bus_usecases,
+        .num_usecases = ARRAY_SIZE(mdp_bus_usecases),
+        .name = "mdss_mdp",
+};
+
+static void bs_init(struct mdp5_encoder *mdp5_encoder)
+{
+        mdp5_encoder->bsc = msm_bus_scale_register_client(
+                        &mdp_bus_scale_table);
+        DBG("bus scale client: %08x", mdp5_encoder->bsc);
+}
+
+static void bs_fini(struct mdp5_encoder *mdp5_encoder)
+{
+        if (mdp5_encoder->bsc) {
+                msm_bus_scale_unregister_client(mdp5_encoder->bsc);
+                mdp5_encoder->bsc = 0;
+        }
+}
+
+static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx)
+{
+        if (mdp5_encoder->bsc) {
+                DBG("set bus scaling: %d", idx);
+                /* HACK: scaling down, and then immediately back up
+                 * seems to leave things broken (underflow).. so
+                 * never disable:
+                 */
+                idx = 1;
+                msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx);
+        }
+}
+#else
+static void bs_init(struct mdp5_encoder *mdp5_encoder) {}
+static void bs_fini(struct mdp5_encoder *mdp5_encoder) {}
+static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {}
+#endif
+
+static void mdp5_encoder_destroy(struct drm_encoder *encoder)
+{
+        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
+        bs_fini(mdp5_encoder);
+        drm_encoder_cleanup(encoder);
+        kfree(mdp5_encoder);
+}
+
+static const struct drm_encoder_funcs mdp5_encoder_funcs = {
+        .destroy = mdp5_encoder_destroy,
+};
+
+static void mdp5_encoder_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
+        struct mdp5_kms *mdp5_kms = get_kms(encoder);
+        int intf = mdp5_encoder->intf;
+        bool enabled = (mode == DRM_MODE_DPMS_ON);
+
+        DBG("mode=%d", mode);
+
+        if (enabled == mdp5_encoder->enabled)
+                return;
+
+        if (enabled) {
+                bs_set(mdp5_encoder, 1);
+                mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1);
+        } else {
+                mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0);
+                bs_set(mdp5_encoder, 0);
+        }
+
+        mdp5_encoder->enabled = enabled;
+}
+
+static bool mdp5_encoder_mode_fixup(struct drm_encoder *encoder,
+                const struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode)
+{
+        return true;
+}
+
+static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
+                struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode)
+{
+        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
+        struct mdp5_kms *mdp5_kms = get_kms(encoder);
+        int intf = mdp5_encoder->intf;
+        uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
+        uint32_t display_v_start, display_v_end;
+        uint32_t hsync_start_x, hsync_end_x;
+        uint32_t format;
+
+        mode = adjusted_mode;
+
+        DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
+                        mode->base.id, mode->name,
+                        mode->vrefresh, mode->clock,
+                        mode->hdisplay, mode->hsync_start,
+                        mode->hsync_end, mode->htotal,
+                        mode->vdisplay, mode->vsync_start,
+                        mode->vsync_end, mode->vtotal,
+                        mode->type, mode->flags);
+
+        ctrl_pol = 0;
+        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+                ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
+        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+                ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
+        /* probably need to get DATA_EN polarity from panel.. */
+
+        dtv_hsync_skew = 0;  /* get this from panel? */
+        format = 0x213f;     /* get this from panel? */
+
+        hsync_start_x = (mode->htotal - mode->hsync_start);
+        hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
+
+        vsync_period = mode->vtotal * mode->htotal;
+        vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
+        display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
+        display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
+
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
+                        MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
+                        MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
+                        MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
+                        MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
+                        MDP5_INTF_ACTIVE_HCTL_START(0) |
+                        MDP5_INTF_ACTIVE_HCTL_END(0));
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3);  /* frame+line? */
+}
+
+static void mdp5_encoder_prepare(struct drm_encoder *encoder)
+{
+        mdp5_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void mdp5_encoder_commit(struct drm_encoder *encoder)
+{
+        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
+        mdp5_crtc_set_intf(encoder->crtc, mdp5_encoder->intf,
+                        mdp5_encoder->intf_id);
+        mdp5_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
+}
+
+static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
+        .dpms = mdp5_encoder_dpms,
+        .mode_fixup = mdp5_encoder_mode_fixup,
+        .mode_set = mdp5_encoder_mode_set,
+        .prepare = mdp5_encoder_prepare,
+        .commit = mdp5_encoder_commit,
+};
+
+/* initialize encoder */
+struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf,
+                enum mdp5_intf intf_id)
+{
+        struct drm_encoder *encoder = NULL;
+        struct mdp5_encoder *mdp5_encoder;
+        int ret;
+
+        mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
+        if (!mdp5_encoder) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+
+        mdp5_encoder->intf = intf;
+        mdp5_encoder->intf_id = intf_id;
+        encoder = &mdp5_encoder->base;
+
+        drm_encoder_init(dev, encoder, &mdp5_encoder_funcs,
+                         DRM_MODE_ENCODER_TMDS);
+        drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
+
+        bs_init(mdp5_encoder);
+
+        return encoder;
+
+fail:
+        if (encoder)
+                mdp5_encoder_destroy(encoder);
+
+        return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
new file mode 100644
index 000000000000..353d494a497f
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "msm_drv.h"
+#include "mdp5_kms.h"
+
+void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
+{
+        mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
+}
+
+static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
+{
+        DRM_ERROR("errors: %08x\n", irqstatus);
+}
+
+void mdp5_irq_preinstall(struct msm_kms *kms)
+{
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+        mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
+}
+
+int mdp5_irq_postinstall(struct msm_kms *kms)
+{
+        struct mdp_kms *mdp_kms = to_mdp_kms(kms);
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
+        struct mdp_irq *error_handler = &mdp5_kms->error_handler;
+
+        error_handler->irq = mdp5_irq_error_handler;
+        error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
+                        MDP5_IRQ_INTF1_UNDER_RUN |
+                        MDP5_IRQ_INTF2_UNDER_RUN |
+                        MDP5_IRQ_INTF3_UNDER_RUN;
+
+        mdp_irq_register(mdp_kms, error_handler);
+
+        return 0;
+}
+
+void mdp5_irq_uninstall(struct msm_kms *kms)
+{
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+        mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
+}
+
+static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
+{
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
+        struct drm_device *dev = mdp5_kms->dev;
+        struct msm_drm_private *priv = dev->dev_private;
+        unsigned int id;
+        uint32_t status;
+
+        status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS);
+        mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
+
+        VERB("status=%08x", status);
+
+        for (id = 0; id < priv->num_crtcs; id++)
+                if (status & mdp5_crtc_vblank(priv->crtcs[id]))
+                        drm_handle_vblank(dev, id);
+
+        mdp_dispatch_irqs(mdp_kms, status);
+}
+
+irqreturn_t mdp5_irq(struct msm_kms *kms)
+{
+        struct mdp_kms *mdp_kms = to_mdp_kms(kms);
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
+        uint32_t intr;
+
+        intr = mdp5_read(mdp5_kms, REG_MDP5_HW_INTR_STATUS);
+
+        VERB("intr=%08x", intr);
+
+        if (intr & MDP5_HW_INTR_STATUS_INTR_MDP)
+                mdp5_irq_mdp(mdp_kms);
+
+        if (intr & MDP5_HW_INTR_STATUS_INTR_HDMI)
+                hdmi_irq(0, mdp5_kms->hdmi);
+
+        return IRQ_HANDLED;
+}
+
+int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
+{
+        mdp_update_vblank_mask(to_mdp_kms(kms),
+                        mdp5_crtc_vblank(crtc), true);
+        return 0;
+}
+
+void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
+{
+        mdp_update_vblank_mask(to_mdp_kms(kms),
+                        mdp5_crtc_vblank(crtc), false);
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
new file mode 100644
index 000000000000..ee8446c1b5f6
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "msm_drv.h"
+#include "msm_mmu.h"
+#include "mdp5_kms.h"
+
+static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);
+
+static int mdp5_hw_init(struct msm_kms *kms)
+{
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+        struct drm_device *dev = mdp5_kms->dev;
+        uint32_t version, major, minor;
+        int ret = 0;
+
+        pm_runtime_get_sync(dev->dev);
+
+        mdp5_enable(mdp5_kms);
+        version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
+        mdp5_disable(mdp5_kms);
+
+        major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
+        minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
+
+        DBG("found MDP5 version v%d.%d", major, minor);
+
+        if ((major != 1) || ((minor != 0) && (minor != 2))) {
+                dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
+                                major, minor);
+                ret = -ENXIO;
+                goto out;
+        }
+
+        mdp5_kms->rev = minor;
+
+        /* Magic unknown register writes:
+         *
+         *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
+         *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
+         *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
+         *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
+         *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
+         *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
+         *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
+         *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
+         *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
+         *
+         * Downstream fbdev driver gets these register offsets/values
+         * from DT.. not really sure what these registers are or if
+         * different values for different boards/SoC's, etc.  I guess
+         * they are the golden registers.
+         *
+         * Not setting these does not seem to cause any problem.  But
+         * we may be getting lucky with the bootloader initializing
+         * them for us.  OTOH, if we can always count on the bootloader
+         * setting the golden registers, then perhaps we don't need to
+         * care.
+         */
+
+        mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(0), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(1), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(2), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(3), 0);
+
+out:
+        pm_runtime_put_sync(dev->dev);
+
+        return ret;
+}
+
+static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
+                struct drm_encoder *encoder)
+{
+        return rate;
+}
+
+static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
+{
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+        struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
+        unsigned i;
+
+        for (i = 0; i < priv->num_crtcs; i++)
+                mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
+}
+
+static void mdp5_destroy(struct msm_kms *kms)
+{
+        struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+        kfree(mdp5_kms);
+}
+
+static const struct mdp_kms_funcs kms_funcs = {
+        .base = {
+                .hw_init         = mdp5_hw_init,
+                .irq_preinstall  = mdp5_irq_preinstall,
+                .irq_postinstall = mdp5_irq_postinstall,
+                .irq_uninstall   = mdp5_irq_uninstall,
+                .irq             = mdp5_irq,
+                .enable_vblank   = mdp5_enable_vblank,
+                .disable_vblank  = mdp5_disable_vblank,
+                .get_format      = mdp_get_format,
+                .round_pixclk    = mdp5_round_pixclk,
+                .preclose        = mdp5_preclose,
+                .destroy         = mdp5_destroy,
+        },
+        .set_irqmask         = mdp5_set_irqmask,
+};
+
+int mdp5_disable(struct mdp5_kms *mdp5_kms)
+{
+        DBG("");
+
+        clk_disable_unprepare(mdp5_kms->ahb_clk);
+        clk_disable_unprepare(mdp5_kms->axi_clk);
+        clk_disable_unprepare(mdp5_kms->core_clk);
+        clk_disable_unprepare(mdp5_kms->lut_clk);
+
+        return 0;
+}
+
+int mdp5_enable(struct mdp5_kms *mdp5_kms)
+{
+        DBG("");
+
+        clk_prepare_enable(mdp5_kms->ahb_clk);
+        clk_prepare_enable(mdp5_kms->axi_clk);
+        clk_prepare_enable(mdp5_kms->core_clk);
+        clk_prepare_enable(mdp5_kms->lut_clk);
+
+        return 0;
+}
+
+static int modeset_init(struct mdp5_kms *mdp5_kms)
+{
+        static const enum mdp5_pipe crtcs[] = {
+                        SSPP_RGB0, SSPP_RGB1, SSPP_RGB2,
+        };
+        struct drm_device *dev = mdp5_kms->dev;
+        struct msm_drm_private *priv = dev->dev_private;
+        struct drm_encoder *encoder;
+        int i, ret;
+
+        /* construct CRTCs: */
+        for (i = 0; i < ARRAY_SIZE(crtcs); i++) {
+                struct drm_plane *plane;
+                struct drm_crtc *crtc;
+
+                plane = mdp5_plane_init(dev, crtcs[i], true);
+                if (IS_ERR(plane)) {
+                        ret = PTR_ERR(plane);
+                        dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
+                                        pipe2name(crtcs[i]), ret);
+                        goto fail;
+                }
+
+                crtc  = mdp5_crtc_init(dev, plane, i);
+                if (IS_ERR(crtc)) {
+                        ret = PTR_ERR(crtc);
+                        dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
+                                        pipe2name(crtcs[i]), ret);
+                        goto fail;
+                }
+                priv->crtcs[priv->num_crtcs++] = crtc;
+        }
+
+        /* Construct encoder for HDMI: */
+        encoder = mdp5_encoder_init(dev, 3, INTF_HDMI);
+        if (IS_ERR(encoder)) {
+                dev_err(dev->dev, "failed to construct encoder\n");
+                ret = PTR_ERR(encoder);
+                goto fail;
+        }
+
+        /* NOTE: the vsync and error irq's are actually associated with
+         * the INTF/encoder.. the easiest way to deal with this (ie. what
+         * we do now) is assume a fixed relationship between crtc's and
+         * encoders.  I'm not sure if there is ever a need to more freely
+         * assign crtcs to encoders, but if there is then we need to take
+         * care of error and vblank irq's that the crtc has registered,
+         * and also update user-requested vblank_mask.
+         */
+        encoder->possible_crtcs = BIT(0);
+        mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI);
+
+        priv->encoders[priv->num_encoders++] = encoder;
+
+        /* Construct bridge/connector for HDMI: */
+        mdp5_kms->hdmi = hdmi_init(dev, encoder);
+        if (IS_ERR(mdp5_kms->hdmi)) {
+                ret = PTR_ERR(mdp5_kms->hdmi);
+                dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
+                goto fail;
+        }
+
+        return 0;
+
+fail:
+        return ret;
+}
+
+static const char *iommu_ports[] = {
+                "mdp_0",
+};
+
+static int get_clk(struct platform_device *pdev, struct clk **clkp,
+                const char *name)
+{
+        struct device *dev = &pdev->dev;
+        struct clk *clk = devm_clk_get(dev, name);
+        if (IS_ERR(clk)) {
+                dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
+                return PTR_ERR(clk);
+        }
+        *clkp = clk;
+        return 0;
+}
+
+struct msm_kms *mdp5_kms_init(struct drm_device *dev)
+{
+        struct platform_device *pdev = dev->platformdev;
+        struct mdp5_platform_config *config = mdp5_get_config(pdev);
+        struct mdp5_kms *mdp5_kms;
+        struct msm_kms *kms = NULL;
+        struct msm_mmu *mmu;
+        int ret;
+
+        mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
+        if (!mdp5_kms) {
+                dev_err(dev->dev, "failed to allocate kms\n");
+                ret = -ENOMEM;
+                goto fail;
+        }
+
+        mdp_kms_init(&mdp5_kms->base, &kms_funcs);
+
+        kms = &mdp5_kms->base.base;
+
+        mdp5_kms->dev = dev;
+        mdp5_kms->smp_blk_cnt = config->smp_blk_cnt;
+
+        mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
+        if (IS_ERR(mdp5_kms->mmio)) {
+                ret = PTR_ERR(mdp5_kms->mmio);
+                goto fail;
+        }
+
+        mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
+        if (IS_ERR(mdp5_kms->vbif)) {
+                ret = PTR_ERR(mdp5_kms->vbif);
+                goto fail;
+        }
+
+        mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
+        if (IS_ERR(mdp5_kms->vdd)) {
+                ret = PTR_ERR(mdp5_kms->vdd);
+                goto fail;
+        }
+
+        ret = regulator_enable(mdp5_kms->vdd);
+        if (ret) {
+                dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
+                goto fail;
+        }
+
+        ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk") ||
+                        get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk") ||
+                        get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src") ||
+                        get_clk(pdev, &mdp5_kms->core_clk, "core_clk") ||
+                        get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk") ||
+                        get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
+        if (ret)
+                goto fail;
+
+        ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk);
+
+        /* make sure things are off before attaching iommu (bootloader could
+         * have left things on, in which case we'll start getting faults if
+         * we don't disable):
+         */
+        mdp5_enable(mdp5_kms);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(0), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(1), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(2), 0);
+        mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(3), 0);
+        mdp5_disable(mdp5_kms);
+        mdelay(16);
+
+        if (config->iommu) {
+                mmu = msm_iommu_new(dev, config->iommu);
+                if (IS_ERR(mmu)) {
+                        ret = PTR_ERR(mmu);
+                        goto fail;
+                }
+                ret = mmu->funcs->attach(mmu, iommu_ports,
+                                ARRAY_SIZE(iommu_ports));
+                if (ret)
+                        goto fail;
+        } else {
+                dev_info(dev->dev, "no iommu, fallback to phys "
+                                "contig buffers for scanout\n");
+                mmu = NULL;
+        }
+
+        mdp5_kms->id = msm_register_mmu(dev, mmu);
+        if (mdp5_kms->id < 0) {
+                ret = mdp5_kms->id;
+                dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
+                goto fail;
+        }
+
+        ret = modeset_init(mdp5_kms);
+        if (ret) {
+                dev_err(dev->dev, "modeset_init failed: %d\n", ret);
+                goto fail;
+        }
+
+        return kms;
+
+fail:
+        if (kms)
+                mdp5_destroy(kms);
+        return ERR_PTR(ret);
+}
+
+static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev)
+{
+        static struct mdp5_platform_config config = {};
+#ifdef CONFIG_OF
+        /* TODO */
+#endif
+        return &config;
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
new file mode 100644
index 000000000000..c8b1a2522c25
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MDP5_KMS_H__
+#define __MDP5_KMS_H__
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "mdp/mdp_kms.h"
+#include "mdp5.xml.h"
+#include "mdp5_smp.h"
+
+struct mdp5_kms {
+        struct mdp_kms base;
+
+        struct drm_device *dev;
+
+        int rev;
+
+        /* mapper-id used to request GEM buffer mapped for scanout: */
+        int id;
+
+        /* for tracking smp allocation amongst pipes: */
+        mdp5_smp_state_t smp_state;
+        struct mdp5_client_smp_state smp_client_state[CID_MAX];
+        int smp_blk_cnt;
+
+        /* io/register spaces: */
+        void __iomem *mmio, *vbif;
+
+        struct regulator *vdd;
+
+        struct clk *axi_clk;
+        struct clk *ahb_clk;
+        struct clk *src_clk;
+        struct clk *core_clk;
+        struct clk *lut_clk;
+        struct clk *vsync_clk;
+
+        struct hdmi *hdmi;
+
+        struct mdp_irq error_handler;
+};
+#define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
+
+/* platform config data (ie. from DT, or pdata) */
+struct mdp5_platform_config {
+        struct iommu_domain *iommu;
+        uint32_t max_clk;
+        int smp_blk_cnt;
+};
+
+static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
+{
+        msm_writel(data, mdp5_kms->mmio + reg);
+}
+
+static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
+{
+        return msm_readl(mdp5_kms->mmio + reg);
+}
+
+static inline const char *pipe2name(enum mdp5_pipe pipe)
+{
+        static const char *names[] = {
+#define NAME(n) [SSPP_ ## n] = #n
+                NAME(VIG0), NAME(VIG1), NAME(VIG2),
+                NAME(RGB0), NAME(RGB1), NAME(RGB2),
+                NAME(DMA0), NAME(DMA1),
+#undef NAME
+        };
+        return names[pipe];
+}
+
+static inline uint32_t pipe2flush(enum mdp5_pipe pipe)
+{
+        switch (pipe) {
+        case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0;
+        case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1;
+        case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2;
+        case SSPP_RGB0: return MDP5_CTL_FLUSH_RGB0;
+        case SSPP_RGB1: return MDP5_CTL_FLUSH_RGB1;
+        case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2;
+        case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0;
+        case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1;
+        default:        return 0;
+        }
+}
+
+static inline int pipe2nclients(enum mdp5_pipe pipe)
+{
+        switch (pipe) {
+        case SSPP_RGB0:
+        case SSPP_RGB1:
+        case SSPP_RGB2:
+                return 1;
+        default:
+                return 3;
+        }
+}
+
+static inline enum mdp5_client_id pipe2client(enum mdp5_pipe pipe, int plane)
+{
+        WARN_ON(plane >= pipe2nclients(pipe));
+        switch (pipe) {
+        case SSPP_VIG0: return CID_VIG0_Y + plane;
+        case SSPP_VIG1: return CID_VIG1_Y + plane;
+        case SSPP_VIG2: return CID_VIG2_Y + plane;
+        case SSPP_RGB0: return CID_RGB0;
+        case SSPP_RGB1: return CID_RGB1;
+        case SSPP_RGB2: return CID_RGB2;
+        case SSPP_DMA0: return CID_DMA0_Y + plane;
+        case SSPP_DMA1: return CID_DMA1_Y + plane;
+        default:        return CID_UNUSED;
+        }
+}
+
+static inline uint32_t mixer2flush(int lm)
+{
+        switch (lm) {
+        case 0:  return MDP5_CTL_FLUSH_LM0;
+        case 1:  return MDP5_CTL_FLUSH_LM1;
+        case 2:  return MDP5_CTL_FLUSH_LM2;
+        default: return 0;
+        }
+}
+
+static inline uint32_t intf2err(int intf)
+{
+        switch (intf) {
+        case 0:  return MDP5_IRQ_INTF0_UNDER_RUN;
+        case 1:  return MDP5_IRQ_INTF1_UNDER_RUN;
+        case 2:  return MDP5_IRQ_INTF2_UNDER_RUN;
+        case 3:  return MDP5_IRQ_INTF3_UNDER_RUN;
+        default: return 0;
+        }
+}
+
+static inline uint32_t intf2vblank(int intf)
+{
+        switch (intf) {
+        case 0:  return MDP5_IRQ_INTF0_VSYNC;
+        case 1:  return MDP5_IRQ_INTF1_VSYNC;
+        case 2:  return MDP5_IRQ_INTF2_VSYNC;
+        case 3:  return MDP5_IRQ_INTF3_VSYNC;
+        default: return 0;
+        }
+}
+
+int mdp5_disable(struct mdp5_kms *mdp5_kms);
+int mdp5_enable(struct mdp5_kms *mdp5_kms);
+
+void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
+void mdp5_irq_preinstall(struct msm_kms *kms);
+int mdp5_irq_postinstall(struct msm_kms *kms);
+void mdp5_irq_uninstall(struct msm_kms *kms);
+irqreturn_t mdp5_irq(struct msm_kms *kms);
+int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
+void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
+
+static inline
+uint32_t mdp5_get_formats(enum mdp5_pipe pipe, uint32_t *pixel_formats,
+                uint32_t max_formats)
+{
+        /* TODO when we have YUV, we need to filter supported formats
+         * based on pipe id..
+         */
+        return mdp_get_formats(pixel_formats, max_formats);
+}
+
+void mdp5_plane_install_properties(struct drm_plane *plane,
+                struct drm_mode_object *obj);
+void mdp5_plane_set_scanout(struct drm_plane *plane,
+                struct drm_framebuffer *fb);
+int mdp5_plane_mode_set(struct drm_plane *plane,
+                struct drm_crtc *crtc, struct drm_framebuffer *fb,
+                int crtc_x, int crtc_y,
+                unsigned int crtc_w, unsigned int crtc_h,
+                uint32_t src_x, uint32_t src_y,
+                uint32_t src_w, uint32_t src_h);
+void mdp5_plane_complete_flip(struct drm_plane *plane);
+enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
+struct drm_plane *mdp5_plane_init(struct drm_device *dev,
+                enum mdp5_pipe pipe, bool private_plane);
+
+uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
+
+void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
+void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
+                enum mdp5_intf intf_id);
+void mdp5_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane);
+void mdp5_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane);
+struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
+                struct drm_plane *plane, int id);
+
+struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf,
+                enum mdp5_intf intf_id);
+
+#endif /* __MDP5_KMS_H__ */
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
new file mode 100644
index 000000000000..0ac8bb5e7e85
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "mdp5_kms.h"
+
+
+struct mdp5_plane {
+        struct drm_plane base;
+        const char *name;
+
+        enum mdp5_pipe pipe;
+
+        uint32_t nformats;
+        uint32_t formats[32];
+
+        bool enabled;
+};
+#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
+
+static struct mdp5_kms *get_kms(struct drm_plane *plane)
+{
+        struct msm_drm_private *priv = plane->dev->dev_private;
+        return to_mdp5_kms(to_mdp_kms(priv->kms));
+}
+
+static int mdp5_plane_update(struct drm_plane *plane,
+                struct drm_crtc *crtc, struct drm_framebuffer *fb,
+                int crtc_x, int crtc_y,
+                unsigned int crtc_w, unsigned int crtc_h,
+                uint32_t src_x, uint32_t src_y,
+                uint32_t src_w, uint32_t src_h)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+
+        mdp5_plane->enabled = true;
+
+        if (plane->fb)
+                drm_framebuffer_unreference(plane->fb);
+
+        drm_framebuffer_reference(fb);
+
+        return mdp5_plane_mode_set(plane, crtc, fb,
+                        crtc_x, crtc_y, crtc_w, crtc_h,
+                        src_x, src_y, src_w, src_h);
+}
+
+static int mdp5_plane_disable(struct drm_plane *plane)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+        struct mdp5_kms *mdp5_kms = get_kms(plane);
+        enum mdp5_pipe pipe = mdp5_plane->pipe;
+        int i;
+
+        DBG("%s: disable", mdp5_plane->name);
+
+        /* update our SMP request to zero (release all our blks): */
+        for (i = 0; i < pipe2nclients(pipe); i++)
+                mdp5_smp_request(mdp5_kms, pipe2client(pipe, i), 0);
+
+        /* TODO detaching now will cause us not to get the last
+         * vblank and mdp5_smp_commit().. so other planes will
+         * still see smp blocks previously allocated to us as
+         * in-use..
+         */
+        if (plane->crtc)
+                mdp5_crtc_detach(plane->crtc, plane);
+
+        return 0;
+}
+
+static void mdp5_plane_destroy(struct drm_plane *plane)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+
+        mdp5_plane_disable(plane);
+        drm_plane_cleanup(plane);
+
+        kfree(mdp5_plane);
+}
+
+/* helper to install properties which are common to planes and crtcs */
+void mdp5_plane_install_properties(struct drm_plane *plane,
+                struct drm_mode_object *obj)
+{
+        // XXX
+}
+
+int mdp5_plane_set_property(struct drm_plane *plane,
+                struct drm_property *property, uint64_t val)
+{
+        // XXX
+        return -EINVAL;
+}
+
+static const struct drm_plane_funcs mdp5_plane_funcs = {
+                .update_plane = mdp5_plane_update,
+                .disable_plane = mdp5_plane_disable,
+                .destroy = mdp5_plane_destroy,
+                .set_property = mdp5_plane_set_property,
+};
+
+void mdp5_plane_set_scanout(struct drm_plane *plane,
+                struct drm_framebuffer *fb)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+        struct mdp5_kms *mdp5_kms = get_kms(plane);
+        enum mdp5_pipe pipe = mdp5_plane->pipe;
+        uint32_t nplanes = drm_format_num_planes(fb->pixel_format);
+        uint32_t iova[4];
+        int i;
+
+        for (i = 0; i < nplanes; i++) {
+                struct drm_gem_object *bo = msm_framebuffer_bo(fb, i);
+                msm_gem_get_iova(bo, mdp5_kms->id, &iova[i]);
+        }
+        for (; i < 4; i++)
+                iova[i] = 0;
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
+                        MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
+                        MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
+                        MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
+                        MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), iova[0]);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), iova[1]);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), iova[2]);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), iova[3]);
+
+        plane->fb = fb;
+}
+
+/* NOTE: looks like if horizontal decimation is used (if we supported that)
+ * then the width used to calculate SMP block requirements is the post-
+ * decimated width.  Ie. SMP buffering sits downstream of decimation (which
+ * presumably happens during the dma from scanout buffer).
+ */
+static int request_smp_blocks(struct drm_plane *plane, uint32_t format,
+                uint32_t nplanes, uint32_t width)
+{
+        struct drm_device *dev = plane->dev;
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+        struct mdp5_kms *mdp5_kms = get_kms(plane);
+        enum mdp5_pipe pipe = mdp5_plane->pipe;
+        int i, hsub, nlines, nblks, ret;
+
+        hsub = drm_format_horz_chroma_subsampling(format);
+
+        /* different if BWC (compressed framebuffer?) enabled: */
+        nlines = 2;
+
+        for (i = 0, nblks = 0; i < nplanes; i++) {
+                int n, fetch_stride, cpp;
+
+                cpp = drm_format_plane_cpp(format, i);
+                fetch_stride = width * cpp / (i ? hsub : 1);
+
+                n = DIV_ROUND_UP(fetch_stride * nlines, SMP_BLK_SIZE);
+
+                /* for hw rev v1.00 */
+                if (mdp5_kms->rev == 0)
+                        n = roundup_pow_of_two(n);
+
+                DBG("%s[%d]: request %d SMP blocks", mdp5_plane->name, i, n);
+                ret = mdp5_smp_request(mdp5_kms, pipe2client(pipe, i), n);
+                if (ret) {
+                        dev_err(dev->dev, "Could not allocate %d SMP blocks: %d\n",
+                                        n, ret);
+                        return ret;
+                }
+
+                nblks += n;
+        }
+
+        /* in success case, return total # of blocks allocated: */
+        return nblks;
+}
+
+static void set_fifo_thresholds(struct drm_plane *plane, int nblks)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+        struct mdp5_kms *mdp5_kms = get_kms(plane);
+        enum mdp5_pipe pipe = mdp5_plane->pipe;
+        uint32_t val;
+
+        /* 1/4 of SMP pool that is being fetched */
+        val = (nblks * SMP_ENTRIES_PER_BLK) / 4;
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), val * 1);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), val * 2);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), val * 3);
+
+}
+
+int mdp5_plane_mode_set(struct drm_plane *plane,
+                struct drm_crtc *crtc, struct drm_framebuffer *fb,
+                int crtc_x, int crtc_y,
+                unsigned int crtc_w, unsigned int crtc_h,
+                uint32_t src_x, uint32_t src_y,
+                uint32_t src_w, uint32_t src_h)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+        struct mdp5_kms *mdp5_kms = get_kms(plane);
+        enum mdp5_pipe pipe = mdp5_plane->pipe;
+        const struct mdp_format *format;
+        uint32_t nplanes, config = 0;
+        uint32_t phasex_step = 0, phasey_step = 0;
+        uint32_t hdecm = 0, vdecm = 0;
+        int i, nblks;
+
+        nplanes = drm_format_num_planes(fb->pixel_format);
+
+        /* bad formats should already be rejected: */
+        if (WARN_ON(nplanes > pipe2nclients(pipe)))
+                return -EINVAL;
+
+        /* src values are in Q16 fixed point, convert to integer: */
+        src_x = src_x >> 16;
+        src_y = src_y >> 16;
+        src_w = src_w >> 16;
+        src_h = src_h >> 16;
+
+        DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name,
+                        fb->base.id, src_x, src_y, src_w, src_h,
+                        crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
+
+        /*
+         * Calculate and request required # of smp blocks:
+         */
+        nblks = request_smp_blocks(plane, fb->pixel_format, nplanes, src_w);
+        if (nblks < 0)
+                return nblks;
+
+        /*
+         * Currently we update the hw for allocations/requests immediately,
+         * but once atomic modeset/pageflip is in place, the allocation
+         * would move into atomic->check_plane_state(), while updating the
+         * hw would remain here:
+         */
+        for (i = 0; i < pipe2nclients(pipe); i++)
+                mdp5_smp_configure(mdp5_kms, pipe2client(pipe, i));
+
+        if (src_w != crtc_w) {
+                config |= MDP5_PIPE_SCALE_CONFIG_SCALEX_EN;
+                /* TODO calc phasex_step, hdecm */
+        }
+
+        if (src_h != crtc_h) {
+                config |= MDP5_PIPE_SCALE_CONFIG_SCALEY_EN;
+                /* TODO calc phasey_step, vdecm */
+        }
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
+                        MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_w) |
+                        MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_h));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
+                        MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
+                        MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
+                        MDP5_PIPE_SRC_XY_X(src_x) |
+                        MDP5_PIPE_SRC_XY_Y(src_y));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
+                        MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
+                        MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
+                        MDP5_PIPE_OUT_XY_X(crtc_x) |
+                        MDP5_PIPE_OUT_XY_Y(crtc_y));
+
+        mdp5_plane_set_scanout(plane, fb);
+
+        format = to_mdp_format(msm_framebuffer_format(fb));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
+                        MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
+                        MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
+                        MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
+                        MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+                        COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
+                        MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+                        MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
+                        COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
+                        MDP5_PIPE_SRC_FORMAT_NUM_PLANES(nplanes - 1) |
+                        MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(CHROMA_RGB));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
+                        MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
+                        MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
+                        MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
+                        MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
+                        MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
+
+        /* not using secure mode: */
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
+
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), phasex_step);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), phasey_step);
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
+                        MDP5_PIPE_DECIMATION_VERT(vdecm) |
+                        MDP5_PIPE_DECIMATION_HORZ(hdecm));
+        mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
+                        MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(SCALE_FILTER_NEAREST) |
+                        MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(SCALE_FILTER_NEAREST) |
+                        MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(SCALE_FILTER_NEAREST) |
+                        MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(SCALE_FILTER_NEAREST) |
+                        MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(SCALE_FILTER_NEAREST) |
+                        MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(SCALE_FILTER_NEAREST));
+
+        set_fifo_thresholds(plane, nblks);
+
+        /* TODO detach from old crtc (if we had more than one) */
+        mdp5_crtc_attach(crtc, plane);
+
+        return 0;
+}
+
+void mdp5_plane_complete_flip(struct drm_plane *plane)
+{
+        struct mdp5_kms *mdp5_kms = get_kms(plane);
+        enum mdp5_pipe pipe = to_mdp5_plane(plane)->pipe;
+        int i;
+
+        for (i = 0; i < pipe2nclients(pipe); i++)
+                mdp5_smp_commit(mdp5_kms, pipe2client(pipe, i));
+}
+
+enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
+{
+        struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
+        return mdp5_plane->pipe;
+}
+
+/* initialize plane */
+struct drm_plane *mdp5_plane_init(struct drm_device *dev,
+                enum mdp5_pipe pipe, bool private_plane)
+{
+        struct drm_plane *plane = NULL;
+        struct mdp5_plane *mdp5_plane;
+        int ret;
+
+        mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
+        if (!mdp5_plane) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+
+        plane = &mdp5_plane->base;
+
+        mdp5_plane->pipe = pipe;
+        mdp5_plane->name = pipe2name(pipe);
+
+        mdp5_plane->nformats = mdp5_get_formats(pipe, mdp5_plane->formats,
+                        ARRAY_SIZE(mdp5_plane->formats));
+
+        drm_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
+                        mdp5_plane->formats, mdp5_plane->nformats,
+                        private_plane);
+
+        mdp5_plane_install_properties(plane, &plane->base);
+
+        return plane;
+
+fail:
+        if (plane)
+                mdp5_plane_destroy(plane);
+
+        return ERR_PTR(ret);
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
new file mode 100644
index 000000000000..2d0236b963a6
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "mdp5_kms.h"
+#include "mdp5_smp.h"
+
+
+/* SMP - Shared Memory Pool
+ *
+ * These are shared between all the clients, where each plane in a
+ * scanout buffer is a SMP client.  Ie. scanout of 3 plane I420 on
+ * pipe VIG0 => 3 clients: VIG0_Y, VIG0_CB, VIG0_CR.
+ *
+ * Based on the size of the attached scanout buffer, a certain # of
+ * blocks must be allocated to that client out of the shared pool.
+ *
+ * For each block, it can be either free, or pending/in-use by a
+ * client.  The updates happen in three steps:
+ *
+ *  1) mdp5_smp_request():
+ *     When plane scanout is setup, calculate required number of
+ *     blocks needed per client, and request.  Blocks not inuse or
+ *     pending by any other client are added to client's pending
+ *     set.
+ *
+ *  2) mdp5_smp_configure():
+ *     As hw is programmed, before FLUSH, MDP5_SMP_ALLOC registers
+ *     are configured for the union(pending, inuse)
+ *
+ *  3) mdp5_smp_commit():
+ *     After next vblank, copy pending -> inuse.  Optionally update
+ *     MDP5_SMP_ALLOC registers if there are newly unused blocks
+ *
+ * On the next vblank after changes have been committed to hw, the
+ * client's pending blocks become it's in-use blocks (and no-longer
+ * in-use blocks become available to other clients).
+ *
+ * btw, hurray for confusing overloaded acronyms!  :-/
+ *
+ * NOTE: for atomic modeset/pageflip NONBLOCK operations, step #1
+ * should happen at (or before)? atomic->check().  And we'd need
+ * an API to discard previous requests if update is aborted or
+ * (test-only).
+ *
+ * TODO would perhaps be nice to have debugfs to dump out kernel
+ * inuse and pending state of all clients..
+ */
+
+static DEFINE_SPINLOCK(smp_lock);
+
+
+/* step #1: update # of blocks pending for the client: */
+int mdp5_smp_request(struct mdp5_kms *mdp5_kms,
+                enum mdp5_client_id cid, int nblks)
+{
+        struct mdp5_client_smp_state *ps = &mdp5_kms->smp_client_state[cid];
+        int i, ret, avail, cur_nblks, cnt = mdp5_kms->smp_blk_cnt;
+        unsigned long flags;
+
+        spin_lock_irqsave(&smp_lock, flags);
+
+        avail = cnt - bitmap_weight(mdp5_kms->smp_state, cnt);
+        if (nblks > avail) {
+                ret = -ENOSPC;
+                goto fail;
+        }
+
+        cur_nblks = bitmap_weight(ps->pending, cnt);
+        if (nblks > cur_nblks) {
+                /* grow the existing pending reservation: */
+                for (i = cur_nblks; i < nblks; i++) {
+                        int blk = find_first_zero_bit(mdp5_kms->smp_state, cnt);
+                        set_bit(blk, ps->pending);
+                        set_bit(blk, mdp5_kms->smp_state);
+                }
+        } else {
+                /* shrink the existing pending reservation: */
+                for (i = cur_nblks; i > nblks; i--) {
+                        int blk = find_first_bit(ps->pending, cnt);
+                        clear_bit(blk, ps->pending);
+                        /* don't clear in global smp_state until _commit() */
+                }
+        }
+
+fail:
+        spin_unlock_irqrestore(&smp_lock, flags);
+        return 0;
+}
+
+static void update_smp_state(struct mdp5_kms *mdp5_kms,
+                enum mdp5_client_id cid, mdp5_smp_state_t *assigned)
+{
+        int cnt = mdp5_kms->smp_blk_cnt;
+        uint32_t blk, val;
+
+        for_each_set_bit(blk, *assigned, cnt) {
+                int idx = blk / 3;
+                int fld = blk % 3;
+
+                val = mdp5_read(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx));
+
+                switch (fld) {
+                case 0:
+                        val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
+                        val |= MDP5_SMP_ALLOC_W_REG_CLIENT0(cid);
+                        break;
+                case 1:
+                        val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
+                        val |= MDP5_SMP_ALLOC_W_REG_CLIENT1(cid);
+                        break;
+                case 2:
+                        val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
+                        val |= MDP5_SMP_ALLOC_W_REG_CLIENT2(cid);
+                        break;
+                }
+
+                mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val);
+                mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val);
+        }
+}
+
+/* step #2: configure hw for union(pending, inuse): */
+void mdp5_smp_configure(struct mdp5_kms *mdp5_kms, enum mdp5_client_id cid)
+{
+        struct mdp5_client_smp_state *ps = &mdp5_kms->smp_client_state[cid];
+        int cnt = mdp5_kms->smp_blk_cnt;
+        mdp5_smp_state_t assigned;
+
+        bitmap_or(assigned, ps->inuse, ps->pending, cnt);
+        update_smp_state(mdp5_kms, cid, &assigned);
+}
+
+/* step #3: after vblank, copy pending -> inuse: */
+void mdp5_smp_commit(struct mdp5_kms *mdp5_kms, enum mdp5_client_id cid)
+{
+        struct mdp5_client_smp_state *ps = &mdp5_kms->smp_client_state[cid];
+        int cnt = mdp5_kms->smp_blk_cnt;
+        mdp5_smp_state_t released;
+
+        /*
+         * Figure out if there are any blocks we where previously
+         * using, which can be released and made available to other
+         * clients:
+         */
+        if (bitmap_andnot(released, ps->inuse, ps->pending, cnt)) {
+                unsigned long flags;
+
+                spin_lock_irqsave(&smp_lock, flags);
+                /* clear released blocks: */
+                bitmap_andnot(mdp5_kms->smp_state, mdp5_kms->smp_state,
+                                released, cnt);
+                spin_unlock_irqrestore(&smp_lock, flags);
+
+                update_smp_state(mdp5_kms, CID_UNUSED, &released);
+        }
+
+        bitmap_copy(ps->inuse, ps->pending, cnt);
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h
new file mode 100644
index 000000000000..0ab739e1a1dd
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MDP5_SMP_H__
+#define __MDP5_SMP_H__
+
+#include "msm_drv.h"
+
+#define MAX_SMP_BLOCKS  22
+#define SMP_BLK_SIZE    4096
+#define SMP_ENTRIES_PER_BLK (SMP_BLK_SIZE / 16)
+
+typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);
+
+struct mdp5_client_smp_state {
+        mdp5_smp_state_t inuse;
+        mdp5_smp_state_t pending;
+};
+
+struct mdp5_kms;
+
+int mdp5_smp_request(struct mdp5_kms *mdp5_kms, enum mdp5_client_id cid, int nblks);
+void mdp5_smp_configure(struct mdp5_kms *mdp5_kms, enum mdp5_client_id cid);
+void mdp5_smp_commit(struct mdp5_kms *mdp5_kms, enum mdp5_client_id cid);
+
+
+#endif /* __MDP5_SMP_H__ */
diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
new file mode 100644
index 000000000000..a9629b85b983
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
@@ -0,0 +1,78 @@
+#ifndef MDP_COMMON_XML
+#define MDP_COMMON_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/freedreno/envytools/
+git clone https://github.com/freedreno/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    647 bytes, from 2013-11-30 14:45:35)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  17996 bytes, from 2013-12-01 19:10:31)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   1615 bytes, from 2013-11-30 15:00:52)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  22517 bytes, from 2013-12-03 20:59:13)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  20932 bytes, from 2013-12-01 15:13:04)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum mdp_mixer_stage_id {
+        STAGE_UNUSED = 0,
+        STAGE_BASE = 1,
+        STAGE0 = 2,
+        STAGE1 = 3,
+        STAGE2 = 4,
+        STAGE3 = 5,
+};
+
+enum mdp_alpha_type {
+        FG_CONST = 0,
+        BG_CONST = 1,
+        FG_PIXEL = 2,
+        BG_PIXEL = 3,
+};
+
+enum mdp_bpc {
+        BPC1 = 0,
+        BPC5 = 1,
+        BPC6 = 2,
+        BPC8 = 3,
+};
+
+enum mdp_bpc_alpha {
+        BPC1A = 0,
+        BPC4A = 1,
+        BPC6A = 2,
+        BPC8A = 3,
+};
+
+
+#endif /* MDP_COMMON_XML */
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_format.c b/drivers/gpu/drm/msm/mdp/mdp_format.c
index 17330b0927b2..e0a6ffbe6ab4 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_format.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_format.c
@@ -17,7 +17,7 @@
 
 
 #include "msm_drv.h"
-#include "mdp4_kms.h"
+#include "mdp_kms.h"
 
 #define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt) { \
                 .base = { .pixel_format = DRM_FORMAT_ ## name }, \
@@ -34,7 +34,7 @@
 
 #define BPC0A 0
 
-static const struct mdp4_format formats[] = {
+static const struct mdp_format formats[] = {
         /*  name      a  r  g  b   e0 e1 e2 e3  alpha   tight  cpp cnt */
         FMT(ARGB8888, 8, 8, 8, 8,  1, 0, 2, 3,  true,   true,  4,  4),
         FMT(XRGB8888, 8, 8, 8, 8,  1, 0, 2, 3,  false,  true,  4,  4),
@@ -44,12 +44,11 @@ static const struct mdp4_format formats[] = {
         FMT(BGR565,   0, 5, 6, 5,  2, 0, 1, 0,  false,  true,  2,  3),
 };
 
-uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
-                uint32_t max_formats)
+uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats)
 {
         uint32_t i;
         for (i = 0; i < ARRAY_SIZE(formats); i++) {
-                const struct mdp4_format *f = &formats[i];
+                const struct mdp_format *f = &formats[i];
 
                 if (i == max_formats)
                         break;
@@ -60,11 +59,11 @@ uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
         return i;
 }
 
-const struct msm_format *mdp4_get_format(struct msm_kms *kms, uint32_t format)
+const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format)
 {
         int i;
         for (i = 0; i < ARRAY_SIZE(formats); i++) {
-                const struct mdp4_format *f = &formats[i];
+                const struct mdp_format *f = &formats[i];
                 if (f->base.pixel_format == format)
                         return &f->base;
         }
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.c b/drivers/gpu/drm/msm/mdp/mdp_kms.c
new file mode 100644
index 000000000000..3be48f7c36be
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include "msm_drv.h"
+#include "mdp_kms.h"
+
+
+struct mdp_irq_wait {
+        struct mdp_irq irq;
+        int count;
+};
+
+static DECLARE_WAIT_QUEUE_HEAD(wait_event);
+
+static DEFINE_SPINLOCK(list_lock);
+
+static void update_irq(struct mdp_kms *mdp_kms)
+{
+        struct mdp_irq *irq;
+        uint32_t irqmask = mdp_kms->vblank_mask;
+
+        BUG_ON(!spin_is_locked(&list_lock));
+
+        list_for_each_entry(irq, &mdp_kms->irq_list, node)
+                irqmask |= irq->irqmask;
+
+        mdp_kms->funcs->set_irqmask(mdp_kms, irqmask);
+}
+
+static void update_irq_unlocked(struct mdp_kms *mdp_kms)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&list_lock, flags);
+        update_irq(mdp_kms);
+        spin_unlock_irqrestore(&list_lock, flags);
+}
+
+void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status)
+{
+        struct mdp_irq *handler, *n;
+        unsigned long flags;
+
+        spin_lock_irqsave(&list_lock, flags);
+        mdp_kms->in_irq = true;
+        list_for_each_entry_safe(handler, n, &mdp_kms->irq_list, node) {
+                if (handler->irqmask & status) {
+                        spin_unlock_irqrestore(&list_lock, flags);
+                        handler->irq(handler, handler->irqmask & status);
+                        spin_lock_irqsave(&list_lock, flags);
+                }
+        }
+        mdp_kms->in_irq = false;
+        update_irq(mdp_kms);
+        spin_unlock_irqrestore(&list_lock, flags);
+
+}
+
+void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&list_lock, flags);
+        if (enable)
+                mdp_kms->vblank_mask |= mask;
+        else
+                mdp_kms->vblank_mask &= ~mask;
+        update_irq(mdp_kms);
+        spin_unlock_irqrestore(&list_lock, flags);
+}
+
+static void wait_irq(struct mdp_irq *irq, uint32_t irqstatus)
+{
+        struct mdp_irq_wait *wait =
+                        container_of(irq, struct mdp_irq_wait, irq);
+        wait->count--;
+        wake_up_all(&wait_event);
+}
+
+void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask)
+{
+        struct mdp_irq_wait wait = {
+                .irq = {
+                        .irq = wait_irq,
+                        .irqmask = irqmask,
+                },
+                .count = 1,
+        };
+        mdp_irq_register(mdp_kms, &wait.irq);
+        wait_event(wait_event, (wait.count <= 0));
+        mdp_irq_unregister(mdp_kms, &wait.irq);
+}
+
+void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq)
+{
+        unsigned long flags;
+        bool needs_update = false;
+
+        spin_lock_irqsave(&list_lock, flags);
+
+        if (!irq->registered) {
+                irq->registered = true;
+                list_add(&irq->node, &mdp_kms->irq_list);
+                needs_update = !mdp_kms->in_irq;
+        }
+
+        spin_unlock_irqrestore(&list_lock, flags);
+
+        if (needs_update)
+                update_irq_unlocked(mdp_kms);
+}
+
+void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq)
+{
+        unsigned long flags;
+        bool needs_update = false;
+
+        spin_lock_irqsave(&list_lock, flags);
+
+        if (irq->registered) {
+                irq->registered = false;
+                list_del(&irq->node);
+                needs_update = !mdp_kms->in_irq;
+        }
+
+        spin_unlock_irqrestore(&list_lock, flags);
+
+        if (needs_update)
+                update_irq_unlocked(mdp_kms);
+}
diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h b/drivers/gpu/drm/msm/mdp/mdp_kms.h
new file mode 100644
index 000000000000..99557b5ad4fd
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MDP_KMS_H__
+#define __MDP_KMS_H__
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#include "msm_drv.h"
+#include "msm_kms.h"
+#include "mdp_common.xml.h"
+
+struct mdp_kms;
+
+struct mdp_kms_funcs {
+        struct msm_kms_funcs base;
+        void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask);
+};
+
+struct mdp_kms {
+        struct msm_kms base;
+
+        const struct mdp_kms_funcs *funcs;
+
+        /* irq handling: */
+        bool in_irq;
+        struct list_head irq_list;    /* list of mdp4_irq */
+        uint32_t vblank_mask;         /* irq bits set for userspace vblank */
+};
+#define to_mdp_kms(x) container_of(x, struct mdp_kms, base)
+
+static inline void mdp_kms_init(struct mdp_kms *mdp_kms,
+                const struct mdp_kms_funcs *funcs)
+{
+        mdp_kms->funcs = funcs;
+        INIT_LIST_HEAD(&mdp_kms->irq_list);
+        msm_kms_init(&mdp_kms->base, &funcs->base);
+}
+
+/*
+ * irq helpers:
+ */
+
+/* For transiently registering for different MDP irqs that various parts
+ * of the KMS code need during setup/configuration.  These are not
+ * necessarily the same as what drm_vblank_get/put() are requesting, and
+ * the hysteresis in drm_vblank_put() is not necessarily desirable for
+ * internal housekeeping related irq usage.
+ */
+struct mdp_irq {
+        struct list_head node;
+        uint32_t irqmask;
+        bool registered;
+        void (*irq)(struct mdp_irq *irq, uint32_t irqstatus);
+};
+
+void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status);
+void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable);
+void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
+void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
+void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
+
+
+/*
+ * pixel format helpers:
+ */
+
+struct mdp_format {
+        struct msm_format base;
+        enum mdp_bpc bpc_r, bpc_g, bpc_b;
+        enum mdp_bpc_alpha bpc_a;
+        uint8_t unpack[4];
+        bool alpha_enable, unpack_tight;
+        uint8_t cpp, unpack_count;
+};
+#define to_mdp_format(x) container_of(x, struct mdp_format, base)
+
+uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats);
+const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
+
+#endif /* __MDP_KMS_H__ */
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_irq.c b/drivers/gpu/drm/msm/mdp4/mdp4_irq.c
deleted file mode 100644
index 5c6b7fca4edd..000000000000
--- a/drivers/gpu/drm/msm/mdp4/mdp4_irq.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright (C) 2013 Red Hat
- * Author: Rob Clark <robdclark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-#include "msm_drv.h"
-#include "mdp4_kms.h"
-
-
-struct mdp4_irq_wait {
-        struct mdp4_irq irq;
-        int count;
-};
-
-static DECLARE_WAIT_QUEUE_HEAD(wait_event);
-
-static DEFINE_SPINLOCK(list_lock);
-
-static void update_irq(struct mdp4_kms *mdp4_kms)
-{
-        struct mdp4_irq *irq;
-        uint32_t irqmask = mdp4_kms->vblank_mask;
-
-        BUG_ON(!spin_is_locked(&list_lock));
-
-        list_for_each_entry(irq, &mdp4_kms->irq_list, node)
-                irqmask |= irq->irqmask;
-
-        mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, irqmask);
-}
-
-static void update_irq_unlocked(struct mdp4_kms *mdp4_kms)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&list_lock, flags);
-        update_irq(mdp4_kms);
-        spin_unlock_irqrestore(&list_lock, flags);
-}
-
-static void mdp4_irq_error_handler(struct mdp4_irq *irq, uint32_t irqstatus)
-{
-        DRM_ERROR("errors: %08x\n", irqstatus);
-}
-
-void mdp4_irq_preinstall(struct msm_kms *kms)
-{
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
-        mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff);
-}
-
-int mdp4_irq_postinstall(struct msm_kms *kms)
-{
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
-        struct mdp4_irq *error_handler = &mdp4_kms->error_handler;
-
-        INIT_LIST_HEAD(&mdp4_kms->irq_list);
-
-        error_handler->irq = mdp4_irq_error_handler;
-        error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN |
-                        MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
-
-        mdp4_irq_register(mdp4_kms, error_handler);
-
-        return 0;
-}
-
-void mdp4_irq_uninstall(struct msm_kms *kms)
-{
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
-        mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000);
-}
-
-irqreturn_t mdp4_irq(struct msm_kms *kms)
-{
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
-        struct drm_device *dev = mdp4_kms->dev;
-        struct msm_drm_private *priv = dev->dev_private;
-        struct mdp4_irq *handler, *n;
-        unsigned long flags;
-        unsigned int id;
-        uint32_t status;
-
-        status = mdp4_read(mdp4_kms, REG_MDP4_INTR_STATUS);
-        mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status);
-
-        VERB("status=%08x", status);
-
-        for (id = 0; id < priv->num_crtcs; id++)
-                if (status & mdp4_crtc_vblank(priv->crtcs[id]))
-                        drm_handle_vblank(dev, id);
-
-        spin_lock_irqsave(&list_lock, flags);
-        mdp4_kms->in_irq = true;
-        list_for_each_entry_safe(handler, n, &mdp4_kms->irq_list, node) {
-                if (handler->irqmask & status) {
-                        spin_unlock_irqrestore(&list_lock, flags);
-                        handler->irq(handler, handler->irqmask & status);
-                        spin_lock_irqsave(&list_lock, flags);
-                }
-        }
-        mdp4_kms->in_irq = false;
-        update_irq(mdp4_kms);
-        spin_unlock_irqrestore(&list_lock, flags);
-
-        return IRQ_HANDLED;
-}
-
-int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
-{
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
-        unsigned long flags;
-
-        spin_lock_irqsave(&list_lock, flags);
-        mdp4_kms->vblank_mask |= mdp4_crtc_vblank(crtc);
-        update_irq(mdp4_kms);
-        spin_unlock_irqrestore(&list_lock, flags);
-
-        return 0;
-}
-
-void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
-{
-        struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
-        unsigned long flags;
-
-        spin_lock_irqsave(&list_lock, flags);
-        mdp4_kms->vblank_mask &= ~mdp4_crtc_vblank(crtc);
-        update_irq(mdp4_kms);
-        spin_unlock_irqrestore(&list_lock, flags);
-}
-
-static void wait_irq(struct mdp4_irq *irq, uint32_t irqstatus)
-{
-        struct mdp4_irq_wait *wait =
-                        container_of(irq, struct mdp4_irq_wait, irq);
-        wait->count--;
-        wake_up_all(&wait_event);
-}
-
-void mdp4_irq_wait(struct mdp4_kms *mdp4_kms, uint32_t irqmask)
-{
-        struct mdp4_irq_wait wait = {
-                .irq = {
-                        .irq = wait_irq,
-                        .irqmask = irqmask,
-                },
-                .count = 1,
-        };
-        mdp4_irq_register(mdp4_kms, &wait.irq);
-        wait_event(wait_event, (wait.count <= 0));
-        mdp4_irq_unregister(mdp4_kms, &wait.irq);
-}
-
-void mdp4_irq_register(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq)
-{
-        unsigned long flags;
-        bool needs_update = false;
-
-        spin_lock_irqsave(&list_lock, flags);
-
-        if (!irq->registered) {
-                irq->registered = true;
-                list_add(&irq->node, &mdp4_kms->irq_list);
-                needs_update = !mdp4_kms->in_irq;
-        }
-
-        spin_unlock_irqrestore(&list_lock, flags);
-
-        if (needs_update)
-                update_irq_unlocked(mdp4_kms);
-}
-
-void mdp4_irq_unregister(struct mdp4_kms *mdp4_kms, struct mdp4_irq *irq)
-{
-        unsigned long flags;
-        bool needs_update = false;
-
-        spin_lock_irqsave(&list_lock, flags);
-
-        if (irq->registered) {
-                irq->registered = false;
-                list_del(&irq->node);
-                needs_update = !mdp4_kms->in_irq;
-        }
-
-        spin_unlock_irqrestore(&list_lock, flags);
-
-        if (needs_update)
-                update_irq_unlocked(mdp4_kms);
-}
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 28b57eb6f9a1..63ed79fe8a05 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -17,6 +17,7 @@
 
 #include "msm_drv.h"
 #include "msm_gpu.h"
+#include "msm_kms.h"
 
 static void msm_fb_output_poll_changed(struct drm_device *dev)
 {
@@ -30,50 +31,19 @@ static const struct drm_mode_config_funcs mode_config_funcs = {
         .output_poll_changed = msm_fb_output_poll_changed,
 };
 
-static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev,
-                unsigned long iova, int flags, void *arg)
-{
-        DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
-        return 0;
-}
-
-int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu)
+int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
 {
         struct msm_drm_private *priv = dev->dev_private;
-        int idx = priv->num_iommus++;
+        int idx = priv->num_mmus++;
 
-        if (WARN_ON(idx >= ARRAY_SIZE(priv->iommus)))
+        if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
                 return -EINVAL;
 
-        priv->iommus[idx] = iommu;
-
-        iommu_set_fault_handler(iommu, msm_fault_handler, dev);
-
-        /* need to iommu_attach_device() somewhere??  on resume?? */
+        priv->mmus[idx] = mmu;
 
         return idx;
 }
 
-int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu,
-                const char **names, int cnt)
-{
-        int i, ret;
-
-        for (i = 0; i < cnt; i++) {
-                /* TODO maybe some day msm iommu won't require this hack: */
-                struct device *msm_iommu_get_ctx(const char *ctx_name);
-                struct device *ctx = msm_iommu_get_ctx(names[i]);
-                if (!ctx)
-                        continue;
-                ret = iommu_attach_device(iommu, ctx);
-                if (ret) {
-                        dev_warn(dev->dev, "could not attach iommu to %s", names[i]);
-                        return ret;
-                }
-        }
-        return 0;
-}
-
 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
 static bool reglog = false;
 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
@@ -82,6 +52,10 @@ module_param(reglog, bool, 0600);
 #define reglog 0
 #endif
 
+static char *vram;
+MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
+module_param(vram, charp, 0);
+
 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
                 const char *dbgname)
 {
@@ -161,6 +135,14 @@ static int msm_unload(struct drm_device *dev)
                 mutex_unlock(&dev->struct_mutex);
         }
 
+        if (priv->vram.paddr) {
+                DEFINE_DMA_ATTRS(attrs);
+                dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+                drm_mm_takedown(&priv->vram.mm);
+                dma_free_attrs(dev->dev, priv->vram.size, NULL,
+                                priv->vram.paddr, &attrs);
+        }
+
         dev->dev_private = NULL;
 
         kfree(priv);
@@ -168,6 +150,24 @@ static int msm_unload(struct drm_device *dev)
         return 0;
 }
 
+static int get_mdp_ver(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+        const static struct of_device_id match_types[] = { {
+                .compatible = "qcom,mdss_mdp",
+                .data   = (void *)5,
+        }, {
+                /* end node */
+        } };
+        struct device *dev = &pdev->dev;
+        const struct of_device_id *match;
+        match = of_match_node(match_types, dev->of_node);
+        if (match)
+                return (int)match->data;
+#endif
+        return 4;
+}
+
 static int msm_load(struct drm_device *dev, unsigned long flags)
 {
         struct platform_device *pdev = dev->platformdev;
@@ -191,7 +191,53 @@ static int msm_load(struct drm_device *dev, unsigned long flags)
 
         drm_mode_config_init(dev);
 
-        kms = mdp4_kms_init(dev);
+        /* if we have no IOMMU, then we need to use carveout allocator.
+         * Grab the entire CMA chunk carved out in early startup in
+         * mach-msm:
+         */
+        if (!iommu_present(&platform_bus_type)) {
+                DEFINE_DMA_ATTRS(attrs);
+                unsigned long size;
+                void *p;
+
+                DBG("using %s VRAM carveout", vram);
+                size = memparse(vram, NULL);
+                priv->vram.size = size;
+
+                drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
+
+                dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+                dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
+
+                /* note that for no-kernel-mapping, the vaddr returned
+                 * is bogus, but non-null if allocation succeeded:
+                 */
+                p = dma_alloc_attrs(dev->dev, size,
+                                &priv->vram.paddr, 0, &attrs);
+                if (!p) {
+                        dev_err(dev->dev, "failed to allocate VRAM\n");
+                        priv->vram.paddr = 0;
+                        ret = -ENOMEM;
+                        goto fail;
+                }
+
+                dev_info(dev->dev, "VRAM: %08x->%08x\n",
+                                (uint32_t)priv->vram.paddr,
+                                (uint32_t)(priv->vram.paddr + size));
+        }
+
+        switch (get_mdp_ver(pdev)) {
+        case 4:
+                kms = mdp4_kms_init(dev);
+                break;
+        case 5:
+                kms = mdp5_kms_init(dev);
+                break;
+        default:
+                kms = ERR_PTR(-ENODEV);
+                break;
+        }
+
         if (IS_ERR(kms)) {
                 /*
                  * NOTE: once we have GPU support, having no kms should not
@@ -778,6 +824,7 @@ static const struct dev_pm_ops msm_pm_ops = {
 
 static int msm_pdev_probe(struct platform_device *pdev)
 {
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
         return drm_platform_init(&msm_driver, pdev);
 }
 
@@ -793,12 +840,19 @@ static const struct platform_device_id msm_id[] = {
         { }
 };
 
+static const struct of_device_id dt_match[] = {
+        { .compatible = "qcom,mdss_mdp" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, dt_match);
+
 static struct platform_driver msm_platform_driver = {
         .probe      = msm_pdev_probe,
         .remove     = msm_pdev_remove,
         .driver     = {
                 .owner  = THIS_MODULE,
                 .name   = "msm",
+                .of_match_table = dt_match,
                 .pm     = &msm_pm_ops,
         },
         .id_table   = msm_id,
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index d39f0862b19e..3d63269c5b29 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -31,6 +31,15 @@
 #include <linux/types.h>
 #include <asm/sizes.h>
 
+
+#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM)
+/* stubs we need for compile-test: */
+static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
+{
+        return NULL;
+}
+#endif
+
 #ifndef CONFIG_OF
 #include <mach/board.h>
 #include <mach/socinfo.h>
@@ -44,6 +53,7 @@
 
 struct msm_kms;
 struct msm_gpu;
+struct msm_mmu;
 
 #define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */
 
@@ -76,9 +86,9 @@ struct msm_drm_private {
         /* callbacks deferred until bo is inactive: */
         struct list_head fence_cbs;
 
-        /* registered IOMMU domains: */
-        unsigned int num_iommus;
-        struct iommu_domain *iommus[NUM_DOMAINS];
+        /* registered MMUs: */
+        unsigned int num_mmus;
+        struct msm_mmu *mmus[NUM_DOMAINS];
 
         unsigned int num_planes;
         struct drm_plane *planes[8];
@@ -94,6 +104,16 @@ struct msm_drm_private {
 
         unsigned int num_connectors;
         struct drm_connector *connectors[8];
+
+        /* VRAM carveout, used when no IOMMU: */
+        struct {
+                unsigned long size;
+                dma_addr_t paddr;
+                /* NOTE: mm managed at the page level, size is in # of pages
+                 * and position mm_node->start is in # of pages:
+                 */
+                struct drm_mm mm;
+        } vram;
 };
 
 struct msm_format {
@@ -114,39 +134,7 @@ void __msm_fence_worker(struct work_struct *work);
                 (_cb)->func = _func;                         \
         } while (0)
 
-/* As there are different display controller blocks depending on the
- * snapdragon version, the kms support is split out and the appropriate
- * implementation is loaded at runtime.  The kms module is responsible
- * for constructing the appropriate planes/crtcs/encoders/connectors.
- */
-struct msm_kms_funcs {
-        /* hw initialization: */
-        int (*hw_init)(struct msm_kms *kms);
-        /* irq handling: */
-        void (*irq_preinstall)(struct msm_kms *kms);
-        int (*irq_postinstall)(struct msm_kms *kms);
-        void (*irq_uninstall)(struct msm_kms *kms);
-        irqreturn_t (*irq)(struct msm_kms *kms);
-        int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
-        void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
-        /* misc: */
-        const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
-        long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
-                        struct drm_encoder *encoder);
-        /* cleanup: */
-        void (*preclose)(struct msm_kms *kms, struct drm_file *file);
-        void (*destroy)(struct msm_kms *kms);
-};
-
-struct msm_kms {
-        const struct msm_kms_funcs *funcs;
-};
-
-struct msm_kms *mdp4_kms_init(struct drm_device *dev);
-
-int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu);
-int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu,
-                const char **names, int cnt);
+int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 
 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
                 struct timespec *timeout);
@@ -202,7 +190,9 @@ struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
 
 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
 
-int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
+struct hdmi;
+struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
+irqreturn_t hdmi_irq(int irq, void *dev_id);
 void __init hdmi_register(void);
 void __exit hdmi_unregister(void);
 
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index 0286c0eeb10c..81bafdf19ab3 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -16,6 +16,7 @@
  */
 
 #include "msm_drv.h"
+#include "msm_kms.h"
 
 #include "drm_crtc.h"
 #include "drm_crtc_helper.h"
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index e587d251c590..d8d60c969ac7 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -22,7 +22,45 @@
 #include "msm_drv.h"
 #include "msm_gem.h"
 #include "msm_gpu.h"
+#include "msm_mmu.h"
 
+static dma_addr_t physaddr(struct drm_gem_object *obj)
+{
+        struct msm_gem_object *msm_obj = to_msm_bo(obj);
+        struct msm_drm_private *priv = obj->dev->dev_private;
+        return (((dma_addr_t)msm_obj->vram_node->start) << PAGE_SHIFT) +
+                        priv->vram.paddr;
+}
+
+/* allocate pages from VRAM carveout, used when no IOMMU: */
+static struct page **get_pages_vram(struct drm_gem_object *obj,
+                int npages)
+{
+        struct msm_gem_object *msm_obj = to_msm_bo(obj);
+        struct msm_drm_private *priv = obj->dev->dev_private;
+        dma_addr_t paddr;
+        struct page **p;
+        int ret, i;
+
+        p = drm_malloc_ab(npages, sizeof(struct page *));
+        if (!p)
+                return ERR_PTR(-ENOMEM);
+
+        ret = drm_mm_insert_node(&priv->vram.mm, msm_obj->vram_node,
+                        npages, 0, DRM_MM_SEARCH_DEFAULT);
+        if (ret) {
+                drm_free_large(p);
+                return ERR_PTR(ret);
+        }
+
+        paddr = physaddr(obj);
+        for (i = 0; i < npages; i++) {
+                p[i] = phys_to_page(paddr);
+                paddr += PAGE_SIZE;
+        }
+
+        return p;
+}
 
 /* called with dev->struct_mutex held */
 static struct page **get_pages(struct drm_gem_object *obj)
@@ -31,9 +69,14 @@ static struct page **get_pages(struct drm_gem_object *obj)
 
         if (!msm_obj->pages) {
                 struct drm_device *dev = obj->dev;
-                struct page **p = drm_gem_get_pages(obj, 0);
+                struct page **p;
                 int npages = obj->size >> PAGE_SHIFT;
 
+                if (iommu_present(&platform_bus_type))
+                        p = drm_gem_get_pages(obj, 0);
+                else
+                        p = get_pages_vram(obj, npages);
+
                 if (IS_ERR(p)) {
                         dev_err(dev->dev, "could not get pages: %ld\n",
                                         PTR_ERR(p));
@@ -73,7 +116,11 @@ static void put_pages(struct drm_gem_object *obj)
                 sg_free_table(msm_obj->sgt);
                 kfree(msm_obj->sgt);
 
-                drm_gem_put_pages(obj, msm_obj->pages, true, false);
+                if (iommu_present(&platform_bus_type))
+                        drm_gem_put_pages(obj, msm_obj->pages, true, false);
+                else
+                        drm_mm_remove_node(msm_obj->vram_node);
+
                 msm_obj->pages = NULL;
         }
 }
@@ -138,7 +185,6 @@ int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 {
         struct drm_gem_object *obj = vma->vm_private_data;
-        struct msm_gem_object *msm_obj = to_msm_bo(obj);
         struct drm_device *dev = obj->dev;
         struct page **pages;
         unsigned long pfn;
@@ -163,7 +209,7 @@ int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
         pgoff = ((unsigned long)vmf->virtual_address -
                         vma->vm_start) >> PAGE_SHIFT;
 
-        pfn = page_to_pfn(msm_obj->pages[pgoff]);
+        pfn = page_to_pfn(pages[pgoff]);
 
         VERB("Inserting %p pfn %lx, pa %lx", vmf->virtual_address,
                         pfn, pfn << PAGE_SHIFT);
@@ -219,67 +265,6 @@ uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj)
         return offset;
 }
 
-/* helpers for dealing w/ iommu: */
-static int map_range(struct iommu_domain *domain, unsigned int iova,
-                struct sg_table *sgt, unsigned int len, int prot)
-{
-        struct scatterlist *sg;
-        unsigned int da = iova;
-        unsigned int i, j;
-        int ret;
-
-        if (!domain || !sgt)
-                return -EINVAL;
-
-        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
-                u32 pa = sg_phys(sg) - sg->offset;
-                size_t bytes = sg->length + sg->offset;
-
-                VERB("map[%d]: %08x %08x(%x)", i, iova, pa, bytes);
-
-                ret = iommu_map(domain, da, pa, bytes, prot);
-                if (ret)
-                        goto fail;
-
-                da += bytes;
-        }
-
-        return 0;
-
-fail:
-        da = iova;
-
-        for_each_sg(sgt->sgl, sg, i, j) {
-                size_t bytes = sg->length + sg->offset;
-                iommu_unmap(domain, da, bytes);
-                da += bytes;
-        }
-        return ret;
-}
-
-static void unmap_range(struct iommu_domain *domain, unsigned int iova,
-                struct sg_table *sgt, unsigned int len)
-{
-        struct scatterlist *sg;
-        unsigned int da = iova;
-        int i;
-
-        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
-                size_t bytes = sg->length + sg->offset;
-                size_t unmapped;
-
-                unmapped = iommu_unmap(domain, da, bytes);
-                if (unmapped < bytes)
-                        break;
-
-                VERB("unmap[%d]: %08x(%x)", i, iova, bytes);
-
-                BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
-
-                da += bytes;
-        }
-}
-
 /* should be called under struct_mutex.. although it can be called
  * from atomic context without struct_mutex to acquire an extra
  * iova ref if you know one is already held.
@@ -295,15 +280,20 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
 
         if (!msm_obj->domain[id].iova) {
                 struct msm_drm_private *priv = obj->dev->dev_private;
-                uint32_t offset = (uint32_t)mmap_offset(obj);
-                struct page **pages;
-                pages = get_pages(obj);
+                struct msm_mmu *mmu = priv->mmus[id];
+                struct page **pages = get_pages(obj);
+
                 if (IS_ERR(pages))
                         return PTR_ERR(pages);
-                // XXX ideally we would not map buffers writable when not needed...
-                ret = map_range(priv->iommus[id], offset, msm_obj->sgt,
-                                obj->size, IOMMU_READ | IOMMU_WRITE);
-                msm_obj->domain[id].iova = offset;
+
+                if (iommu_present(&platform_bus_type)) {
+                        uint32_t offset = (uint32_t)mmap_offset(obj);
+                        ret = mmu->funcs->map(mmu, offset, msm_obj->sgt,
+                                        obj->size, IOMMU_READ | IOMMU_WRITE);
+                        msm_obj->domain[id].iova = offset;
+                } else {
+                        msm_obj->domain[id].iova = physaddr(obj);
+                }
         }
 
         if (!ret)
@@ -514,6 +504,7 @@ void msm_gem_describe_objects(struct list_head *list, struct seq_file *m)
 void msm_gem_free_object(struct drm_gem_object *obj)
 {
         struct drm_device *dev = obj->dev;
+        struct msm_drm_private *priv = obj->dev->dev_private;
         struct msm_gem_object *msm_obj = to_msm_bo(obj);
         int id;
 
@@ -525,11 +516,10 @@ void msm_gem_free_object(struct drm_gem_object *obj)
         list_del(&msm_obj->mm_list);
 
         for (id = 0; id < ARRAY_SIZE(msm_obj->domain); id++) {
-                if (msm_obj->domain[id].iova) {
-                        struct msm_drm_private *priv = obj->dev->dev_private;
+                struct msm_mmu *mmu = priv->mmus[id];
+                if (mmu && msm_obj->domain[id].iova) {
                         uint32_t offset = (uint32_t)mmap_offset(obj);
-                        unmap_range(priv->iommus[id], offset,
-                                        msm_obj->sgt, obj->size);
+                        mmu->funcs->unmap(mmu, offset, msm_obj->sgt, obj->size);
                 }
         }
 
@@ -591,6 +581,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
 {
         struct msm_drm_private *priv = dev->dev_private;
         struct msm_gem_object *msm_obj;
+        unsigned sz;
 
         switch (flags & MSM_BO_CACHE_MASK) {
         case MSM_BO_UNCACHED:
@@ -603,10 +594,17 @@ static int msm_gem_new_impl(struct drm_device *dev,
                 return -EINVAL;
         }
 
-        msm_obj = kzalloc(sizeof(*msm_obj), GFP_KERNEL);
+        sz = sizeof(*msm_obj);
+        if (!iommu_present(&platform_bus_type))
+                sz += sizeof(struct drm_mm_node);
+
+        msm_obj = kzalloc(sz, GFP_KERNEL);
         if (!msm_obj)
                 return -ENOMEM;
 
+        if (!iommu_present(&platform_bus_type))
+                msm_obj->vram_node = (void *)&msm_obj[1];
+
         msm_obj->flags = flags;
 
         msm_obj->resv = &msm_obj->_resv;
@@ -623,7 +621,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
                 uint32_t size, uint32_t flags)
 {
-        struct drm_gem_object *obj;
+        struct drm_gem_object *obj = NULL;
         int ret;
 
         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -634,9 +632,13 @@ struct drm_gem_object *msm_gem_new(struct drm_device *dev,
         if (ret)
                 goto fail;
 
-        ret = drm_gem_object_init(dev, obj, size);
-        if (ret)
-                goto fail;
+        if (iommu_present(&platform_bus_type)) {
+                ret = drm_gem_object_init(dev, obj, size);
+                if (ret)
+                        goto fail;
+        } else {
+                drm_gem_private_object_init(dev, obj, size);
+        }
 
         return obj;
 
@@ -654,6 +656,12 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev,
         struct drm_gem_object *obj;
         int ret, npages;
 
+        /* if we don't have IOMMU, don't bother pretending we can import: */
+        if (!iommu_present(&platform_bus_type)) {
+                dev_err(dev->dev, "cannot import without IOMMU\n");
+                return ERR_PTR(-EINVAL);
+        }
+
         size = PAGE_ALIGN(size);
 
         ret = msm_gem_new_impl(dev, size, MSM_BO_WC, &obj);
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index f4f23a578d9d..3246bb46c4f2 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -57,6 +57,11 @@ struct msm_gem_object {
         /* normally (resv == &_resv) except for imported bo's */
         struct reservation_object *resv;
         struct reservation_object _resv;
+
+        /* For physically contiguous buffers.  Used when we don't have
+         * an IOMMU.
+         */
+        struct drm_mm_node *vram_node;
 };
 #define to_msm_bo(x) container_of(x, struct msm_gem_object, base)
 
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 4583d61556f5..4ebce8be489d 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -17,6 +17,7 @@
 
 #include "msm_gpu.h"
 #include "msm_gem.h"
+#include "msm_mmu.h"
 
 
 /*
@@ -25,20 +26,10 @@
 
 #ifdef CONFIG_MSM_BUS_SCALING
 #include <mach/board.h>
-#include <mach/kgsl.h>
-static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev)
+static void bs_init(struct msm_gpu *gpu)
 {
-        struct drm_device *dev = gpu->dev;
-        struct kgsl_device_platform_data *pdata;
-
-        if (!pdev) {
-                dev_err(dev->dev, "could not find dtv pdata\n");
-                return;
-        }
-
-        pdata = pdev->dev.platform_data;
-        if (pdata->bus_scale_table) {
-                gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table);
+        if (gpu->bus_scale_table) {
+                gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
                 DBG("bus scale client: %08x", gpu->bsc);
         }
 }
@@ -59,7 +50,7 @@ static void bs_set(struct msm_gpu *gpu, int idx)
         }
 }
 #else
-static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev) {}
+static void bs_init(struct msm_gpu *gpu) {}
 static void bs_fini(struct msm_gpu *gpu) {}
 static void bs_set(struct msm_gpu *gpu, int idx) {}
 #endif
@@ -363,6 +354,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
                 const char *name, const char *ioname, const char *irqname, int ringsz)
 {
+        struct iommu_domain *iommu;
         int i, ret;
 
         gpu->dev = drm;
@@ -428,13 +420,14 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
          * and have separate page tables per context.  For now, to keep things
          * simple and to get something working, just use a single address space:
          */
-        gpu->iommu = iommu_domain_alloc(&platform_bus_type);
-        if (!gpu->iommu) {
-                dev_err(drm->dev, "failed to allocate IOMMU\n");
-                ret = -ENOMEM;
-                goto fail;
+        iommu = iommu_domain_alloc(&platform_bus_type);
+        if (iommu) {
+                dev_info(drm->dev, "%s: using IOMMU\n", name);
+                gpu->mmu = msm_iommu_new(drm, iommu);
+        } else {
+                dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
         }
-        gpu->id = msm_register_iommu(drm, gpu->iommu);
+        gpu->id = msm_register_mmu(drm, gpu->mmu);
 
         /* Create ringbuffer: */
         gpu->rb = msm_ringbuffer_new(gpu, ringsz);
@@ -452,7 +445,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                 goto fail;
         }
 
-        bs_init(gpu, pdev);
+        bs_init(gpu);
 
         return 0;
 
@@ -474,6 +467,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
                 msm_ringbuffer_destroy(gpu->rb);
         }
 
-        if (gpu->iommu)
-                iommu_domain_free(gpu->iommu);
+        if (gpu->mmu)
+                gpu->mmu->funcs->destroy(gpu->mmu);
 }
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 8cd829e520bb..458db8c64c28 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -78,14 +78,18 @@ struct msm_gpu {
         void __iomem *mmio;
         int irq;
 
-        struct iommu_domain *iommu;
+        struct msm_mmu *mmu;
         int id;
 
         /* Power Control: */
         struct regulator *gpu_reg, *gpu_cx;
         struct clk *ebi1_clk, *grp_clks[5];
         uint32_t fast_rate, slow_rate, bus_freq;
+
+#ifdef CONFIG_MSM_BUS_SCALING
+        struct msm_bus_scale_pdata *bus_scale_table;
         uint32_t bsc;
+#endif
 
         /* Hang Detction: */
 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
new file mode 100644
index 000000000000..92b745986231
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "msm_drv.h"
+#include "msm_mmu.h"
+
+struct msm_iommu {
+        struct msm_mmu base;
+        struct iommu_domain *domain;
+};
+#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
+
+static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev,
+                unsigned long iova, int flags, void *arg)
+{
+        DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
+        return 0;
+}
+
+static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt)
+{
+        struct drm_device *dev = mmu->dev;
+        struct msm_iommu *iommu = to_msm_iommu(mmu);
+        int i, ret;
+
+        for (i = 0; i < cnt; i++) {
+                struct device *msm_iommu_get_ctx(const char *ctx_name);
+                struct device *ctx = msm_iommu_get_ctx(names[i]);
+                if (IS_ERR_OR_NULL(ctx))
+                        continue;
+                ret = iommu_attach_device(iommu->domain, ctx);
+                if (ret) {
+                        dev_warn(dev->dev, "could not attach iommu to %s", names[i]);
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova,
+                struct sg_table *sgt, unsigned len, int prot)
+{
+        struct msm_iommu *iommu = to_msm_iommu(mmu);
+        struct iommu_domain *domain = iommu->domain;
+        struct scatterlist *sg;
+        unsigned int da = iova;
+        unsigned int i, j;
+        int ret;
+
+        if (!domain || !sgt)
+                return -EINVAL;
+
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                u32 pa = sg_phys(sg) - sg->offset;
+                size_t bytes = sg->length + sg->offset;
+
+                VERB("map[%d]: %08x %08x(%x)", i, iova, pa, bytes);
+
+                ret = iommu_map(domain, da, pa, bytes, prot);
+                if (ret)
+                        goto fail;
+
+                da += bytes;
+        }
+
+        return 0;
+
+fail:
+        da = iova;
+
+        for_each_sg(sgt->sgl, sg, i, j) {
+                size_t bytes = sg->length + sg->offset;
+                iommu_unmap(domain, da, bytes);
+                da += bytes;
+        }
+        return ret;
+}
+
+static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova,
+                struct sg_table *sgt, unsigned len)
+{
+        struct msm_iommu *iommu = to_msm_iommu(mmu);
+        struct iommu_domain *domain = iommu->domain;
+        struct scatterlist *sg;
+        unsigned int da = iova;
+        int i;
+
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                size_t bytes = sg->length + sg->offset;
+                size_t unmapped;
+
+                unmapped = iommu_unmap(domain, da, bytes);
+                if (unmapped < bytes)
+                        return unmapped;
+
+                VERB("unmap[%d]: %08x(%x)", i, iova, bytes);
+
+                BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
+
+                da += bytes;
+        }
+
+        return 0;
+}
+
+static void msm_iommu_destroy(struct msm_mmu *mmu)
+{
+        struct msm_iommu *iommu = to_msm_iommu(mmu);
+        iommu_domain_free(iommu->domain);
+        kfree(iommu);
+}
+
+static const struct msm_mmu_funcs funcs = {
+                .attach = msm_iommu_attach,
+                .map = msm_iommu_map,
+                .unmap = msm_iommu_unmap,
+                .destroy = msm_iommu_destroy,
+};
+
+struct msm_mmu *msm_iommu_new(struct drm_device *dev, struct iommu_domain *domain)
+{
+        struct msm_iommu *iommu;
+
+        iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
+        if (!iommu)
+                return ERR_PTR(-ENOMEM);
+
+        iommu->domain = domain;
+        msm_mmu_init(&iommu->base, dev, &funcs);
+        iommu_set_fault_handler(domain, msm_fault_handler, dev);
+
+        return &iommu->base;
+}
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
new file mode 100644
index 000000000000..06437745bc2c
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MSM_KMS_H__
+#define __MSM_KMS_H__
+
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+#include "msm_drv.h"
+
+/* As there are different display controller blocks depending on the
+ * snapdragon version, the kms support is split out and the appropriate
+ * implementation is loaded at runtime.  The kms module is responsible
+ * for constructing the appropriate planes/crtcs/encoders/connectors.
+ */
+struct msm_kms_funcs {
+        /* hw initialization: */
+        int (*hw_init)(struct msm_kms *kms);
+        /* irq handling: */
+        void (*irq_preinstall)(struct msm_kms *kms);
+        int (*irq_postinstall)(struct msm_kms *kms);
+        void (*irq_uninstall)(struct msm_kms *kms);
+        irqreturn_t (*irq)(struct msm_kms *kms);
+        int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
+        void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
+        /* misc: */
+        const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
+        long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
+                        struct drm_encoder *encoder);
+        /* cleanup: */
+        void (*preclose)(struct msm_kms *kms, struct drm_file *file);
+        void (*destroy)(struct msm_kms *kms);
+};
+
+struct msm_kms {
+        const struct msm_kms_funcs *funcs;
+
+        /* irq handling: */
+        bool in_irq;
+        struct list_head irq_list;    /* list of mdp4_irq */
+        uint32_t vblank_mask;         /* irq bits set for userspace vblank */
+};
+
+static inline void msm_kms_init(struct msm_kms *kms,
+                const struct msm_kms_funcs *funcs)
+{
+        kms->funcs = funcs;
+}
+
+struct msm_kms *mdp4_kms_init(struct drm_device *dev);
+struct msm_kms *mdp5_kms_init(struct drm_device *dev);
+
+#endif /* __MSM_KMS_H__ */
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
new file mode 100644
index 000000000000..030324482b4a
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_mmu.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MSM_MMU_H__
+#define __MSM_MMU_H__
+
+#include <linux/iommu.h>
+
+struct msm_mmu_funcs {
+        int (*attach)(struct msm_mmu *mmu, const char **names, int cnt);
+        int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
+                        unsigned len, int prot);
+        int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
+                        unsigned len);
+        void (*destroy)(struct msm_mmu *mmu);
+};
+
+struct msm_mmu {
+        const struct msm_mmu_funcs *funcs;
+        struct drm_device *dev;
+};
+
+static inline void msm_mmu_init(struct msm_mmu *mmu, struct drm_device *dev,
+                const struct msm_mmu_funcs *funcs)
+{
+        mmu->dev = dev;
+        mmu->funcs = funcs;
+}
+
+struct msm_mmu *msm_iommu_new(struct drm_device *dev, struct iommu_domain *domain);
+struct msm_mmu *msm_gpummu_new(struct drm_device *dev, struct msm_gpu *gpu);
+
+#endif /* __MSM_MMU_H__ */
diff --git a/drivers/gpu/drm/radeon/atombios_i2c.c b/drivers/gpu/drm/radeon/atombios_i2c.c
index f685035dbe39..b5162c3b6111 100644
--- a/drivers/gpu/drm/radeon/atombios_i2c.c
+++ b/drivers/gpu/drm/radeon/atombios_i2c.c
@@ -27,8 +27,6 @@
 #include "radeon.h"
 #include "atom.h"
 
-extern void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
-
 #define TARGET_HW_I2C_CLOCK 50
 
 /* these are a limitation of ProcessI2cChannelTransaction not the hw */
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 9b6950d9b3c0..0fbd36f3d4e9 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -49,6 +49,7 @@ struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
 
+extern int ni_mc_load_microcode(struct radeon_device *rdev);
 
 //********* BARTS **************//
 static const u32 barts_cgcg_cgls_default[] =
@@ -2510,21 +2511,6 @@ int btc_dpm_enable(struct radeon_device *rdev)
         if (eg_pi->ls_clock_gating)
                 btc_ls_clock_gating_enable(rdev, true);
 
-        if (rdev->irq.installed &&
-            r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
-                PPSMC_Result result;
-
-                ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
-                if (ret)
-                        return ret;
-                rdev->irq.dpm_thermal = true;
-                radeon_irq_set(rdev);
-                result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
-
-                if (result != PPSMC_Result_OK)
-                        DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
-        }
-
         rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
 
         btc_init_stutter_mode(rdev);
@@ -2576,7 +2562,11 @@ void btc_dpm_disable(struct radeon_device *rdev)
 void btc_dpm_setup_asic(struct radeon_device *rdev)
 {
         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+        int r;
 
+        r = ni_mc_load_microcode(rdev);
+        if (r)
+                DRM_ERROR("Failed to load MC firmware!\n");
         rv770_get_memory_type(rdev);
         rv740_read_clock_registers(rdev);
         btc_read_arb_registers(rdev);
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 1ed479976358..8d49104ca6c2 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -171,8 +171,7 @@ extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
                                                      struct atom_voltage_table *voltage_table);
 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
-extern void cik_update_cg(struct radeon_device *rdev,
-                          u32 block, bool enable);
+extern int ci_mc_load_microcode(struct radeon_device *rdev);
 
 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
                                          struct atom_voltage_table_entry *voltage_table,
@@ -4503,8 +4502,8 @@ static void ci_get_memory_type(struct radeon_device *rdev)
 
 }
 
-void ci_update_current_ps(struct radeon_device *rdev,
-                          struct radeon_ps *rps)
+static void ci_update_current_ps(struct radeon_device *rdev,
+                                 struct radeon_ps *rps)
 {
         struct ci_ps *new_ps = ci_get_ps(rps);
         struct ci_power_info *pi = ci_get_pi(rdev);
@@ -4514,8 +4513,8 @@ void ci_update_current_ps(struct radeon_device *rdev,
         pi->current_rps.ps_priv = &pi->current_ps;
 }
 
-void ci_update_requested_ps(struct radeon_device *rdev,
-                            struct radeon_ps *rps)
+static void ci_update_requested_ps(struct radeon_device *rdev,
+                                   struct radeon_ps *rps)
 {
         struct ci_ps *new_ps = ci_get_ps(rps);
         struct ci_power_info *pi = ci_get_pi(rdev);
@@ -4549,6 +4548,11 @@ void ci_dpm_post_set_power_state(struct radeon_device *rdev)
 
 void ci_dpm_setup_asic(struct radeon_device *rdev)
 {
+        int r;
+
+        r = ci_mc_load_microcode(rdev);
+        if (r)
+                DRM_ERROR("Failed to load MC firmware!\n");
         ci_read_clock_registers(rdev);
         ci_get_memory_type(rdev);
         ci_enable_acpi_power_management(rdev);
@@ -4561,13 +4565,6 @@ int ci_dpm_enable(struct radeon_device *rdev)
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
         int ret;
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_MC |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_UVD |
-                             RADEON_CG_BLOCK_HDP), false);
-
         if (ci_is_smc_running(rdev))
                 return -EINVAL;
         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
@@ -4665,6 +4662,18 @@ int ci_dpm_enable(struct radeon_device *rdev)
                 DRM_ERROR("ci_enable_power_containment failed\n");
                 return ret;
         }
+
+        ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
+
+        ci_update_current_ps(rdev, boot_ps);
+
+        return 0;
+}
+
+int ci_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
         if (rdev->irq.installed &&
             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
 #if 0
@@ -4685,19 +4694,8 @@ int ci_dpm_enable(struct radeon_device *rdev)
 #endif
         }
 
-        ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
-
         ci_dpm_powergate_uvd(rdev, true);
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_MC |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_UVD |
-                             RADEON_CG_BLOCK_HDP), true);
-
-        ci_update_current_ps(rdev, boot_ps);
-
         return 0;
 }
 
@@ -4706,12 +4704,6 @@ void ci_dpm_disable(struct radeon_device *rdev)
         struct ci_power_info *pi = ci_get_pi(rdev);
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_MC |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_UVD |
-                             RADEON_CG_BLOCK_HDP), false);
-
         ci_dpm_powergate_uvd(rdev, false);
 
         if (!ci_is_smc_running(rdev))
@@ -4742,13 +4734,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
         struct radeon_ps *old_ps = &pi->current_rps;
         int ret;
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_MC |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_UVD |
-                             RADEON_CG_BLOCK_HDP), false);
-
         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
         if (pi->pcie_performance_request)
                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
@@ -4804,13 +4789,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
         if (pi->pcie_performance_request)
                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_MC |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_UVD |
-                             RADEON_CG_BLOCK_HDP), true);
-
         return 0;
 }
 
@@ -5023,8 +5001,8 @@ static int ci_parse_power_table(struct radeon_device *rdev)
         return 0;
 }
 
-int ci_get_vbios_boot_values(struct radeon_device *rdev,
-                             struct ci_vbios_boot_state *boot_state)
+static int ci_get_vbios_boot_values(struct radeon_device *rdev,
+                                    struct ci_vbios_boot_state *boot_state)
 {
         struct radeon_mode_info *mode_info = &rdev->mode_info;
         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c
index 9c745dd22438..8debc9d47362 100644
--- a/drivers/gpu/drm/radeon/ci_smc.c
+++ b/drivers/gpu/drm/radeon/ci_smc.c
@@ -28,6 +28,7 @@
 #include "cikd.h"
 #include "ppsmc.h"
 #include "radeon_ucode.h"
+#include "ci_dpm.h"
 
 static int ci_set_smc_sram_address(struct radeon_device *rdev,
                                    u32 smc_address, u32 limit)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b43a3a3c9067..9e50dd5d0e42 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1697,7 +1697,7 @@ static void cik_srbm_select(struct radeon_device *rdev,
  * Load the GDDR MC ucode into the hw (CIK).
  * Returns 0 on success, error on failure.
  */
-static int ci_mc_load_microcode(struct radeon_device *rdev)
+int ci_mc_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
         u32 running, blackout = 0;
@@ -4015,15 +4015,43 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
         return 0;
 }
 
-u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
-                              struct radeon_ring *ring)
+u32 cik_gfx_get_rptr(struct radeon_device *rdev,
+                     struct radeon_ring *ring)
 {
         u32 rptr;
 
+        if (rdev->wb.enabled)
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        else
+                rptr = RREG32(CP_RB0_RPTR);
 
+        return rptr;
+}
+
+u32 cik_gfx_get_wptr(struct radeon_device *rdev,
+                     struct radeon_ring *ring)
+{
+        u32 wptr;
+
+        wptr = RREG32(CP_RB0_WPTR);
+
+        return wptr;
+}
+
+void cik_gfx_set_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring)
+{
+        WREG32(CP_RB0_WPTR, ring->wptr);
+        (void)RREG32(CP_RB0_WPTR);
+}
+
+u32 cik_compute_get_rptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring)
+{
+        u32 rptr;
 
         if (rdev->wb.enabled) {
-                rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
         } else {
                 mutex_lock(&rdev->srbm_mutex);
                 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
@@ -4035,13 +4063,14 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
         return rptr;
 }
 
-u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
-                              struct radeon_ring *ring)
+u32 cik_compute_get_wptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring)
 {
         u32 wptr;
 
         if (rdev->wb.enabled) {
-                wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]);
+                /* XXX check if swapping is necessary on BE */
+                wptr = rdev->wb.wb[ring->wptr_offs/4];
         } else {
                 mutex_lock(&rdev->srbm_mutex);
                 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
@@ -4053,10 +4082,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
         return wptr;
 }
 
-void cik_compute_ring_set_wptr(struct radeon_device *rdev,
-                               struct radeon_ring *ring)
+void cik_compute_set_wptr(struct radeon_device *rdev,
+                          struct radeon_ring *ring)
 {
-        rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr);
+        /* XXX check if swapping is necessary on BE */
+        rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
         WDOORBELL32(ring->doorbell_index, ring->wptr);
 }
 
@@ -4850,6 +4880,160 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
         cik_print_gpu_status_regs(rdev);
 }
 
+struct kv_reset_save_regs {
+        u32 gmcon_reng_execute;
+        u32 gmcon_misc;
+        u32 gmcon_misc3;
+};
+
+static void kv_save_regs_for_reset(struct radeon_device *rdev,
+                                   struct kv_reset_save_regs *save)
+{
+        save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
+        save->gmcon_misc = RREG32(GMCON_MISC);
+        save->gmcon_misc3 = RREG32(GMCON_MISC3);
+
+        WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
+        WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
+                                                STCTRL_STUTTER_EN));
+}
+
+static void kv_restore_regs_for_reset(struct radeon_device *rdev,
+                                      struct kv_reset_save_regs *save)
+{
+        int i;
+
+        WREG32(GMCON_PGFSM_WRITE, 0);
+        WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0);
+        WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x210000);
+        WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x21003);
+        WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x2b00);
+        WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0);
+        WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x420000);
+        WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x120202);
+        WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
+        WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
+        WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
+
+        for (i = 0; i < 5; i++)
+                WREG32(GMCON_PGFSM_WRITE, 0);
+
+        WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
+        WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
+
+        WREG32(GMCON_MISC3, save->gmcon_misc3);
+        WREG32(GMCON_MISC, save->gmcon_misc);
+        WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
+}
+
+static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
+{
+        struct evergreen_mc_save save;
+        struct kv_reset_save_regs kv_save = { 0 };
+        u32 tmp, i;
+
+        dev_info(rdev->dev, "GPU pci config reset\n");
+
+        /* disable dpm? */
+
+        /* disable cg/pg */
+        cik_fini_pg(rdev);
+        cik_fini_cg(rdev);
+
+        /* Disable GFX parsing/prefetching */
+        WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+
+        /* Disable MEC parsing/prefetching */
+        WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
+
+        /* sdma0 */
+        tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
+        tmp |= SDMA_HALT;
+        WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
+        /* sdma1 */
+        tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
+        tmp |= SDMA_HALT;
+        WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
+        /* XXX other engines? */
+
+        /* halt the rlc, disable cp internal ints */
+        cik_rlc_stop(rdev);
+
+        udelay(50);
+
+        /* disable mem access */
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
+        }
+
+        if (rdev->flags & RADEON_IS_IGP)
+                kv_save_regs_for_reset(rdev, &kv_save);
+
+        /* disable BM */
+        pci_clear_master(rdev->pdev);
+        /* reset */
+        radeon_pci_config_reset(rdev);
+
+        udelay(100);
+
+        /* wait for asic to come out of reset */
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
+                        break;
+                udelay(1);
+        }
+
+        /* does asic init need to be run first??? */
+        if (rdev->flags & RADEON_IS_IGP)
+                kv_restore_regs_for_reset(rdev, &kv_save);
+}
+
 /**
  * cik_asic_reset - soft reset GPU
  *
@@ -4868,10 +5052,17 @@ int cik_asic_reset(struct radeon_device *rdev)
         if (reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, true);
 
+        /* try soft reset */
         cik_gpu_soft_reset(rdev, reset_mask);
 
         reset_mask = cik_gpu_check_soft_reset(rdev);
 
+        /* try pci config reset */
+        if (reset_mask && radeon_hard_reset)
+                cik_gpu_pci_config_reset(rdev);
+
+        reset_mask = cik_gpu_check_soft_reset(rdev);
+
         if (!reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, false);
 
@@ -7501,26 +7692,7 @@ static int cik_startup(struct radeon_device *rdev)
 
         cik_mc_program(rdev);
 
-        if (rdev->flags & RADEON_IS_IGP) {
-                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
-                    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
-                        r = cik_init_microcode(rdev);
-                        if (r) {
-                                DRM_ERROR("Failed to load firmware!\n");
-                                return r;
-                        }
-                }
-        } else {
-                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
-                    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
-                    !rdev->mc_fw) {
-                        r = cik_init_microcode(rdev);
-                        if (r) {
-                                DRM_ERROR("Failed to load firmware!\n");
-                                return r;
-                        }
-                }
-
+        if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
                 r = ci_mc_load_microcode(rdev);
                 if (r) {
                         DRM_ERROR("Failed to load MC firmware!\n");
@@ -7625,7 +7797,6 @@ static int cik_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             CP_RB0_RPTR, CP_RB0_WPTR,
                              PACKET3(PACKET3_NOP, 0x3FFF));
         if (r)
                 return r;
@@ -7634,7 +7805,6 @@ static int cik_startup(struct radeon_device *rdev)
         /* type-2 packets are deprecated on MEC, use type-3 instead */
         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
-                             CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
                              PACKET3(PACKET3_NOP, 0x3FFF));
         if (r)
                 return r;
@@ -7646,7 +7816,6 @@ static int cik_startup(struct radeon_device *rdev)
         /* type-2 packets are deprecated on MEC, use type-3 instead */
         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
-                             CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
                              PACKET3(PACKET3_NOP, 0x3FFF));
         if (r)
                 return r;
@@ -7658,16 +7827,12 @@ static int cik_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,
-                             SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,
                              SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
-                             SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,
-                             SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET,
                              SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
         if (r)
                 return r;
@@ -7683,7 +7848,6 @@ static int cik_startup(struct radeon_device *rdev)
         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
         if (ring->ring_size) {
                 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                      RADEON_CP_PACKET2);
                 if (!r)
                         r = uvd_v1_0_init(rdev);
@@ -7729,6 +7893,8 @@ int cik_resume(struct radeon_device *rdev)
         /* init golden registers */
         cik_init_golden_registers(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = cik_startup(rdev);
         if (r) {
@@ -7752,6 +7918,7 @@ int cik_resume(struct radeon_device *rdev)
  */
 int cik_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         dce6_audio_fini(rdev);
         radeon_vm_manager_fini(rdev);
         cik_cp_enable(rdev, false);
@@ -7833,6 +8000,30 @@ int cik_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (rdev->flags & RADEON_IS_IGP) {
+                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+                    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
+                        r = cik_init_microcode(rdev);
+                        if (r) {
+                                DRM_ERROR("Failed to load firmware!\n");
+                                return r;
+                        }
+                }
+        } else {
+                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+                    !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
+                    !rdev->mc_fw) {
+                        r = cik_init_microcode(rdev);
+                        if (r) {
+                                DRM_ERROR("Failed to load firmware!\n");
+                                return r;
+                        }
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
@@ -7913,6 +8104,7 @@ int cik_init(struct radeon_device *rdev)
  */
 void cik_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         cik_cp_fini(rdev);
         cik_sdma_fini(rdev);
         cik_fini_pg(rdev);
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 0300727a4f70..f0f9e1089409 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -52,6 +52,75 @@ u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
  */
 
 /**
+ * cik_sdma_get_rptr - get the current read pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current rptr from the hardware (CIK+).
+ */
+uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
+                           struct radeon_ring *ring)
+{
+        u32 rptr, reg;
+
+        if (rdev->wb.enabled) {
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        } else {
+                if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                        reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
+                else
+                        reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
+
+                rptr = RREG32(reg);
+        }
+
+        return (rptr & 0x3fffc) >> 2;
+}
+
+/**
+ * cik_sdma_get_wptr - get the current write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current wptr from the hardware (CIK+).
+ */
+uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
+                           struct radeon_ring *ring)
+{
+        u32 reg;
+
+        if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
+        else
+                reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
+
+        return (RREG32(reg) & 0x3fffc) >> 2;
+}
+
+/**
+ * cik_sdma_set_wptr - commit the write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Write the wptr back to the hardware (CIK+).
+ */
+void cik_sdma_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring)
+{
+        u32 reg;
+
+        if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
+        else
+                reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
+
+        WREG32(reg, (ring->wptr << 2) & 0x3fffc);
+}
+
+/**
  * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
  *
  * @rdev: radeon_device pointer
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 5964af5e5b2d..98bae9d7b74d 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -724,6 +724,17 @@
 
 #define ATC_MISC_CG                                     0x3350
 
+#define GMCON_RENG_EXECUTE                              0x3508
+#define         RENG_EXECUTE_ON_PWR_UP                  (1 << 0)
+#define GMCON_MISC                                      0x350c
+#define         RENG_EXECUTE_ON_REG_UPDATE              (1 << 11)
+#define         STCTRL_STUTTER_EN                       (1 << 16)
+
+#define GMCON_PGFSM_CONFIG                              0x3538
+#define GMCON_PGFSM_WRITE                               0x353c
+#define GMCON_PGFSM_READ                                0x3540
+#define GMCON_MISC3                                     0x3544
+
 #define MC_SEQ_CNTL_3                                     0x3600
 #       define CAC_EN                                     (1 << 31)
 #define MC_SEQ_G5PDX_CTRL                                 0x3604
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c
index 920e1e4a52c5..cf783fc0ef21 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -1905,21 +1905,6 @@ int cypress_dpm_enable(struct radeon_device *rdev)
         if (pi->mg_clock_gating)
                 cypress_mg_clock_gating_enable(rdev, true);
 
-        if (rdev->irq.installed &&
-            r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
-                PPSMC_Result result;
-
-                ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
-                if (ret)
-                        return ret;
-                rdev->irq.dpm_thermal = true;
-                radeon_irq_set(rdev);
-                result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
-
-                if (result != PPSMC_Result_OK)
-                        DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
-        }
-
         rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
 
         return 0;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 9702e55e924e..4116d0279596 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -146,6 +146,7 @@ extern u32 si_get_csb_size(struct radeon_device *rdev);
 extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
 extern u32 cik_get_csb_size(struct radeon_device *rdev);
 extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
+extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 
 static const u32 evergreen_golden_registers[] =
 {
@@ -3867,6 +3868,48 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
         evergreen_print_gpu_status_regs(rdev);
 }
 
+void evergreen_gpu_pci_config_reset(struct radeon_device *rdev)
+{
+        struct evergreen_mc_save save;
+        u32 tmp, i;
+
+        dev_info(rdev->dev, "GPU pci config reset\n");
+
+        /* disable dpm? */
+
+        /* Disable CP parsing/prefetching */
+        WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
+        udelay(50);
+        /* Disable DMA */
+        tmp = RREG32(DMA_RB_CNTL);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL, tmp);
+        /* XXX other engines? */
+
+        /* halt the rlc */
+        r600_rlc_stop(rdev);
+
+        udelay(50);
+
+        /* set mclk/sclk to bypass */
+        rv770_set_clk_bypass_mode(rdev);
+        /* disable BM */
+        pci_clear_master(rdev->pdev);
+        /* disable mem access */
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
+        }
+        /* reset */
+        radeon_pci_config_reset(rdev);
+        /* wait for asic to come out of reset */
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
+                        break;
+                udelay(1);
+        }
+}
+
 int evergreen_asic_reset(struct radeon_device *rdev)
 {
         u32 reset_mask;
@@ -3876,10 +3919,17 @@ int evergreen_asic_reset(struct radeon_device *rdev)
         if (reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, true);
 
+        /* try soft reset */
         evergreen_gpu_soft_reset(rdev, reset_mask);
 
         reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
+        /* try pci config reset */
+        if (reset_mask && radeon_hard_reset)
+                evergreen_gpu_pci_config_reset(rdev);
+
+        reset_mask = evergreen_gpu_check_soft_reset(rdev);
+
         if (!reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, false);
 
@@ -5109,27 +5159,12 @@ static int evergreen_startup(struct radeon_device *rdev)
 
         evergreen_mc_program(rdev);
 
-        if (ASIC_IS_DCE5(rdev)) {
-                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
-                        r = ni_init_microcode(rdev);
-                        if (r) {
-                                DRM_ERROR("Failed to load firmware!\n");
-                                return r;
-                        }
-                }
+        if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {
                 r = ni_mc_load_microcode(rdev);
                 if (r) {
                         DRM_ERROR("Failed to load MC firmware!\n");
                         return r;
                 }
-        } else {
-                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
-                        r = r600_init_microcode(rdev);
-                        if (r) {
-                                DRM_ERROR("Failed to load firmware!\n");
-                                return r;
-                        }
-                }
         }
 
         if (rdev->flags & RADEON_IS_AGP) {
@@ -5199,14 +5234,12 @@ static int evergreen_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             R600_CP_RB_RPTR, R600_CP_RB_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_RB_RPTR, DMA_RB_WPTR,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0));
         if (r)
                 return r;
@@ -5224,7 +5257,6 @@ static int evergreen_startup(struct radeon_device *rdev)
         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
         if (ring->ring_size) {
                 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                      RADEON_CP_PACKET2);
                 if (!r)
                         r = uvd_v1_0_init(rdev);
@@ -5267,6 +5299,8 @@ int evergreen_resume(struct radeon_device *rdev)
         /* init golden registers */
         evergreen_init_golden_registers(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = evergreen_startup(rdev);
         if (r) {
@@ -5281,6 +5315,7 @@ int evergreen_resume(struct radeon_device *rdev)
 
 int evergreen_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r600_audio_fini(rdev);
         uvd_v1_0_fini(rdev);
         radeon_uvd_suspend(rdev);
@@ -5357,6 +5392,27 @@ int evergreen_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (ASIC_IS_DCE5(rdev)) {
+                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
+                        r = ni_init_microcode(rdev);
+                        if (r) {
+                                DRM_ERROR("Failed to load firmware!\n");
+                                return r;
+                        }
+                }
+        } else {
+                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+                        r = r600_init_microcode(rdev);
+                        if (r) {
+                                DRM_ERROR("Failed to load firmware!\n");
+                                return r;
+                        }
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -5409,6 +5465,7 @@ int evergreen_init(struct radeon_device *rdev)
 
 void evergreen_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r600_audio_fini(rdev);
         r700_cp_fini(rdev);
         r600_dma_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index eb8ac315f92f..c7cac07f139b 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -967,7 +967,10 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
         if (track->cb_dirty) {
                 tmp = track->cb_target_mask;
                 for (i = 0; i < 8; i++) {
-                        if ((tmp >> (i * 4)) & 0xF) {
+                        u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
+
+                        if (format != V_028C70_COLOR_INVALID &&
+                            (tmp >> (i * 4)) & 0xF) {
                                 /* at least one component is enabled */
                                 if (track->cb_color_bo[i] == NULL) {
                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index 8a4e641f0e3c..a0f63ff5a5e9 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -33,6 +33,7 @@
 #define EVERGREEN_PIF_PHY0_DATA                         0xc
 #define EVERGREEN_PIF_PHY1_INDEX                        0x10
 #define EVERGREEN_PIF_PHY1_DATA                         0x14
+#define EVERGREEN_MM_INDEX_HI                           0x18
 
 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS               0x310
 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH          0x324
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 17f990798992..f9c7963b3ee6 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -82,12 +82,16 @@
 #define CG_SPLL_FUNC_CNTL_2                             0x604
 #define         SCLK_MUX_SEL(x)                         ((x) << 0)
 #define         SCLK_MUX_SEL_MASK                       (0x1ff << 0)
+#define         SCLK_MUX_UPDATE                         (1 << 26)
 #define CG_SPLL_FUNC_CNTL_3                             0x608
 #define         SPLL_FB_DIV(x)                          ((x) << 0)
 #define         SPLL_FB_DIV_MASK                        (0x3ffffff << 0)
 #define         SPLL_DITHEN                             (1 << 28)
+#define CG_SPLL_STATUS                                  0x60c
+#define         SPLL_CHG_STATUS                         (1 << 1)
 
 #define MPLL_CNTL_MODE                                  0x61c
+#       define MPLL_MCLK_SEL                            (1 << 11)
 #       define SS_SSEN                                  (1 << 24)
 #       define SS_DSMODE_EN                             (1 << 25)
 
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index b41905573cd2..b6e01d5d2cce 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -1126,11 +1126,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
         struct kv_power_info *pi = kv_get_pi(rdev);
         int ret;
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_HDP), false);
-
         ret = kv_process_firmware_header(rdev);
         if (ret) {
                 DRM_ERROR("kv_process_firmware_header failed\n");
@@ -1215,6 +1210,21 @@ int kv_dpm_enable(struct radeon_device *rdev)
 
         kv_reset_acp_boot_level(rdev);
 
+        ret = kv_smc_bapm_enable(rdev, false);
+        if (ret) {
+                DRM_ERROR("kv_smc_bapm_enable failed\n");
+                return ret;
+        }
+
+        kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
+
+        return ret;
+}
+
+int kv_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
         if (rdev->irq.installed &&
             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
                 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1226,35 +1236,17 @@ int kv_dpm_enable(struct radeon_device *rdev)
                 radeon_irq_set(rdev);
         }
 
-        ret = kv_smc_bapm_enable(rdev, false);
-        if (ret) {
-                DRM_ERROR("kv_smc_bapm_enable failed\n");
-                return ret;
-        }
-
         /* powerdown unused blocks for now */
         kv_dpm_powergate_acp(rdev, true);
         kv_dpm_powergate_samu(rdev, true);
         kv_dpm_powergate_vce(rdev, true);
         kv_dpm_powergate_uvd(rdev, true);
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_HDP), true);
-
-        kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
-
         return ret;
 }
 
 void kv_dpm_disable(struct radeon_device *rdev)
 {
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_HDP), false);
-
         kv_smc_bapm_enable(rdev, false);
 
         /* powerup blocks */
@@ -1779,11 +1771,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
         /*struct radeon_ps *old_ps = &pi->current_rps;*/
         int ret;
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_HDP), false);
-
         if (pi->bapm_enable) {
                 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
                 if (ret) {
@@ -1849,11 +1836,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
                 }
         }
 
-        cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                             RADEON_CG_BLOCK_SDMA |
-                             RADEON_CG_BLOCK_BIF |
-                             RADEON_CG_BLOCK_HDP), true);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 11aab2ab54ce..9f11a55962b5 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -174,6 +174,7 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
 extern void evergreen_program_aspm(struct radeon_device *rdev);
 extern void sumo_rlc_fini(struct radeon_device *rdev);
 extern int sumo_rlc_init(struct radeon_device *rdev);
+extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
 
 /* Firmware Names */
 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -1386,6 +1387,55 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
         }
 }
 
+u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
+                        struct radeon_ring *ring)
+{
+        u32 rptr;
+
+        if (rdev->wb.enabled)
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        else {
+                if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
+                        rptr = RREG32(CP_RB0_RPTR);
+                else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
+                        rptr = RREG32(CP_RB1_RPTR);
+                else
+                        rptr = RREG32(CP_RB2_RPTR);
+        }
+
+        return rptr;
+}
+
+u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
+                        struct radeon_ring *ring)
+{
+        u32 wptr;
+
+        if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
+                wptr = RREG32(CP_RB0_WPTR);
+        else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
+                wptr = RREG32(CP_RB1_WPTR);
+        else
+                wptr = RREG32(CP_RB2_WPTR);
+
+        return wptr;
+}
+
+void cayman_gfx_set_wptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring)
+{
+        if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
+                WREG32(CP_RB0_WPTR, ring->wptr);
+                (void)RREG32(CP_RB0_WPTR);
+        } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
+                WREG32(CP_RB1_WPTR, ring->wptr);
+                (void)RREG32(CP_RB1_WPTR);
+        } else {
+                WREG32(CP_RB2_WPTR, ring->wptr);
+                (void)RREG32(CP_RB2_WPTR);
+        }
+}
+
 static int cayman_cp_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
@@ -1514,6 +1564,16 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                 CP_RB1_BASE,
                 CP_RB2_BASE
         };
+        static const unsigned cp_rb_rptr[] = {
+                CP_RB0_RPTR,
+                CP_RB1_RPTR,
+                CP_RB2_RPTR
+        };
+        static const unsigned cp_rb_wptr[] = {
+                CP_RB0_WPTR,
+                CP_RB1_WPTR,
+                CP_RB2_WPTR
+        };
         struct radeon_ring *ring;
         int i, r;
 
@@ -1572,8 +1632,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
 
                 ring->rptr = ring->wptr = 0;
-                WREG32(ring->rptr_reg, ring->rptr);
-                WREG32(ring->wptr_reg, ring->wptr);
+                WREG32(cp_rb_rptr[i], ring->rptr);
+                WREG32(cp_rb_wptr[i], ring->wptr);
 
                 mdelay(1);
                 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
@@ -1819,8 +1879,10 @@ int cayman_asic_reset(struct radeon_device *rdev)
 
         reset_mask = cayman_gpu_check_soft_reset(rdev);
 
-        if (!reset_mask)
-                r600_set_bios_scratch_engine_hung(rdev, false);
+        if (reset_mask)
+                evergreen_gpu_pci_config_reset(rdev);
+
+        r600_set_bios_scratch_engine_hung(rdev, false);
 
         return 0;
 }
@@ -1866,23 +1928,7 @@ static int cayman_startup(struct radeon_device *rdev)
 
         evergreen_mc_program(rdev);
 
-        if (rdev->flags & RADEON_IS_IGP) {
-                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
-                        r = ni_init_microcode(rdev);
-                        if (r) {
-                                DRM_ERROR("Failed to load firmware!\n");
-                                return r;
-                        }
-                }
-        } else {
-                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
-                        r = ni_init_microcode(rdev);
-                        if (r) {
-                                DRM_ERROR("Failed to load firmware!\n");
-                                return r;
-                        }
-                }
-
+        if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
                 r = ni_mc_load_microcode(rdev);
                 if (r) {
                         DRM_ERROR("Failed to load MC firmware!\n");
@@ -1969,23 +2015,18 @@ static int cayman_startup(struct radeon_device *rdev)
         evergreen_irq_set(rdev);
 
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             CP_RB0_RPTR, CP_RB0_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
-                             DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
-                             DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
-                             DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
         if (r)
                 return r;
@@ -2004,7 +2045,6 @@ static int cayman_startup(struct radeon_device *rdev)
         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
         if (ring->ring_size) {
                 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                      RADEON_CP_PACKET2);
                 if (!r)
                         r = uvd_v1_0_init(rdev);
@@ -2051,6 +2091,8 @@ int cayman_resume(struct radeon_device *rdev)
         /* init golden registers */
         ni_init_golden_registers(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = cayman_startup(rdev);
         if (r) {
@@ -2063,6 +2105,7 @@ int cayman_resume(struct radeon_device *rdev)
 
 int cayman_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         if (ASIC_IS_DCE6(rdev))
                 dce6_audio_fini(rdev);
         else
@@ -2133,6 +2176,27 @@ int cayman_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (rdev->flags & RADEON_IS_IGP) {
+                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+                        r = ni_init_microcode(rdev);
+                        if (r) {
+                                DRM_ERROR("Failed to load firmware!\n");
+                                return r;
+                        }
+                }
+        } else {
+                if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
+                        r = ni_init_microcode(rdev);
+                        if (r) {
+                                DRM_ERROR("Failed to load firmware!\n");
+                                return r;
+                        }
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
 
@@ -2192,6 +2256,7 @@ int cayman_init(struct radeon_device *rdev)
 
 void cayman_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         cayman_cp_fini(rdev);
         cayman_dma_fini(rdev);
         r600_irq_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
index bdeb65ed3658..51424ab79432 100644
--- a/drivers/gpu/drm/radeon/ni_dma.c
+++ b/drivers/gpu/drm/radeon/ni_dma.c
@@ -43,6 +43,75 @@ u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);
  */
 
 /**
+ * cayman_dma_get_rptr - get the current read pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current rptr from the hardware (cayman+).
+ */
+uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
+                             struct radeon_ring *ring)
+{
+        u32 rptr, reg;
+
+        if (rdev->wb.enabled) {
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        } else {
+                if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                        reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;
+                else
+                        reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;
+
+                rptr = RREG32(reg);
+        }
+
+        return (rptr & 0x3fffc) >> 2;
+}
+
+/**
+ * cayman_dma_get_wptr - get the current write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current wptr from the hardware (cayman+).
+ */
+uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
+                           struct radeon_ring *ring)
+{
+        u32 reg;
+
+        if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
+        else
+                reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
+
+        return (RREG32(reg) & 0x3fffc) >> 2;
+}
+
+/**
+ * cayman_dma_set_wptr - commit the write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Write the wptr back to the hardware (cayman+).
+ */
+void cayman_dma_set_wptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring)
+{
+        u32 reg;
+
+        if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
+        else
+                reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
+
+        WREG32(reg, (ring->wptr << 2) & 0x3fffc);
+}
+
+/**
  * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
  *
  * @rdev: radeon_device pointer
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 49c4d48f54d6..c351226ecb31 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -720,6 +720,8 @@ static const u32 cayman_sysls_enable[] =
 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
 
+extern int ni_mc_load_microcode(struct radeon_device *rdev);
+
 struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
 {
         struct ni_power_info *pi = rdev->pm.dpm.priv;
@@ -3565,7 +3567,11 @@ void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
 void ni_dpm_setup_asic(struct radeon_device *rdev)
 {
         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+        int r;
 
+        r = ni_mc_load_microcode(rdev);
+        if (r)
+                DRM_ERROR("Failed to load MC firmware!\n");
         ni_read_clock_registers(rdev);
         btc_read_arb_registers(rdev);
         rv770_get_memory_type(rdev);
@@ -3710,21 +3716,6 @@ int ni_dpm_enable(struct radeon_device *rdev)
         if (eg_pi->ls_clock_gating)
                 ni_ls_clockgating_enable(rdev, true);
 
-        if (rdev->irq.installed &&
-            r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
-                PPSMC_Result result;
-
-                ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, 0xff * 1000);
-                if (ret)
-                        return ret;
-                rdev->irq.dpm_thermal = true;
-                radeon_irq_set(rdev);
-                result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
-
-                if (result != PPSMC_Result_OK)
-                        DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
-        }
-
         rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
 
         ni_update_current_ps(rdev, boot_ps);
diff --git a/drivers/gpu/drm/radeon/pptable.h b/drivers/gpu/drm/radeon/pptable.h
index da43ab328833..2d532996c697 100644
--- a/drivers/gpu/drm/radeon/pptable.h
+++ b/drivers/gpu/drm/radeon/pptable.h
@@ -23,7 +23,7 @@
 #ifndef _PPTABLE_H
 #define _PPTABLE_H
 
-#pragma pack(push, 1)
+#pragma pack(1)
 
 typedef struct _ATOM_PPLIB_THERMALCONTROLLER
 
@@ -677,6 +677,6 @@ typedef struct _ATOM_PPLIB_PPM_Table
       ULONG  ulTjmax;
 } ATOM_PPLIB_PPM_Table;
 
-#pragma pack(pop)
+#pragma pack()
 
 #endif
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 10abc4d5a6cc..ef024ce3f7cc 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1050,6 +1050,36 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
         return err;
 }
 
+u32 r100_gfx_get_rptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring)
+{
+        u32 rptr;
+
+        if (rdev->wb.enabled)
+                rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
+        else
+                rptr = RREG32(RADEON_CP_RB_RPTR);
+
+        return rptr;
+}
+
+u32 r100_gfx_get_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring)
+{
+        u32 wptr;
+
+        wptr = RREG32(RADEON_CP_RB_WPTR);
+
+        return wptr;
+}
+
+void r100_gfx_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring)
+{
+        WREG32(RADEON_CP_RB_WPTR, ring->wptr);
+        (void)RREG32(RADEON_CP_RB_WPTR);
+}
+
 static void r100_cp_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
@@ -1102,7 +1132,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
         ring_size = (1 << (rb_bufsz + 1)) * 4;
         r100_cp_load_microcode(rdev);
         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
                              RADEON_CP_PACKET2);
         if (r) {
                 return r;
@@ -3913,6 +3942,8 @@ int r100_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = r100_startup(rdev);
         if (r) {
@@ -3923,6 +3954,7 @@ int r100_resume(struct radeon_device *rdev)
 
 int r100_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
@@ -3933,6 +3965,7 @@ int r100_suspend(struct radeon_device *rdev)
 
 void r100_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
         radeon_ib_pool_fini(rdev);
@@ -4039,6 +4072,9 @@ int r100_init(struct radeon_device *rdev)
         }
         r100_set_safe_registers(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = r100_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index d8dd269b9159..7c63ef840e86 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1430,6 +1430,8 @@ int r300_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = r300_startup(rdev);
         if (r) {
@@ -1440,6 +1442,7 @@ int r300_resume(struct radeon_device *rdev)
 
 int r300_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
@@ -1452,6 +1455,7 @@ int r300_suspend(struct radeon_device *rdev)
 
 void r300_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
         radeon_ib_pool_fini(rdev);
@@ -1538,6 +1542,9 @@ int r300_init(struct radeon_device *rdev)
         }
         r300_set_reg_safe(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = r300_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 6edf2b3a52b4..3768aab2710b 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -325,6 +325,8 @@ int r420_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = r420_startup(rdev);
         if (r) {
@@ -335,6 +337,7 @@ int r420_resume(struct radeon_device *rdev)
 
 int r420_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r420_cp_errata_fini(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
@@ -348,6 +351,7 @@ int r420_suspend(struct radeon_device *rdev)
 
 void r420_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
         radeon_ib_pool_fini(rdev);
@@ -444,6 +448,9 @@ int r420_init(struct radeon_device *rdev)
         }
         r420_set_reg_safe(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = r420_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index e1aece73b370..e209eb75024f 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -240,6 +240,8 @@ int r520_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = r520_startup(rdev);
         if (r) {
@@ -312,6 +314,9 @@ int r520_init(struct radeon_device *rdev)
                 return r;
         rv515_set_safe_registers(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = r520_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 9ad06732a78b..ad99bae2e85c 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -105,6 +105,7 @@ void r600_fini(struct radeon_device *rdev);
 void r600_irq_disable(struct radeon_device *rdev);
 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 extern int evergreen_rlc_resume(struct radeon_device *rdev);
+extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 
 /**
  * r600_get_xclk - get the xclk
@@ -1644,6 +1645,67 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
         r600_print_gpu_status_regs(rdev);
 }
 
+static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
+{
+        struct rv515_mc_save save;
+        u32 tmp, i;
+
+        dev_info(rdev->dev, "GPU pci config reset\n");
+
+        /* disable dpm? */
+
+        /* Disable CP parsing/prefetching */
+        if (rdev->family >= CHIP_RV770)
+                WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
+        else
+                WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
+
+        /* disable the RLC */
+        WREG32(RLC_CNTL, 0);
+
+        /* Disable DMA */
+        tmp = RREG32(DMA_RB_CNTL);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL, tmp);
+
+        mdelay(50);
+
+        /* set mclk/sclk to bypass */
+        if (rdev->family >= CHIP_RV770)
+                rv770_set_clk_bypass_mode(rdev);
+        /* disable BM */
+        pci_clear_master(rdev->pdev);
+        /* disable mem access */
+        rv515_mc_stop(rdev, &save);
+        if (r600_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        /* BIF reset workaround.  Not sure if this is needed on 6xx */
+        tmp = RREG32(BUS_CNTL);
+        tmp |= VGA_COHE_SPEC_TIMER_DIS;
+        WREG32(BUS_CNTL, tmp);
+
+        tmp = RREG32(BIF_SCRATCH0);
+
+        /* reset */
+        radeon_pci_config_reset(rdev);
+        mdelay(1);
+
+        /* BIF reset workaround.  Not sure if this is needed on 6xx */
+        tmp = SOFT_RESET_BIF;
+        WREG32(SRBM_SOFT_RESET, tmp);
+        mdelay(1);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        /* wait for asic to come out of reset */
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
+                        break;
+                udelay(1);
+        }
+}
+
 int r600_asic_reset(struct radeon_device *rdev)
 {
         u32 reset_mask;
@@ -1653,10 +1715,17 @@ int r600_asic_reset(struct radeon_device *rdev)
         if (reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, true);
 
+        /* try soft reset */
         r600_gpu_soft_reset(rdev, reset_mask);
 
         reset_mask = r600_gpu_check_soft_reset(rdev);
 
+        /* try pci config reset */
+        if (reset_mask && radeon_hard_reset)
+                r600_gpu_pci_config_reset(rdev);
+
+        reset_mask = r600_gpu_check_soft_reset(rdev);
+
         if (!reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, false);
 
@@ -2382,6 +2451,36 @@ out:
         return err;
 }
 
+u32 r600_gfx_get_rptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring)
+{
+        u32 rptr;
+
+        if (rdev->wb.enabled)
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        else
+                rptr = RREG32(R600_CP_RB_RPTR);
+
+        return rptr;
+}
+
+u32 r600_gfx_get_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring)
+{
+        u32 wptr;
+
+        wptr = RREG32(R600_CP_RB_WPTR);
+
+        return wptr;
+}
+
+void r600_gfx_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring)
+{
+        WREG32(R600_CP_RB_WPTR, ring->wptr);
+        (void)RREG32(R600_CP_RB_WPTR);
+}
+
 static int r600_cp_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
@@ -2775,14 +2874,6 @@ static int r600_startup(struct radeon_device *rdev)
 
         r600_mc_program(rdev);
 
-        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
-                r = r600_init_microcode(rdev);
-                if (r) {
-                        DRM_ERROR("Failed to load firmware!\n");
-                        return r;
-                }
-        }
-
         if (rdev->flags & RADEON_IS_AGP) {
                 r600_agp_enable(rdev);
         } else {
@@ -2826,14 +2917,12 @@ static int r600_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             R600_CP_RB_RPTR, R600_CP_RB_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_RB_RPTR, DMA_RB_WPTR,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
         if (r)
                 return r;
@@ -2889,6 +2978,8 @@ int r600_resume(struct radeon_device *rdev)
         /* post card */
         atom_asic_init(rdev->mode_info.atom_context);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = r600_startup(rdev);
         if (r) {
@@ -2902,6 +2993,7 @@ int r600_resume(struct radeon_device *rdev)
 
 int r600_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r600_audio_fini(rdev);
         r600_cp_stop(rdev);
         r600_dma_stop(rdev);
@@ -2970,6 +3062,17 @@ int r600_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+                r = r600_init_microcode(rdev);
+                if (r) {
+                        DRM_ERROR("Failed to load firmware!\n");
+                        return r;
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -3002,6 +3105,7 @@ int r600_init(struct radeon_device *rdev)
 
 void r600_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r600_audio_fini(rdev);
         r600_cp_fini(rdev);
         r600_dma_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index d824f7fed47d..7b399dc5fd54 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -749,7 +749,10 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
                 }
 
                 for (i = 0; i < 8; i++) {
-                        if ((tmp >> (i * 4)) & 0xF) {
+                        u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
+
+                        if (format != V_0280A0_COLOR_INVALID &&
+                            (tmp >> (i * 4)) & 0xF) {
                                 /* at least one component is enabled */
                                 if (track->cb_color_bo[i] == NULL) {
                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index 7844d15c139f..3452c8410bd7 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -51,7 +51,14 @@ u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);
 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
                            struct radeon_ring *ring)
 {
-        return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2;
+        u32 rptr;
+
+        if (rdev->wb.enabled)
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        else
+                rptr = RREG32(DMA_RB_RPTR);
+
+        return (rptr & 0x3fffc) >> 2;
 }
 
 /**
@@ -65,7 +72,7 @@ uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
                            struct radeon_ring *ring)
 {
-        return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2;
+        return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
 }
 
 /**
@@ -79,7 +86,7 @@ uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
 void r600_dma_set_wptr(struct radeon_device *rdev,
                        struct radeon_ring *ring)
 {
-        WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc);
+        WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 5513d8f06252..e4cc9b314ce9 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -729,8 +729,8 @@ bool r600_is_uvd_state(u32 class, u32 class2)
         return false;
 }
 
-int r600_set_thermal_temperature_range(struct radeon_device *rdev,
-                                       int min_temp, int max_temp)
+static int r600_set_thermal_temperature_range(struct radeon_device *rdev,
+                                              int min_temp, int max_temp)
 {
         int low_temp = 0 * 1000;
         int high_temp = 255 * 1000;
@@ -777,6 +777,22 @@ bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
         }
 }
 
+int r600_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
+        if (rdev->irq.installed &&
+            r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
+                ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
+                if (ret)
+                        return ret;
+                rdev->irq.dpm_thermal = true;
+                radeon_irq_set(rdev);
+        }
+
+        return 0;
+}
+
 union power_info {
         struct _ATOM_POWERPLAY_INFO info;
         struct _ATOM_POWERPLAY_INFO_V2 info_2;
diff --git a/drivers/gpu/drm/radeon/r600_dpm.h b/drivers/gpu/drm/radeon/r600_dpm.h
index 1000bf9719f2..07eab2b04e81 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.h
+++ b/drivers/gpu/drm/radeon/r600_dpm.h
@@ -213,8 +213,6 @@ void r600_wait_for_power_level(struct radeon_device *rdev,
 void r600_start_dpm(struct radeon_device *rdev);
 void r600_stop_dpm(struct radeon_device *rdev);
 
-int r600_set_thermal_temperature_range(struct radeon_device *rdev,
-                                       int min_temp, int max_temp);
 bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
 
 int r600_parse_extended_power_table(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index b7d3ecba43e3..3016fc14f502 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -250,7 +250,7 @@ static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
                  value, ~HDMI0_AUDIO_TEST_EN);
 }
 
-void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
+static void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 {
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index ebe38724a976..3fca4b9c65ad 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -701,11 +701,18 @@
 #define RLC_UCODE_DATA                                    0x3f30
 
 #define SRBM_SOFT_RESET                                   0xe60
+#       define SOFT_RESET_BIF                             (1 << 1)
 #       define SOFT_RESET_DMA                             (1 << 12)
 #       define SOFT_RESET_RLC                             (1 << 13)
 #       define SOFT_RESET_UVD                             (1 << 18)
 #       define RV770_SOFT_RESET_DMA                       (1 << 20)
 
+#define BIF_SCRATCH0                                      0x5438
+
+#define BUS_CNTL                                          0x5420
+#       define BIOS_ROM_DIS                               (1 << 1)
+#       define VGA_COHE_SPEC_TIMER_DIS                    (1 << 9)
+
 #define CP_INT_CNTL                                       0xc124
 #       define CNTX_BUSY_INT_ENABLE                       (1 << 19)
 #       define CNTX_EMPTY_INT_ENABLE                      (1 << 20)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b1f990d0eaa1..746c0c6c269b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -99,6 +99,7 @@ extern int radeon_fastfb;
 extern int radeon_dpm;
 extern int radeon_aspm;
 extern int radeon_runtime_pm;
+extern int radeon_hard_reset;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -139,6 +140,9 @@ extern int radeon_runtime_pm;
 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 
+/* hard reset data */
+#define RADEON_ASIC_RESET_DATA                  0x39d5e86b
+
 /* reset flags */
 #define RADEON_RESET_GFX                        (1 << 0)
 #define RADEON_RESET_COMPUTE                    (1 << 1)
@@ -252,6 +256,7 @@ struct radeon_clock {
  * Power management
  */
 int radeon_pm_init(struct radeon_device *rdev);
+int radeon_pm_late_init(struct radeon_device *rdev);
 void radeon_pm_fini(struct radeon_device *rdev);
 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 void radeon_pm_suspend(struct radeon_device *rdev);
@@ -413,6 +418,11 @@ struct radeon_mman {
         struct ttm_bo_device            bdev;
         bool                            mem_global_referenced;
         bool                            initialized;
+
+#if defined(CONFIG_DEBUG_FS)
+        struct dentry                   *vram;
+        struct dentry                   *gtt;
+#endif
 };
 
 /* bo virtual address in a specific vm */
@@ -779,13 +789,11 @@ struct radeon_ring {
         volatile uint32_t       *ring;
         unsigned                rptr;
         unsigned                rptr_offs;
-        unsigned                rptr_reg;
         unsigned                rptr_save_reg;
         u64                     next_rptr_gpu_addr;
         volatile u32            *next_rptr_cpu_addr;
         unsigned                wptr;
         unsigned                wptr_old;
-        unsigned                wptr_reg;
         unsigned                ring_size;
         unsigned                ring_free_dw;
         int                     count_dw;
@@ -949,7 +957,7 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring
 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
                         unsigned size, uint32_t *data);
 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
-                     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
+                     unsigned rptr_offs, u32 nop);
 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 
 
@@ -1775,6 +1783,7 @@ struct radeon_asic {
                 int (*init)(struct radeon_device *rdev);
                 void (*setup_asic)(struct radeon_device *rdev);
                 int (*enable)(struct radeon_device *rdev);
+                int (*late_enable)(struct radeon_device *rdev);
                 void (*disable)(struct radeon_device *rdev);
                 int (*pre_set_power_state)(struct radeon_device *rdev);
                 int (*set_power_state)(struct radeon_device *rdev);
@@ -2650,6 +2659,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
+#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
@@ -2668,6 +2678,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 /* Common functions */
 /* AGP */
 extern int radeon_gpu_reset(struct radeon_device *rdev);
+extern void radeon_pci_config_reset(struct radeon_device *rdev);
 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
 extern void radeon_agp_disable(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index e354ce94cdd1..f55879dd11c6 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -182,9 +182,9 @@ static struct radeon_asic_ring r100_gfx_ring = {
         .ring_test = &r100_ring_test,
         .ib_test = &r100_ib_test,
         .is_lockup = &r100_gpu_is_lockup,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &r100_gfx_get_rptr,
+        .get_wptr = &r100_gfx_get_wptr,
+        .set_wptr = &r100_gfx_set_wptr,
 };
 
 static struct radeon_asic r100_asic = {
@@ -330,9 +330,9 @@ static struct radeon_asic_ring r300_gfx_ring = {
         .ring_test = &r100_ring_test,
         .ib_test = &r100_ib_test,
         .is_lockup = &r100_gpu_is_lockup,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &r100_gfx_get_rptr,
+        .get_wptr = &r100_gfx_get_wptr,
+        .set_wptr = &r100_gfx_set_wptr,
 };
 
 static struct radeon_asic r300_asic = {
@@ -883,9 +883,9 @@ static struct radeon_asic_ring r600_gfx_ring = {
         .ring_test = &r600_ring_test,
         .ib_test = &r600_ib_test,
         .is_lockup = &r600_gfx_is_lockup,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &r600_gfx_get_rptr,
+        .get_wptr = &r600_gfx_get_wptr,
+        .set_wptr = &r600_gfx_set_wptr,
 };
 
 static struct radeon_asic_ring r600_dma_ring = {
@@ -1045,6 +1045,7 @@ static struct radeon_asic rv6xx_asic = {
                 .init = &rv6xx_dpm_init,
                 .setup_asic = &rv6xx_setup_asic,
                 .enable = &rv6xx_dpm_enable,
+                .late_enable = &r600_dpm_late_enable,
                 .disable = &rv6xx_dpm_disable,
                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
                 .set_power_state = &rv6xx_dpm_set_power_state,
@@ -1135,6 +1136,7 @@ static struct radeon_asic rs780_asic = {
                 .init = &rs780_dpm_init,
                 .setup_asic = &rs780_dpm_setup_asic,
                 .enable = &rs780_dpm_enable,
+                .late_enable = &r600_dpm_late_enable,
                 .disable = &rs780_dpm_disable,
                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
                 .set_power_state = &rs780_dpm_set_power_state,
@@ -1239,6 +1241,7 @@ static struct radeon_asic rv770_asic = {
                 .init = &rv770_dpm_init,
                 .setup_asic = &rv770_dpm_setup_asic,
                 .enable = &rv770_dpm_enable,
+                .late_enable = &rv770_dpm_late_enable,
                 .disable = &rv770_dpm_disable,
                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
                 .set_power_state = &rv770_dpm_set_power_state,
@@ -1267,9 +1270,9 @@ static struct radeon_asic_ring evergreen_gfx_ring = {
         .ring_test = &r600_ring_test,
         .ib_test = &r600_ib_test,
         .is_lockup = &evergreen_gfx_is_lockup,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &r600_gfx_get_rptr,
+        .get_wptr = &r600_gfx_get_wptr,
+        .set_wptr = &r600_gfx_set_wptr,
 };
 
 static struct radeon_asic_ring evergreen_dma_ring = {
@@ -1357,6 +1360,7 @@ static struct radeon_asic evergreen_asic = {
                 .init = &cypress_dpm_init,
                 .setup_asic = &cypress_dpm_setup_asic,
                 .enable = &cypress_dpm_enable,
+                .late_enable = &rv770_dpm_late_enable,
                 .disable = &cypress_dpm_disable,
                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
                 .set_power_state = &cypress_dpm_set_power_state,
@@ -1449,6 +1453,7 @@ static struct radeon_asic sumo_asic = {
                 .init = &sumo_dpm_init,
                 .setup_asic = &sumo_dpm_setup_asic,
                 .enable = &sumo_dpm_enable,
+                .late_enable = &sumo_dpm_late_enable,
                 .disable = &sumo_dpm_disable,
                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
                 .set_power_state = &sumo_dpm_set_power_state,
@@ -1540,6 +1545,7 @@ static struct radeon_asic btc_asic = {
                 .init = &btc_dpm_init,
                 .setup_asic = &btc_dpm_setup_asic,
                 .enable = &btc_dpm_enable,
+                .late_enable = &rv770_dpm_late_enable,
                 .disable = &btc_dpm_disable,
                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
                 .set_power_state = &btc_dpm_set_power_state,
@@ -1570,9 +1576,9 @@ static struct radeon_asic_ring cayman_gfx_ring = {
         .ib_test = &r600_ib_test,
         .is_lockup = &cayman_gfx_is_lockup,
         .vm_flush = &cayman_vm_flush,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &cayman_gfx_get_rptr,
+        .get_wptr = &cayman_gfx_get_wptr,
+        .set_wptr = &cayman_gfx_set_wptr,
 };
 
 static struct radeon_asic_ring cayman_dma_ring = {
@@ -1585,9 +1591,9 @@ static struct radeon_asic_ring cayman_dma_ring = {
         .ib_test = &r600_dma_ib_test,
         .is_lockup = &cayman_dma_is_lockup,
         .vm_flush = &cayman_dma_vm_flush,
-        .get_rptr = &r600_dma_get_rptr,
-        .get_wptr = &r600_dma_get_wptr,
-        .set_wptr = &r600_dma_set_wptr
+        .get_rptr = &cayman_dma_get_rptr,
+        .get_wptr = &cayman_dma_get_wptr,
+        .set_wptr = &cayman_dma_set_wptr
 };
 
 static struct radeon_asic_ring cayman_uvd_ring = {
@@ -1683,6 +1689,7 @@ static struct radeon_asic cayman_asic = {
                 .init = &ni_dpm_init,
                 .setup_asic = &ni_dpm_setup_asic,
                 .enable = &ni_dpm_enable,
+                .late_enable = &rv770_dpm_late_enable,
                 .disable = &ni_dpm_disable,
                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
                 .set_power_state = &ni_dpm_set_power_state,
@@ -1783,6 +1790,7 @@ static struct radeon_asic trinity_asic = {
                 .init = &trinity_dpm_init,
                 .setup_asic = &trinity_dpm_setup_asic,
                 .enable = &trinity_dpm_enable,
+                .late_enable = &trinity_dpm_late_enable,
                 .disable = &trinity_dpm_disable,
                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
                 .set_power_state = &trinity_dpm_set_power_state,
@@ -1813,9 +1821,9 @@ static struct radeon_asic_ring si_gfx_ring = {
         .ib_test = &r600_ib_test,
         .is_lockup = &si_gfx_is_lockup,
         .vm_flush = &si_vm_flush,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &cayman_gfx_get_rptr,
+        .get_wptr = &cayman_gfx_get_wptr,
+        .set_wptr = &cayman_gfx_set_wptr,
 };
 
 static struct radeon_asic_ring si_dma_ring = {
@@ -1828,9 +1836,9 @@ static struct radeon_asic_ring si_dma_ring = {
         .ib_test = &r600_dma_ib_test,
         .is_lockup = &si_dma_is_lockup,
         .vm_flush = &si_dma_vm_flush,
-        .get_rptr = &r600_dma_get_rptr,
-        .get_wptr = &r600_dma_get_wptr,
-        .set_wptr = &r600_dma_set_wptr,
+        .get_rptr = &cayman_dma_get_rptr,
+        .get_wptr = &cayman_dma_get_wptr,
+        .set_wptr = &cayman_dma_set_wptr,
 };
 
 static struct radeon_asic si_asic = {
@@ -1913,6 +1921,7 @@ static struct radeon_asic si_asic = {
                 .init = &si_dpm_init,
                 .setup_asic = &si_dpm_setup_asic,
                 .enable = &si_dpm_enable,
+                .late_enable = &si_dpm_late_enable,
                 .disable = &si_dpm_disable,
                 .pre_set_power_state = &si_dpm_pre_set_power_state,
                 .set_power_state = &si_dpm_set_power_state,
@@ -1943,9 +1952,9 @@ static struct radeon_asic_ring ci_gfx_ring = {
         .ib_test = &cik_ib_test,
         .is_lockup = &cik_gfx_is_lockup,
         .vm_flush = &cik_vm_flush,
-        .get_rptr = &radeon_ring_generic_get_rptr,
-        .get_wptr = &radeon_ring_generic_get_wptr,
-        .set_wptr = &radeon_ring_generic_set_wptr,
+        .get_rptr = &cik_gfx_get_rptr,
+        .get_wptr = &cik_gfx_get_wptr,
+        .set_wptr = &cik_gfx_set_wptr,
 };
 
 static struct radeon_asic_ring ci_cp_ring = {
@@ -1958,9 +1967,9 @@ static struct radeon_asic_ring ci_cp_ring = {
         .ib_test = &cik_ib_test,
         .is_lockup = &cik_gfx_is_lockup,
         .vm_flush = &cik_vm_flush,
-        .get_rptr = &cik_compute_ring_get_rptr,
-        .get_wptr = &cik_compute_ring_get_wptr,
-        .set_wptr = &cik_compute_ring_set_wptr,
+        .get_rptr = &cik_compute_get_rptr,
+        .get_wptr = &cik_compute_get_wptr,
+        .set_wptr = &cik_compute_set_wptr,
 };
 
 static struct radeon_asic_ring ci_dma_ring = {
@@ -1973,9 +1982,9 @@ static struct radeon_asic_ring ci_dma_ring = {
         .ib_test = &cik_sdma_ib_test,
         .is_lockup = &cik_sdma_is_lockup,
         .vm_flush = &cik_dma_vm_flush,
-        .get_rptr = &r600_dma_get_rptr,
-        .get_wptr = &r600_dma_get_wptr,
-        .set_wptr = &r600_dma_set_wptr,
+        .get_rptr = &cik_sdma_get_rptr,
+        .get_wptr = &cik_sdma_get_wptr,
+        .set_wptr = &cik_sdma_set_wptr,
 };
 
 static struct radeon_asic ci_asic = {
@@ -2058,6 +2067,7 @@ static struct radeon_asic ci_asic = {
                 .init = &ci_dpm_init,
                 .setup_asic = &ci_dpm_setup_asic,
                 .enable = &ci_dpm_enable,
+                .late_enable = &ci_dpm_late_enable,
                 .disable = &ci_dpm_disable,
                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
                 .set_power_state = &ci_dpm_set_power_state,
@@ -2159,6 +2169,7 @@ static struct radeon_asic kv_asic = {
                 .init = &kv_dpm_init,
                 .setup_asic = &kv_dpm_setup_asic,
                 .enable = &kv_dpm_enable,
+                .late_enable = &kv_dpm_late_enable,
                 .disable = &kv_dpm_disable,
                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
                 .set_power_state = &kv_dpm_set_power_state,
@@ -2449,7 +2460,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                         rdev->cg_flags =
                                 RADEON_CG_SUPPORT_GFX_MGCG |
                                 RADEON_CG_SUPPORT_GFX_MGLS |
-                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
+                                RADEON_CG_SUPPORT_GFX_CGCG |
                                 RADEON_CG_SUPPORT_GFX_CGLS |
                                 RADEON_CG_SUPPORT_GFX_CGTS |
                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
@@ -2468,7 +2479,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                         rdev->cg_flags =
                                 RADEON_CG_SUPPORT_GFX_MGCG |
                                 RADEON_CG_SUPPORT_GFX_MGLS |
-                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
+                                RADEON_CG_SUPPORT_GFX_CGCG |
                                 RADEON_CG_SUPPORT_GFX_CGLS |
                                 RADEON_CG_SUPPORT_GFX_CGTS |
                                 RADEON_CG_SUPPORT_GFX_CP_LS |
@@ -2493,7 +2504,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                         rdev->cg_flags =
                                 RADEON_CG_SUPPORT_GFX_MGCG |
                                 RADEON_CG_SUPPORT_GFX_MGLS |
-                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
+                                RADEON_CG_SUPPORT_GFX_CGCG |
                                 RADEON_CG_SUPPORT_GFX_CGLS |
                                 RADEON_CG_SUPPORT_GFX_CGTS |
                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
@@ -2521,7 +2532,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                         rdev->cg_flags =
                                 RADEON_CG_SUPPORT_GFX_MGCG |
                                 RADEON_CG_SUPPORT_GFX_MGLS |
-                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
+                                RADEON_CG_SUPPORT_GFX_CGCG |
                                 RADEON_CG_SUPPORT_GFX_CGLS |
                                 RADEON_CG_SUPPORT_GFX_CGTS |
                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c9fd97b58076..b3bc433eed4c 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -47,13 +47,6 @@ u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
 
-u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
-                                 struct radeon_ring *ring);
-u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
-                                 struct radeon_ring *ring);
-void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
-                                  struct radeon_ring *ring);
-
 /*
  * r100,rv100,rs100,rv200,rs200
  */
@@ -148,6 +141,13 @@ extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
 
+u32 r100_gfx_get_rptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+u32 r100_gfx_get_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+void r100_gfx_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring);
+
 /*
  * r200,rv250,rs300,rv280
  */
@@ -368,6 +368,12 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
 int r600_pcie_gart_init(struct radeon_device *rdev);
 void r600_scratch_init(struct radeon_device *rdev);
 int r600_init_microcode(struct radeon_device *rdev);
+u32 r600_gfx_get_rptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+u32 r600_gfx_get_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+void r600_gfx_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring);
 /* r600 irq */
 int r600_irq_process(struct radeon_device *rdev);
 int r600_irq_init(struct radeon_device *rdev);
@@ -392,6 +398,7 @@ int rv6xx_get_temp(struct radeon_device *rdev);
 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 void r600_dpm_post_set_power_state(struct radeon_device *rdev);
+int r600_dpm_late_enable(struct radeon_device *rdev);
 /* r600 dma */
 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
                            struct radeon_ring *ring);
@@ -454,6 +461,7 @@ int rv770_get_temp(struct radeon_device *rdev);
 /* rv7xx pm */
 int rv770_dpm_init(struct radeon_device *rdev);
 int rv770_dpm_enable(struct radeon_device *rdev);
+int rv770_dpm_late_enable(struct radeon_device *rdev);
 void rv770_dpm_disable(struct radeon_device *rdev);
 int rv770_dpm_set_power_state(struct radeon_device *rdev);
 void rv770_dpm_setup_asic(struct radeon_device *rdev);
@@ -545,6 +553,7 @@ u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
 bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
 int sumo_dpm_init(struct radeon_device *rdev);
 int sumo_dpm_enable(struct radeon_device *rdev);
+int sumo_dpm_late_enable(struct radeon_device *rdev);
 void sumo_dpm_disable(struct radeon_device *rdev);
 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
 int sumo_dpm_set_power_state(struct radeon_device *rdev);
@@ -591,6 +600,19 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
 
 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 
+u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
+                        struct radeon_ring *ring);
+u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
+                        struct radeon_ring *ring);
+void cayman_gfx_set_wptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring);
+uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
+                             struct radeon_ring *ring);
+uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
+                             struct radeon_ring *ring);
+void cayman_dma_set_wptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring);
+
 int ni_dpm_init(struct radeon_device *rdev);
 void ni_dpm_setup_asic(struct radeon_device *rdev);
 int ni_dpm_enable(struct radeon_device *rdev);
@@ -610,6 +632,7 @@ int ni_dpm_force_performance_level(struct radeon_device *rdev,
 bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
 int trinity_dpm_init(struct radeon_device *rdev);
 int trinity_dpm_enable(struct radeon_device *rdev);
+int trinity_dpm_late_enable(struct radeon_device *rdev);
 void trinity_dpm_disable(struct radeon_device *rdev);
 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
 int trinity_dpm_set_power_state(struct radeon_device *rdev);
@@ -669,6 +692,7 @@ int si_get_temp(struct radeon_device *rdev);
 int si_dpm_init(struct radeon_device *rdev);
 void si_dpm_setup_asic(struct radeon_device *rdev);
 int si_dpm_enable(struct radeon_device *rdev);
+int si_dpm_late_enable(struct radeon_device *rdev);
 void si_dpm_disable(struct radeon_device *rdev);
 int si_dpm_pre_set_power_state(struct radeon_device *rdev);
 int si_dpm_set_power_state(struct radeon_device *rdev);
@@ -739,17 +763,30 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
                           uint32_t incr, uint32_t flags);
 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
-u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
-                              struct radeon_ring *ring);
-u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
-                              struct radeon_ring *ring);
-void cik_compute_ring_set_wptr(struct radeon_device *rdev,
-                               struct radeon_ring *ring);
+u32 cik_gfx_get_rptr(struct radeon_device *rdev,
+                     struct radeon_ring *ring);
+u32 cik_gfx_get_wptr(struct radeon_device *rdev,
+                     struct radeon_ring *ring);
+void cik_gfx_set_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+u32 cik_compute_get_rptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring);
+u32 cik_compute_get_wptr(struct radeon_device *rdev,
+                         struct radeon_ring *ring);
+void cik_compute_set_wptr(struct radeon_device *rdev,
+                          struct radeon_ring *ring);
+u32 cik_sdma_get_rptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+u32 cik_sdma_get_wptr(struct radeon_device *rdev,
+                      struct radeon_ring *ring);
+void cik_sdma_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring);
 int ci_get_temp(struct radeon_device *rdev);
 int kv_get_temp(struct radeon_device *rdev);
 
 int ci_dpm_init(struct radeon_device *rdev);
 int ci_dpm_enable(struct radeon_device *rdev);
+int ci_dpm_late_enable(struct radeon_device *rdev);
 void ci_dpm_disable(struct radeon_device *rdev);
 int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
 int ci_dpm_set_power_state(struct radeon_device *rdev);
@@ -770,6 +807,7 @@ void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 
 int kv_dpm_init(struct radeon_device *rdev);
 int kv_dpm_enable(struct radeon_device *rdev);
+int kv_dpm_late_enable(struct radeon_device *rdev);
 void kv_dpm_disable(struct radeon_device *rdev);
 int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
 int kv_dpm_set_power_state(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5c39bf7c3d88..80a56ad40c52 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -30,27 +30,10 @@
 #include "atom.h"
 #include "atom-bits.h"
 
-/* from radeon_encoder.c */
-extern uint32_t
-radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
-                        uint8_t dac);
-extern void radeon_link_encoder_connector(struct drm_device *dev);
 extern void
 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
                         uint32_t supported_device, u16 caps);
 
-/* from radeon_connector.c */
-extern void
-radeon_add_atom_connector(struct drm_device *dev,
-                          uint32_t connector_id,
-                          uint32_t supported_device,
-                          int connector_type,
-                          struct radeon_i2c_bus_rec *i2c_bus,
-                          uint32_t igp_lane_info,
-                          uint16_t connector_object_id,
-                          struct radeon_hpd *hpd,
-                          struct radeon_router *router);
-
 /* from radeon_legacy_encoder.c */
 extern void
 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 68ce36056019..6651177110f0 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -37,22 +37,6 @@
 #include <asm/pci-bridge.h>
 #endif /* CONFIG_PPC_PMAC */
 
-/* from radeon_encoder.c */
-extern uint32_t
-radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
-                        uint8_t dac);
-extern void radeon_link_encoder_connector(struct drm_device *dev);
-
-/* from radeon_connector.c */
-extern void
-radeon_add_legacy_connector(struct drm_device *dev,
-                            uint32_t connector_id,
-                            uint32_t supported_device,
-                            int connector_type,
-                            struct radeon_i2c_bus_rec *i2c_bus,
-                            uint16_t connector_object_id,
-                            struct radeon_hpd *hpd);
-
 /* from radeon_legacy_encoder.c */
 extern void
 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 20a768ac89a8..82d4f865546e 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -33,15 +33,6 @@
 
 #include <linux/pm_runtime.h>
 
-extern void
-radeon_combios_connected_scratch_regs(struct drm_connector *connector,
-                                      struct drm_encoder *encoder,
-                                      bool connected);
-extern void
-radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
-                                       struct drm_encoder *encoder,
-                                       bool connected);
-
 void radeon_connector_hotplug(struct drm_connector *connector)
 {
         struct drm_device *dev = connector->dev;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 39b033b441d2..b012cbbc3ed5 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -144,6 +144,11 @@ void radeon_program_register_sequence(struct radeon_device *rdev,
         }
 }
 
+void radeon_pci_config_reset(struct radeon_device *rdev)
+{
+        pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
+}
+
 /**
  * radeon_surface_init - Clear GPU surface registers.
  *
@@ -249,7 +254,7 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  * Init doorbell driver information (CIK)
  * Returns 0 on success, error on failure.
  */
-int radeon_doorbell_init(struct radeon_device *rdev)
+static int radeon_doorbell_init(struct radeon_device *rdev)
 {
         /* doorbell bar mapping */
         rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
@@ -278,7 +283,7 @@ int radeon_doorbell_init(struct radeon_device *rdev)
  *
  * Tear down doorbell driver information (CIK)
  */
-void radeon_doorbell_fini(struct radeon_device *rdev)
+static void radeon_doorbell_fini(struct radeon_device *rdev)
 {
         iounmap(rdev->doorbell.ptr);
         rdev->doorbell.ptr = NULL;
@@ -1330,6 +1335,7 @@ int radeon_device_init(struct radeon_device *rdev,
                 if (r)
                         return r;
         }
+
         if ((radeon_testing & 1)) {
                 if (rdev->accel_working)
                         radeon_test_moves(rdev);
@@ -1455,7 +1461,6 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
 
         radeon_save_bios_scratch_regs(rdev);
 
-        radeon_pm_suspend(rdev);
         radeon_suspend(rdev);
         radeon_hpd_fini(rdev);
         /* evict remaining vram memory */
@@ -1516,14 +1521,22 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
         if (r)
                 DRM_ERROR("ib ring test failed (%d).\n", r);
 
-        radeon_pm_resume(rdev);
+        if (rdev->pm.dpm_enabled) {
+                /* do dpm late init */
+                r = radeon_pm_late_init(rdev);
+                if (r) {
+                        rdev->pm.dpm_enabled = false;
+                        DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
+                }
+        }
+
         radeon_restore_bios_scratch_regs(rdev);
 
         if (fbcon) {
                 radeon_fbdev_set_suspend(rdev, 0);
                 console_unlock();
         }
-       
+
         /* init dig PHYs, disp eng pll */
         if (rdev->is_atom_bios) {
                 radeon_atom_encoder_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 7b253815a323..7ea647b84733 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1464,12 +1464,22 @@ int radeon_modeset_init(struct radeon_device *rdev)
         /* setup afmt */
         radeon_afmt_init(rdev);
 
-        /* Initialize power management */
-        radeon_pm_init(rdev);
-
         radeon_fbdev_init(rdev);
         drm_kms_helper_poll_init(rdev->ddev);
 
+        if (rdev->pm.dpm_enabled) {
+                /* do dpm late init */
+                ret = radeon_pm_late_init(rdev);
+                if (ret) {
+                        rdev->pm.dpm_enabled = false;
+                        DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
+                }
+                /* set the dpm state for PX since there won't be
+                 * a modeset to call this.
+                 */
+                radeon_pm_compute_clocks(rdev);
+        }
+
         return 0;
 }
 
@@ -1477,7 +1487,6 @@ void radeon_modeset_fini(struct radeon_device *rdev)
 {
         radeon_fbdev_fini(rdev);
         kfree(rdev->mode_info.bios_hardcoded_edid);
-        radeon_pm_fini(rdev);
 
         if (rdev->mode_info.mode_config_initialized) {
                 radeon_afmt_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index f6f30b9e9ff5..e91d548063ef 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -167,6 +167,7 @@ int radeon_fastfb = 0;
 int radeon_dpm = -1;
 int radeon_aspm = -1;
 int radeon_runtime_pm = -1;
+int radeon_hard_reset = 0;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -231,6 +232,9 @@ module_param_named(aspm, radeon_aspm, int, 0444);
 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
 module_param_named(runpm, radeon_runtime_pm, int, 0444);
 
+MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
+module_param_named(hard_reset, radeon_hard_reset, int, 0444);
+
 static struct pci_device_id pciidlist[] = {
         radeon_PCI_IDS
 };
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index d3a86e43c012..866744e47cfa 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -841,6 +841,8 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
                 if (!rdev->fence_drv[i].initialized)
                         continue;
 
+                radeon_fence_process(rdev, i);
+
                 seq_printf(m, "--- ring %d ---\n", i);
                 seq_printf(m, "Last signaled fence 0x%016llx\n",
                            (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 805c5e566b9a..b96c819024b3 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -86,7 +86,7 @@ retry:
         return 0;
 }
 
-int radeon_gem_set_domain(struct drm_gem_object *gobj,
+static int radeon_gem_set_domain(struct drm_gem_object *gobj,
                           uint32_t rdomain, uint32_t wdomain)
 {
         struct radeon_bo *robj;
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index fc60b74ee304..e24ca6ab96de 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -1020,6 +1020,9 @@ void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
 /* Add the default buses */
 void radeon_i2c_init(struct radeon_device *rdev)
 {
+        if (radeon_hw_i2c)
+                DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
+
         if (rdev->is_atom_bios)
                 radeon_atombios_i2c_init(rdev);
         else
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index daa28b6a6832..c44574e248d1 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -191,7 +191,7 @@ static void radeon_set_filp_rights(struct drm_device *dev,
  * etc. (all asics).
  * Returns 0 on success, -EINVAL on failure.
  */
-int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 {
         struct radeon_device *rdev = dev->dev_private;
         struct drm_radeon_info *info = data;
@@ -707,7 +707,8 @@ int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 }
 
 #define KMS_INVALID_IOCTL(name)                                         \
-int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
+static int name(struct drm_device *dev, void *data, struct drm_file     \
+                *file_priv)                                             \
 {                                                                       \
         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
         return -EINVAL;                                                 \
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3f0dd664af90..28bba631b80c 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -624,6 +624,30 @@ struct atom_voltage_table
         struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
 };
 
+
+extern void
+radeon_add_atom_connector(struct drm_device *dev,
+                          uint32_t connector_id,
+                          uint32_t supported_device,
+                          int connector_type,
+                          struct radeon_i2c_bus_rec *i2c_bus,
+                          uint32_t igp_lane_info,
+                          uint16_t connector_object_id,
+                          struct radeon_hpd *hpd,
+                          struct radeon_router *router);
+extern void
+radeon_add_legacy_connector(struct drm_device *dev,
+                            uint32_t connector_id,
+                            uint32_t supported_device,
+                            int connector_type,
+                            struct radeon_i2c_bus_rec *i2c_bus,
+                            uint16_t connector_object_id,
+                            struct radeon_hpd *hpd);
+extern uint32_t
+radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
+                        uint8_t dac);
+extern void radeon_link_encoder_connector(struct drm_device *dev);
+
 extern enum radeon_tv_std
 radeon_combios_get_tv_info(struct radeon_device *rdev);
 extern enum radeon_tv_std
@@ -631,6 +655,15 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev);
 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
                                                  u16 *vddc, u16 *vddci, u16 *mvdd);
 
+extern void
+radeon_combios_connected_scratch_regs(struct drm_connector *connector,
+                                      struct drm_encoder *encoder,
+                                      bool connected);
+extern void
+radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
+                                       struct drm_encoder *encoder,
+                                       bool connected);
+
 extern struct drm_connector *
 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
 extern struct drm_connector *
@@ -666,6 +699,7 @@ extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
                                 u8 write_byte, u8 *read_byte);
+void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
 
 extern void radeon_i2c_init(struct radeon_device *rdev);
 extern void radeon_i2c_fini(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index c0fa4aa9ceea..08595cf90b01 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -46,7 +46,7 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  * function are calling it.
  */
 
-void radeon_bo_clear_va(struct radeon_bo *bo)
+static void radeon_bo_clear_va(struct radeon_bo *bo)
 {
         struct radeon_bo_va *bo_va, *tmp;
 
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 984097b907ef..0b24c4c7dcf9 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1010,8 +1010,10 @@ static void radeon_pm_resume_old(struct radeon_device *rdev)
         rdev->pm.current_clock_mode_index = 0;
         rdev->pm.current_sclk = rdev->pm.default_sclk;
         rdev->pm.current_mclk = rdev->pm.default_mclk;
-        rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
-        rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
+        if (rdev->pm.power_state) {
+                rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
+                rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
+        }
         if (rdev->pm.pm_method == PM_METHOD_DYNPM
             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
@@ -1032,25 +1034,27 @@ static void radeon_pm_resume_dpm(struct radeon_device *rdev)
         radeon_dpm_setup_asic(rdev);
         ret = radeon_dpm_enable(rdev);
         mutex_unlock(&rdev->pm.mutex);
-        if (ret) {
-                DRM_ERROR("radeon: dpm resume failed\n");
-                if ((rdev->family >= CHIP_BARTS) &&
-                    (rdev->family <= CHIP_CAYMAN) &&
-                    rdev->mc_fw) {
-                        if (rdev->pm.default_vddc)
-                                radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
-                                                        SET_VOLTAGE_TYPE_ASIC_VDDC);
-                        if (rdev->pm.default_vddci)
-                                radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
-                                                        SET_VOLTAGE_TYPE_ASIC_VDDCI);
-                        if (rdev->pm.default_sclk)
-                                radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
-                        if (rdev->pm.default_mclk)
-                                radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
-                }
-        } else {
-                rdev->pm.dpm_enabled = true;
-                radeon_pm_compute_clocks(rdev);
+        if (ret)
+                goto dpm_resume_fail;
+        rdev->pm.dpm_enabled = true;
+        radeon_pm_compute_clocks(rdev);
+        return;
+
+dpm_resume_fail:
+        DRM_ERROR("radeon: dpm resume failed\n");
+        if ((rdev->family >= CHIP_BARTS) &&
+            (rdev->family <= CHIP_CAYMAN) &&
+            rdev->mc_fw) {
+                if (rdev->pm.default_vddc)
+                        radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
+                                                SET_VOLTAGE_TYPE_ASIC_VDDC);
+                if (rdev->pm.default_vddci)
+                        radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
+                                                SET_VOLTAGE_TYPE_ASIC_VDDCI);
+                if (rdev->pm.default_sclk)
+                        radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
+                if (rdev->pm.default_mclk)
+                        radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
         }
 }
 
@@ -1170,51 +1174,50 @@ static int radeon_pm_init_dpm(struct radeon_device *rdev)
         radeon_dpm_setup_asic(rdev);
         ret = radeon_dpm_enable(rdev);
         mutex_unlock(&rdev->pm.mutex);
-        if (ret) {
-                rdev->pm.dpm_enabled = false;
-                if ((rdev->family >= CHIP_BARTS) &&
-                    (rdev->family <= CHIP_CAYMAN) &&
-                    rdev->mc_fw) {
-                        if (rdev->pm.default_vddc)
-                                radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
-                                                        SET_VOLTAGE_TYPE_ASIC_VDDC);
-                        if (rdev->pm.default_vddci)
-                                radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
-                                                        SET_VOLTAGE_TYPE_ASIC_VDDCI);
-                        if (rdev->pm.default_sclk)
-                                radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
-                        if (rdev->pm.default_mclk)
-                                radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
-                }
-                DRM_ERROR("radeon: dpm initialization failed\n");
-                return ret;
-        }
+        if (ret)
+                goto dpm_failed;
         rdev->pm.dpm_enabled = true;
-        radeon_pm_compute_clocks(rdev);
 
-        if (rdev->pm.num_power_states > 1) {
-                ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
-                if (ret)
-                        DRM_ERROR("failed to create device file for dpm state\n");
-                ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
-                if (ret)
-                        DRM_ERROR("failed to create device file for dpm state\n");
-                /* XXX: these are noops for dpm but are here for backwards compat */
-                ret = device_create_file(rdev->dev, &dev_attr_power_profile);
-                if (ret)
-                        DRM_ERROR("failed to create device file for power profile\n");
-                ret = device_create_file(rdev->dev, &dev_attr_power_method);
-                if (ret)
-                        DRM_ERROR("failed to create device file for power method\n");
-
-                if (radeon_debugfs_pm_init(rdev)) {
-                        DRM_ERROR("Failed to register debugfs file for dpm!\n");
-                }
+        ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
+        if (ret)
+                DRM_ERROR("failed to create device file for dpm state\n");
+        ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
+        if (ret)
+                DRM_ERROR("failed to create device file for dpm state\n");
+        /* XXX: these are noops for dpm but are here for backwards compat */
+        ret = device_create_file(rdev->dev, &dev_attr_power_profile);
+        if (ret)
+                DRM_ERROR("failed to create device file for power profile\n");
+        ret = device_create_file(rdev->dev, &dev_attr_power_method);
+        if (ret)
+                DRM_ERROR("failed to create device file for power method\n");
 
-                DRM_INFO("radeon: dpm initialized\n");
+        if (radeon_debugfs_pm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for dpm!\n");
         }
 
+        DRM_INFO("radeon: dpm initialized\n");
+
         return 0;
+
+dpm_failed:
+        rdev->pm.dpm_enabled = false;
+        if ((rdev->family >= CHIP_BARTS) &&
+            (rdev->family <= CHIP_CAYMAN) &&
+            rdev->mc_fw) {
+                if (rdev->pm.default_vddc)
+                        radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
+                                                SET_VOLTAGE_TYPE_ASIC_VDDC);
+                if (rdev->pm.default_vddci)
+                        radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
+                                                SET_VOLTAGE_TYPE_ASIC_VDDCI);
+                if (rdev->pm.default_sclk)
+                        radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
+                if (rdev->pm.default_mclk)
+                        radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
+        }
+        DRM_ERROR("radeon: dpm initialization failed\n");
+        return ret;
 }
 
 int radeon_pm_init(struct radeon_device *rdev)
@@ -1229,10 +1232,6 @@ int radeon_pm_init(struct radeon_device *rdev)
         case CHIP_RS780:
         case CHIP_RS880:
         case CHIP_CAYMAN:
-        case CHIP_BONAIRE:
-        case CHIP_KABINI:
-        case CHIP_KAVERI:
-        case CHIP_HAWAII:
                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
                 if (!rdev->rlc_fw)
                         rdev->pm.pm_method = PM_METHOD_PROFILE;
@@ -1266,6 +1265,10 @@ int radeon_pm_init(struct radeon_device *rdev)
         case CHIP_VERDE:
         case CHIP_OLAND:
         case CHIP_HAINAN:
+        case CHIP_BONAIRE:
+        case CHIP_KABINI:
+        case CHIP_KAVERI:
+        case CHIP_HAWAII:
                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
                 if (!rdev->rlc_fw)
                         rdev->pm.pm_method = PM_METHOD_PROFILE;
@@ -1290,6 +1293,18 @@ int radeon_pm_init(struct radeon_device *rdev)
                 return radeon_pm_init_old(rdev);
 }
 
+int radeon_pm_late_init(struct radeon_device *rdev)
+{
+        int ret = 0;
+
+        if (rdev->pm.pm_method == PM_METHOD_DPM) {
+                mutex_lock(&rdev->pm.mutex);
+                ret = radeon_dpm_late_enable(rdev);
+                mutex_unlock(&rdev->pm.mutex);
+        }
+        return ret;
+}
+
 static void radeon_pm_fini_old(struct radeon_device *rdev)
 {
         if (rdev->pm.num_power_states > 1) {
@@ -1420,6 +1435,9 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
         struct drm_crtc *crtc;
         struct radeon_crtc *radeon_crtc;
 
+        if (!rdev->pm.dpm_enabled)
+                return;
+
         mutex_lock(&rdev->pm.mutex);
 
         /* update active crtc counts */
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index ca2d71afeb02..1b783f0e6d3a 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -332,36 +332,6 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
         }
 }
 
-u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
-                                 struct radeon_ring *ring)
-{
-        u32 rptr;
-
-        if (rdev->wb.enabled)
-                rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
-        else
-                rptr = RREG32(ring->rptr_reg);
-
-        return rptr;
-}
-
-u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
-                                 struct radeon_ring *ring)
-{
-        u32 wptr;
-
-        wptr = RREG32(ring->wptr_reg);
-
-        return wptr;
-}
-
-void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
-                                  struct radeon_ring *ring)
-{
-        WREG32(ring->wptr_reg, ring->wptr);
-        (void)RREG32(ring->wptr_reg);
-}
-
 /**
  * radeon_ring_free_size - update the free size
  *
@@ -689,22 +659,18 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
  * @ring: radeon_ring structure holding ring information
  * @ring_size: size of the ring
  * @rptr_offs: offset of the rptr writeback location in the WB buffer
- * @rptr_reg: MMIO offset of the rptr register
- * @wptr_reg: MMIO offset of the wptr register
  * @nop: nop packet for this ring
  *
  * Initialize the driver information for the selected ring (all asics).
  * Returns 0 on success, error on failure.
  */
 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
-                     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop)
+                     unsigned rptr_offs, u32 nop)
 {
         int r;
 
         ring->ring_size = ring_size;
         ring->rptr_offs = rptr_offs;
-        ring->rptr_reg = rptr_reg;
-        ring->wptr_reg = wptr_reg;
         ring->nop = nop;
         /* Allocate ring buffer */
         if (ring->ring_obj == NULL) {
@@ -790,34 +756,54 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
         struct radeon_device *rdev = dev->dev_private;
         int ridx = *(int*)node->info_ent->data;
         struct radeon_ring *ring = &rdev->ring[ridx];
+
+        uint32_t rptr, wptr, rptr_next;
         unsigned count, i, j;
-        u32 tmp;
 
         radeon_ring_free_size(rdev, ring);
         count = (ring->ring_size / 4) - ring->ring_free_dw;
-        tmp = radeon_ring_get_wptr(rdev, ring);
-        seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
-        tmp = radeon_ring_get_rptr(rdev, ring);
-        seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
+
+        wptr = radeon_ring_get_wptr(rdev, ring);
+        seq_printf(m, "wptr: 0x%08x [%5d]\n",
+                   wptr, wptr);
+
+        rptr = radeon_ring_get_rptr(rdev, ring);
+        seq_printf(m, "rptr: 0x%08x [%5d]\n",
+                   rptr, rptr);
+
         if (ring->rptr_save_reg) {
-                seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
-                           RREG32(ring->rptr_save_reg));
-        }
-        seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
-        seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
-        seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
-        seq_printf(m, "last semaphore wait addr   : 0x%016llx\n", ring->last_semaphore_wait_addr);
+                rptr_next = RREG32(ring->rptr_save_reg);
+                seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
+                           ring->rptr_save_reg, rptr_next, rptr_next);
+        } else
+                rptr_next = ~0;
+
+        seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
+                   ring->wptr, ring->wptr);
+        seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n",
+                   ring->rptr, ring->rptr);
+        seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
+                   ring->last_semaphore_signal_addr);
+        seq_printf(m, "last semaphore wait addr   : 0x%016llx\n",
+                   ring->last_semaphore_wait_addr);
         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
         seq_printf(m, "%u dwords in ring\n", count);
+
+        if (!ring->ready)
+                return 0;
+
         /* print 8 dw before current rptr as often it's the last executed
          * packet that is the root issue
          */
-        i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
-        if (ring->ready) {
-                for (j = 0; j <= (count + 32); j++) {
-                        seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
-                        i = (i + 1) & ring->ptr_mask;
-                }
+        i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
+        for (j = 0; j <= (count + 32); j++) {
+                seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
+                if (rptr == i)
+                        seq_puts(m, " *");
+                if (rptr_next == i)
+                        seq_puts(m, " #");
+                seq_puts(m, "\n");
+                i = (i + 1) & ring->ptr_mask;
         }
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index f0bac68254b7..c0625805cdd7 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -402,13 +402,15 @@ void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
 
         spin_lock(&sa_manager->wq.lock);
         list_for_each_entry(i, &sa_manager->olist, olist) {
+                uint64_t soffset = i->soffset + sa_manager->gpu_addr;
+                uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
                 if (&i->olist == sa_manager->hole) {
                         seq_printf(m, ">");
                 } else {
                         seq_printf(m, " ");
                 }
-                seq_printf(m, "[0x%08x 0x%08x] size %8d",
-                           i->soffset, i->eoffset, i->eoffset - i->soffset);
+                seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
+                           soffset, eoffset, eoffset - soffset);
                 if (i->fence) {
                         seq_printf(m, " protected by 0x%016llx on ring %d",
                                    i->fence->seq, i->fence->ring);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 051fa874065a..77f5b0c3edb8 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -39,12 +39,14 @@
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/swiotlb.h>
+#include <linux/debugfs.h>
 #include "radeon_reg.h"
 #include "radeon.h"
 
 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
 
 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
+static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
 
 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
 {
@@ -753,6 +755,7 @@ void radeon_ttm_fini(struct radeon_device *rdev)
 
         if (!rdev->mman.initialized)
                 return;
+        radeon_ttm_debugfs_fini(rdev);
         if (rdev->stollen_vga_memory) {
                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
                 if (r == 0) {
@@ -832,16 +835,15 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
         return 0;
 }
 
-
-#define RADEON_DEBUGFS_MEM_TYPES 2
-
 #if defined(CONFIG_DEBUG_FS)
+
 static int radeon_mm_dump_table(struct seq_file *m, void *data)
 {
         struct drm_info_node *node = (struct drm_info_node *)m->private;
-        struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
+        unsigned ttm_pl = *(int *)node->info_ent->data;
         struct drm_device *dev = node->minor->dev;
         struct radeon_device *rdev = dev->dev_private;
+        struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
         int ret;
         struct ttm_bo_global *glob = rdev->mman.bdev.glob;
 
@@ -850,46 +852,169 @@ static int radeon_mm_dump_table(struct seq_file *m, void *data)
         spin_unlock(&glob->lru_lock);
         return ret;
 }
+
+static int ttm_pl_vram = TTM_PL_VRAM;
+static int ttm_pl_tt = TTM_PL_TT;
+
+static struct drm_info_list radeon_ttm_debugfs_list[] = {
+        {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
+        {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
+        {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
+#ifdef CONFIG_SWIOTLB
+        {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
 #endif
+};
 
-static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
+static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
 {
-#if defined(CONFIG_DEBUG_FS)
-        static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2];
-        static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32];
-        unsigned i;
+        struct radeon_device *rdev = inode->i_private;
+        i_size_write(inode, rdev->mc.mc_vram_size);
+        filep->private_data = inode->i_private;
+        return 0;
+}
 
-        for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
-                if (i == 0)
-                        sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
-                else
-                        sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
-                radeon_mem_types_list[i].name = radeon_mem_types_names[i];
-                radeon_mem_types_list[i].show = &radeon_mm_dump_table;
-                radeon_mem_types_list[i].driver_features = 0;
-                if (i == 0)
-                        radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
-                else
-                        radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
+static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
+                                    size_t size, loff_t *pos)
+{
+        struct radeon_device *rdev = f->private_data;
+        ssize_t result = 0;
+        int r;
 
+        if (size & 0x3 || *pos & 0x3)
+                return -EINVAL;
+
+        while (size) {
+                unsigned long flags;
+                uint32_t value;
+
+                if (*pos >= rdev->mc.mc_vram_size)
+                        return result;
+
+                spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
+                WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
+                if (rdev->family >= CHIP_CEDAR)
+                        WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
+                value = RREG32(RADEON_MM_DATA);
+                spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
+
+                r = put_user(value, (uint32_t *)buf);
+                if (r)
+                        return r;
+
+                result += 4;
+                buf += 4;
+                *pos += 4;
+                size -= 4;
         }
-        /* Add ttm page pool to debugfs */
-        sprintf(radeon_mem_types_names[i], "ttm_page_pool");
-        radeon_mem_types_list[i].name = radeon_mem_types_names[i];
-        radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
-        radeon_mem_types_list[i].driver_features = 0;
-        radeon_mem_types_list[i++].data = NULL;
-#ifdef CONFIG_SWIOTLB
-        if (swiotlb_nr_tbl()) {
-                sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool");
-                radeon_mem_types_list[i].name = radeon_mem_types_names[i];
-                radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs;
-                radeon_mem_types_list[i].driver_features = 0;
-                radeon_mem_types_list[i++].data = NULL;
+
+        return result;
+}
+
+static const struct file_operations radeon_ttm_vram_fops = {
+        .owner = THIS_MODULE,
+        .open = radeon_ttm_vram_open,
+        .read = radeon_ttm_vram_read,
+        .llseek = default_llseek
+};
+
+static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
+{
+        struct radeon_device *rdev = inode->i_private;
+        i_size_write(inode, rdev->mc.gtt_size);
+        filep->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
+                                   size_t size, loff_t *pos)
+{
+        struct radeon_device *rdev = f->private_data;
+        ssize_t result = 0;
+        int r;
+
+        while (size) {
+                loff_t p = *pos / PAGE_SIZE;
+                unsigned off = *pos & ~PAGE_MASK;
+                ssize_t cur_size = min(size, PAGE_SIZE - off);
+                struct page *page;
+                void *ptr;
+
+                if (p >= rdev->gart.num_cpu_pages)
+                        return result;
+
+                page = rdev->gart.pages[p];
+                if (page) {
+                        ptr = kmap(page);
+                        ptr += off;
+
+                        r = copy_to_user(buf, ptr, cur_size);
+                        kunmap(rdev->gart.pages[p]);
+                } else
+                        r = clear_user(buf, cur_size);
+
+                if (r)
+                        return -EFAULT;
+
+                result += cur_size;
+                buf += cur_size;
+                *pos += cur_size;
+                size -= cur_size;
         }
+
+        return result;
+}
+
+static const struct file_operations radeon_ttm_gtt_fops = {
+        .owner = THIS_MODULE,
+        .open = radeon_ttm_gtt_open,
+        .read = radeon_ttm_gtt_read,
+        .llseek = default_llseek
+};
+
 #endif
-        return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i);
 
+static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        unsigned count;
+
+        struct drm_minor *minor = rdev->ddev->primary;
+        struct dentry *ent, *root = minor->debugfs_root;
+
+        ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
+                                  rdev, &radeon_ttm_vram_fops);
+        if (IS_ERR(ent))
+                return PTR_ERR(ent);
+        rdev->mman.vram = ent;
+
+        ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
+                                  rdev, &radeon_ttm_gtt_fops);
+        if (IS_ERR(ent))
+                return PTR_ERR(ent);
+        rdev->mman.gtt = ent;
+
+        count = ARRAY_SIZE(radeon_ttm_debugfs_list);
+
+#ifdef CONFIG_SWIOTLB
+        if (!swiotlb_nr_tbl())
+                --count;
 #endif
+
+        return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
+#else
+
         return 0;
+#endif
+}
+
+static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+
+        debugfs_remove(rdev->mman.vram);
+        rdev->mman.vram = NULL;
+
+        debugfs_remove(rdev->mman.gtt);
+        rdev->mman.gtt = NULL;
+#endif
 }
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 9566b5940a5a..b5c2369cda2f 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -474,6 +474,8 @@ int rs400_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = rs400_startup(rdev);
         if (r) {
@@ -484,6 +486,7 @@ int rs400_resume(struct radeon_device *rdev)
 
 int rs400_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
@@ -493,6 +496,7 @@ int rs400_suspend(struct radeon_device *rdev)
 
 void rs400_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
         radeon_ib_pool_fini(rdev);
@@ -560,6 +564,9 @@ int rs400_init(struct radeon_device *rdev)
                 return r;
         r300_set_reg_safe(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = rs400_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 76cc8d3aafec..fdcde7693032 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -1048,6 +1048,8 @@ int rs600_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = rs600_startup(rdev);
         if (r) {
@@ -1058,6 +1060,7 @@ int rs600_resume(struct radeon_device *rdev)
 
 int rs600_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r600_audio_fini(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
@@ -1068,6 +1071,7 @@ int rs600_suspend(struct radeon_device *rdev)
 
 void rs600_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r600_audio_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
@@ -1136,6 +1140,9 @@ int rs600_init(struct radeon_device *rdev)
                 return r;
         rs600_set_safe_registers(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = rs600_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1c560629575a..e461b45f29a9 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -746,6 +746,8 @@ int rs690_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = rs690_startup(rdev);
         if (r) {
@@ -756,6 +758,7 @@ int rs690_resume(struct radeon_device *rdev)
 
 int rs690_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r600_audio_fini(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
@@ -766,6 +769,7 @@ int rs690_suspend(struct radeon_device *rdev)
 
 void rs690_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r600_audio_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
@@ -835,6 +839,9 @@ int rs690_init(struct radeon_device *rdev)
                 return r;
         rs600_set_safe_registers(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = rs690_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c
index 6af8505cf4d2..8512085b0aef 100644
--- a/drivers/gpu/drm/radeon/rs780_dpm.c
+++ b/drivers/gpu/drm/radeon/rs780_dpm.c
@@ -623,14 +623,6 @@ int rs780_dpm_enable(struct radeon_device *rdev)
         if (pi->gfx_clock_gating)
                 r600_gfx_clockgating_enable(rdev, true);
 
-        if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
-                ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
-                if (ret)
-                        return ret;
-                rdev->irq.dpm_thermal = true;
-                radeon_irq_set(rdev);
-        }
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 5d1c316115ef..98e8138ff779 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -586,6 +586,8 @@ int rv515_resume(struct radeon_device *rdev)
         /* Initialize surface registers */
         radeon_surface_init(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r =  rv515_startup(rdev);
         if (r) {
@@ -596,6 +598,7 @@ int rv515_resume(struct radeon_device *rdev)
 
 int rv515_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r100_cp_disable(rdev);
         radeon_wb_disable(rdev);
         rs600_irq_disable(rdev);
@@ -612,6 +615,7 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 
 void rv515_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         radeon_wb_fini(rdev);
         radeon_ib_pool_fini(rdev);
@@ -685,6 +689,9 @@ int rv515_init(struct radeon_device *rdev)
                 return r;
         rv515_set_safe_registers(rdev);
 
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->accel_working = true;
         r = rv515_startup(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index 26633a025252..bebf31c4d841 100644
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -1546,7 +1546,6 @@ int rv6xx_dpm_enable(struct radeon_device *rdev)
 {
         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
-        int ret;
 
         if (r600_dynamicpm_enabled(rdev))
                 return -EINVAL;
@@ -1594,15 +1593,6 @@ int rv6xx_dpm_enable(struct radeon_device *rdev)
         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
 
-        if (rdev->irq.installed &&
-            r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
-                ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
-                if (ret)
-                        return ret;
-                rdev->irq.dpm_thermal = true;
-                radeon_irq_set(rdev);
-        }
-
         rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
 
         r600_start_dpm(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 9f5846743c9e..18e02889ec7d 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1123,6 +1123,35 @@ void r700_cp_fini(struct radeon_device *rdev)
         radeon_scratch_free(rdev, ring->rptr_save_reg);
 }
 
+void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
+{
+        u32 tmp, i;
+
+        if (rdev->flags & RADEON_IS_IGP)
+                return;
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
+        tmp &= SCLK_MUX_SEL_MASK;
+        tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
+        WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
+                        break;
+                udelay(1);
+        }
+
+        tmp &= ~SCLK_MUX_UPDATE;
+        WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
+
+        tmp = RREG32(MPLL_CNTL_MODE);
+        if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
+                tmp &= ~RV730_MPLL_MCLK_SEL;
+        else
+                tmp &= ~MPLL_MCLK_SEL;
+        WREG32(MPLL_CNTL_MODE, tmp);
+}
+
 /*
  * Core functions
  */
@@ -1665,14 +1694,6 @@ static int rv770_startup(struct radeon_device *rdev)
 
         rv770_mc_program(rdev);
 
-        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
-                r = r600_init_microcode(rdev);
-                if (r) {
-                        DRM_ERROR("Failed to load firmware!\n");
-                        return r;
-                }
-        }
-
         if (rdev->flags & RADEON_IS_AGP) {
                 rv770_agp_enable(rdev);
         } else {
@@ -1728,14 +1749,12 @@ static int rv770_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             R600_CP_RB_RPTR, R600_CP_RB_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_RB_RPTR, DMA_RB_WPTR,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
         if (r)
                 return r;
@@ -1754,7 +1773,6 @@ static int rv770_startup(struct radeon_device *rdev)
         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
         if (ring->ring_size) {
                 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-                                     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                      RADEON_CP_PACKET2);
                 if (!r)
                         r = uvd_v1_0_init(rdev);
@@ -1792,6 +1810,8 @@ int rv770_resume(struct radeon_device *rdev)
         /* init golden registers */
         rv770_init_golden_registers(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = rv770_startup(rdev);
         if (r) {
@@ -1806,6 +1826,7 @@ int rv770_resume(struct radeon_device *rdev)
 
 int rv770_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         r600_audio_fini(rdev);
         uvd_v1_0_fini(rdev);
         radeon_uvd_suspend(rdev);
@@ -1876,6 +1897,17 @@ int rv770_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+                r = r600_init_microcode(rdev);
+                if (r) {
+                        DRM_ERROR("Failed to load firmware!\n");
+                        return r;
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -1915,6 +1947,7 @@ int rv770_init(struct radeon_device *rdev)
 
 void rv770_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         r700_cp_fini(rdev);
         r600_dma_fini(rdev);
         r600_irq_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 913b025ae9b3..4aaeb118a3ff 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -1863,8 +1863,8 @@ void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
         }
 }
 
-int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
-                                        int min_temp, int max_temp)
+static int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
+                                               int min_temp, int max_temp)
 {
         int low_temp = 0 * 1000;
         int high_temp = 255 * 1000;
@@ -1966,6 +1966,15 @@ int rv770_dpm_enable(struct radeon_device *rdev)
         if (pi->mg_clock_gating)
                 rv770_mg_clock_gating_enable(rdev, true);
 
+        rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
+
+        return 0;
+}
+
+int rv770_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
         if (rdev->irq.installed &&
             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
                 PPSMC_Result result;
@@ -1981,8 +1990,6 @@ int rv770_dpm_enable(struct radeon_device *rdev)
                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
         }
 
-        rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h
index 9244effc6b59..f776634840c9 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.h
+++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -283,8 +283,4 @@ int rv770_read_smc_soft_register(struct radeon_device *rdev,
 int rv770_write_smc_soft_register(struct radeon_device *rdev,
                                   u16 reg_offset, u32 value);
 
-/* thermal */
-int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
-                                        int min_temp, int max_temp);
-
 #endif
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 1ae277152cc7..3cf1e2921545 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -100,14 +100,21 @@
 #define CG_SPLL_FUNC_CNTL_2                             0x604
 #define         SCLK_MUX_SEL(x)                         ((x) << 0)
 #define         SCLK_MUX_SEL_MASK                       (0x1ff << 0)
+#define         SCLK_MUX_UPDATE                         (1 << 26)
 #define CG_SPLL_FUNC_CNTL_3                             0x608
 #define         SPLL_FB_DIV(x)                          ((x) << 0)
 #define         SPLL_FB_DIV_MASK                        (0x3ffffff << 0)
 #define         SPLL_DITHEN                             (1 << 28)
+#define CG_SPLL_STATUS                                  0x60c
+#define         SPLL_CHG_STATUS                         (1 << 1)
 
 #define SPLL_CNTL_MODE                                  0x610
 #define         SPLL_DIV_SYNC                           (1 << 5)
 
+#define MPLL_CNTL_MODE                                  0x61c
+#       define MPLL_MCLK_SEL                            (1 << 11)
+#       define RV730_MPLL_MCLK_SEL                      (1 << 25)
+
 #define MPLL_AD_FUNC_CNTL                               0x624
 #define         CLKF(x)                                 ((x) << 0)
 #define         CLKF_MASK                               (0x7f << 0)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a36736dab5e0..626163ef483d 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -80,6 +80,8 @@ extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
                                          bool enable);
+static void si_init_pg(struct radeon_device *rdev);
+static void si_init_cg(struct radeon_device *rdev);
 static void si_fini_pg(struct radeon_device *rdev);
 static void si_fini_cg(struct radeon_device *rdev);
 static void si_rlc_stop(struct radeon_device *rdev);
@@ -1460,7 +1462,7 @@ static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 };
 
 /* ucode loading */
-static int si_mc_load_microcode(struct radeon_device *rdev)
+int si_mc_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
         u32 running, blackout = 0;
@@ -3722,6 +3724,106 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
         evergreen_print_gpu_status_regs(rdev);
 }
 
+static void si_set_clk_bypass_mode(struct radeon_device *rdev)
+{
+        u32 tmp, i;
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL);
+        tmp |= SPLL_BYPASS_EN;
+        WREG32(CG_SPLL_FUNC_CNTL, tmp);
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
+        tmp |= SPLL_CTLREQ_CHG;
+        WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
+                        break;
+                udelay(1);
+        }
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
+        tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
+        WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
+
+        tmp = RREG32(MPLL_CNTL_MODE);
+        tmp &= ~MPLL_MCLK_SEL;
+        WREG32(MPLL_CNTL_MODE, tmp);
+}
+
+static void si_spll_powerdown(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        tmp = RREG32(SPLL_CNTL_MODE);
+        tmp |= SPLL_SW_DIR_CONTROL;
+        WREG32(SPLL_CNTL_MODE, tmp);
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL);
+        tmp |= SPLL_RESET;
+        WREG32(CG_SPLL_FUNC_CNTL, tmp);
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL);
+        tmp |= SPLL_SLEEP;
+        WREG32(CG_SPLL_FUNC_CNTL, tmp);
+
+        tmp = RREG32(SPLL_CNTL_MODE);
+        tmp &= ~SPLL_SW_DIR_CONTROL;
+        WREG32(SPLL_CNTL_MODE, tmp);
+}
+
+static void si_gpu_pci_config_reset(struct radeon_device *rdev)
+{
+        struct evergreen_mc_save save;
+        u32 tmp, i;
+
+        dev_info(rdev->dev, "GPU pci config reset\n");
+
+        /* disable dpm? */
+
+        /* disable cg/pg */
+        si_fini_pg(rdev);
+        si_fini_cg(rdev);
+
+        /* Disable CP parsing/prefetching */
+        WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+        /* dma0 */
+        tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
+        /* dma1 */
+        tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
+        /* XXX other engines? */
+
+        /* halt the rlc, disable cp internal ints */
+        si_rlc_stop(rdev);
+
+        udelay(50);
+
+        /* disable mem access */
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
+        }
+
+        /* set mclk/sclk to bypass */
+        si_set_clk_bypass_mode(rdev);
+        /* powerdown spll */
+        si_spll_powerdown(rdev);
+        /* disable BM */
+        pci_clear_master(rdev->pdev);
+        /* reset */
+        radeon_pci_config_reset(rdev);
+        /* wait for asic to come out of reset */
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
+                        break;
+                udelay(1);
+        }
+}
+
 int si_asic_reset(struct radeon_device *rdev)
 {
         u32 reset_mask;
@@ -3731,10 +3833,17 @@ int si_asic_reset(struct radeon_device *rdev)
         if (reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, true);
 
+        /* try soft reset */
         si_gpu_soft_reset(rdev, reset_mask);
 
         reset_mask = si_gpu_check_soft_reset(rdev);
 
+        /* try pci config reset */
+        if (reset_mask && radeon_hard_reset)
+                si_gpu_pci_config_reset(rdev);
+
+        reset_mask = si_gpu_check_soft_reset(rdev);
+
         if (!reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, false);
 
@@ -5210,8 +5319,8 @@ static void si_enable_hdp_ls(struct radeon_device *rdev,
                 WREG32(HDP_MEM_POWER_LS, data);
 }
 
-void si_update_cg(struct radeon_device *rdev,
-                  u32 block, bool enable)
+static void si_update_cg(struct radeon_device *rdev,
+                         u32 block, bool enable)
 {
         if (block & RADEON_CG_BLOCK_GFX) {
                 si_enable_gui_idle_interrupt(rdev, false);
@@ -6322,21 +6431,14 @@ static int si_startup(struct radeon_device *rdev)
 
         si_mc_program(rdev);
 
-        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
-            !rdev->rlc_fw || !rdev->mc_fw) {
-                r = si_init_microcode(rdev);
+        if (!rdev->pm.dpm_enabled) {
+                r = si_mc_load_microcode(rdev);
                 if (r) {
-                        DRM_ERROR("Failed to load firmware!\n");
+                        DRM_ERROR("Failed to load MC firmware!\n");
                         return r;
                 }
         }
 
-        r = si_mc_load_microcode(rdev);
-        if (r) {
-                DRM_ERROR("Failed to load MC firmware!\n");
-                return r;
-        }
-
         r = si_pcie_gart_enable(rdev);
         if (r)
                 return r;
@@ -6419,37 +6521,30 @@ static int si_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             CP_RB0_RPTR, CP_RB0_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
-                             CP_RB1_RPTR, CP_RB1_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
-                             CP_RB2_RPTR, CP_RB2_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
-                             DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
-                             DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
-                             DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
         if (r)
                 return r;
@@ -6469,7 +6564,6 @@ static int si_startup(struct radeon_device *rdev)
                 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
                 if (ring->ring_size) {
                         r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-                                             UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                              RADEON_CP_PACKET2);
                         if (!r)
                                 r = uvd_v1_0_init(rdev);
@@ -6511,6 +6605,8 @@ int si_resume(struct radeon_device *rdev)
         /* init golden registers */
         si_init_golden_registers(rdev);
 
+        radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = si_startup(rdev);
         if (r) {
@@ -6525,6 +6621,7 @@ int si_resume(struct radeon_device *rdev)
 
 int si_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         dce6_audio_fini(rdev);
         radeon_vm_manager_fini(rdev);
         si_cp_enable(rdev, false);
@@ -6598,6 +6695,18 @@ int si_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+            !rdev->rlc_fw || !rdev->mc_fw) {
+                r = si_init_microcode(rdev);
+                if (r) {
+                        DRM_ERROR("Failed to load firmware!\n");
+                        return r;
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
@@ -6664,6 +6773,7 @@ int si_init(struct radeon_device *rdev)
 
 void si_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         si_cp_fini(rdev);
         cayman_dma_fini(rdev);
         si_fini_pg(rdev);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 0b00c790fb77..512919b0156a 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -1738,6 +1738,8 @@ struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
 
+extern int si_mc_load_microcode(struct radeon_device *rdev);
+
 static int si_populate_voltage_value(struct radeon_device *rdev,
                                      const struct atom_voltage_table *table,
                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
@@ -1753,9 +1755,6 @@ static int si_calculate_sclk_params(struct radeon_device *rdev,
                                     u32 engine_clock,
                                     SISLANDS_SMC_SCLK_VALUE *sclk);
 
-extern void si_update_cg(struct radeon_device *rdev,
-                         u32 block, bool enable);
-
 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
 {
         struct si_power_info *pi = rdev->pm.dpm.priv;
@@ -5754,6 +5753,11 @@ static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
 
 void si_dpm_setup_asic(struct radeon_device *rdev)
 {
+        int r;
+
+        r = si_mc_load_microcode(rdev);
+        if (r)
+                DRM_ERROR("Failed to load MC firmware!\n");
         rv770_get_memory_type(rdev);
         si_read_clock_registers(rdev);
         si_enable_acpi_power_management(rdev);
@@ -5791,13 +5795,6 @@ int si_dpm_enable(struct radeon_device *rdev)
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
         int ret;
 
-        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                            RADEON_CG_BLOCK_MC |
-                            RADEON_CG_BLOCK_SDMA |
-                            RADEON_CG_BLOCK_BIF |
-                            RADEON_CG_BLOCK_UVD |
-                            RADEON_CG_BLOCK_HDP), false);
-
         if (si_is_smc_running(rdev))
                 return -EINVAL;
         if (pi->voltage_control)
@@ -5900,6 +5897,17 @@ int si_dpm_enable(struct radeon_device *rdev)
         si_enable_sclk_control(rdev, true);
         si_start_dpm(rdev);
 
+        si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
+
+        ni_update_current_ps(rdev, boot_ps);
+
+        return 0;
+}
+
+int si_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
         if (rdev->irq.installed &&
             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
                 PPSMC_Result result;
@@ -5915,17 +5923,6 @@ int si_dpm_enable(struct radeon_device *rdev)
                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
         }
 
-        si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
-
-        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                            RADEON_CG_BLOCK_MC |
-                            RADEON_CG_BLOCK_SDMA |
-                            RADEON_CG_BLOCK_BIF |
-                            RADEON_CG_BLOCK_UVD |
-                            RADEON_CG_BLOCK_HDP), true);
-
-        ni_update_current_ps(rdev, boot_ps);
-
         return 0;
 }
 
@@ -5934,13 +5931,6 @@ void si_dpm_disable(struct radeon_device *rdev)
         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
 
-        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                            RADEON_CG_BLOCK_MC |
-                            RADEON_CG_BLOCK_SDMA |
-                            RADEON_CG_BLOCK_BIF |
-                            RADEON_CG_BLOCK_UVD |
-                            RADEON_CG_BLOCK_HDP), false);
-
         if (!si_is_smc_running(rdev))
                 return;
         si_disable_ulv(rdev);
@@ -6005,13 +5995,6 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
         struct radeon_ps *old_ps = &eg_pi->current_rps;
         int ret;
 
-        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                            RADEON_CG_BLOCK_MC |
-                            RADEON_CG_BLOCK_SDMA |
-                            RADEON_CG_BLOCK_BIF |
-                            RADEON_CG_BLOCK_UVD |
-                            RADEON_CG_BLOCK_HDP), false);
-
         ret = si_disable_ulv(rdev);
         if (ret) {
                 DRM_ERROR("si_disable_ulv failed\n");
@@ -6104,13 +6087,6 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
                 return ret;
         }
 
-        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
-                            RADEON_CG_BLOCK_MC |
-                            RADEON_CG_BLOCK_SDMA |
-                            RADEON_CG_BLOCK_BIF |
-                            RADEON_CG_BLOCK_UVD |
-                            RADEON_CG_BLOCK_HDP), true);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/si_smc.c b/drivers/gpu/drm/radeon/si_smc.c
index d422a1cbf727..e80efcf0c230 100644
--- a/drivers/gpu/drm/radeon/si_smc.c
+++ b/drivers/gpu/drm/radeon/si_smc.c
@@ -28,6 +28,7 @@
 #include "sid.h"
 #include "ppsmc.h"
 #include "radeon_ucode.h"
+#include "sislands_smc.h"
 
 static int si_set_smc_sram_address(struct radeon_device *rdev,
                                    u32 smc_address, u32 limit)
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index b322acc48097..caa3e61a38c2 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -94,6 +94,8 @@
 #define CG_SPLL_FUNC_CNTL_2                             0x604
 #define         SCLK_MUX_SEL(x)                         ((x) << 0)
 #define         SCLK_MUX_SEL_MASK                       (0x1ff << 0)
+#define         SPLL_CTLREQ_CHG                         (1 << 23)
+#define         SCLK_MUX_UPDATE                         (1 << 26)
 #define CG_SPLL_FUNC_CNTL_3                             0x608
 #define         SPLL_FB_DIV(x)                          ((x) << 0)
 #define         SPLL_FB_DIV_MASK                        (0x3ffffff << 0)
@@ -101,7 +103,10 @@
 #define         SPLL_DITHEN                             (1 << 28)
 #define CG_SPLL_FUNC_CNTL_4                             0x60c
 
+#define SPLL_STATUS                                     0x614
+#define         SPLL_CHG_STATUS                         (1 << 1)
 #define SPLL_CNTL_MODE                                  0x618
+#define         SPLL_SW_DIR_CONTROL                     (1 << 0)
 #       define SPLL_REFCLK_SEL(x)                       ((x) << 8)
 #       define SPLL_REFCLK_SEL_MASK                     0xFF00
 
@@ -559,6 +564,8 @@
 #       define MRDCK0_BYPASS                            (1 << 24)
 #       define MRDCK1_BYPASS                            (1 << 25)
 
+#define MPLL_CNTL_MODE                                  0x2bb0
+#       define MPLL_MCLK_SEL                            (1 << 11)
 #define MPLL_FUNC_CNTL                                  0x2bb4
 #define         BWCTRL(x)                               ((x) << 20)
 #define         BWCTRL_MASK                             (0xff << 20)
diff --git a/drivers/gpu/drm/radeon/sislands_smc.h b/drivers/gpu/drm/radeon/sislands_smc.h
index 5578e9837026..10e945a49479 100644
--- a/drivers/gpu/drm/radeon/sislands_smc.h
+++ b/drivers/gpu/drm/radeon/sislands_smc.h
@@ -374,8 +374,6 @@ typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
 
 #pragma pack(pop)
 
-int si_set_smc_sram_address(struct radeon_device *rdev,
-                            u32 smc_address, u32 limit);
 int si_copy_bytes_to_smc(struct radeon_device *rdev,
                          u32 smc_start_address,
                          const u8 *src, u32 byte_count, u32 limit);
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index 96ea6db8bf57..f121efe12dc5 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -71,7 +71,7 @@ static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
         SUMO_DTC_DFLT_14,
 };
 
-struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
+static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
 {
         struct sumo_ps *ps = rps->ps_priv;
 
@@ -1202,14 +1202,10 @@ static void sumo_update_requested_ps(struct radeon_device *rdev,
 int sumo_dpm_enable(struct radeon_device *rdev)
 {
         struct sumo_power_info *pi = sumo_get_pi(rdev);
-        int ret;
 
         if (sumo_dpm_enabled(rdev))
                 return -EINVAL;
 
-        ret = sumo_enable_clock_power_gating(rdev);
-        if (ret)
-                return ret;
         sumo_program_bootup_state(rdev);
         sumo_init_bsp(rdev);
         sumo_reset_am(rdev);
@@ -1233,6 +1229,19 @@ int sumo_dpm_enable(struct radeon_device *rdev)
         if (pi->enable_boost)
                 sumo_enable_boost_timer(rdev);
 
+        sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
+
+        return 0;
+}
+
+int sumo_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
+        ret = sumo_enable_clock_power_gating(rdev);
+        if (ret)
+                return ret;
+
         if (rdev->irq.installed &&
             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
                 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1242,8 +1251,6 @@ int sumo_dpm_enable(struct radeon_device *rdev)
                 radeon_irq_set(rdev);
         }
 
-        sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/sumo_smc.c b/drivers/gpu/drm/radeon/sumo_smc.c
index 18abba5b5810..fb081d2ae374 100644
--- a/drivers/gpu/drm/radeon/sumo_smc.c
+++ b/drivers/gpu/drm/radeon/sumo_smc.c
@@ -31,7 +31,6 @@
 #define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY  27
 #define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20  20
 
-struct sumo_ps *sumo_get_ps(struct radeon_ps *rps);
 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
 
 static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c
index d700698a1f22..2d447192d6f7 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -342,14 +342,14 @@ static void trinity_apply_state_adjust_rules(struct radeon_device *rdev,
                                              struct radeon_ps *new_rps,
                                              struct radeon_ps *old_rps);
 
-struct trinity_ps *trinity_get_ps(struct radeon_ps *rps)
+static struct trinity_ps *trinity_get_ps(struct radeon_ps *rps)
 {
         struct trinity_ps *ps = rps->ps_priv;
 
         return ps;
 }
 
-struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev)
+static struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev)
 {
         struct trinity_power_info *pi = rdev->pm.dpm.priv;
 
@@ -1082,7 +1082,6 @@ void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
 int trinity_dpm_enable(struct radeon_device *rdev)
 {
         struct trinity_power_info *pi = trinity_get_pi(rdev);
-        int ret;
 
         trinity_acquire_mutex(rdev);
 
@@ -1091,7 +1090,6 @@ int trinity_dpm_enable(struct radeon_device *rdev)
                 return -EINVAL;
         }
 
-        trinity_enable_clock_power_gating(rdev);
         trinity_program_bootup_state(rdev);
         sumo_program_vc(rdev, 0x00C00033);
         trinity_start_am(rdev);
@@ -1105,6 +1103,18 @@ int trinity_dpm_enable(struct radeon_device *rdev)
         trinity_dpm_bapm_enable(rdev, false);
         trinity_release_mutex(rdev);
 
+        trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
+
+        return 0;
+}
+
+int trinity_dpm_late_enable(struct radeon_device *rdev)
+{
+        int ret;
+
+        trinity_acquire_mutex(rdev);
+        trinity_enable_clock_power_gating(rdev);
+
         if (rdev->irq.installed &&
             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
                 ret = trinity_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1115,8 +1125,7 @@ int trinity_dpm_enable(struct radeon_device *rdev)
                 rdev->irq.dpm_thermal = true;
                 radeon_irq_set(rdev);
         }
-
-        trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
+        trinity_release_mutex(rdev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/trinity_smc.c b/drivers/gpu/drm/radeon/trinity_smc.c
index 9672bcbc7312..99dd0455334d 100644
--- a/drivers/gpu/drm/radeon/trinity_smc.c
+++ b/drivers/gpu/drm/radeon/trinity_smc.c
@@ -27,9 +27,6 @@
 #include "trinity_dpm.h"
 #include "ppsmc.h"
 
-struct trinity_ps *trinity_get_ps(struct radeon_ps *rps);
-struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev);
-
 static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id)
 {
         int i;