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-rw-r--r--drivers/gpu/drm/radeon/r520.c267
-rw-r--r--drivers/gpu/drm/radeon/r520d.h187
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h43
-rw-r--r--drivers/gpu/drm/radeon/rv515.c2
5 files changed, 376 insertions, 128 deletions
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 2723486ad380..0bf13fccdaf2 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -26,107 +26,13 @@
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h" 29#include "radeon.h"
30#include "atom.h"
31#include "r520d.h"
31 32
32/* r520,rv530,rv560,rv570,r580 depends on : */ 33/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
33void r100_hdp_reset(struct radeon_device *rdev);
34void r420_pipes_init(struct radeon_device *rdev);
35void rs600_mc_disable_clients(struct radeon_device *rdev);
36int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38 34
39/* This files gather functions specifics to: 35static int r520_mc_wait_for_idle(struct radeon_device *rdev)
40 * r520,rv530,rv560,rv570,r580
41 *
42 * Some of these functions might be used by newer ASICs.
43 */
44void r520_gpu_init(struct radeon_device *rdev);
45int r520_mc_wait_for_idle(struct radeon_device *rdev);
46
47
48/*
49 * MC
50 */
51int r520_mc_init(struct radeon_device *rdev)
52{
53 uint32_t tmp;
54 int r;
55
56 if (r100_debugfs_rbbm_init(rdev)) {
57 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
58 }
59 if (rv515_debugfs_pipes_info_init(rdev)) {
60 DRM_ERROR("Failed to register debugfs file for pipes !\n");
61 }
62 if (rv515_debugfs_ga_info_init(rdev)) {
63 DRM_ERROR("Failed to register debugfs file for pipes !\n");
64 }
65
66 r520_gpu_init(rdev);
67 rv370_pcie_gart_disable(rdev);
68
69 /* Setup GPU memory space */
70 rdev->mc.vram_location = 0xFFFFFFFFUL;
71 rdev->mc.gtt_location = 0xFFFFFFFFUL;
72 if (rdev->flags & RADEON_IS_AGP) {
73 r = radeon_agp_init(rdev);
74 if (r) {
75 printk(KERN_WARNING "[drm] Disabling AGP\n");
76 rdev->flags &= ~RADEON_IS_AGP;
77 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
78 } else {
79 rdev->mc.gtt_location = rdev->mc.agp_base;
80 }
81 }
82 r = radeon_mc_setup(rdev);
83 if (r) {
84 return r;
85 }
86
87 /* Program GPU memory space */
88 rs600_mc_disable_clients(rdev);
89 if (r520_mc_wait_for_idle(rdev)) {
90 printk(KERN_WARNING "Failed to wait MC idle while "
91 "programming pipes. Bad things might happen.\n");
92 }
93 /* Write VRAM size in case we are limiting it */
94 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
95 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
96 tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
97 tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
98 WREG32_MC(R520_MC_FB_LOCATION, tmp);
99 WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
100 WREG32(0x310, rdev->mc.vram_location);
101 if (rdev->flags & RADEON_IS_AGP) {
102 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
103 tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
104 tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
105 WREG32_MC(R520_MC_AGP_LOCATION, tmp);
106 WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
107 WREG32_MC(R520_MC_AGP_BASE_2, 0);
108 } else {
109 WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
110 WREG32_MC(R520_MC_AGP_BASE, 0);
111 WREG32_MC(R520_MC_AGP_BASE_2, 0);
112 }
113 return 0;
114}
115
116void r520_mc_fini(struct radeon_device *rdev)
117{
118}
119
120
121/*
122 * Global GPU functions
123 */
124void r520_errata(struct radeon_device *rdev)
125{
126 rdev->pll_errata = 0;
127}
128
129int r520_mc_wait_for_idle(struct radeon_device *rdev)
130{ 36{
131 unsigned i; 37 unsigned i;
132 uint32_t tmp; 38 uint32_t tmp;
@@ -142,7 +48,7 @@ int r520_mc_wait_for_idle(struct radeon_device *rdev)
142 return -1; 48 return -1;
143} 49}
144 50
145void r520_gpu_init(struct radeon_device *rdev) 51static void r520_gpu_init(struct radeon_device *rdev)
146{ 52{
147 unsigned pipe_select_current, gb_pipe_select, tmp; 53 unsigned pipe_select_current, gb_pipe_select, tmp;
148 54
@@ -185,10 +91,6 @@ void r520_gpu_init(struct radeon_device *rdev)
185 } 91 }
186} 92}
187 93
188
189/*
190 * VRAM info
191 */
192static void r520_vram_get_type(struct radeon_device *rdev) 94static void r520_vram_get_type(struct radeon_device *rdev)
193{ 95{
194 uint32_t tmp; 96 uint32_t tmp;
@@ -232,13 +134,168 @@ void r520_vram_info(struct radeon_device *rdev)
232 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 134 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
233} 135}
234 136
235void r520_bandwidth_update(struct radeon_device *rdev) 137void r520_mc_program(struct radeon_device *rdev)
138{
139 struct rv515_mc_save save;
140
141 /* Stops all mc clients */
142 rv515_mc_stop(rdev, &save);
143
144 /* Wait for mc idle */
145 if (r520_mc_wait_for_idle(rdev))
146 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
147 /* Write VRAM size in case we are limiting it */
148 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
149 /* Program MC, should be a 32bits limited address space */
150 WREG32_MC(R_000004_MC_FB_LOCATION,
151 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
152 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
153 WREG32(R_000134_HDP_FB_LOCATION,
154 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
155 if (rdev->flags & RADEON_IS_AGP) {
156 WREG32_MC(R_000005_MC_AGP_LOCATION,
157 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
158 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
159 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
160 WREG32_MC(R_000007_AGP_BASE_2,
161 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
162 } else {
163 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
164 WREG32_MC(R_000006_AGP_BASE, 0);
165 WREG32_MC(R_000007_AGP_BASE_2, 0);
166 }
167
168 rv515_mc_resume(rdev, &save);
169}
170
171static int r520_startup(struct radeon_device *rdev)
172{
173 int r;
174
175 r520_mc_program(rdev);
176 /* Resume clock */
177 rv515_clock_startup(rdev);
178 /* Initialize GPU configuration (# pipes, ...) */
179 r520_gpu_init(rdev);
180 /* Initialize GART (initialize after TTM so we can allocate
181 * memory through TTM but finalize after TTM) */
182 if (rdev->flags & RADEON_IS_PCIE) {
183 r = rv370_pcie_gart_enable(rdev);
184 if (r)
185 return r;
186 }
187 /* Enable IRQ */
188 rdev->irq.sw_int = true;
189 r100_irq_set(rdev);
190 /* 1M ring buffer */
191 r = r100_cp_init(rdev, 1024 * 1024);
192 if (r) {
193 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
194 return r;
195 }
196 r = r100_wb_init(rdev);
197 if (r)
198 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
199 r = r100_ib_init(rdev);
200 if (r) {
201 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
202 return r;
203 }
204 return 0;
205}
206
207int r520_resume(struct radeon_device *rdev)
236{ 208{
237 rv515_bandwidth_avivo_update(rdev); 209 /* Make sur GART are not working */
210 if (rdev->flags & RADEON_IS_PCIE)
211 rv370_pcie_gart_disable(rdev);
212 /* Resume clock before doing reset */
213 rv515_clock_startup(rdev);
214 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
215 if (radeon_gpu_reset(rdev)) {
216 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
217 RREG32(R_000E40_RBBM_STATUS),
218 RREG32(R_0007C0_CP_STAT));
219 }
220 /* post */
221 atom_asic_init(rdev->mode_info.atom_context);
222 /* Resume clock after posting */
223 rv515_clock_startup(rdev);
224 return r520_startup(rdev);
238} 225}
239 226
240int r520_init(struct radeon_device *rdev) 227int r520_init(struct radeon_device *rdev)
241{ 228{
229 int r;
230
231 rdev->new_init_path = true;
232 /* Initialize scratch registers */
233 radeon_scratch_init(rdev);
234 /* Initialize surface registers */
235 radeon_surface_init(rdev);
236 /* TODO: disable VGA need to use VGA request */
237 /* BIOS*/
238 if (!radeon_get_bios(rdev)) {
239 if (ASIC_IS_AVIVO(rdev))
240 return -EINVAL;
241 }
242 if (rdev->is_atom_bios) {
243 r = radeon_atombios_init(rdev);
244 if (r)
245 return r;
246 } else {
247 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
248 return -EINVAL;
249 }
250 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
251 if (radeon_gpu_reset(rdev)) {
252 dev_warn(rdev->dev,
253 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
254 RREG32(R_000E40_RBBM_STATUS),
255 RREG32(R_0007C0_CP_STAT));
256 }
257 /* check if cards are posted or not */
258 if (!radeon_card_posted(rdev) && rdev->bios) {
259 DRM_INFO("GPU not posted. posting now...\n");
260 atom_asic_init(rdev->mode_info.atom_context);
261 }
262 /* Initialize clocks */
263 radeon_get_clock_info(rdev->ddev);
264 /* Get vram informations */
265 r520_vram_info(rdev);
266 /* Initialize memory controller (also test AGP) */
267 r = r420_mc_init(rdev);
268 if (r)
269 return r;
270 rv515_debugfs(rdev);
271 /* Fence driver */
272 r = radeon_fence_driver_init(rdev);
273 if (r)
274 return r;
275 r = radeon_irq_kms_init(rdev);
276 if (r)
277 return r;
278 /* Memory manager */
279 r = radeon_object_init(rdev);
280 if (r)
281 return r;
282 r = rv370_pcie_gart_init(rdev);
283 if (r)
284 return r;
242 rv515_set_safe_registers(rdev); 285 rv515_set_safe_registers(rdev);
286 rdev->accel_working = true;
287 r = r520_startup(rdev);
288 if (r) {
289 /* Somethings want wront with the accel init stop accel */
290 dev_err(rdev->dev, "Disabling GPU acceleration\n");
291 rv515_suspend(rdev);
292 r100_cp_fini(rdev);
293 r100_wb_fini(rdev);
294 r100_ib_fini(rdev);
295 rv370_pcie_gart_fini(rdev);
296 radeon_agp_fini(rdev);
297 radeon_irq_kms_fini(rdev);
298 rdev->accel_working = false;
299 }
243 return 0; 300 return 0;
244} 301}
diff --git a/drivers/gpu/drm/radeon/r520d.h b/drivers/gpu/drm/radeon/r520d.h
new file mode 100644
index 000000000000..61af61f644bc
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r520d.h
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __R520D_H__
29#define __R520D_H__
30
31/* Registers */
32#define R_0000F8_CONFIG_MEMSIZE 0x0000F8
33#define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0)
34#define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF)
35#define C_0000F8_CONFIG_MEMSIZE 0x00000000
36#define R_000134_HDP_FB_LOCATION 0x000134
37#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)
38#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)
39#define C_000134_HDP_FB_START 0xFFFF0000
40#define R_0007C0_CP_STAT 0x0007C0
41#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
42#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
43#define C_0007C0_MRU_BUSY 0xFFFFFFFE
44#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
45#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
46#define C_0007C0_MWU_BUSY 0xFFFFFFFD
47#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
48#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
49#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
50#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
51#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
52#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
53#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
54#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
55#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
56#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
57#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
58#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
59#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
60#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
61#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
62#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
63#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
64#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
65#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
66#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
67#define C_0007C0_CSI_BUSY 0xFFFFDFFF
68#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
69#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
70#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
71#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
72#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
73#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
74#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
75#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
76#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
77#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
78#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
79#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
80#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
81#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
82#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
83#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
84#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
85#define C_0007C0_CP_BUSY 0x7FFFFFFF
86#define R_000E40_RBBM_STATUS 0x000E40
87#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
88#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
89#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
90#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
91#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
92#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
93#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
94#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
95#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
96#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
97#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
98#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
99#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
100#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
101#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
102#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
103#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
104#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
105#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
106#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
107#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
108#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
109#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
110#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
111#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
112#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
113#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
114#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
115#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
116#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
117#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
118#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
119#define C_000E40_E2_BUSY 0xFFFDFFFF
120#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
121#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
122#define C_000E40_RB2D_BUSY 0xFFFBFFFF
123#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
124#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
125#define C_000E40_RB3D_BUSY 0xFFF7FFFF
126#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
127#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
128#define C_000E40_VAP_BUSY 0xFFEFFFFF
129#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
130#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
131#define C_000E40_RE_BUSY 0xFFDFFFFF
132#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
133#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
134#define C_000E40_TAM_BUSY 0xFFBFFFFF
135#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
136#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
137#define C_000E40_TDM_BUSY 0xFF7FFFFF
138#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
139#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
140#define C_000E40_PB_BUSY 0xFEFFFFFF
141#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
142#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
143#define C_000E40_TIM_BUSY 0xFDFFFFFF
144#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
145#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
146#define C_000E40_GA_BUSY 0xFBFFFFFF
147#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
148#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
149#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
150#define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28)
151#define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1)
152#define C_000E40_RBBM_HIBUSY 0xEFFFFFFF
153#define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29)
154#define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1)
155#define C_000E40_SKID_CFBUSY 0xDFFFFFFF
156#define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30)
157#define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1)
158#define C_000E40_VAP_VF_BUSY 0xBFFFFFFF
159#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
160#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
161#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
162
163
164#define R_000004_MC_FB_LOCATION 0x000004
165#define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0)
166#define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
167#define C_000004_MC_FB_START 0xFFFF0000
168#define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
169#define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
170#define C_000004_MC_FB_TOP 0x0000FFFF
171#define R_000005_MC_AGP_LOCATION 0x000005
172#define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
173#define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
174#define C_000005_MC_AGP_START 0xFFFF0000
175#define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
176#define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
177#define C_000005_MC_AGP_TOP 0x0000FFFF
178#define R_000006_AGP_BASE 0x000006
179#define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
180#define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
181#define C_000006_AGP_BASE_ADDR 0x00000000
182#define R_000007_AGP_BASE_2 0x000007
183#define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
184#define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
185#define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0
186
187#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 116bedddffe6..7b0965f54958 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1058,6 +1058,11 @@ struct rv515_mc_save {
1058extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 1058extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1059extern void rv515_vga_render_disable(struct radeon_device *rdev); 1059extern void rv515_vga_render_disable(struct radeon_device *rdev);
1060extern void rv515_set_safe_registers(struct radeon_device *rdev); 1060extern void rv515_set_safe_registers(struct radeon_device *rdev);
1061extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1062extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1063extern void rv515_clock_startup(struct radeon_device *rdev);
1064extern void rv515_debugfs(struct radeon_device *rdev);
1065extern int rv515_suspend(struct radeon_device *rdev);
1061 1066
1062/* rs690, rs740 */ 1067/* rs690, rs740 */
1063extern void rs690_line_buffer_adjust(struct radeon_device *rdev, 1068extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index ccbf5253914d..bce0cb063867 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -471,34 +471,33 @@ static struct radeon_asic rv515_asic = {
471 * r520,rv530,rv560,rv570,r580 471 * r520,rv530,rv560,rv570,r580
472 */ 472 */
473int r520_init(struct radeon_device *rdev); 473int r520_init(struct radeon_device *rdev);
474void r520_errata(struct radeon_device *rdev); 474int r520_resume(struct radeon_device *rdev);
475void r520_vram_info(struct radeon_device *rdev);
476int r520_mc_init(struct radeon_device *rdev);
477void r520_mc_fini(struct radeon_device *rdev);
478void r520_bandwidth_update(struct radeon_device *rdev);
479static struct radeon_asic r520_asic = { 475static struct radeon_asic r520_asic = {
480 .init = &r520_init, 476 .init = &r520_init,
481 .errata = &r520_errata, 477 .fini = &rv515_fini,
482 .vram_info = &r520_vram_info, 478 .suspend = &rv515_suspend,
479 .resume = &r520_resume,
480 .errata = NULL,
481 .vram_info = NULL,
483 .gpu_reset = &rv515_gpu_reset, 482 .gpu_reset = &rv515_gpu_reset,
484 .mc_init = &r520_mc_init, 483 .mc_init = NULL,
485 .mc_fini = &r520_mc_fini, 484 .mc_fini = NULL,
486 .wb_init = &r100_wb_init, 485 .wb_init = NULL,
487 .wb_fini = &r100_wb_fini, 486 .wb_fini = NULL,
488 .gart_init = &rv370_pcie_gart_init, 487 .gart_init = NULL,
489 .gart_fini = &rv370_pcie_gart_fini, 488 .gart_fini = NULL,
490 .gart_enable = &rv370_pcie_gart_enable, 489 .gart_enable = NULL,
491 .gart_disable = &rv370_pcie_gart_disable, 490 .gart_disable = NULL,
492 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, 491 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
493 .gart_set_page = &rv370_pcie_gart_set_page, 492 .gart_set_page = &rv370_pcie_gart_set_page,
494 .cp_init = &r100_cp_init, 493 .cp_init = NULL,
495 .cp_fini = &r100_cp_fini, 494 .cp_fini = NULL,
496 .cp_disable = &r100_cp_disable, 495 .cp_disable = NULL,
497 .cp_commit = &r100_cp_commit, 496 .cp_commit = &r100_cp_commit,
498 .ring_start = &rv515_ring_start, 497 .ring_start = &rv515_ring_start,
499 .ring_test = &r100_ring_test, 498 .ring_test = &r100_ring_test,
500 .ring_ib_execute = &r100_ring_ib_execute, 499 .ring_ib_execute = &r100_ring_ib_execute,
501 .ib_test = &r100_ib_test, 500 .ib_test = NULL,
502 .irq_set = &rs600_irq_set, 501 .irq_set = &rs600_irq_set,
503 .irq_process = &rs600_irq_process, 502 .irq_process = &rs600_irq_process,
504 .get_vblank_counter = &rs600_get_vblank_counter, 503 .get_vblank_counter = &rs600_get_vblank_counter,
@@ -513,7 +512,7 @@ static struct radeon_asic r520_asic = {
513 .set_clock_gating = &radeon_atom_set_clock_gating, 512 .set_clock_gating = &radeon_atom_set_clock_gating,
514 .set_surface_reg = r100_set_surface_reg, 513 .set_surface_reg = r100_set_surface_reg,
515 .clear_surface_reg = r100_clear_surface_reg, 514 .clear_surface_reg = r100_clear_surface_reg,
516 .bandwidth_update = &r520_bandwidth_update, 515 .bandwidth_update = &rv515_bandwidth_update,
517}; 516};
518 517
519/* 518/*
@@ -588,7 +587,7 @@ static struct radeon_asic r600_asic = {
588 .set_clock_gating = &radeon_atom_set_clock_gating, 587 .set_clock_gating = &radeon_atom_set_clock_gating,
589 .set_surface_reg = r600_set_surface_reg, 588 .set_surface_reg = r600_set_surface_reg,
590 .clear_surface_reg = r600_clear_surface_reg, 589 .clear_surface_reg = r600_clear_surface_reg,
591 .bandwidth_update = &r520_bandwidth_update, 590 .bandwidth_update = &rv515_bandwidth_update,
592}; 591};
593 592
594/* 593/*
@@ -637,7 +636,7 @@ static struct radeon_asic rv770_asic = {
637 .set_clock_gating = &radeon_atom_set_clock_gating, 636 .set_clock_gating = &radeon_atom_set_clock_gating,
638 .set_surface_reg = r600_set_surface_reg, 637 .set_surface_reg = r600_set_surface_reg,
639 .clear_surface_reg = r600_clear_surface_reg, 638 .clear_surface_reg = r600_clear_surface_reg,
640 .bandwidth_update = &r520_bandwidth_update, 639 .bandwidth_update = &rv515_bandwidth_update,
641}; 640};
642 641
643#endif 642#endif
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index a837ddcada1e..e53b5ca7a253 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -38,7 +38,7 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38void rv515_gpu_init(struct radeon_device *rdev); 38void rv515_gpu_init(struct radeon_device *rdev);
39int rv515_mc_wait_for_idle(struct radeon_device *rdev); 39int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40 40
41static void rv515_debugfs(struct radeon_device *rdev) 41void rv515_debugfs(struct radeon_device *rdev)
42{ 42{
43 if (r100_debugfs_rbbm_init(rdev)) { 43 if (r100_debugfs_rbbm_init(rdev)) {
44 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 44 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 12:13:38 -0500