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-rw-r--r--drivers/gpu/drm/i915/i915_drv.h7
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c93
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c51
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c11
-rw-r--r--drivers/gpu/drm/i915/intel_display.c87
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c12
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h20
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c6
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c18
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c2
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c13
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c2
-rw-r--r--drivers/gpu/drm/radeon/r300.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c12
-rw-r--r--drivers/gpu/drm/radeon/rs600.c65
-rw-r--r--drivers/gpu/drm/radeon/rs690.c64
-rw-r--r--drivers/gpu/drm/radeon/rv515.c2
18 files changed, 294 insertions, 179 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7537f57d8a87..5b4f87e55621 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -222,6 +222,7 @@ typedef struct drm_i915_private {
222 unsigned int edp_support:1; 222 unsigned int edp_support:1;
223 int lvds_ssc_freq; 223 int lvds_ssc_freq;
224 224
225 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
225 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 226 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
226 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 227 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
227 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 228 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
@@ -384,6 +385,9 @@ typedef struct drm_i915_private {
384 */ 385 */
385 struct list_head inactive_list; 386 struct list_head inactive_list;
386 387
388 /** LRU list of objects with fence regs on them. */
389 struct list_head fence_list;
390
387 /** 391 /**
388 * List of breadcrumbs associated with GPU requests currently 392 * List of breadcrumbs associated with GPU requests currently
389 * outstanding. 393 * outstanding.
@@ -451,6 +455,9 @@ struct drm_i915_gem_object {
451 /** This object's place on the active/flushing/inactive lists */ 455 /** This object's place on the active/flushing/inactive lists */
452 struct list_head list; 456 struct list_head list;
453 457
458 /** This object's place on the fenced object LRU */
459 struct list_head fence_list;
460
454 /** 461 /**
455 * This is set if the object is on the active or flushing lists 462 * This is set if the object is on the active or flushing lists
456 * (has pending rendering), and is not set if it's on inactive (ready 463 * (has pending rendering), and is not set if it's on inactive (ready
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 140bee142fc2..7edb5b9d5792 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -978,6 +978,7 @@ int
978i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 978i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv) 979 struct drm_file *file_priv)
980{ 980{
981 struct drm_i915_private *dev_priv = dev->dev_private;
981 struct drm_i915_gem_set_domain *args = data; 982 struct drm_i915_gem_set_domain *args = data;
982 struct drm_gem_object *obj; 983 struct drm_gem_object *obj;
983 uint32_t read_domains = args->read_domains; 984 uint32_t read_domains = args->read_domains;
@@ -1010,8 +1011,18 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1010 obj, obj->size, read_domains, write_domain); 1011 obj, obj->size, read_domains, write_domain);
1011#endif 1012#endif
1012 if (read_domains & I915_GEM_DOMAIN_GTT) { 1013 if (read_domains & I915_GEM_DOMAIN_GTT) {
1014 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1015
1013 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); 1016 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1014 1017
1018 /* Update the LRU on the fence for the CPU access that's
1019 * about to occur.
1020 */
1021 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1022 list_move_tail(&obj_priv->fence_list,
1023 &dev_priv->mm.fence_list);
1024 }
1025
1015 /* Silently promote "you're not bound, there was nothing to do" 1026 /* Silently promote "you're not bound, there was nothing to do"
1016 * to success, since the client was just asking us to 1027 * to success, since the client was just asking us to
1017 * make sure everything was done. 1028 * make sure everything was done.
@@ -1155,8 +1166,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1155 } 1166 }
1156 1167
1157 /* Need a new fence register? */ 1168 /* Need a new fence register? */
1158 if (obj_priv->fence_reg == I915_FENCE_REG_NONE && 1169 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1159 obj_priv->tiling_mode != I915_TILING_NONE) {
1160 ret = i915_gem_object_get_fence_reg(obj); 1170 ret = i915_gem_object_get_fence_reg(obj);
1161 if (ret) { 1171 if (ret) {
1162 mutex_unlock(&dev->struct_mutex); 1172 mutex_unlock(&dev->struct_mutex);
@@ -2208,6 +2218,12 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2208 struct drm_i915_gem_object *old_obj_priv = NULL; 2218 struct drm_i915_gem_object *old_obj_priv = NULL;
2209 int i, ret, avail; 2219 int i, ret, avail;
2210 2220
2221 /* Just update our place in the LRU if our fence is getting used. */
2222 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2223 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2224 return 0;
2225 }
2226
2211 switch (obj_priv->tiling_mode) { 2227 switch (obj_priv->tiling_mode) {
2212 case I915_TILING_NONE: 2228 case I915_TILING_NONE:
2213 WARN(1, "allocating a fence for non-tiled object?\n"); 2229 WARN(1, "allocating a fence for non-tiled object?\n");
@@ -2229,7 +2245,6 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2229 } 2245 }
2230 2246
2231 /* First try to find a free reg */ 2247 /* First try to find a free reg */
2232try_again:
2233 avail = 0; 2248 avail = 0;
2234 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { 2249 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2235 reg = &dev_priv->fence_regs[i]; 2250 reg = &dev_priv->fence_regs[i];
@@ -2243,63 +2258,62 @@ try_again:
2243 2258
2244 /* None available, try to steal one or wait for a user to finish */ 2259 /* None available, try to steal one or wait for a user to finish */
2245 if (i == dev_priv->num_fence_regs) { 2260 if (i == dev_priv->num_fence_regs) {
2246 uint32_t seqno = dev_priv->mm.next_gem_seqno; 2261 struct drm_gem_object *old_obj = NULL;
2247 2262
2248 if (avail == 0) 2263 if (avail == 0)
2249 return -ENOSPC; 2264 return -ENOSPC;
2250 2265
2251 for (i = dev_priv->fence_reg_start; 2266 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2252 i < dev_priv->num_fence_regs; i++) { 2267 fence_list) {
2253 uint32_t this_seqno; 2268 old_obj = old_obj_priv->obj;
2254
2255 reg = &dev_priv->fence_regs[i];
2256 old_obj_priv = reg->obj->driver_private;
2257 2269
2258 if (old_obj_priv->pin_count) 2270 if (old_obj_priv->pin_count)
2259 continue; 2271 continue;
2260 2272
2273 /* Take a reference, as otherwise the wait_rendering
2274 * below may cause the object to get freed out from
2275 * under us.
2276 */
2277 drm_gem_object_reference(old_obj);
2278
2261 /* i915 uses fences for GPU access to tiled buffers */ 2279 /* i915 uses fences for GPU access to tiled buffers */
2262 if (IS_I965G(dev) || !old_obj_priv->active) 2280 if (IS_I965G(dev) || !old_obj_priv->active)
2263 break; 2281 break;
2264 2282
2265 /* find the seqno of the first available fence */ 2283 /* This brings the object to the head of the LRU if it
2266 this_seqno = old_obj_priv->last_rendering_seqno; 2284 * had been written to. The only way this should
2267 if (this_seqno != 0 && 2285 * result in us waiting longer than the expected
2268 reg->obj->write_domain == 0 && 2286 * optimal amount of time is if there was a
2269 i915_seqno_passed(seqno, this_seqno)) 2287 * fence-using buffer later that was read-only.
2270 seqno = this_seqno; 2288 */
2271 } 2289 i915_gem_object_flush_gpu_write_domain(old_obj);
2272 2290 ret = i915_gem_object_wait_rendering(old_obj);
2273 /* 2291 if (ret != 0) {
2274 * Now things get ugly... we have to wait for one of the 2292 drm_gem_object_unreference(old_obj);
2275 * objects to finish before trying again. 2293 return ret;
2276 */
2277 if (i == dev_priv->num_fence_regs) {
2278 if (seqno == dev_priv->mm.next_gem_seqno) {
2279 i915_gem_flush(dev,
2280 I915_GEM_GPU_DOMAINS,
2281 I915_GEM_GPU_DOMAINS);
2282 seqno = i915_add_request(dev, NULL,
2283 I915_GEM_GPU_DOMAINS);
2284 if (seqno == 0)
2285 return -ENOMEM;
2286 } 2294 }
2287 2295
2288 ret = i915_wait_request(dev, seqno); 2296 break;
2289 if (ret)
2290 return ret;
2291 goto try_again;
2292 } 2297 }
2293 2298
2294 /* 2299 /*
2295 * Zap this virtual mapping so we can set up a fence again 2300 * Zap this virtual mapping so we can set up a fence again
2296 * for this object next time we need it. 2301 * for this object next time we need it.
2297 */ 2302 */
2298 i915_gem_release_mmap(reg->obj); 2303 i915_gem_release_mmap(old_obj);
2304
2305 i = old_obj_priv->fence_reg;
2306 reg = &dev_priv->fence_regs[i];
2307
2299 old_obj_priv->fence_reg = I915_FENCE_REG_NONE; 2308 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2309 list_del_init(&old_obj_priv->fence_list);
2310
2311 drm_gem_object_unreference(old_obj);
2300 } 2312 }
2301 2313
2302 obj_priv->fence_reg = i; 2314 obj_priv->fence_reg = i;
2315 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2316
2303 reg->obj = obj; 2317 reg->obj = obj;
2304 2318
2305 if (IS_I965G(dev)) 2319 if (IS_I965G(dev))
@@ -2342,6 +2356,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2342 2356
2343 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; 2357 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2344 obj_priv->fence_reg = I915_FENCE_REG_NONE; 2358 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2359 list_del_init(&obj_priv->fence_list);
2345} 2360}
2346 2361
2347/** 2362/**
@@ -3595,9 +3610,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3595 * Pre-965 chips need a fence register set up in order to 3610 * Pre-965 chips need a fence register set up in order to
3596 * properly handle tiled surfaces. 3611 * properly handle tiled surfaces.
3597 */ 3612 */
3598 if (!IS_I965G(dev) && 3613 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3599 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
3600 obj_priv->tiling_mode != I915_TILING_NONE) {
3601 ret = i915_gem_object_get_fence_reg(obj); 3614 ret = i915_gem_object_get_fence_reg(obj);
3602 if (ret != 0) { 3615 if (ret != 0) {
3603 if (ret != -EBUSY && ret != -ERESTARTSYS) 3616 if (ret != -EBUSY && ret != -ERESTARTSYS)
@@ -3806,6 +3819,7 @@ int i915_gem_init_object(struct drm_gem_object *obj)
3806 obj_priv->obj = obj; 3819 obj_priv->obj = obj;
3807 obj_priv->fence_reg = I915_FENCE_REG_NONE; 3820 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3808 INIT_LIST_HEAD(&obj_priv->list); 3821 INIT_LIST_HEAD(&obj_priv->list);
3822 INIT_LIST_HEAD(&obj_priv->fence_list);
3809 3823
3810 return 0; 3824 return 0;
3811} 3825}
@@ -4253,6 +4267,7 @@ i915_gem_load(struct drm_device *dev)
4253 INIT_LIST_HEAD(&dev_priv->mm.flushing_list); 4267 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4254 INIT_LIST_HEAD(&dev_priv->mm.inactive_list); 4268 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4255 INIT_LIST_HEAD(&dev_priv->mm.request_list); 4269 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4270 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4256 INIT_DELAYED_WORK(&dev_priv->mm.retire_work, 4271 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4257 i915_gem_retire_work_handler); 4272 i915_gem_retire_work_handler);
4258 dev_priv->mm.next_gem_seqno = 1; 4273 dev_priv->mm.next_gem_seqno = 1;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 300aee3296c2..f806fcc54e09 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -59,6 +59,16 @@ find_section(struct bdb_header *bdb, int section_id)
59 return NULL; 59 return NULL;
60} 60}
61 61
62static u16
63get_blocksize(void *p)
64{
65 u16 *block_ptr, block_size;
66
67 block_ptr = (u16 *)((char *)p - 2);
68 block_size = *block_ptr;
69 return block_size;
70}
71
62static void 72static void
63fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, 73fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
64 struct lvds_dvo_timing *dvo_timing) 74 struct lvds_dvo_timing *dvo_timing)
@@ -215,6 +225,41 @@ parse_general_features(struct drm_i915_private *dev_priv,
215} 225}
216 226
217static void 227static void
228parse_general_definitions(struct drm_i915_private *dev_priv,
229 struct bdb_header *bdb)
230{
231 struct bdb_general_definitions *general;
232 const int crt_bus_map_table[] = {
233 GPIOB,
234 GPIOA,
235 GPIOC,
236 GPIOD,
237 GPIOE,
238 GPIOF,
239 };
240
241 /* Set sensible defaults in case we can't find the general block
242 or it is the wrong chipset */
243 dev_priv->crt_ddc_bus = -1;
244
245 general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
246 if (general) {
247 u16 block_size = get_blocksize(general);
248 if (block_size >= sizeof(*general)) {
249 int bus_pin = general->crt_ddc_gmbus_pin;
250 DRM_DEBUG("crt_ddc_bus_pin: %d\n", bus_pin);
251 if ((bus_pin >= 1) && (bus_pin <= 6)) {
252 dev_priv->crt_ddc_bus =
253 crt_bus_map_table[bus_pin-1];
254 }
255 } else {
256 DRM_DEBUG("BDB_GD too small (%d). Invalid.\n",
257 block_size);
258 }
259 }
260}
261
262static void
218parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, 263parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
219 struct bdb_header *bdb) 264 struct bdb_header *bdb)
220{ 265{
@@ -222,7 +267,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
222 struct bdb_general_definitions *p_defs; 267 struct bdb_general_definitions *p_defs;
223 struct child_device_config *p_child; 268 struct child_device_config *p_child;
224 int i, child_device_num, count; 269 int i, child_device_num, count;
225 u16 block_size, *block_ptr; 270 u16 block_size;
226 271
227 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); 272 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
228 if (!p_defs) { 273 if (!p_defs) {
@@ -240,8 +285,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
240 return; 285 return;
241 } 286 }
242 /* get the block size of general definitions */ 287 /* get the block size of general definitions */
243 block_ptr = (u16 *)((char *)p_defs - 2); 288 block_size = get_blocksize(p_defs);
244 block_size = *block_ptr;
245 /* get the number of child device */ 289 /* get the number of child device */
246 child_device_num = (block_size - sizeof(*p_defs)) / 290 child_device_num = (block_size - sizeof(*p_defs)) /
247 sizeof(*p_child); 291 sizeof(*p_child);
@@ -362,6 +406,7 @@ intel_init_bios(struct drm_device *dev)
362 406
363 /* Grab useful general definitions */ 407 /* Grab useful general definitions */
364 parse_general_features(dev_priv, bdb); 408 parse_general_features(dev_priv, bdb);
409 parse_general_definitions(dev_priv, bdb);
365 parse_lfp_panel_data(dev_priv, bdb); 410 parse_lfp_panel_data(dev_priv, bdb);
366 parse_sdvo_panel_data(dev_priv, bdb); 411 parse_sdvo_panel_data(dev_priv, bdb);
367 parse_sdvo_device_mapping(dev_priv, bdb); 412 parse_sdvo_device_mapping(dev_priv, bdb);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4cf8e2e88a40..590f81c8f594 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -508,6 +508,7 @@ void intel_crt_init(struct drm_device *dev)
508{ 508{
509 struct drm_connector *connector; 509 struct drm_connector *connector;
510 struct intel_output *intel_output; 510 struct intel_output *intel_output;
511 struct drm_i915_private *dev_priv = dev->dev_private;
511 u32 i2c_reg; 512 u32 i2c_reg;
512 513
513 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); 514 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
@@ -527,8 +528,12 @@ void intel_crt_init(struct drm_device *dev)
527 /* Set up the DDC bus. */ 528 /* Set up the DDC bus. */
528 if (IS_IGDNG(dev)) 529 if (IS_IGDNG(dev))
529 i2c_reg = PCH_GPIOA; 530 i2c_reg = PCH_GPIOA;
530 else 531 else {
531 i2c_reg = GPIOA; 532 i2c_reg = GPIOA;
533 /* Use VBT information for CRT DDC if available */
534 if (dev_priv->crt_ddc_bus != -1)
535 i2c_reg = dev_priv->crt_ddc_bus;
536 }
532 intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); 537 intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
533 if (!intel_output->ddc_bus) { 538 if (!intel_output->ddc_bus) {
534 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " 539 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
@@ -537,6 +542,10 @@ void intel_crt_init(struct drm_device *dev)
537 } 542 }
538 543
539 intel_output->type = INTEL_OUTPUT_ANALOG; 544 intel_output->type = INTEL_OUTPUT_ANALOG;
545 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
546 (1 << INTEL_ANALOG_CLONE_BIT) |
547 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
548 intel_output->crtc_mask = (1 << 0) | (1 << 1);
540 connector->interlace_allowed = 0; 549 connector->interlace_allowed = 0;
541 connector->doublescan_allowed = 0; 550 connector->doublescan_allowed = 0;
542 551
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6fce2133413..748ed50c55ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -666,7 +666,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
666 intel_clock_t clock; 666 intel_clock_t clock;
667 int err = target; 667 int err = target;
668 668
669 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 669 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
670 (I915_READ(LVDS)) != 0) { 670 (I915_READ(LVDS)) != 0) {
671 /* 671 /*
672 * For LVDS, if the panel is on, just rely on its current 672 * For LVDS, if the panel is on, just rely on its current
@@ -2005,7 +2005,21 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2005 return; 2005 return;
2006} 2006}
2007 2007
2008const static int latency_ns = 3000; /* default for non-igd platforms */ 2008/*
2009 * Latency for FIFO fetches is dependent on several factors:
2010 * - memory configuration (speed, channels)
2011 * - chipset
2012 * - current MCH state
2013 * It can be fairly high in some situations, so here we assume a fairly
2014 * pessimal value. It's a tradeoff between extra memory fetches (if we
2015 * set this value too high, the FIFO will fetch frequently to stay full)
2016 * and power consumption (set it too low to save power and we might see
2017 * FIFO underruns and display "flicker").
2018 *
2019 * A value of 5us seems to be a good balance; safe for very low end
2020 * platforms but not overly aggressive on lower latency configs.
2021 */
2022const static int latency_ns = 5000;
2009 2023
2010static int intel_get_fifo_size(struct drm_device *dev, int plane) 2024static int intel_get_fifo_size(struct drm_device *dev, int plane)
2011{ 2025{
@@ -2396,7 +2410,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2396 if (is_sdvo) { 2410 if (is_sdvo) {
2397 dpll |= DPLL_DVO_HIGH_SPEED; 2411 dpll |= DPLL_DVO_HIGH_SPEED;
2398 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 2412 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2399 if (IS_I945G(dev) || IS_I945GM(dev)) 2413 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2400 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 2414 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2401 else if (IS_IGDNG(dev)) 2415 else if (IS_IGDNG(dev))
2402 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 2416 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
@@ -3170,7 +3184,7 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
3170 3184
3171 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3185 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3172 struct intel_output *intel_output = to_intel_output(connector); 3186 struct intel_output *intel_output = to_intel_output(connector);
3173 if (type_mask & (1 << intel_output->type)) 3187 if (type_mask & intel_output->clone_mask)
3174 index_mask |= (1 << entry); 3188 index_mask |= (1 << entry);
3175 entry++; 3189 entry++;
3176 } 3190 }
@@ -3218,30 +3232,30 @@ static void intel_setup_outputs(struct drm_device *dev)
3218 intel_dp_init(dev, PCH_DP_D); 3232 intel_dp_init(dev, PCH_DP_D);
3219 3233
3220 } else if (IS_I9XX(dev)) { 3234 } else if (IS_I9XX(dev)) {
3221 int found; 3235 bool found = false;
3222 u32 reg;
3223 3236
3224 if (I915_READ(SDVOB) & SDVO_DETECTED) { 3237 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3225 found = intel_sdvo_init(dev, SDVOB); 3238 found = intel_sdvo_init(dev, SDVOB);
3226 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 3239 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3227 intel_hdmi_init(dev, SDVOB); 3240 intel_hdmi_init(dev, SDVOB);
3241
3228 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 3242 if (!found && SUPPORTS_INTEGRATED_DP(dev))
3229 intel_dp_init(dev, DP_B); 3243 intel_dp_init(dev, DP_B);
3230 } 3244 }
3231 3245
3232 /* Before G4X SDVOC doesn't have its own detect register */ 3246 /* Before G4X SDVOC doesn't have its own detect register */
3233 if (IS_G4X(dev))
3234 reg = SDVOC;
3235 else
3236 reg = SDVOB;
3237 3247
3238 if (I915_READ(reg) & SDVO_DETECTED) { 3248 if (I915_READ(SDVOB) & SDVO_DETECTED)
3239 found = intel_sdvo_init(dev, SDVOC); 3249 found = intel_sdvo_init(dev, SDVOC);
3240 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) 3250
3251 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3252
3253 if (SUPPORTS_INTEGRATED_HDMI(dev))
3241 intel_hdmi_init(dev, SDVOC); 3254 intel_hdmi_init(dev, SDVOC);
3242 if (!found && SUPPORTS_INTEGRATED_DP(dev)) 3255 if (SUPPORTS_INTEGRATED_DP(dev))
3243 intel_dp_init(dev, DP_C); 3256 intel_dp_init(dev, DP_C);
3244 } 3257 }
3258
3245 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 3259 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3246 intel_dp_init(dev, DP_D); 3260 intel_dp_init(dev, DP_D);
3247 } else 3261 } else
@@ -3253,51 +3267,10 @@ static void intel_setup_outputs(struct drm_device *dev)
3253 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3267 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3254 struct intel_output *intel_output = to_intel_output(connector); 3268 struct intel_output *intel_output = to_intel_output(connector);
3255 struct drm_encoder *encoder = &intel_output->enc; 3269 struct drm_encoder *encoder = &intel_output->enc;
3256 int crtc_mask = 0, clone_mask = 0;
3257 3270
3258 /* valid crtcs */ 3271 encoder->possible_crtcs = intel_output->crtc_mask;
3259 switch(intel_output->type) { 3272 encoder->possible_clones = intel_connector_clones(dev,
3260 case INTEL_OUTPUT_HDMI: 3273 intel_output->clone_mask);
3261 crtc_mask = ((1 << 0)|
3262 (1 << 1));
3263 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3264 break;
3265 case INTEL_OUTPUT_DVO:
3266 case INTEL_OUTPUT_SDVO:
3267 crtc_mask = ((1 << 0)|
3268 (1 << 1));
3269 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3270 (1 << INTEL_OUTPUT_DVO) |
3271 (1 << INTEL_OUTPUT_SDVO));
3272 break;
3273 case INTEL_OUTPUT_ANALOG:
3274 crtc_mask = ((1 << 0)|
3275 (1 << 1));
3276 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3277 (1 << INTEL_OUTPUT_DVO) |
3278 (1 << INTEL_OUTPUT_SDVO));
3279 break;
3280 case INTEL_OUTPUT_LVDS:
3281 crtc_mask = (1 << 1);
3282 clone_mask = (1 << INTEL_OUTPUT_LVDS);
3283 break;
3284 case INTEL_OUTPUT_TVOUT:
3285 crtc_mask = ((1 << 0) |
3286 (1 << 1));
3287 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3288 break;
3289 case INTEL_OUTPUT_DISPLAYPORT:
3290 crtc_mask = ((1 << 0) |
3291 (1 << 1));
3292 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3293 break;
3294 case INTEL_OUTPUT_EDP:
3295 crtc_mask = (1 << 1);
3296 clone_mask = (1 << INTEL_OUTPUT_EDP);
3297 break;
3298 }
3299 encoder->possible_crtcs = crtc_mask;
3300 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3301 } 3274 }
3302} 3275}
3303 3276
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a6ff15ac548a..f2afc4af4bc9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1254,6 +1254,18 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1254 else 1254 else
1255 intel_output->type = INTEL_OUTPUT_DISPLAYPORT; 1255 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1256 1256
1257 if (output_reg == DP_B)
1258 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1259 else if (output_reg == DP_C)
1260 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1261 else if (output_reg == DP_D)
1262 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1263
1264 if (IS_eDP(intel_output)) {
1265 intel_output->crtc_mask = (1 << 1);
1266 intel_output->clone_mask = (1 << INTEL_OUTPUT_EDP);
1267 } else
1268 intel_output->crtc_mask = (1 << 0) | (1 << 1);
1257 connector->interlace_allowed = true; 1269 connector->interlace_allowed = true;
1258 connector->doublescan_allowed = 0; 1270 connector->doublescan_allowed = 0;
1259 1271
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6f92ea1b553..25aa6facc12d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -57,6 +57,24 @@
57#define INTEL_OUTPUT_DISPLAYPORT 7 57#define INTEL_OUTPUT_DISPLAYPORT 7
58#define INTEL_OUTPUT_EDP 8 58#define INTEL_OUTPUT_EDP 8
59 59
60/* Intel Pipe Clone Bit */
61#define INTEL_HDMIB_CLONE_BIT 1
62#define INTEL_HDMIC_CLONE_BIT 2
63#define INTEL_HDMID_CLONE_BIT 3
64#define INTEL_HDMIE_CLONE_BIT 4
65#define INTEL_HDMIF_CLONE_BIT 5
66#define INTEL_SDVO_NON_TV_CLONE_BIT 6
67#define INTEL_SDVO_TV_CLONE_BIT 7
68#define INTEL_SDVO_LVDS_CLONE_BIT 8
69#define INTEL_ANALOG_CLONE_BIT 9
70#define INTEL_TV_CLONE_BIT 10
71#define INTEL_DP_B_CLONE_BIT 11
72#define INTEL_DP_C_CLONE_BIT 12
73#define INTEL_DP_D_CLONE_BIT 13
74#define INTEL_LVDS_CLONE_BIT 14
75#define INTEL_DVO_TMDS_CLONE_BIT 15
76#define INTEL_DVO_LVDS_CLONE_BIT 16
77
60#define INTEL_DVO_CHIP_NONE 0 78#define INTEL_DVO_CHIP_NONE 0
61#define INTEL_DVO_CHIP_LVDS 1 79#define INTEL_DVO_CHIP_LVDS 1
62#define INTEL_DVO_CHIP_TMDS 2 80#define INTEL_DVO_CHIP_TMDS 2
@@ -86,6 +104,8 @@ struct intel_output {
86 bool needs_tv_clock; 104 bool needs_tv_clock;
87 void *dev_priv; 105 void *dev_priv;
88 void (*hot_plug)(struct intel_output *); 106 void (*hot_plug)(struct intel_output *);
107 int crtc_mask;
108 int clone_mask;
89}; 109};
90 110
91struct intel_crtc { 111struct intel_crtc {
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 13bff20930e8..a4d2606de778 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -435,14 +435,20 @@ void intel_dvo_init(struct drm_device *dev)
435 continue; 435 continue;
436 436
437 intel_output->type = INTEL_OUTPUT_DVO; 437 intel_output->type = INTEL_OUTPUT_DVO;
438 intel_output->crtc_mask = (1 << 0) | (1 << 1);
438 switch (dvo->type) { 439 switch (dvo->type) {
439 case INTEL_DVO_CHIP_TMDS: 440 case INTEL_DVO_CHIP_TMDS:
441 intel_output->clone_mask =
442 (1 << INTEL_DVO_TMDS_CLONE_BIT) |
443 (1 << INTEL_ANALOG_CLONE_BIT);
440 drm_connector_init(dev, connector, 444 drm_connector_init(dev, connector,
441 &intel_dvo_connector_funcs, 445 &intel_dvo_connector_funcs,
442 DRM_MODE_CONNECTOR_DVII); 446 DRM_MODE_CONNECTOR_DVII);
443 encoder_type = DRM_MODE_ENCODER_TMDS; 447 encoder_type = DRM_MODE_ENCODER_TMDS;
444 break; 448 break;
445 case INTEL_DVO_CHIP_LVDS: 449 case INTEL_DVO_CHIP_LVDS:
450 intel_output->clone_mask =
451 (1 << INTEL_DVO_LVDS_CLONE_BIT);
446 drm_connector_init(dev, connector, 452 drm_connector_init(dev, connector,
447 &intel_dvo_connector_funcs, 453 &intel_dvo_connector_funcs,
448 DRM_MODE_CONNECTOR_LVDS); 454 DRM_MODE_CONNECTOR_LVDS);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1842290cded3..fa304e136010 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -230,22 +230,28 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
230 230
231 connector->interlace_allowed = 0; 231 connector->interlace_allowed = 0;
232 connector->doublescan_allowed = 0; 232 connector->doublescan_allowed = 0;
233 intel_output->crtc_mask = (1 << 0) | (1 << 1);
233 234
234 /* Set up the DDC bus. */ 235 /* Set up the DDC bus. */
235 if (sdvox_reg == SDVOB) 236 if (sdvox_reg == SDVOB) {
237 intel_output->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
236 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); 238 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB");
237 else if (sdvox_reg == SDVOC) 239 } else if (sdvox_reg == SDVOC) {
240 intel_output->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
238 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); 241 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC");
239 else if (sdvox_reg == HDMIB) 242 } else if (sdvox_reg == HDMIB) {
243 intel_output->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
240 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE, 244 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE,
241 "HDMIB"); 245 "HDMIB");
242 else if (sdvox_reg == HDMIC) 246 } else if (sdvox_reg == HDMIC) {
247 intel_output->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
243 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD, 248 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD,
244 "HDMIC"); 249 "HDMIC");
245 else if (sdvox_reg == HDMID) 250 } else if (sdvox_reg == HDMID) {
251 intel_output->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
246 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF, 252 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF,
247 "HDMID"); 253 "HDMID");
248 254 }
249 if (!intel_output->ddc_bus) 255 if (!intel_output->ddc_bus)
250 goto err_connector; 256 goto err_connector;
251 257
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 3f445a80c552..8df02ef89261 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -916,6 +916,8 @@ void intel_lvds_init(struct drm_device *dev)
916 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 916 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
917 intel_output->type = INTEL_OUTPUT_LVDS; 917 intel_output->type = INTEL_OUTPUT_LVDS;
918 918
919 intel_output->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
920 intel_output->crtc_mask = (1 << 1);
919 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); 921 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
920 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 922 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
921 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 923 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 5371d9332554..d3b74ba62b4a 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1458,7 +1458,7 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1458 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) 1458 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1459 caps++; 1459 caps++;
1460 if (sdvo_priv->caps.output_flags & 1460 if (sdvo_priv->caps.output_flags &
1461 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID0)) 1461 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1462 caps++; 1462 caps++;
1463 if (sdvo_priv->caps.output_flags & 1463 if (sdvo_priv->caps.output_flags &
1464 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) 1464 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
@@ -1967,6 +1967,9 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1967 intel_sdvo_set_colorimetry(intel_output, 1967 intel_sdvo_set_colorimetry(intel_output,
1968 SDVO_COLORIMETRY_RGB256); 1968 SDVO_COLORIMETRY_RGB256);
1969 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 1969 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
1970 intel_output->clone_mask =
1971 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
1972 (1 << INTEL_ANALOG_CLONE_BIT);
1970 } 1973 }
1971 } else if (flags & SDVO_OUTPUT_SVID0) { 1974 } else if (flags & SDVO_OUTPUT_SVID0) {
1972 1975
@@ -1975,11 +1978,14 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1975 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 1978 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1976 sdvo_priv->is_tv = true; 1979 sdvo_priv->is_tv = true;
1977 intel_output->needs_tv_clock = true; 1980 intel_output->needs_tv_clock = true;
1981 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
1978 } else if (flags & SDVO_OUTPUT_RGB0) { 1982 } else if (flags & SDVO_OUTPUT_RGB0) {
1979 1983
1980 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0; 1984 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1981 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 1985 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1982 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 1986 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1987 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
1988 (1 << INTEL_ANALOG_CLONE_BIT);
1983 } else if (flags & SDVO_OUTPUT_RGB1) { 1989 } else if (flags & SDVO_OUTPUT_RGB1) {
1984 1990
1985 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1; 1991 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
@@ -1991,12 +1997,16 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1991 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 1997 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1992 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 1998 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1993 sdvo_priv->is_lvds = true; 1999 sdvo_priv->is_lvds = true;
2000 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2001 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
1994 } else if (flags & SDVO_OUTPUT_LVDS1) { 2002 } else if (flags & SDVO_OUTPUT_LVDS1) {
1995 2003
1996 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1; 2004 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1997 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2005 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1998 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2006 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1999 sdvo_priv->is_lvds = true; 2007 sdvo_priv->is_lvds = true;
2008 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2009 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2000 } else { 2010 } else {
2001 2011
2002 unsigned char bytes[2]; 2012 unsigned char bytes[2];
@@ -2009,6 +2019,7 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2009 bytes[0], bytes[1]); 2019 bytes[0], bytes[1]);
2010 ret = false; 2020 ret = false;
2011 } 2021 }
2022 intel_output->crtc_mask = (1 << 0) | (1 << 1);
2012 2023
2013 if (ret && registered) 2024 if (ret && registered)
2014 ret = drm_sysfs_connector_add(connector) == 0 ? true : false; 2025 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index da4ab4dc1630..2fbe13a0de81 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1718,6 +1718,7 @@ intel_tv_init(struct drm_device *dev)
1718 if (!intel_output) { 1718 if (!intel_output) {
1719 return; 1719 return;
1720 } 1720 }
1721
1721 connector = &intel_output->base; 1722 connector = &intel_output->base;
1722 1723
1723 drm_connector_init(dev, connector, &intel_tv_connector_funcs, 1724 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
@@ -1729,6 +1730,7 @@ intel_tv_init(struct drm_device *dev)
1729 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 1730 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1730 tv_priv = (struct intel_tv_priv *)(intel_output + 1); 1731 tv_priv = (struct intel_tv_priv *)(intel_output + 1);
1731 intel_output->type = INTEL_OUTPUT_TVOUT; 1732 intel_output->type = INTEL_OUTPUT_TVOUT;
1733 intel_output->clone_mask = (1 << INTEL_TV_CLONE_BIT);
1732 intel_output->enc.possible_crtcs = ((1 << 0) | (1 << 1)); 1734 intel_output->enc.possible_crtcs = ((1 << 0) | (1 << 1));
1733 intel_output->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT); 1735 intel_output->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1734 intel_output->dev_priv = tv_priv; 1736 intel_output->dev_priv = tv_priv;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 053f4ec397f7..051bca6e3a4f 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -995,7 +995,7 @@ static const unsigned r300_reg_safe_bm[159] = {
995 0x00000000, 0x00000000, 0x00000000, 0x00000000, 995 0x00000000, 0x00000000, 0x00000000, 0x00000000,
996 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF, 996 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 997 0x00000000, 0x00000000, 0x00000000, 0x00000000,
998 0x0003FC01, 0xFFFFFFF8, 0xFE800B19, 998 0x0003FC01, 0xFFFFFCF8, 0xFF800B19,
999}; 999};
1000 1000
1001static int r300_packet0_check(struct radeon_cs_parser *p, 1001static int r300_packet0_check(struct radeon_cs_parser *p,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 7ca6c13569b5..93d8f8889302 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -266,6 +266,7 @@ static struct radeon_asic rs400_asic = {
266/* 266/*
267 * rs600. 267 * rs600.
268 */ 268 */
269int rs600_init(struct radeon_device *dev);
269void rs600_errata(struct radeon_device *rdev); 270void rs600_errata(struct radeon_device *rdev);
270void rs600_vram_info(struct radeon_device *rdev); 271void rs600_vram_info(struct radeon_device *rdev);
271int rs600_mc_init(struct radeon_device *rdev); 272int rs600_mc_init(struct radeon_device *rdev);
@@ -281,7 +282,7 @@ uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
281void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 282void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
282void rs600_bandwidth_update(struct radeon_device *rdev); 283void rs600_bandwidth_update(struct radeon_device *rdev);
283static struct radeon_asic rs600_asic = { 284static struct radeon_asic rs600_asic = {
284 .init = &r300_init, 285 .init = &rs600_init,
285 .errata = &rs600_errata, 286 .errata = &rs600_errata,
286 .vram_info = &rs600_vram_info, 287 .vram_info = &rs600_vram_info,
287 .gpu_reset = &r300_gpu_reset, 288 .gpu_reset = &r300_gpu_reset,
@@ -316,7 +317,6 @@ static struct radeon_asic rs600_asic = {
316/* 317/*
317 * rs690,rs740 318 * rs690,rs740
318 */ 319 */
319int rs690_init(struct radeon_device *rdev);
320void rs690_errata(struct radeon_device *rdev); 320void rs690_errata(struct radeon_device *rdev);
321void rs690_vram_info(struct radeon_device *rdev); 321void rs690_vram_info(struct radeon_device *rdev);
322int rs690_mc_init(struct radeon_device *rdev); 322int rs690_mc_init(struct radeon_device *rdev);
@@ -325,7 +325,7 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
325void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 325void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
326void rs690_bandwidth_update(struct radeon_device *rdev); 326void rs690_bandwidth_update(struct radeon_device *rdev);
327static struct radeon_asic rs690_asic = { 327static struct radeon_asic rs690_asic = {
328 .init = &rs690_init, 328 .init = &rs600_init,
329 .errata = &rs690_errata, 329 .errata = &rs690_errata,
330 .vram_info = &rs690_vram_info, 330 .vram_info = &rs690_vram_info,
331 .gpu_reset = &r300_gpu_reset, 331 .gpu_reset = &r300_gpu_reset,
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 14c199802920..d880edf254db 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -274,12 +274,18 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
274 } 274 }
275 robj = gobj->driver_private; 275 robj = gobj->driver_private;
276 r = radeon_object_busy_domain(robj, &cur_placement); 276 r = radeon_object_busy_domain(robj, &cur_placement);
277 if (cur_placement == TTM_PL_VRAM) 277 switch (cur_placement) {
278 case TTM_PL_VRAM:
278 args->domain = RADEON_GEM_DOMAIN_VRAM; 279 args->domain = RADEON_GEM_DOMAIN_VRAM;
279 if (cur_placement == TTM_PL_FLAG_TT) 280 break;
281 case TTM_PL_TT:
280 args->domain = RADEON_GEM_DOMAIN_GTT; 282 args->domain = RADEON_GEM_DOMAIN_GTT;
281 if (cur_placement == TTM_PL_FLAG_SYSTEM) 283 break;
284 case TTM_PL_SYSTEM:
282 args->domain = RADEON_GEM_DOMAIN_CPU; 285 args->domain = RADEON_GEM_DOMAIN_CPU;
286 default:
287 break;
288 }
283 mutex_lock(&dev->struct_mutex); 289 mutex_lock(&dev->struct_mutex);
284 drm_gem_object_unreference(gobj); 290 drm_gem_object_unreference(gobj);
285 mutex_unlock(&dev->struct_mutex); 291 mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 7e8ce983a908..02fd11aad6a2 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -409,3 +409,68 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
409 ((reg) & RS600_MC_ADDR_MASK)); 409 ((reg) & RS600_MC_ADDR_MASK));
410 WREG32(RS600_MC_DATA, v); 410 WREG32(RS600_MC_DATA, v);
411} 411}
412
413static const unsigned rs600_reg_safe_bm[219] = {
414 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
415 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
416 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
417 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
418 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
419 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
420 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
421 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
422 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
423 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
424 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
425 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
426 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
427 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
428 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
429 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
430 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
431 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
432 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
433 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
434 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
435 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
436 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
437 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
438 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
439 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
440 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
441 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
442 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
443 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
444 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
445 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
446 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
447 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
448 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
449 0x00000000, 0x0000C100, 0x00000000, 0x00000000,
450 0x00000000, 0x00000000, 0x00000000, 0x00000000,
451 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
452 0x00000000, 0x00000000, 0x00000000, 0x00000000,
453 0x0003FC01, 0xFFFFFCF8, 0xFF800B19, 0xFFFFFFFF,
454 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
455 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
456 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
457 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
458 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
459 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
460 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
461 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
462 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
463 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
464 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
465 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
466 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
467 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
468 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
469};
470
471int rs600_init(struct radeon_device *rdev)
472{
473 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
474 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
475 return 0;
476}
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index bc6b7c5339bc..879882533e45 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -653,67 +653,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
653 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 653 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
654} 654}
655 655
656static const unsigned rs690_reg_safe_bm[219] = {
657 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
658 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
659 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
660 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
661 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
662 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
663 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
664 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
665 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
666 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
667 0x17FF1FFF,0xFFFFFFFC,0xFFFFFFFF,0xFF30FFBF,
668 0xFFFFFFF8,0xC3E6FFFF,0xFFFFF6DF,0xFFFFFFFF,
669 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
670 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
671 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFF03F,
672 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
673 0xFFFFFFFF,0xFFFFEFCE,0xF00EBFFF,0x007C0000,
674 0xF0000078,0xFF000009,0xFFFFFFFF,0xFFFFFFFF,
675 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
676 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
677 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
678 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
679 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
680 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
681 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
682 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
683 0xFFFFF7FF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
684 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
685 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
686 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
687 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
688 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
689 0xFFFFFC78,0xFFFFFFFF,0xFFFFFFFE,0xFFFFFFFF,
690 0x38FF8F50,0xFFF88082,0xF000000C,0xFAE009FF,
691 0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000,
692 0x00000000,0x0000C100,0x00000000,0x00000000,
693 0x00000000,0x00000000,0x00000000,0x00000000,
694 0x00000000,0xFFFF0000,0xFFFFFFFF,0xFF80FFFF,
695 0x00000000,0x00000000,0x00000000,0x00000000,
696 0x0003FC01,0xFFFFFFF8,0xFE800B19,0xFFFFFFFF,
697 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
698 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
699 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
700 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
701 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
702 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
703 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
704 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
705 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
706 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
707 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
708 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
709 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
710 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
711 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
712};
713
714int rs690_init(struct radeon_device *rdev)
715{
716 rdev->config.r300.reg_safe_bm = rs690_reg_safe_bm;
717 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs690_reg_safe_bm);
718 return 0;
719}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 31a7f668ae5a..0566fb67e460 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -508,7 +508,7 @@ static const unsigned r500_reg_safe_bm[219] = {
508 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 508 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
509 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, 509 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
510 0x00000000, 0x00000000, 0x00000000, 0x00000000, 510 0x00000000, 0x00000000, 0x00000000, 0x00000000,
511 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF, 511 0x0003FC01, 0x3FFFFCF8, 0xFF800B19, 0xFFDFFFFF,
512 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 512 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
513 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 513 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
514 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 514 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 00:38:33 -0500