129 files changed, 7169 insertions, 3064 deletions

diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index e8605bf738b3..d8e398275ca8 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -894,7 +894,7 @@ static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
  * and a mode_set.
  */
 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
-        struct drm_framebuffer *fb, struct drm_pending_vblank_event *event)
+        struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
 {
         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
         struct armada_frame_work *work;
diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c
index 7aede900a221..4f2b28354915 100644
--- a/drivers/gpu/drm/armada/armada_drv.c
+++ b/drivers/gpu/drm/armada/armada_drv.c
@@ -349,7 +349,6 @@ static struct drm_driver armada_drm_driver = {
         .debugfs_init           = armada_drm_debugfs_init,
         .debugfs_cleanup        = armada_drm_debugfs_cleanup,
 #endif
-        .gem_init_object        = NULL,
         .gem_free_object        = armada_gem_free_object,
         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
index 32e270dc714e..5137f15dba19 100644
--- a/drivers/gpu/drm/ast/ast_drv.c
+++ b/drivers/gpu/drm/ast/ast_drv.c
@@ -211,7 +211,6 @@ static struct drm_driver driver = {
         .minor = DRIVER_MINOR,
         .patchlevel = DRIVER_PATCHLEVEL,
 
-        .gem_init_object = ast_gem_init_object,
         .gem_free_object = ast_gem_free_object,
         .dumb_create = ast_dumb_create,
         .dumb_map_offset = ast_dumb_mmap_offset,
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index 8492b68e873c..9833a1b1acc1 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -323,7 +323,6 @@ extern int ast_dumb_create(struct drm_file *file,
                            struct drm_device *dev,
                            struct drm_mode_create_dumb *args);
 
-extern int ast_gem_init_object(struct drm_gem_object *obj);
 extern void ast_gem_free_object(struct drm_gem_object *obj);
 extern int ast_dumb_mmap_offset(struct drm_file *file,
                                 struct drm_device *dev,
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 7f6152d374ca..af0b868a9dfd 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -449,12 +449,6 @@ int ast_dumb_create(struct drm_file *file,
         return 0;
 }
 
-int ast_gem_init_object(struct drm_gem_object *obj)
-{
-        BUG();
-        return 0;
-}
-
 void ast_bo_unref(struct ast_bo **bo)
 {
         struct ttm_buffer_object *tbo;
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c b/drivers/gpu/drm/cirrus/cirrus_drv.c
index 138364d91782..953fc8aea69c 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.c
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.c
@@ -97,7 +97,6 @@ static struct drm_driver driver = {
         .major = DRIVER_MAJOR,
         .minor = DRIVER_MINOR,
         .patchlevel = DRIVER_PATCHLEVEL,
-        .gem_init_object = cirrus_gem_init_object,
         .gem_free_object = cirrus_gem_free_object,
         .dumb_create = cirrus_dumb_create,
         .dumb_map_offset = cirrus_dumb_mmap_offset,
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.h b/drivers/gpu/drm/cirrus/cirrus_drv.h
index 9b0bb9184afd..b6aded73838b 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.h
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.h
@@ -191,7 +191,6 @@ int cirrus_device_init(struct cirrus_device *cdev,
                       struct pci_dev *pdev,
                       uint32_t flags);
 void cirrus_device_fini(struct cirrus_device *cdev);
-int cirrus_gem_init_object(struct drm_gem_object *obj);
 void cirrus_gem_free_object(struct drm_gem_object *obj);
 int cirrus_dumb_mmap_offset(struct drm_file *file,
                             struct drm_device *dev,
diff --git a/drivers/gpu/drm/cirrus/cirrus_main.c b/drivers/gpu/drm/cirrus/cirrus_main.c
index f130a533a512..78e76f24343d 100644
--- a/drivers/gpu/drm/cirrus/cirrus_main.c
+++ b/drivers/gpu/drm/cirrus/cirrus_main.c
@@ -255,12 +255,6 @@ int cirrus_dumb_create(struct drm_file *file,
         return 0;
 }
 
-int cirrus_gem_init_object(struct drm_gem_object *obj)
-{
-        BUG();
-        return 0;
-}
-
 void cirrus_bo_unref(struct cirrus_bo **bo)
 {
         struct ttm_buffer_object *tbo;
diff --git a/drivers/gpu/drm/drm_context.c b/drivers/gpu/drm/drm_context.c
index 224ff965bcf7..a4b017b6849e 100644
--- a/drivers/gpu/drm/drm_context.c
+++ b/drivers/gpu/drm/drm_context.c
@@ -334,7 +334,6 @@ int drm_addctx(struct drm_device *dev, void *data,
 
         mutex_lock(&dev->ctxlist_mutex);
         list_add(&ctx_entry->head, &dev->ctxlist);
-        ++dev->ctx_count;
         mutex_unlock(&dev->ctxlist_mutex);
 
         return 0;
@@ -432,7 +431,6 @@ int drm_rmctx(struct drm_device *dev, void *data,
                         if (pos->handle == ctx->handle) {
                                 list_del(&pos->head);
                                 kfree(pos);
-                                --dev->ctx_count;
                         }
                 }
         }
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index bff2fa941f60..d7a8370e3cdc 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -202,6 +202,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
         { DRM_MODE_CONNECTOR_TV, "TV" },
         { DRM_MODE_CONNECTOR_eDP, "eDP" },
         { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" },
+        { DRM_MODE_CONNECTOR_DSI, "DSI" },
 };
 
 static const struct drm_prop_enum_list drm_encoder_enum_list[] =
@@ -211,6 +212,7 @@ static const struct drm_prop_enum_list drm_encoder_enum_list[] =
         { DRM_MODE_ENCODER_LVDS, "LVDS" },
         { DRM_MODE_ENCODER_TVDAC, "TV" },
         { DRM_MODE_ENCODER_VIRTUAL, "Virtual" },
+        { DRM_MODE_ENCODER_DSI, "DSI" },
 };
 
 void drm_connector_ida_init(void)
@@ -1317,6 +1319,9 @@ static int drm_crtc_convert_umode(struct drm_display_mode *out,
         if (in->clock > INT_MAX || in->vrefresh > INT_MAX)
                 return -ERANGE;
 
+        if ((in->flags & DRM_MODE_FLAG_3D_MASK) > DRM_MODE_FLAG_3D_MAX)
+                return -EINVAL;
+
         out->clock = in->clock;
         out->hdisplay = in->hdisplay;
         out->hsync_start = in->hsync_start;
@@ -1579,6 +1584,19 @@ out:
         return ret;
 }
 
+static bool drm_mode_expose_to_userspace(const struct drm_display_mode *mode,
+                                         const struct drm_file *file_priv)
+{
+        /*
+         * If user-space hasn't configured the driver to expose the stereo 3D
+         * modes, don't expose them.
+         */
+        if (!file_priv->stereo_allowed && drm_mode_is_stereo(mode))
+                return false;
+
+        return true;
+}
+
 /**
  * drm_mode_getconnector - get connector configuration
  * @dev: drm device for the ioctl
@@ -1644,7 +1662,8 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
 
         /* delayed so we get modes regardless of pre-fill_modes state */
         list_for_each_entry(mode, &connector->modes, head)
-                mode_count++;
+                if (drm_mode_expose_to_userspace(mode, file_priv))
+                        mode_count++;
 
         out_resp->connector_id = connector->base.id;
         out_resp->connector_type = connector->connector_type;
@@ -1666,6 +1685,9 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
                 copied = 0;
                 mode_ptr = (struct drm_mode_modeinfo __user *)(unsigned long)out_resp->modes_ptr;
                 list_for_each_entry(mode, &connector->modes, head) {
+                        if (!drm_mode_expose_to_userspace(mode, file_priv))
+                                continue;
+
                         drm_crtc_convert_to_umode(&u_mode, mode);
                         if (copy_to_user(mode_ptr + copied,
                                          &u_mode, sizeof(u_mode))) {
@@ -2040,6 +2062,45 @@ int drm_mode_set_config_internal(struct drm_mode_set *set)
 }
 EXPORT_SYMBOL(drm_mode_set_config_internal);
 
+/*
+ * Checks that the framebuffer is big enough for the CRTC viewport
+ * (x, y, hdisplay, vdisplay)
+ */
+static int drm_crtc_check_viewport(const struct drm_crtc *crtc,
+                                   int x, int y,
+                                   const struct drm_display_mode *mode,
+                                   const struct drm_framebuffer *fb)
+
+{
+        int hdisplay, vdisplay;
+
+        hdisplay = mode->hdisplay;
+        vdisplay = mode->vdisplay;
+
+        if (drm_mode_is_stereo(mode)) {
+                struct drm_display_mode adjusted = *mode;
+
+                drm_mode_set_crtcinfo(&adjusted, CRTC_STEREO_DOUBLE);
+                hdisplay = adjusted.crtc_hdisplay;
+                vdisplay = adjusted.crtc_vdisplay;
+        }
+
+        if (crtc->invert_dimensions)
+                swap(hdisplay, vdisplay);
+
+        if (hdisplay > fb->width ||
+            vdisplay > fb->height ||
+            x > fb->width - hdisplay ||
+            y > fb->height - vdisplay) {
+                DRM_DEBUG_KMS("Invalid fb size %ux%u for CRTC viewport %ux%u+%d+%d%s.\n",
+                              fb->width, fb->height, hdisplay, vdisplay, x, y,
+                              crtc->invert_dimensions ? " (inverted)" : "");
+                return -ENOSPC;
+        }
+
+        return 0;
+}
+
 /**
  * drm_mode_setcrtc - set CRTC configuration
  * @dev: drm device for the ioctl
@@ -2087,7 +2148,6 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
 
         if (crtc_req->mode_valid) {
-                int hdisplay, vdisplay;
                 /* If we have a mode we need a framebuffer. */
                 /* If we pass -1, set the mode with the currently bound fb */
                 if (crtc_req->fb_id == -1) {
@@ -2123,23 +2183,11 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 
                 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
 
-                hdisplay = mode->hdisplay;
-                vdisplay = mode->vdisplay;
-
-                if (crtc->invert_dimensions)
-                        swap(hdisplay, vdisplay);
-
-                if (hdisplay > fb->width ||
-                    vdisplay > fb->height ||
-                    crtc_req->x > fb->width - hdisplay ||
-                    crtc_req->y > fb->height - vdisplay) {
-                        DRM_DEBUG_KMS("Invalid fb size %ux%u for CRTC viewport %ux%u+%d+%d%s.\n",
-                                      fb->width, fb->height,
-                                      hdisplay, vdisplay, crtc_req->x, crtc_req->y,
-                                      crtc->invert_dimensions ? " (inverted)" : "");
-                        ret = -ENOSPC;
+                ret = drm_crtc_check_viewport(crtc, crtc_req->x, crtc_req->y,
+                                              mode, fb);
+                if (ret)
                         goto out;
-                }
+
         }
 
         if (crtc_req->count_connectors == 0 && mode) {
@@ -3556,7 +3604,6 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
         struct drm_framebuffer *fb = NULL, *old_fb = NULL;
         struct drm_pending_vblank_event *e = NULL;
         unsigned long flags;
-        int hdisplay, vdisplay;
         int ret = -EINVAL;
 
         if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
@@ -3588,22 +3635,9 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
         if (!fb)
                 goto out;
 
-        hdisplay = crtc->mode.hdisplay;
-        vdisplay = crtc->mode.vdisplay;
-
-        if (crtc->invert_dimensions)
-                swap(hdisplay, vdisplay);
-
-        if (hdisplay > fb->width ||
-            vdisplay > fb->height ||
-            crtc->x > fb->width - hdisplay ||
-            crtc->y > fb->height - vdisplay) {
-                DRM_DEBUG_KMS("Invalid fb size %ux%u for CRTC viewport %ux%u+%d+%d%s.\n",
-                              fb->width, fb->height, hdisplay, vdisplay, crtc->x, crtc->y,
-                              crtc->invert_dimensions ? " (inverted)" : "");
-                ret = -ENOSPC;
+        ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y, &crtc->mode, fb);
+        if (ret)
                 goto out;
-        }
 
         if (crtc->fb->pixel_format != fb->pixel_format) {
                 DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index c722c3b5404d..5fcb9d487672 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -76,7 +76,8 @@ static void drm_mode_validate_flag(struct drm_connector *connector,
 {
         struct drm_display_mode *mode;
 
-        if (flags == (DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_INTERLACE))
+        if (flags == (DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_INTERLACE |
+                      DRM_MODE_FLAG_3D_MASK))
                 return;
 
         list_for_each_entry(mode, &connector->modes, head) {
@@ -86,6 +87,9 @@ static void drm_mode_validate_flag(struct drm_connector *connector,
                 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) &&
                                 !(flags & DRM_MODE_FLAG_DBLSCAN))
                         mode->status = MODE_NO_DBLESCAN;
+                if ((mode->flags & DRM_MODE_FLAG_3D_MASK) &&
+                                !(flags & DRM_MODE_FLAG_3D_MASK))
+                        mode->status = MODE_NO_STEREO;
         }
 
         return;
@@ -105,9 +109,9 @@ static void drm_mode_validate_flag(struct drm_connector *connector,
  * then culled (based on validity and the @maxX, @maxY parameters) and put into
  * the normal modes list.
  *
- * Intended to be use as a generic implementation of the ->probe() @connector
- * callback for drivers that use the crtc helpers for output mode filtering and
- * detection.
+ * Intended to be use as a generic implementation of the ->fill_modes()
+ * @connector vfunc for drivers that use the crtc helpers for output mode
+ * filtering and detection.
  *
  * RETURNS:
  * Number of modes found on @connector.
@@ -175,6 +179,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
                 mode_flags |= DRM_MODE_FLAG_INTERLACE;
         if (connector->doublescan_allowed)
                 mode_flags |= DRM_MODE_FLAG_DBLSCAN;
+        if (connector->stereo_allowed)
+                mode_flags |= DRM_MODE_FLAG_3D_MASK;
         drm_mode_validate_flag(connector, mode_flags);
 
         list_for_each_entry(mode, &connector->modes, head) {
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 89e196627160..9e978aae8972 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -228,12 +228,12 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
 EXPORT_SYMBOL(i2c_dp_aux_add_bus);
 
 /* Helpers for DP link training */
-static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
+static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
 {
         return link_status[r - DP_LANE0_1_STATUS];
 }
 
-static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
+static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
                              int lane)
 {
         int i = DP_LANE0_1_STATUS + (lane >> 1);
@@ -242,7 +242,7 @@ static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
         return (l >> s) & 0xf;
 }
 
-bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
+bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
                           int lane_count)
 {
         u8 lane_align;
@@ -262,7 +262,7 @@ bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
 
-bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
+bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
                               int lane_count)
 {
         int lane;
@@ -277,7 +277,7 @@ bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
 
-u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
+u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
                                      int lane)
 {
         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
@@ -290,7 +290,7 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
 
-u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
+u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
                                           int lane)
 {
         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
@@ -303,7 +303,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
 }
 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 
-void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
+void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
         if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
                 udelay(100);
         else
@@ -311,7 +311,7 @@ void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
 }
 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 
-void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
+void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
         if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
                 udelay(400);
         else
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index e572dd20bdee..b55f138bd990 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -69,6 +69,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
         DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED),
         DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, DRM_UNLOCKED),
         DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, 0),
         DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
 
         DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
@@ -170,76 +171,6 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
 
 #define DRM_CORE_IOCTL_COUNT    ARRAY_SIZE( drm_ioctls )
 
-/**
- * drm_legacy_dev_reinit
- *
- * Reinitializes a legacy/ums drm device in it's lastclose function.
- */
-static void drm_legacy_dev_reinit(struct drm_device *dev)
-{
-        int i;
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                return;
-
-        atomic_set(&dev->ioctl_count, 0);
-        atomic_set(&dev->vma_count, 0);
-
-        for (i = 0; i < ARRAY_SIZE(dev->counts); i++)
-                atomic_set(&dev->counts[i], 0);
-
-        dev->sigdata.lock = NULL;
-
-        dev->context_flag = 0;
-        dev->last_context = 0;
-        dev->if_version = 0;
-}
-
-/**
- * Take down the DRM device.
- *
- * \param dev DRM device structure.
- *
- * Frees every resource in \p dev.
- *
- * \sa drm_device
- */
-int drm_lastclose(struct drm_device * dev)
-{
-        struct drm_vma_entry *vma, *vma_temp;
-
-        DRM_DEBUG("\n");
-
-        if (dev->driver->lastclose)
-                dev->driver->lastclose(dev);
-        DRM_DEBUG("driver lastclose completed\n");
-
-        if (dev->irq_enabled && !drm_core_check_feature(dev, DRIVER_MODESET))
-                drm_irq_uninstall(dev);
-
-        mutex_lock(&dev->struct_mutex);
-
-        drm_agp_clear(dev);
-
-        drm_legacy_sg_cleanup(dev);
-
-        /* Clear vma list (only built for debugging) */
-        list_for_each_entry_safe(vma, vma_temp, &dev->vmalist, head) {
-                list_del(&vma->head);
-                kfree(vma);
-        }
-
-        drm_legacy_dma_takedown(dev);
-
-        dev->dev_mapping = NULL;
-        mutex_unlock(&dev->struct_mutex);
-
-        drm_legacy_dev_reinit(dev);
-
-        DRM_DEBUG("lastclose completed\n");
-        return 0;
-}
-
 /** File operations structure */
 static const struct file_operations drm_stub_fops = {
         .owner = THIS_MODULE,
@@ -385,7 +316,6 @@ long drm_ioctl(struct file *filp,
                 return -ENODEV;
 
         atomic_inc(&dev->ioctl_count);
-        atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
         ++file_priv->ioctl_count;
 
         if ((nr >= DRM_CORE_IOCTL_COUNT) &&
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1688ff500513..9e81609b1e29 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1264,6 +1264,18 @@ struct edid *drm_get_edid(struct drm_connector *connector,
 }
 EXPORT_SYMBOL(drm_get_edid);
 
+/**
+ * drm_edid_duplicate - duplicate an EDID and the extensions
+ * @edid: EDID to duplicate
+ *
+ * Return duplicate edid or NULL on allocation failure.
+ */
+struct edid *drm_edid_duplicate(const struct edid *edid)
+{
+        return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
+}
+EXPORT_SYMBOL(drm_edid_duplicate);
+
 /*** EDID parsing ***/
 
 /**
@@ -2404,7 +2416,7 @@ u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
 
                 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
                      KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
-                    drm_mode_equal_no_clocks(to_match, cea_mode))
+                    drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
                         return mode + 1;
         }
         return 0;
@@ -2453,7 +2465,7 @@ static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
 
                 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
                      KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
-                    drm_mode_equal_no_clocks(to_match, hdmi_mode))
+                    drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
                         return mode + 1;
         }
         return 0;
@@ -2507,6 +2519,9 @@ add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
                 if (!newmode)
                         continue;
 
+                /* Carry over the stereo flags */
+                newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
+
                 /*
                  * The current mode could be either variant. Make
                  * sure to pick the "other" clock for the new mode.
@@ -2553,18 +2568,102 @@ do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
         return modes;
 }
 
+struct stereo_mandatory_mode {
+        int width, height, vrefresh;
+        unsigned int flags;
+};
+
+static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
+        { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
+        { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
+        { 1920, 1080, 50,
+          DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
+        { 1920, 1080, 60,
+          DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
+        { 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
+        { 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
+        { 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
+        { 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
+};
+
+static bool
+stereo_match_mandatory(const struct drm_display_mode *mode,
+                       const struct stereo_mandatory_mode *stereo_mode)
+{
+        unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
+
+        return mode->hdisplay == stereo_mode->width &&
+               mode->vdisplay == stereo_mode->height &&
+               interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
+               drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
+}
+
+static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
+{
+        struct drm_device *dev = connector->dev;
+        const struct drm_display_mode *mode;
+        struct list_head stereo_modes;
+        int modes = 0, i;
+
+        INIT_LIST_HEAD(&stereo_modes);
+
+        list_for_each_entry(mode, &connector->probed_modes, head) {
+                for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
+                        const struct stereo_mandatory_mode *mandatory;
+                        struct drm_display_mode *new_mode;
+
+                        if (!stereo_match_mandatory(mode,
+                                                    &stereo_mandatory_modes[i]))
+                                continue;
+
+                        mandatory = &stereo_mandatory_modes[i];
+                        new_mode = drm_mode_duplicate(dev, mode);
+                        if (!new_mode)
+                                continue;
+
+                        new_mode->flags |= mandatory->flags;
+                        list_add_tail(&new_mode->head, &stereo_modes);
+                        modes++;
+                }
+        }
+
+        list_splice_tail(&stereo_modes, &connector->probed_modes);
+
+        return modes;
+}
+
+static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
+{
+        struct drm_device *dev = connector->dev;
+        struct drm_display_mode *newmode;
+
+        vic--; /* VICs start at 1 */
+        if (vic >= ARRAY_SIZE(edid_4k_modes)) {
+                DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
+                return 0;
+        }
+
+        newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
+        if (!newmode)
+                return 0;
+
+        drm_mode_probed_add(connector, newmode);
+
+        return 1;
+}
+
 /*
  * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
  * @connector: connector corresponding to the HDMI sink
  * @db: start of the CEA vendor specific block
  * @len: length of the CEA block payload, ie. one can access up to db[len]
  *
- * Parses the HDMI VSDB looking for modes to add to @connector.
+ * Parses the HDMI VSDB looking for modes to add to @connector. This function
+ * also adds the stereo 3d modes when applicable.
  */
 static int
 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
 {
-        struct drm_device *dev = connector->dev;
         int modes = 0, offset = 0, i;
         u8 vic_len;
 
@@ -2585,30 +2684,22 @@ do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
 
         /* the declared length is not long enough for the 2 first bytes
          * of additional video format capabilities */
-        offset += 2;
-        if (len < (8 + offset))
+        if (len < (8 + offset + 2))
                 goto out;
 
+        /* 3D_Present */
+        offset++;
+        if (db[8 + offset] & (1 << 7))
+                modes += add_hdmi_mandatory_stereo_modes(connector);
+
+        offset++;
         vic_len = db[8 + offset] >> 5;
 
         for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
-                struct drm_display_mode *newmode;
                 u8 vic;
 
                 vic = db[9 + offset + i];
-
-                vic--; /* VICs start at 1 */
-                if (vic >= ARRAY_SIZE(edid_4k_modes)) {
-                        DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
-                        continue;
-                }
-
-                newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
-                if (!newmode)
-                        continue;
-
-                drm_mode_probed_add(connector, newmode);
-                modes++;
+                modes += add_hdmi_mode(connector, vic);
         }
 
 out:
@@ -2668,8 +2759,8 @@ static int
 add_cea_modes(struct drm_connector *connector, struct edid *edid)
 {
         const u8 *cea = drm_find_cea_extension(edid);
-        const u8 *db;
-        u8 dbl;
+        const u8 *db, *hdmi = NULL;
+        u8 dbl, hdmi_len;
         int modes = 0;
 
         if (cea && cea_revision(cea) >= 3) {
@@ -2684,11 +2775,20 @@ add_cea_modes(struct drm_connector *connector, struct edid *edid)
 
                         if (cea_db_tag(db) == VIDEO_BLOCK)
                                 modes += do_cea_modes(connector, db + 1, dbl);
-                        else if (cea_db_is_hdmi_vsdb(db))
-                                modes += do_hdmi_vsdb_modes(connector, db, dbl);
+                        else if (cea_db_is_hdmi_vsdb(db)) {
+                                hdmi = db;
+                                hdmi_len = dbl;
+                        }
                 }
         }
 
+        /*
+         * We parse the HDMI VSDB after having added the cea modes as we will
+         * be patching their flags when the sink supports stereo 3D.
+         */
+        if (hdmi)
+                modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len);
+
         return modes;
 }
 
@@ -2925,6 +3025,8 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
                         /* Speaker Allocation Data Block */
                         if (dbl == 3) {
                                 *sadb = kmalloc(dbl, GFP_KERNEL);
+                                if (!*sadb)
+                                        return -ENOMEM;
                                 memcpy(*sadb, &db[1], dbl);
                                 count = dbl;
                                 break;
@@ -3319,6 +3421,33 @@ drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
 }
 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
 
+static enum hdmi_3d_structure
+s3d_structure_from_display_mode(const struct drm_display_mode *mode)
+{
+        u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
+
+        switch (layout) {
+        case DRM_MODE_FLAG_3D_FRAME_PACKING:
+                return HDMI_3D_STRUCTURE_FRAME_PACKING;
+        case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
+                return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
+        case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
+                return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
+        case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
+                return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
+        case DRM_MODE_FLAG_3D_L_DEPTH:
+                return HDMI_3D_STRUCTURE_L_DEPTH;
+        case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
+                return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
+        case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
+                return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
+        case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
+                return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
+        default:
+                return HDMI_3D_STRUCTURE_INVALID;
+        }
+}
+
 /**
  * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
  * data from a DRM display mode
@@ -3336,20 +3465,29 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
                                             const struct drm_display_mode *mode)
 {
         int err;
+        u32 s3d_flags;
         u8 vic;
 
         if (!frame || !mode)
                 return -EINVAL;
 
         vic = drm_match_hdmi_mode(mode);
-        if (!vic)
+        s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
+
+        if (!vic && !s3d_flags)
+                return -EINVAL;
+
+        if (vic && s3d_flags)
                 return -EINVAL;
 
         err = hdmi_vendor_infoframe_init(frame);
         if (err < 0)
                 return err;
 
-        frame->vic = vic;
+        if (vic)
+                frame->vic = vic;
+        else
+                frame->s3d_struct = s3d_structure_from_display_mode(mode);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
index 271b42bbfb72..9081172ef057 100644
--- a/drivers/gpu/drm/drm_edid_load.c
+++ b/drivers/gpu/drm/drm_edid_load.c
@@ -32,7 +32,7 @@ MODULE_PARM_DESC(edid_firmware, "Do not probe monitor, use specified EDID blob "
         "from built-in data or /lib/firmware instead. ");
 
 #define GENERIC_EDIDS 5
-static char *generic_edid_name[GENERIC_EDIDS] = {
+static const char *generic_edid_name[GENERIC_EDIDS] = {
         "edid/1024x768.bin",
         "edid/1280x1024.bin",
         "edid/1600x1200.bin",
@@ -40,7 +40,7 @@ static char *generic_edid_name[GENERIC_EDIDS] = {
         "edid/1920x1080.bin",
 };
 
-static u8 generic_edid[GENERIC_EDIDS][128] = {
+static const u8 generic_edid[GENERIC_EDIDS][128] = {
         {
         0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
         0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -133,63 +133,68 @@ static u8 generic_edid[GENERIC_EDIDS][128] = {
         },
 };
 
+static int edid_size(const u8 *edid, int data_size)
+{
+        if (data_size < EDID_LENGTH)
+                return 0;
+
+        return (edid[0x7e] + 1) * EDID_LENGTH;
+}
+
 static u8 *edid_load(struct drm_connector *connector, const char *name,
                         const char *connector_name)
 {
-        const struct firmware *fw;
-        struct platform_device *pdev;
-        u8 *fwdata = NULL, *edid, *new_edid;
-        int fwsize, expected;
-        int builtin = 0, err = 0;
+        const struct firmware *fw = NULL;
+        const u8 *fwdata;
+        u8 *edid;
+        int fwsize, builtin;
         int i, valid_extensions = 0;
         bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
 
-        pdev = platform_device_register_simple(connector_name, -1, NULL, 0);
-        if (IS_ERR(pdev)) {
-                DRM_ERROR("Failed to register EDID firmware platform device "
-                    "for connector \"%s\"\n", connector_name);
-                err = -EINVAL;
-                goto out;
-        }
-
-        err = request_firmware(&fw, name, &pdev->dev);
-        platform_device_unregister(pdev);
-
-        if (err) {
-                i = 0;
-                while (i < GENERIC_EDIDS && strcmp(name, generic_edid_name[i]))
-                        i++;
-                if (i < GENERIC_EDIDS) {
-                        err = 0;
-                        builtin = 1;
+        builtin = 0;
+        for (i = 0; i < GENERIC_EDIDS; i++) {
+                if (strcmp(name, generic_edid_name[i]) == 0) {
                         fwdata = generic_edid[i];
                         fwsize = sizeof(generic_edid[i]);
+                        builtin = 1;
+                        break;
                 }
         }
+        if (!builtin) {
+                struct platform_device *pdev;
+                int err;
 
-        if (err) {
-                DRM_ERROR("Requesting EDID firmware \"%s\" failed (err=%d)\n",
-                    name, err);
-                goto out;
-        }
+                pdev = platform_device_register_simple(connector_name, -1, NULL, 0);
+                if (IS_ERR(pdev)) {
+                        DRM_ERROR("Failed to register EDID firmware platform device "
+                                  "for connector \"%s\"\n", connector_name);
+                        return ERR_CAST(pdev);
+                }
+
+                err = request_firmware(&fw, name, &pdev->dev);
+                platform_device_unregister(pdev);
+                if (err) {
+                        DRM_ERROR("Requesting EDID firmware \"%s\" failed (err=%d)\n",
+                                  name, err);
+                        return ERR_PTR(err);
+                }
 
-        if (fwdata == NULL) {
-                fwdata = (u8 *) fw->data;
+                fwdata = fw->data;
                 fwsize = fw->size;
         }
 
-        expected = (fwdata[0x7e] + 1) * EDID_LENGTH;
-        if (expected != fwsize) {
+        if (edid_size(fwdata, fwsize) != fwsize) {
                 DRM_ERROR("Size of EDID firmware \"%s\" is invalid "
-                    "(expected %d, got %d)\n", name, expected, (int) fwsize);
-                err = -EINVAL;
-                goto relfw_out;
+                          "(expected %d, got %d\n", name,
+                          edid_size(fwdata, fwsize), (int)fwsize);
+                edid = ERR_PTR(-EINVAL);
+                goto out;
         }
 
         edid = kmemdup(fwdata, fwsize, GFP_KERNEL);
         if (edid == NULL) {
-                err = -ENOMEM;
-                goto relfw_out;
+                edid = ERR_PTR(-ENOMEM);
+                goto out;
         }
 
         if (!drm_edid_block_valid(edid, 0, print_bad_edid)) {
@@ -197,8 +202,8 @@ static u8 *edid_load(struct drm_connector *connector, const char *name,
                 DRM_ERROR("Base block of EDID firmware \"%s\" is invalid ",
                     name);
                 kfree(edid);
-                err = -EINVAL;
-                goto relfw_out;
+                edid = ERR_PTR(-EINVAL);
+                goto out;
         }
 
         for (i = 1; i <= edid[0x7e]; i++) {
@@ -210,19 +215,18 @@ static u8 *edid_load(struct drm_connector *connector, const char *name,
         }
 
         if (valid_extensions != edid[0x7e]) {
+                u8 *new_edid;
+
                 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
                 DRM_INFO("Found %d valid extensions instead of %d in EDID data "
                     "\"%s\" for connector \"%s\"\n", valid_extensions,
                     edid[0x7e], name, connector_name);
                 edid[0x7e] = valid_extensions;
+
                 new_edid = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH,
-                    GFP_KERNEL);
-                if (new_edid == NULL) {
-                        err = -ENOMEM;
-                        kfree(edid);
-                        goto relfw_out;
-                }
-                edid = new_edid;
+                                    GFP_KERNEL);
+                if (new_edid)
+                        edid = new_edid;
         }
 
         DRM_INFO("Got %s EDID base block and %d extension%s from "
@@ -230,13 +234,9 @@ static u8 *edid_load(struct drm_connector *connector, const char *name,
             "external", valid_extensions, valid_extensions == 1 ? "" : "s",
             name, connector_name);
 
-relfw_out:
-        release_firmware(fw);
-
 out:
-        if (err)
-                return ERR_PTR(err);
-
+        if (fw)
+                release_firmware(fw);
         return edid;
 }
 
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index f6f6cc7fc133..21742a81cb9c 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -852,7 +852,6 @@ int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
         struct drm_fb_helper *fb_helper = info->par;
         struct drm_device *dev = fb_helper->dev;
         struct drm_mode_set *modeset;
-        struct drm_crtc *crtc;
         int ret = 0;
         int i;
 
@@ -863,8 +862,6 @@ int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
         }
 
         for (i = 0; i < fb_helper->crtc_count; i++) {
-                crtc = fb_helper->crtc_info[i].mode_set.crtc;
-
                 modeset = &fb_helper->crtc_info[i].mode_set;
 
                 modeset->x = var->xoffset;
@@ -1360,7 +1357,6 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
         struct drm_connector *connector;
         struct drm_connector_helper_funcs *connector_funcs;
         struct drm_encoder *encoder;
-        struct drm_fb_helper_crtc *best_crtc;
         int my_score, best_score, score;
         struct drm_fb_helper_crtc **crtcs, *crtc;
         struct drm_fb_helper_connector *fb_helper_conn;
@@ -1372,7 +1368,6 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
         connector = fb_helper_conn->connector;
 
         best_crtcs[n] = NULL;
-        best_crtc = NULL;
         best_score = drm_pick_crtcs(fb_helper, best_crtcs, modes, n+1, width, height);
         if (modes[n] == NULL)
                 return best_score;
@@ -1421,7 +1416,6 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
                 score = my_score + drm_pick_crtcs(fb_helper, crtcs, modes, n + 1,
                                                   width, height);
                 if (score > best_score) {
-                        best_crtc = crtc;
                         best_score = score;
                         memcpy(best_crtcs, crtcs,
                                dev->mode_config.num_connector *
@@ -1588,8 +1582,7 @@ EXPORT_SYMBOL(drm_fb_helper_initial_config);
 int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper)
 {
         struct drm_device *dev = fb_helper->dev;
-        int count = 0;
-        u32 max_width, max_height, bpp_sel;
+        u32 max_width, max_height;
 
         if (!fb_helper->fb)
                 return 0;
@@ -1604,10 +1597,8 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper)
 
         max_width = fb_helper->fb->width;
         max_height = fb_helper->fb->height;
-        bpp_sel = fb_helper->fb->bits_per_pixel;
 
-        count = drm_fb_helper_probe_connector_modes(fb_helper, max_width,
-                                                    max_height);
+        drm_fb_helper_probe_connector_modes(fb_helper, max_width, max_height);
         mutex_unlock(&fb_helper->dev->mode_config.mutex);
 
         drm_modeset_lock_all(dev);
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 3f84277d7036..d0e27667a4eb 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -113,7 +113,6 @@ int drm_open(struct inode *inode, struct file *filp)
         retcode = drm_open_helper(inode, filp, dev);
         if (retcode)
                 goto err_undo;
-        atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
         if (need_setup) {
                 retcode = drm_setup(dev);
                 if (retcode)
@@ -386,6 +385,71 @@ static void drm_events_release(struct drm_file *file_priv)
 }
 
 /**
+ * drm_legacy_dev_reinit
+ *
+ * Reinitializes a legacy/ums drm device in it's lastclose function.
+ */
+static void drm_legacy_dev_reinit(struct drm_device *dev)
+{
+        if (drm_core_check_feature(dev, DRIVER_MODESET))
+                return;
+
+        atomic_set(&dev->ioctl_count, 0);
+        atomic_set(&dev->vma_count, 0);
+
+        dev->sigdata.lock = NULL;
+
+        dev->context_flag = 0;
+        dev->last_context = 0;
+        dev->if_version = 0;
+}
+
+/**
+ * Take down the DRM device.
+ *
+ * \param dev DRM device structure.
+ *
+ * Frees every resource in \p dev.
+ *
+ * \sa drm_device
+ */
+int drm_lastclose(struct drm_device * dev)
+{
+        struct drm_vma_entry *vma, *vma_temp;
+
+        DRM_DEBUG("\n");
+
+        if (dev->driver->lastclose)
+                dev->driver->lastclose(dev);
+        DRM_DEBUG("driver lastclose completed\n");
+
+        if (dev->irq_enabled && !drm_core_check_feature(dev, DRIVER_MODESET))
+                drm_irq_uninstall(dev);
+
+        mutex_lock(&dev->struct_mutex);
+
+        drm_agp_clear(dev);
+
+        drm_legacy_sg_cleanup(dev);
+
+        /* Clear vma list (only built for debugging) */
+        list_for_each_entry_safe(vma, vma_temp, &dev->vmalist, head) {
+                list_del(&vma->head);
+                kfree(vma);
+        }
+
+        drm_legacy_dma_takedown(dev);
+
+        dev->dev_mapping = NULL;
+        mutex_unlock(&dev->struct_mutex);
+
+        drm_legacy_dev_reinit(dev);
+
+        DRM_DEBUG("lastclose completed\n");
+        return 0;
+}
+
+/**
  * Release file.
  *
  * \param inode device inode
@@ -454,7 +518,6 @@ int drm_release(struct inode *inode, struct file *filp)
 
                                 list_del(&pos->head);
                                 kfree(pos);
-                                --dev->ctx_count;
                         }
                 }
         }
@@ -516,7 +579,6 @@ int drm_release(struct inode *inode, struct file *filp)
          * End inline drm_release
          */
 
-        atomic_inc(&dev->counts[_DRM_STAT_CLOSES]);
         if (!--dev->open_count) {
                 if (atomic_read(&dev->ioctl_count)) {
                         DRM_ERROR("Device busy: %d\n",
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 49293bdc972a..4761adedad2a 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -160,35 +160,6 @@ void drm_gem_private_object_init(struct drm_device *dev,
 }
 EXPORT_SYMBOL(drm_gem_private_object_init);
 
-/**
- * Allocate a GEM object of the specified size with shmfs backing store
- */
-struct drm_gem_object *
-drm_gem_object_alloc(struct drm_device *dev, size_t size)
-{
-        struct drm_gem_object *obj;
-
-        obj = kzalloc(sizeof(*obj), GFP_KERNEL);
-        if (!obj)
-                goto free;
-
-        if (drm_gem_object_init(dev, obj, size) != 0)
-                goto free;
-
-        if (dev->driver->gem_init_object != NULL &&
-            dev->driver->gem_init_object(obj) != 0) {
-                goto fput;
-        }
-        return obj;
-fput:
-        /* Object_init mangles the global counters - readjust them. */
-        fput(obj->filp);
-free:
-        kfree(obj);
-        return NULL;
-}
-EXPORT_SYMBOL(drm_gem_object_alloc);
-
 static void
 drm_gem_remove_prime_handles(struct drm_gem_object *obj, struct drm_file *filp)
 {
diff --git a/drivers/gpu/drm/drm_global.c b/drivers/gpu/drm/drm_global.c
index f7311162a61d..3d2e91c4d78e 100644
--- a/drivers/gpu/drm/drm_global.c
+++ b/drivers/gpu/drm/drm_global.c
@@ -67,7 +67,6 @@ int drm_global_item_ref(struct drm_global_reference *ref)
 {
         int ret;
         struct drm_global_item *item = &glob[ref->global_type];
-        void *object;
 
         mutex_lock(&item->mutex);
         if (item->refcount == 0) {
@@ -85,7 +84,6 @@ int drm_global_item_ref(struct drm_global_reference *ref)
         }
         ++item->refcount;
         ref->object = item->object;
-        object = item->object;
         mutex_unlock(&item->mutex);
         return 0;
 out_err:
diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c
index 53298320080b..7d5a152eeb02 100644
--- a/drivers/gpu/drm/drm_info.c
+++ b/drivers/gpu/drm/drm_info.c
@@ -163,13 +163,13 @@ int drm_vblank_info(struct seq_file *m, void *data)
         mutex_lock(&dev->struct_mutex);
         for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
                 seq_printf(m, "CRTC %d enable:     %d\n",
-                           crtc, atomic_read(&dev->vblank_refcount[crtc]));
+                           crtc, atomic_read(&dev->vblank[crtc].refcount));
                 seq_printf(m, "CRTC %d counter:    %d\n",
                            crtc, drm_vblank_count(dev, crtc));
                 seq_printf(m, "CRTC %d last wait:  %d\n",
-                           crtc, dev->last_vblank_wait[crtc]);
+                           crtc, dev->vblank[crtc].last_wait);
                 seq_printf(m, "CRTC %d in modeset: %d\n",
-                           crtc, dev->vblank_inmodeset[crtc]);
+                           crtc, dev->vblank[crtc].inmodeset);
         }
         mutex_unlock(&dev->struct_mutex);
         return 0;
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 07247e2855a2..dffc836144cc 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -303,6 +303,27 @@ int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
 }
 
 /**
+ * Set device/driver capabilities
+ */
+int
+drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
+{
+        struct drm_set_client_cap *req = data;
+
+        switch (req->capability) {
+        case DRM_CLIENT_CAP_STEREO_3D:
+                if (req->value > 1)
+                        return -EINVAL;
+                file_priv->stereo_allowed = req->value;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/**
  * Setversion ioctl.
  *
  * \param inode device inode.
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index f92da0a32f0d..f9af048828ea 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -43,9 +43,8 @@
 #include <linux/export.h>
 
 /* Access macro for slots in vblank timestamp ringbuffer. */
-#define vblanktimestamp(dev, crtc, count) ( \
-        (dev)->_vblank_time[(crtc) * DRM_VBLANKTIME_RBSIZE + \
-        ((count) % DRM_VBLANKTIME_RBSIZE)])
+#define vblanktimestamp(dev, crtc, count) \
+        ((dev)->vblank[crtc].time[(count) % DRM_VBLANKTIME_RBSIZE])
 
 /* Retry timestamp calculation up to 3 times to satisfy
  * drm_timestamp_precision before giving up.
@@ -89,8 +88,7 @@ int drm_irq_by_busid(struct drm_device *dev, void *data,
  */
 static void clear_vblank_timestamps(struct drm_device *dev, int crtc)
 {
-        memset(&dev->_vblank_time[crtc * DRM_VBLANKTIME_RBSIZE], 0,
-                DRM_VBLANKTIME_RBSIZE * sizeof(struct timeval));
+        memset(dev->vblank[crtc].time, 0, sizeof(dev->vblank[crtc].time));
 }
 
 /*
@@ -115,7 +113,7 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
         spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
 
         dev->driver->disable_vblank(dev, crtc);
-        dev->vblank_enabled[crtc] = 0;
+        dev->vblank[crtc].enabled = false;
 
         /* No further vblank irq's will be processed after
          * this point. Get current hardware vblank count and
@@ -130,9 +128,9 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
          * delayed gpu counter increment.
          */
         do {
-                dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc);
+                dev->vblank[crtc].last = dev->driver->get_vblank_counter(dev, crtc);
                 vblrc = drm_get_last_vbltimestamp(dev, crtc, &tvblank, 0);
-        } while (dev->last_vblank[crtc] != dev->driver->get_vblank_counter(dev, crtc) && (--count) && vblrc);
+        } while (dev->vblank[crtc].last != dev->driver->get_vblank_counter(dev, crtc) && (--count) && vblrc);
 
         if (!count)
                 vblrc = 0;
@@ -140,7 +138,7 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
         /* Compute time difference to stored timestamp of last vblank
          * as updated by last invocation of drm_handle_vblank() in vblank irq.
          */
-        vblcount = atomic_read(&dev->_vblank_count[crtc]);
+        vblcount = atomic_read(&dev->vblank[crtc].count);
         diff_ns = timeval_to_ns(&tvblank) -
                   timeval_to_ns(&vblanktimestamp(dev, crtc, vblcount));
 
@@ -157,7 +155,7 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
          * hope for the best.
          */
         if ((vblrc > 0) && (abs64(diff_ns) > 1000000)) {
-                atomic_inc(&dev->_vblank_count[crtc]);
+                atomic_inc(&dev->vblank[crtc].count);
                 smp_mb__after_atomic_inc();
         }
 
@@ -178,8 +176,8 @@ static void vblank_disable_fn(unsigned long arg)
 
         for (i = 0; i < dev->num_crtcs; i++) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
-                if (atomic_read(&dev->vblank_refcount[i]) == 0 &&
-                    dev->vblank_enabled[i]) {
+                if (atomic_read(&dev->vblank[i].refcount) == 0 &&
+                    dev->vblank[i].enabled) {
                         DRM_DEBUG("disabling vblank on crtc %d\n", i);
                         vblank_disable_and_save(dev, i);
                 }
@@ -197,14 +195,7 @@ void drm_vblank_cleanup(struct drm_device *dev)
 
         vblank_disable_fn((unsigned long)dev);
 
-        kfree(dev->vbl_queue);
-        kfree(dev->_vblank_count);
-        kfree(dev->vblank_refcount);
-        kfree(dev->vblank_enabled);
-        kfree(dev->last_vblank);
-        kfree(dev->last_vblank_wait);
-        kfree(dev->vblank_inmodeset);
-        kfree(dev->_vblank_time);
+        kfree(dev->vblank);
 
         dev->num_crtcs = 0;
 }
@@ -221,40 +212,12 @@ int drm_vblank_init(struct drm_device *dev, int num_crtcs)
 
         dev->num_crtcs = num_crtcs;
 
-        dev->vbl_queue = kmalloc(sizeof(wait_queue_head_t) * num_crtcs,
-                                 GFP_KERNEL);
-        if (!dev->vbl_queue)
+        dev->vblank = kcalloc(num_crtcs, sizeof(*dev->vblank), GFP_KERNEL);
+        if (!dev->vblank)
                 goto err;
 
-        dev->_vblank_count = kmalloc(sizeof(atomic_t) * num_crtcs, GFP_KERNEL);
-        if (!dev->_vblank_count)
-                goto err;
-
-        dev->vblank_refcount = kmalloc(sizeof(atomic_t) * num_crtcs,
-                                       GFP_KERNEL);
-        if (!dev->vblank_refcount)
-                goto err;
-
-        dev->vblank_enabled = kcalloc(num_crtcs, sizeof(int), GFP_KERNEL);
-        if (!dev->vblank_enabled)
-                goto err;
-
-        dev->last_vblank = kcalloc(num_crtcs, sizeof(u32), GFP_KERNEL);
-        if (!dev->last_vblank)
-                goto err;
-
-        dev->last_vblank_wait = kcalloc(num_crtcs, sizeof(u32), GFP_KERNEL);
-        if (!dev->last_vblank_wait)
-                goto err;
-
-        dev->vblank_inmodeset = kcalloc(num_crtcs, sizeof(int), GFP_KERNEL);
-        if (!dev->vblank_inmodeset)
-                goto err;
-
-        dev->_vblank_time = kcalloc(num_crtcs * DRM_VBLANKTIME_RBSIZE,
-                                    sizeof(struct timeval), GFP_KERNEL);
-        if (!dev->_vblank_time)
-                goto err;
+        for (i = 0; i < num_crtcs; i++)
+                init_waitqueue_head(&dev->vblank[i].queue);
 
         DRM_INFO("Supports vblank timestamp caching Rev 1 (10.10.2010).\n");
 
@@ -264,14 +227,8 @@ int drm_vblank_init(struct drm_device *dev, int num_crtcs)
         else
                 DRM_INFO("No driver support for vblank timestamp query.\n");
 
-        /* Zero per-crtc vblank stuff */
-        for (i = 0; i < num_crtcs; i++) {
-                init_waitqueue_head(&dev->vbl_queue[i]);
-                atomic_set(&dev->_vblank_count[i], 0);
-                atomic_set(&dev->vblank_refcount[i], 0);
-        }
+        dev->vblank_disable_allowed = false;
 
-        dev->vblank_disable_allowed = 0;
         return 0;
 
 err:
@@ -336,7 +293,7 @@ int drm_irq_install(struct drm_device *dev)
                 mutex_unlock(&dev->struct_mutex);
                 return -EBUSY;
         }
-        dev->irq_enabled = 1;
+        dev->irq_enabled = true;
         mutex_unlock(&dev->struct_mutex);
 
         DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
@@ -359,7 +316,7 @@ int drm_irq_install(struct drm_device *dev)
 
         if (ret < 0) {
                 mutex_lock(&dev->struct_mutex);
-                dev->irq_enabled = 0;
+                dev->irq_enabled = false;
                 mutex_unlock(&dev->struct_mutex);
                 return ret;
         }
@@ -373,7 +330,7 @@ int drm_irq_install(struct drm_device *dev)
 
         if (ret < 0) {
                 mutex_lock(&dev->struct_mutex);
-                dev->irq_enabled = 0;
+                dev->irq_enabled = false;
                 mutex_unlock(&dev->struct_mutex);
                 if (!drm_core_check_feature(dev, DRIVER_MODESET))
                         vga_client_register(dev->pdev, NULL, NULL, NULL);
@@ -394,14 +351,15 @@ EXPORT_SYMBOL(drm_irq_install);
 int drm_irq_uninstall(struct drm_device *dev)
 {
         unsigned long irqflags;
-        int irq_enabled, i;
+        bool irq_enabled;
+        int i;
 
         if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
                 return -EINVAL;
 
         mutex_lock(&dev->struct_mutex);
         irq_enabled = dev->irq_enabled;
-        dev->irq_enabled = 0;
+        dev->irq_enabled = false;
         mutex_unlock(&dev->struct_mutex);
 
         /*
@@ -410,9 +368,9 @@ int drm_irq_uninstall(struct drm_device *dev)
         if (dev->num_crtcs) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
                 for (i = 0; i < dev->num_crtcs; i++) {
-                        DRM_WAKEUP(&dev->vbl_queue[i]);
-                        dev->vblank_enabled[i] = 0;
-                        dev->last_vblank[i] =
+                        DRM_WAKEUP(&dev->vblank[i].queue);
+                        dev->vblank[i].enabled = false;
+                        dev->vblank[i].last =
                                 dev->driver->get_vblank_counter(dev, i);
                 }
                 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
@@ -795,7 +753,7 @@ EXPORT_SYMBOL(drm_get_last_vbltimestamp);
  */
 u32 drm_vblank_count(struct drm_device *dev, int crtc)
 {
-        return atomic_read(&dev->_vblank_count[crtc]);
+        return atomic_read(&dev->vblank[crtc].count);
 }
 EXPORT_SYMBOL(drm_vblank_count);
 
@@ -824,10 +782,10 @@ u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
          * a seqlock.
          */
         do {
-                cur_vblank = atomic_read(&dev->_vblank_count[crtc]);
+                cur_vblank = atomic_read(&dev->vblank[crtc].count);
                 *vblanktime = vblanktimestamp(dev, crtc, cur_vblank);
                 smp_rmb();
-        } while (cur_vblank != atomic_read(&dev->_vblank_count[crtc]));
+        } while (cur_vblank != atomic_read(&dev->vblank[crtc].count));
 
         return cur_vblank;
 }
@@ -914,12 +872,12 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc)
         } while (cur_vblank != dev->driver->get_vblank_counter(dev, crtc));
 
         /* Deal with counter wrap */
-        diff = cur_vblank - dev->last_vblank[crtc];
-        if (cur_vblank < dev->last_vblank[crtc]) {
+        diff = cur_vblank - dev->vblank[crtc].last;
+        if (cur_vblank < dev->vblank[crtc].last) {
                 diff += dev->max_vblank_count;
 
                 DRM_DEBUG("last_vblank[%d]=0x%x, cur_vblank=0x%x => diff=0x%x\n",
-                          crtc, dev->last_vblank[crtc], cur_vblank, diff);
+                          crtc, dev->vblank[crtc].last, cur_vblank, diff);
         }
 
         DRM_DEBUG("enabling vblank interrupts on crtc %d, missed %d\n",
@@ -930,12 +888,12 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc)
          * reinitialize delayed at next vblank interrupt in that case.
          */
         if (rc) {
-                tslot = atomic_read(&dev->_vblank_count[crtc]) + diff;
+                tslot = atomic_read(&dev->vblank[crtc].count) + diff;
                 vblanktimestamp(dev, crtc, tslot) = t_vblank;
         }
 
         smp_mb__before_atomic_inc();
-        atomic_add(diff, &dev->_vblank_count[crtc]);
+        atomic_add(diff, &dev->vblank[crtc].count);
         smp_mb__after_atomic_inc();
 }
 
@@ -957,9 +915,9 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
 
         spin_lock_irqsave(&dev->vbl_lock, irqflags);
         /* Going from 0->1 means we have to enable interrupts again */
-        if (atomic_add_return(1, &dev->vblank_refcount[crtc]) == 1) {
+        if (atomic_add_return(1, &dev->vblank[crtc].refcount) == 1) {
                 spin_lock_irqsave(&dev->vblank_time_lock, irqflags2);
-                if (!dev->vblank_enabled[crtc]) {
+                if (!dev->vblank[crtc].enabled) {
                         /* Enable vblank irqs under vblank_time_lock protection.
                          * All vblank count & timestamp updates are held off
                          * until we are done reinitializing master counter and
@@ -970,16 +928,16 @@ int drm_vblank_get(struct drm_device *dev, int crtc)
                         DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n",
                                   crtc, ret);
                         if (ret)
-                                atomic_dec(&dev->vblank_refcount[crtc]);
+                                atomic_dec(&dev->vblank[crtc].refcount);
                         else {
-                                dev->vblank_enabled[crtc] = 1;
+                                dev->vblank[crtc].enabled = true;
                                 drm_update_vblank_count(dev, crtc);
                         }
                 }
                 spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags2);
         } else {
-                if (!dev->vblank_enabled[crtc]) {
-                        atomic_dec(&dev->vblank_refcount[crtc]);
+                if (!dev->vblank[crtc].enabled) {
+                        atomic_dec(&dev->vblank[crtc].refcount);
                         ret = -EINVAL;
                 }
         }
@@ -999,10 +957,10 @@ EXPORT_SYMBOL(drm_vblank_get);
  */
 void drm_vblank_put(struct drm_device *dev, int crtc)
 {
-        BUG_ON(atomic_read(&dev->vblank_refcount[crtc]) == 0);
+        BUG_ON(atomic_read(&dev->vblank[crtc].refcount) == 0);
 
         /* Last user schedules interrupt disable */
-        if (atomic_dec_and_test(&dev->vblank_refcount[crtc]) &&
+        if (atomic_dec_and_test(&dev->vblank[crtc].refcount) &&
             (drm_vblank_offdelay > 0))
                 mod_timer(&dev->vblank_disable_timer,
                           jiffies + ((drm_vblank_offdelay * DRM_HZ)/1000));
@@ -1025,7 +983,7 @@ void drm_vblank_off(struct drm_device *dev, int crtc)
 
         spin_lock_irqsave(&dev->vbl_lock, irqflags);
         vblank_disable_and_save(dev, crtc);
-        DRM_WAKEUP(&dev->vbl_queue[crtc]);
+        DRM_WAKEUP(&dev->vblank[crtc].queue);
 
         /* Send any queued vblank events, lest the natives grow disquiet */
         seq = drm_vblank_count_and_time(dev, crtc, &now);
@@ -1067,10 +1025,10 @@ void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
          * to avoid corrupting the count if multiple, mismatch calls occur),
          * so that interrupts remain enabled in the interim.
          */
-        if (!dev->vblank_inmodeset[crtc]) {
-                dev->vblank_inmodeset[crtc] = 0x1;
+        if (!dev->vblank[crtc].inmodeset) {
+                dev->vblank[crtc].inmodeset = 0x1;
                 if (drm_vblank_get(dev, crtc) == 0)
-                        dev->vblank_inmodeset[crtc] |= 0x2;
+                        dev->vblank[crtc].inmodeset |= 0x2;
         }
 }
 EXPORT_SYMBOL(drm_vblank_pre_modeset);
@@ -1083,15 +1041,15 @@ void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
         if (!dev->num_crtcs)
                 return;
 
-        if (dev->vblank_inmodeset[crtc]) {
+        if (dev->vblank[crtc].inmodeset) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
-                dev->vblank_disable_allowed = 1;
+                dev->vblank_disable_allowed = true;
                 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 
-                if (dev->vblank_inmodeset[crtc] & 0x2)
+                if (dev->vblank[crtc].inmodeset & 0x2)
                         drm_vblank_put(dev, crtc);
 
-                dev->vblank_inmodeset[crtc] = 0;
+                dev->vblank[crtc].inmodeset = 0;
         }
 }
 EXPORT_SYMBOL(drm_vblank_post_modeset);
@@ -1288,8 +1246,8 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
 
         DRM_DEBUG("waiting on vblank count %d, crtc %d\n",
                   vblwait->request.sequence, crtc);
-        dev->last_vblank_wait[crtc] = vblwait->request.sequence;
-        DRM_WAIT_ON(ret, dev->vbl_queue[crtc], 3 * DRM_HZ,
+        dev->vblank[crtc].last_wait = vblwait->request.sequence;
+        DRM_WAIT_ON(ret, dev->vblank[crtc].queue, 3 * DRM_HZ,
                     (((drm_vblank_count(dev, crtc) -
                        vblwait->request.sequence) <= (1 << 23)) ||
                      !dev->irq_enabled));
@@ -1367,7 +1325,7 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
         spin_lock_irqsave(&dev->vblank_time_lock, irqflags);
 
         /* Vblank irq handling disabled. Nothing to do. */
-        if (!dev->vblank_enabled[crtc]) {
+        if (!dev->vblank[crtc].enabled) {
                 spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
                 return false;
         }
@@ -1377,7 +1335,7 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
          */
 
         /* Get current timestamp and count. */
-        vblcount = atomic_read(&dev->_vblank_count[crtc]);
+        vblcount = atomic_read(&dev->vblank[crtc].count);
         drm_get_last_vbltimestamp(dev, crtc, &tvblank, DRM_CALLED_FROM_VBLIRQ);
 
         /* Compute time difference to timestamp of last vblank */
@@ -1401,14 +1359,14 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
                  * the timestamp computed above.
                  */
                 smp_mb__before_atomic_inc();
-                atomic_inc(&dev->_vblank_count[crtc]);
+                atomic_inc(&dev->vblank[crtc].count);
                 smp_mb__after_atomic_inc();
         } else {
                 DRM_DEBUG("crtc %d: Redundant vblirq ignored. diff_ns = %d\n",
                           crtc, (int) diff_ns);
         }
 
-        DRM_WAKEUP(&dev->vbl_queue[crtc]);
+        DRM_WAKEUP(&dev->vblank[crtc].queue);
         drm_handle_vblank_events(dev, crtc);
 
         spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
diff --git a/drivers/gpu/drm/drm_lock.c b/drivers/gpu/drm/drm_lock.c
index d752c96d6090..f6452682141b 100644
--- a/drivers/gpu/drm/drm_lock.c
+++ b/drivers/gpu/drm/drm_lock.c
@@ -86,7 +86,6 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
                 if (drm_lock_take(&master->lock, lock->context)) {
                         master->lock.file_priv = file_priv;
                         master->lock.lock_time = jiffies;
-                        atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
                         break;  /* Got lock */
                 }
 
@@ -157,8 +156,6 @@ int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
                 return -EINVAL;
         }
 
-        atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]);
-
         if (drm_lock_free(&master->lock, lock->context)) {
                 /* FIXME: Should really bail out here. */
         }
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index fc2adb62b757..b0733153dfd2 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -707,18 +707,25 @@ EXPORT_SYMBOL(drm_mode_vrefresh);
 /**
  * drm_mode_set_crtcinfo - set CRTC modesetting parameters
  * @p: mode
- * @adjust_flags: unused? (FIXME)
+ * @adjust_flags: a combination of adjustment flags
  *
  * LOCKING:
  * None.
  *
  * Setup the CRTC modesetting parameters for @p, adjusting if necessary.
+ *
+ * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
+ *   interlaced modes.
+ * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
+ *   buffers containing two eyes (only adjust the timings when needed, eg. for
+ *   "frame packing" or "side by side full").
  */
 void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
 {
         if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
                 return;
 
+        p->crtc_clock = p->clock;
         p->crtc_hdisplay = p->hdisplay;
         p->crtc_hsync_start = p->hsync_start;
         p->crtc_hsync_end = p->hsync_end;
@@ -752,6 +759,20 @@ void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
                 p->crtc_vtotal *= p->vscan;
         }
 
+        if (adjust_flags & CRTC_STEREO_DOUBLE) {
+                unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
+
+                switch (layout) {
+                case DRM_MODE_FLAG_3D_FRAME_PACKING:
+                        p->crtc_clock *= 2;
+                        p->crtc_vdisplay += p->crtc_vtotal;
+                        p->crtc_vsync_start += p->crtc_vtotal;
+                        p->crtc_vsync_end += p->crtc_vtotal;
+                        p->crtc_vtotal += p->crtc_vtotal;
+                        break;
+                }
+        }
+
         p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
         p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
         p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
@@ -830,12 +851,16 @@ bool drm_mode_equal(const struct drm_display_mode *mode1, const struct drm_displ
         } else if (mode1->clock != mode2->clock)
                 return false;
 
-        return drm_mode_equal_no_clocks(mode1, mode2);
+        if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) !=
+            (mode2->flags & DRM_MODE_FLAG_3D_MASK))
+                return false;
+
+        return drm_mode_equal_no_clocks_no_stereo(mode1, mode2);
 }
 EXPORT_SYMBOL(drm_mode_equal);
 
 /**
- * drm_mode_equal_no_clocks - test modes for equality
+ * drm_mode_equal_no_clocks_no_stereo - test modes for equality
  * @mode1: first mode
  * @mode2: second mode
  *
@@ -843,12 +868,13 @@ EXPORT_SYMBOL(drm_mode_equal);
  * None.
  *
  * Check to see if @mode1 and @mode2 are equivalent, but
- * don't check the pixel clocks.
+ * don't check the pixel clocks nor the stereo layout.
  *
  * RETURNS:
  * True if the modes are equal, false otherwise.
  */
-bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
+bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
+                                        const struct drm_display_mode *mode2)
 {
         if (mode1->hdisplay == mode2->hdisplay &&
             mode1->hsync_start == mode2->hsync_start &&
@@ -860,12 +886,13 @@ bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const struct
             mode1->vsync_end == mode2->vsync_end &&
             mode1->vtotal == mode2->vtotal &&
             mode1->vscan == mode2->vscan &&
-            mode1->flags == mode2->flags)
+            (mode1->flags & ~DRM_MODE_FLAG_3D_MASK) ==
+             (mode2->flags & ~DRM_MODE_FLAG_3D_MASK))
                 return true;
 
         return false;
 }
-EXPORT_SYMBOL(drm_mode_equal_no_clocks);
+EXPORT_SYMBOL(drm_mode_equal_no_clocks_no_stereo);
 
 /**
  * drm_mode_validate_size - make sure modes adhere to size constraints
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index 1f96cee6eee8..f00d7a9671ea 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -322,83 +322,36 @@ int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
 
         DRM_DEBUG("\n");
 
-        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        dev = drm_dev_alloc(driver, &pdev->dev);
         if (!dev)
                 return -ENOMEM;
 
         ret = pci_enable_device(pdev);
         if (ret)
-                goto err_g1;
+                goto err_free;
 
         dev->pdev = pdev;
-        dev->dev = &pdev->dev;
-
-        dev->pci_device = pdev->device;
-        dev->pci_vendor = pdev->vendor;
-
 #ifdef __alpha__
         dev->hose = pdev->sysdata;
 #endif
 
-        mutex_lock(&drm_global_mutex);
-
-        if ((ret = drm_fill_in_dev(dev, ent, driver))) {
-                printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
-                goto err_g2;
-        }
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+        if (drm_core_check_feature(dev, DRIVER_MODESET))
                 pci_set_drvdata(pdev, dev);
-                ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
-                if (ret)
-                        goto err_g2;
-        }
-
-        if (drm_core_check_feature(dev, DRIVER_RENDER) && drm_rnodes) {
-                ret = drm_get_minor(dev, &dev->render, DRM_MINOR_RENDER);
-                if (ret)
-                        goto err_g21;
-        }
-
-        if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
-                goto err_g3;
-
-        if (dev->driver->load) {
-                ret = dev->driver->load(dev, ent->driver_data);
-                if (ret)
-                        goto err_g4;
-        }
 
-        /* setup the grouping for the legacy output */
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                ret = drm_mode_group_init_legacy_group(dev,
-                                                &dev->primary->mode_group);
-                if (ret)
-                        goto err_g4;
-        }
-
-        list_add_tail(&dev->driver_item, &driver->device_list);
+        ret = drm_dev_register(dev, ent->driver_data);
+        if (ret)
+                goto err_pci;
 
         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
                  driver->name, driver->major, driver->minor, driver->patchlevel,
                  driver->date, pci_name(pdev), dev->primary->index);
 
-        mutex_unlock(&drm_global_mutex);
         return 0;
 
-err_g4:
-        drm_put_minor(&dev->primary);
-err_g3:
-        if (dev->render)
-                drm_put_minor(&dev->render);
-err_g21:
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                drm_put_minor(&dev->control);
-err_g2:
+err_pci:
         pci_disable_device(pdev);
-err_g1:
-        kfree(dev);
-        mutex_unlock(&drm_global_mutex);
+err_free:
+        drm_dev_free(dev);
         return ret;
 }
 EXPORT_SYMBOL(drm_get_pci_dev);
diff --git a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c
index f7a18c6ba4c4..fc24fee8ec83 100644
--- a/drivers/gpu/drm/drm_platform.c
+++ b/drivers/gpu/drm/drm_platform.c
@@ -47,55 +47,15 @@ static int drm_get_platform_dev(struct platform_device *platdev,
 
         DRM_DEBUG("\n");
 
-        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        dev = drm_dev_alloc(driver, &platdev->dev);
         if (!dev)
                 return -ENOMEM;
 
         dev->platformdev = platdev;
-        dev->dev = &platdev->dev;
 
-        mutex_lock(&drm_global_mutex);
-
-        ret = drm_fill_in_dev(dev, NULL, driver);
-
-        if (ret) {
-                printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
-                goto err_g1;
-        }
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
-                if (ret)
-                        goto err_g1;
-        }
-
-        if (drm_core_check_feature(dev, DRIVER_RENDER) && drm_rnodes) {
-                ret = drm_get_minor(dev, &dev->render, DRM_MINOR_RENDER);
-                if (ret)
-                        goto err_g11;
-        }
-
-        ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY);
+        ret = drm_dev_register(dev, 0);
         if (ret)
-                goto err_g2;
-
-        if (dev->driver->load) {
-                ret = dev->driver->load(dev, 0);
-                if (ret)
-                        goto err_g3;
-        }
-
-        /* setup the grouping for the legacy output */
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                ret = drm_mode_group_init_legacy_group(dev,
-                                &dev->primary->mode_group);
-                if (ret)
-                        goto err_g3;
-        }
-
-        list_add_tail(&dev->driver_item, &driver->device_list);
-
-        mutex_unlock(&drm_global_mutex);
+                goto err_free;
 
         DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
                  driver->name, driver->major, driver->minor, driver->patchlevel,
@@ -103,17 +63,8 @@ static int drm_get_platform_dev(struct platform_device *platdev,
 
         return 0;
 
-err_g3:
-        drm_put_minor(&dev->primary);
-err_g2:
-        if (dev->render)
-                drm_put_minor(&dev->render);
-err_g11:
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                drm_put_minor(&dev->control);
-err_g1:
-        kfree(dev);
-        mutex_unlock(&drm_global_mutex);
+err_free:
+        drm_dev_free(dev);
         return ret;
 }
 
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 276d470f7b3e..56805c39c906 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -637,14 +637,13 @@ int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
         unsigned count;
         struct scatterlist *sg;
         struct page *page;
-        u32 len, offset;
+        u32 len;
         int pg_index;
         dma_addr_t addr;
 
         pg_index = 0;
         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
                 len = sg->length;
-                offset = sg->offset;
                 page = sg_page(sg);
                 addr = sg_dma_address(sg);
 
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index 39d864576be4..26055abf94ee 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -254,70 +254,6 @@ int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
         return 0;
 }
 
-int drm_fill_in_dev(struct drm_device *dev,
-                           const struct pci_device_id *ent,
-                           struct drm_driver *driver)
-{
-        int retcode;
-
-        INIT_LIST_HEAD(&dev->filelist);
-        INIT_LIST_HEAD(&dev->ctxlist);
-        INIT_LIST_HEAD(&dev->vmalist);
-        INIT_LIST_HEAD(&dev->maplist);
-        INIT_LIST_HEAD(&dev->vblank_event_list);
-
-        spin_lock_init(&dev->count_lock);
-        spin_lock_init(&dev->event_lock);
-        mutex_init(&dev->struct_mutex);
-        mutex_init(&dev->ctxlist_mutex);
-
-        if (drm_ht_create(&dev->map_hash, 12)) {
-                return -ENOMEM;
-        }
-
-        /* the DRM has 6 basic counters */
-        dev->counters = 6;
-        dev->types[0] = _DRM_STAT_LOCK;
-        dev->types[1] = _DRM_STAT_OPENS;
-        dev->types[2] = _DRM_STAT_CLOSES;
-        dev->types[3] = _DRM_STAT_IOCTLS;
-        dev->types[4] = _DRM_STAT_LOCKS;
-        dev->types[5] = _DRM_STAT_UNLOCKS;
-
-        dev->driver = driver;
-
-        if (dev->driver->bus->agp_init) {
-                retcode = dev->driver->bus->agp_init(dev);
-                if (retcode)
-                        goto error_out_unreg;
-        }
-
-
-
-        retcode = drm_ctxbitmap_init(dev);
-        if (retcode) {
-                DRM_ERROR("Cannot allocate memory for context bitmap.\n");
-                goto error_out_unreg;
-        }
-
-        if (driver->driver_features & DRIVER_GEM) {
-                retcode = drm_gem_init(dev);
-                if (retcode) {
-                        DRM_ERROR("Cannot initialize graphics execution "
-                                  "manager (GEM)\n");
-                        goto error_out_unreg;
-                }
-        }
-
-        return 0;
-
-      error_out_unreg:
-        drm_lastclose(dev);
-        return retcode;
-}
-EXPORT_SYMBOL(drm_fill_in_dev);
-
-
 /**
  * Get a secondary minor number.
  *
@@ -427,66 +363,237 @@ static void drm_unplug_minor(struct drm_minor *minor)
  */
 void drm_put_dev(struct drm_device *dev)
 {
-        struct drm_driver *driver;
-        struct drm_map_list *r_list, *list_temp;
-
         DRM_DEBUG("\n");
 
         if (!dev) {
                 DRM_ERROR("cleanup called no dev\n");
                 return;
         }
-        driver = dev->driver;
 
-        drm_lastclose(dev);
+        drm_dev_unregister(dev);
+        drm_dev_free(dev);
+}
+EXPORT_SYMBOL(drm_put_dev);
 
-        if (dev->driver->unload)
-                dev->driver->unload(dev);
+void drm_unplug_dev(struct drm_device *dev)
+{
+        /* for a USB device */
+        if (drm_core_check_feature(dev, DRIVER_MODESET))
+                drm_unplug_minor(dev->control);
+        if (dev->render)
+                drm_unplug_minor(dev->render);
+        drm_unplug_minor(dev->primary);
 
-        if (dev->driver->bus->agp_destroy)
-                dev->driver->bus->agp_destroy(dev);
+        mutex_lock(&drm_global_mutex);
 
-        drm_vblank_cleanup(dev);
+        drm_device_set_unplugged(dev);
 
-        list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
-                drm_rmmap(dev, r_list->map);
-        drm_ht_remove(&dev->map_hash);
+        if (dev->open_count == 0) {
+                drm_put_dev(dev);
+        }
+        mutex_unlock(&drm_global_mutex);
+}
+EXPORT_SYMBOL(drm_unplug_dev);
 
-        drm_ctxbitmap_cleanup(dev);
+/**
+ * drm_dev_alloc - Allocate new drm device
+ * @driver: DRM driver to allocate device for
+ * @parent: Parent device object
+ *
+ * Allocate and initialize a new DRM device. No device registration is done.
+ * Call drm_dev_register() to advertice the device to user space and register it
+ * with other core subsystems.
+ *
+ * RETURNS:
+ * Pointer to new DRM device, or NULL if out of memory.
+ */
+struct drm_device *drm_dev_alloc(struct drm_driver *driver,
+                                 struct device *parent)
+{
+        struct drm_device *dev;
+        int ret;
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                drm_put_minor(&dev->control);
+        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        if (!dev)
+                return NULL;
 
-        if (dev->render)
-                drm_put_minor(&dev->render);
+        dev->dev = parent;
+        dev->driver = driver;
+
+        INIT_LIST_HEAD(&dev->filelist);
+        INIT_LIST_HEAD(&dev->ctxlist);
+        INIT_LIST_HEAD(&dev->vmalist);
+        INIT_LIST_HEAD(&dev->maplist);
+        INIT_LIST_HEAD(&dev->vblank_event_list);
+
+        spin_lock_init(&dev->count_lock);
+        spin_lock_init(&dev->event_lock);
+        mutex_init(&dev->struct_mutex);
+        mutex_init(&dev->ctxlist_mutex);
+
+        if (drm_ht_create(&dev->map_hash, 12))
+                goto err_free;
 
-        if (driver->driver_features & DRIVER_GEM)
+        ret = drm_ctxbitmap_init(dev);
+        if (ret) {
+                DRM_ERROR("Cannot allocate memory for context bitmap.\n");
+                goto err_ht;
+        }
+
+        if (driver->driver_features & DRIVER_GEM) {
+                ret = drm_gem_init(dev);
+                if (ret) {
+                        DRM_ERROR("Cannot initialize graphics execution manager (GEM)\n");
+                        goto err_ctxbitmap;
+                }
+        }
+
+        return dev;
+
+err_ctxbitmap:
+        drm_ctxbitmap_cleanup(dev);
+err_ht:
+        drm_ht_remove(&dev->map_hash);
+err_free:
+        kfree(dev);
+        return NULL;
+}
+EXPORT_SYMBOL(drm_dev_alloc);
+
+/**
+ * drm_dev_free - Free DRM device
+ * @dev: DRM device to free
+ *
+ * Free a DRM device that has previously been allocated via drm_dev_alloc().
+ * You must not use kfree() instead or you will leak memory.
+ *
+ * This must not be called once the device got registered. Use drm_put_dev()
+ * instead, which then calls drm_dev_free().
+ */
+void drm_dev_free(struct drm_device *dev)
+{
+        if (dev->driver->driver_features & DRIVER_GEM)
                 drm_gem_destroy(dev);
 
-        drm_put_minor(&dev->primary);
+        drm_ctxbitmap_cleanup(dev);
+        drm_ht_remove(&dev->map_hash);
 
-        list_del(&dev->driver_item);
         kfree(dev->devname);
         kfree(dev);
 }
-EXPORT_SYMBOL(drm_put_dev);
+EXPORT_SYMBOL(drm_dev_free);
 
-void drm_unplug_dev(struct drm_device *dev)
+/**
+ * drm_dev_register - Register DRM device
+ * @dev: Device to register
+ *
+ * Register the DRM device @dev with the system, advertise device to user-space
+ * and start normal device operation. @dev must be allocated via drm_dev_alloc()
+ * previously.
+ *
+ * Never call this twice on any device!
+ *
+ * RETURNS:
+ * 0 on success, negative error code on failure.
+ */
+int drm_dev_register(struct drm_device *dev, unsigned long flags)
 {
-        /* for a USB device */
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                drm_unplug_minor(dev->control);
-        if (dev->render)
-                drm_unplug_minor(dev->render);
-        drm_unplug_minor(dev->primary);
+        int ret;
 
         mutex_lock(&drm_global_mutex);
 
-        drm_device_set_unplugged(dev);
+        if (dev->driver->bus->agp_init) {
+                ret = dev->driver->bus->agp_init(dev);
+                if (ret)
+                        goto out_unlock;
+        }
 
-        if (dev->open_count == 0) {
-                drm_put_dev(dev);
+        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+                ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
+                if (ret)
+                        goto err_agp;
         }
+
+        if (drm_core_check_feature(dev, DRIVER_RENDER) && drm_rnodes) {
+                ret = drm_get_minor(dev, &dev->render, DRM_MINOR_RENDER);
+                if (ret)
+                        goto err_control_node;
+        }
+
+        ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY);
+        if (ret)
+                goto err_render_node;
+
+        if (dev->driver->load) {
+                ret = dev->driver->load(dev, flags);
+                if (ret)
+                        goto err_primary_node;
+        }
+
+        /* setup grouping for legacy outputs */
+        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+                ret = drm_mode_group_init_legacy_group(dev,
+                                &dev->primary->mode_group);
+                if (ret)
+                        goto err_unload;
+        }
+
+        list_add_tail(&dev->driver_item, &dev->driver->device_list);
+
+        ret = 0;
+        goto out_unlock;
+
+err_unload:
+        if (dev->driver->unload)
+                dev->driver->unload(dev);
+err_primary_node:
+        drm_put_minor(&dev->primary);
+err_render_node:
+        if (dev->render)
+                drm_put_minor(&dev->render);
+err_control_node:
+        if (dev->control)
+                drm_put_minor(&dev->control);
+err_agp:
+        if (dev->driver->bus->agp_destroy)
+                dev->driver->bus->agp_destroy(dev);
+out_unlock:
         mutex_unlock(&drm_global_mutex);
+        return ret;
 }
-EXPORT_SYMBOL(drm_unplug_dev);
+EXPORT_SYMBOL(drm_dev_register);
+
+/**
+ * drm_dev_unregister - Unregister DRM device
+ * @dev: Device to unregister
+ *
+ * Unregister the DRM device from the system. This does the reverse of
+ * drm_dev_register() but does not deallocate the device. The caller must call
+ * drm_dev_free() to free all resources.
+ */
+void drm_dev_unregister(struct drm_device *dev)
+{
+        struct drm_map_list *r_list, *list_temp;
+
+        drm_lastclose(dev);
+
+        if (dev->driver->unload)
+                dev->driver->unload(dev);
+
+        if (dev->driver->bus->agp_destroy)
+                dev->driver->bus->agp_destroy(dev);
+
+        drm_vblank_cleanup(dev);
+
+        list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
+                drm_rmmap(dev, r_list->map);
+
+        if (dev->control)
+                drm_put_minor(&dev->control);
+        if (dev->render)
+                drm_put_minor(&dev->render);
+        drm_put_minor(&dev->primary);
+
+        list_del(&dev->driver_item);
+}
+EXPORT_SYMBOL(drm_dev_unregister);
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 2290b3b73832..dae42c79154f 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -22,8 +22,8 @@
 #include <drm/drm_core.h>
 #include <drm/drmP.h>
 
-#define to_drm_minor(d) container_of(d, struct drm_minor, kdev)
-#define to_drm_connector(d) container_of(d, struct drm_connector, kdev)
+#define to_drm_minor(d) dev_get_drvdata(d)
+#define to_drm_connector(d) dev_get_drvdata(d)
 
 static struct device_type drm_sysfs_device_minor = {
         .name = "drm_minor"
@@ -162,20 +162,6 @@ void drm_sysfs_destroy(void)
         drm_class = NULL;
 }
 
-/**
- * drm_sysfs_device_release - do nothing
- * @dev: Linux device
- *
- * Normally, this would free the DRM device associated with @dev, along
- * with cleaning up any other stuff.  But we do that in the DRM core, so
- * this function can just return and hope that the core does its job.
- */
-static void drm_sysfs_device_release(struct device *dev)
-{
-        memset(dev, 0, sizeof(struct device));
-        return;
-}
-
 /*
  * Connector properties
  */
@@ -394,29 +380,26 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
         int i;
         int ret;
 
-        /* We shouldn't get called more than once for the same connector */
-        BUG_ON(device_is_registered(&connector->kdev));
-
-        connector->kdev.parent = &dev->primary->kdev;
-        connector->kdev.class = drm_class;
-        connector->kdev.release = drm_sysfs_device_release;
+        if (connector->kdev)
+                return 0;
 
+        /* We shouldn't get called more than once for the same connector */
+        connector->kdev = device_create(drm_class, dev->primary->kdev,
+                                        0, connector, "card%d-%s",
+                                        dev->primary->index, drm_get_connector_name(connector));
         DRM_DEBUG("adding \"%s\" to sysfs\n",
                   drm_get_connector_name(connector));
 
-        dev_set_name(&connector->kdev, "card%d-%s",
-                     dev->primary->index, drm_get_connector_name(connector));
-        ret = device_register(&connector->kdev);
-
-        if (ret) {
-                DRM_ERROR("failed to register connector device: %d\n", ret);
+        if (IS_ERR(connector->kdev)) {
+                DRM_ERROR("failed to register connector device: %ld\n", PTR_ERR(connector->kdev));
+                ret = PTR_ERR(connector->kdev);
                 goto out;
         }
 
         /* Standard attributes */
 
         for (attr_cnt = 0; attr_cnt < ARRAY_SIZE(connector_attrs); attr_cnt++) {
-                ret = device_create_file(&connector->kdev, &connector_attrs[attr_cnt]);
+                ret = device_create_file(connector->kdev, &connector_attrs[attr_cnt]);
                 if (ret)
                         goto err_out_files;
         }
@@ -433,7 +416,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
                 case DRM_MODE_CONNECTOR_Component:
                 case DRM_MODE_CONNECTOR_TV:
                         for (opt_cnt = 0; opt_cnt < ARRAY_SIZE(connector_attrs_opt1); opt_cnt++) {
-                                ret = device_create_file(&connector->kdev, &connector_attrs_opt1[opt_cnt]);
+                                ret = device_create_file(connector->kdev, &connector_attrs_opt1[opt_cnt]);
                                 if (ret)
                                         goto err_out_files;
                         }
@@ -442,7 +425,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
                         break;
         }
 
-        ret = sysfs_create_bin_file(&connector->kdev.kobj, &edid_attr);
+        ret = sysfs_create_bin_file(&connector->kdev->kobj, &edid_attr);
         if (ret)
                 goto err_out_files;
 
@@ -453,10 +436,11 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
 
 err_out_files:
         for (i = 0; i < opt_cnt; i++)
-                device_remove_file(&connector->kdev, &connector_attrs_opt1[i]);
+                device_remove_file(connector->kdev, &connector_attrs_opt1[i]);
         for (i = 0; i < attr_cnt; i++)
-                device_remove_file(&connector->kdev, &connector_attrs[i]);
-        device_unregister(&connector->kdev);
+                device_remove_file(connector->kdev, &connector_attrs[i]);
+        put_device(connector->kdev);
+        device_unregister(connector->kdev);
 
 out:
         return ret;
@@ -480,16 +464,17 @@ void drm_sysfs_connector_remove(struct drm_connector *connector)
 {
         int i;
 
-        if (!connector->kdev.parent)
+        if (!connector->kdev)
                 return;
         DRM_DEBUG("removing \"%s\" from sysfs\n",
                   drm_get_connector_name(connector));
 
         for (i = 0; i < ARRAY_SIZE(connector_attrs); i++)
-                device_remove_file(&connector->kdev, &connector_attrs[i]);
-        sysfs_remove_bin_file(&connector->kdev.kobj, &edid_attr);
-        device_unregister(&connector->kdev);
-        connector->kdev.parent = NULL;
+                device_remove_file(connector->kdev, &connector_attrs[i]);
+        sysfs_remove_bin_file(&connector->kdev->kobj, &edid_attr);
+        put_device(connector->kdev);
+        device_unregister(connector->kdev);
+        connector->kdev = NULL;
 }
 EXPORT_SYMBOL(drm_sysfs_connector_remove);
 
@@ -508,7 +493,7 @@ void drm_sysfs_hotplug_event(struct drm_device *dev)
 
         DRM_DEBUG("generating hotplug event\n");
 
-        kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
+        kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp);
 }
 EXPORT_SYMBOL(drm_sysfs_hotplug_event);
 
@@ -523,15 +508,8 @@ EXPORT_SYMBOL(drm_sysfs_hotplug_event);
  */
 int drm_sysfs_device_add(struct drm_minor *minor)
 {
-        int err;
         char *minor_str;
 
-        minor->kdev.parent = minor->dev->dev;
-
-        minor->kdev.class = drm_class;
-        minor->kdev.release = drm_sysfs_device_release;
-        minor->kdev.devt = minor->device;
-        minor->kdev.type = &drm_sysfs_device_minor;
         if (minor->type == DRM_MINOR_CONTROL)
                 minor_str = "controlD%d";
         else if (minor->type == DRM_MINOR_RENDER)
@@ -539,18 +517,14 @@ int drm_sysfs_device_add(struct drm_minor *minor)
         else
                 minor_str = "card%d";
 
-        dev_set_name(&minor->kdev, minor_str, minor->index);
-
-        err = device_register(&minor->kdev);
-        if (err) {
-                DRM_ERROR("device add failed: %d\n", err);
-                goto err_out;
+        minor->kdev = device_create(drm_class, minor->dev->dev,
+                                    MKDEV(DRM_MAJOR, minor->index),
+                                    minor, minor_str, minor->index);
+        if (IS_ERR(minor->kdev)) {
+                DRM_ERROR("device create failed %ld\n", PTR_ERR(minor->kdev));
+                return PTR_ERR(minor->kdev);
         }
-
         return 0;
-
-err_out:
-        return err;
 }
 
 /**
@@ -562,9 +536,9 @@ err_out:
  */
 void drm_sysfs_device_remove(struct drm_minor *minor)
 {
-        if (minor->kdev.parent)
-                device_unregister(&minor->kdev);
-        minor->kdev.parent = NULL;
+        if (minor->kdev)
+                device_destroy(drm_class, MKDEV(DRM_MAJOR, minor->index));
+        minor->kdev = NULL;
 }
 
 
diff --git a/drivers/gpu/drm/drm_usb.c b/drivers/gpu/drm/drm_usb.c
index 87664723b9ce..b179b70e7853 100644
--- a/drivers/gpu/drm/drm_usb.c
+++ b/drivers/gpu/drm/drm_usb.c
@@ -7,57 +7,20 @@ int drm_get_usb_dev(struct usb_interface *interface,
                     struct drm_driver *driver)
 {
         struct drm_device *dev;
-        struct usb_device *usbdev;
         int ret;
 
         DRM_DEBUG("\n");
 
-        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        dev = drm_dev_alloc(driver, &interface->dev);
         if (!dev)
                 return -ENOMEM;
 
-        usbdev = interface_to_usbdev(interface);
-        dev->usbdev = usbdev;
-        dev->dev = &interface->dev;
-
-        mutex_lock(&drm_global_mutex);
-
-        ret = drm_fill_in_dev(dev, NULL, driver);
-        if (ret) {
-                printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
-                goto err_g1;
-        }
-
+        dev->usbdev = interface_to_usbdev(interface);
         usb_set_intfdata(interface, dev);
-        ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
-        if (ret)
-                goto err_g1;
-
-        if (drm_core_check_feature(dev, DRIVER_RENDER) && drm_rnodes) {
-                ret = drm_get_minor(dev, &dev->render, DRM_MINOR_RENDER);
-                if (ret)
-                        goto err_g11;
-        }
 
-        ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY);
+        ret = drm_dev_register(dev, 0);
         if (ret)
-                goto err_g2;
-
-        if (dev->driver->load) {
-                ret = dev->driver->load(dev, 0);
-                if (ret)
-                        goto err_g3;
-        }
-
-        /* setup the grouping for the legacy output */
-        ret = drm_mode_group_init_legacy_group(dev,
-                                               &dev->primary->mode_group);
-        if (ret)
-                goto err_g3;
-
-        list_add_tail(&dev->driver_item, &driver->device_list);
-
-        mutex_unlock(&drm_global_mutex);
+                goto err_free;
 
         DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
                  driver->name, driver->major, driver->minor, driver->patchlevel,
@@ -65,16 +28,8 @@ int drm_get_usb_dev(struct usb_interface *interface,
 
         return 0;
 
-err_g3:
-        drm_put_minor(&dev->primary);
-err_g2:
-        if (dev->render)
-                drm_put_minor(&dev->render);
-err_g11:
-        drm_put_minor(&dev->control);
-err_g1:
-        kfree(dev);
-        mutex_unlock(&drm_global_mutex);
+err_free:
+        drm_dev_free(dev);
         return ret;
 
 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index bb82ef78ca85..3a1e6d9b25f7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -264,7 +264,6 @@ static struct drm_driver exynos_drm_driver = {
         .get_vblank_counter     = drm_vblank_count,
         .enable_vblank          = exynos_drm_crtc_enable_vblank,
         .disable_vblank         = exynos_drm_crtc_disable_vblank,
-        .gem_init_object        = exynos_drm_gem_init_object,
         .gem_free_object        = exynos_drm_gem_free_object,
         .gem_vm_ops             = &exynos_drm_gem_vm_ops,
         .dumb_create            = exynos_drm_gem_dumb_create,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 868a14d52995..23da72b5eae9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -716,20 +716,20 @@ static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 {
         /*
          * enable drm irq mode.
-         * - with irq_enabled = 1, we can use the vblank feature.
+         * - with irq_enabled = true, we can use the vblank feature.
          *
          * P.S. note that we wouldn't use drm irq handler but
          *      just specific driver own one instead because
          *      drm framework supports only one irq handler.
          */
-        drm_dev->irq_enabled = 1;
+        drm_dev->irq_enabled = true;
 
         /*
-         * with vblank_disable_allowed = 1, vblank interrupt will be disabled
+         * with vblank_disable_allowed = true, vblank interrupt will be disabled
          * by drm timer once a current process gives up ownership of
          * vblank event.(after drm_vblank_put function is called)
          */
-        drm_dev->vblank_disable_allowed = 1;
+        drm_dev->vblank_disable_allowed = true;
 
         /* attach this sub driver to iommu mapping if supported. */
         if (is_drm_iommu_supported(drm_dev))
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 49f9cd232757..1ade191d84f4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -630,11 +630,6 @@ void exynos_gem_unmap_sgt_from_dma(struct drm_device *drm_dev,
         dma_unmap_sg(drm_dev->dev, sgt->sgl, sgt->nents, dir);
 }
 
-int exynos_drm_gem_init_object(struct drm_gem_object *obj)
-{
-        return 0;
-}
-
 void exynos_drm_gem_free_object(struct drm_gem_object *obj)
 {
         struct exynos_drm_gem_obj *exynos_gem_obj;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h
index 09555afdfe9c..702ec3abe85c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
@@ -135,9 +135,6 @@ unsigned long exynos_drm_gem_get_size(struct drm_device *dev,
                                                 unsigned int gem_handle,
                                                 struct drm_file *file_priv);
 
-/* initialize gem object. */
-int exynos_drm_gem_init_object(struct drm_gem_object *obj);
-
 /* free gem object. */
 void exynos_drm_gem_free_object(struct drm_gem_object *gem_obj);
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 4400330e4449..ddaaedde173d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -101,7 +101,6 @@ static struct edid *vidi_get_edid(struct device *dev,
 {
         struct vidi_context *ctx = get_vidi_context(dev);
         struct edid *edid;
-        int edid_len;
 
         /*
          * the edid data comes from user side and it would be set
@@ -112,8 +111,7 @@ static struct edid *vidi_get_edid(struct device *dev,
                 return ERR_PTR(-EFAULT);
         }
 
-        edid_len = (1 + ctx->raw_edid->extensions) * EDID_LENGTH;
-        edid = kmemdup(ctx->raw_edid, edid_len, GFP_KERNEL);
+        edid = drm_edid_duplicate(ctx->raw_edid);
         if (!edid) {
                 DRM_DEBUG_KMS("failed to allocate edid\n");
                 return ERR_PTR(-ENOMEM);
@@ -385,20 +383,20 @@ static int vidi_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 {
         /*
          * enable drm irq mode.
-         * - with irq_enabled = 1, we can use the vblank feature.
+         * - with irq_enabled = true, we can use the vblank feature.
          *
          * P.S. note that we wouldn't use drm irq handler but
          *      just specific driver own one instead because
          *      drm framework supports only one irq handler.
          */
-        drm_dev->irq_enabled = 1;
+        drm_dev->irq_enabled = true;
 
         /*
-         * with vblank_disable_allowed = 1, vblank interrupt will be disabled
+         * with vblank_disable_allowed = true, vblank interrupt will be disabled
          * by drm timer once a current process gives up ownership of
          * vblank event.(after drm_vblank_put function is called)
          */
-        drm_dev->vblank_disable_allowed = 1;
+        drm_dev->vblank_disable_allowed = true;
 
         return 0;
 }
@@ -485,7 +483,6 @@ int vidi_connection_ioctl(struct drm_device *drm_dev, void *data,
         struct exynos_drm_manager *manager;
         struct exynos_drm_display_ops *display_ops;
         struct drm_exynos_vidi_connection *vidi = data;
-        int edid_len;
 
         if (!vidi) {
                 DRM_DEBUG_KMS("user data for vidi is null.\n");
@@ -524,8 +521,7 @@ int vidi_connection_ioctl(struct drm_device *drm_dev, void *data,
                         DRM_DEBUG_KMS("edid data is invalid.\n");
                         return -EINVAL;
                 }
-                edid_len = (1 + raw_edid->extensions) * EDID_LENGTH;
-                ctx->raw_edid = kmemdup(raw_edid, edid_len, GFP_KERNEL);
+                ctx->raw_edid = drm_edid_duplicate(raw_edid);
                 if (!ctx->raw_edid) {
                         DRM_DEBUG_KMS("failed to allocate raw_edid.\n");
                         return -ENOMEM;
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index f4eb43573cad..f88a1815d87c 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -666,7 +666,7 @@ cdv_intel_dp_i2c_init(struct gma_connector *connector,
         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
         intel_dp->adapter.algo_data = &intel_dp->algo;
-        intel_dp->adapter.dev.parent = &connector->base.kdev;
+        intel_dp->adapter.dev.parent = connector->base.kdev;
 
         if (is_edp(encoder))
                 cdv_intel_edp_panel_vdd_on(encoder);
diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c
index 10ae8c52d06f..e2db48a81ed0 100644
--- a/drivers/gpu/drm/gma500/gem.c
+++ b/drivers/gpu/drm/gma500/gem.c
@@ -29,11 +29,6 @@
 #include <drm/drm_vma_manager.h>
 #include "psb_drv.h"
 
-int psb_gem_init_object(struct drm_gem_object *obj)
-{
-        return -EINVAL;
-}
-
 void psb_gem_free_object(struct drm_gem_object *obj)
 {
         struct gtt_range *gtt = container_of(obj, struct gtt_range, gem);
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index fcb4e9ff1f20..dd607f820a26 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -359,7 +359,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 
         drm_irq_install(dev);
 
-        dev->vblank_disable_allowed = 1;
+        dev->vblank_disable_allowed = true;
 
         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 
@@ -646,7 +646,6 @@ static struct drm_driver driver = {
         .preclose = psb_driver_preclose,
         .postclose = psb_driver_close,
 
-        .gem_init_object = psb_gem_init_object,
         .gem_free_object = psb_gem_free_object,
         .gem_vm_ops = &psb_gem_vm_ops,
         .dumb_create = psb_gem_dumb_create,
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 4535ac7708f8..0bab46bd73d2 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -44,10 +44,10 @@ enum {
         CHIP_MFLD_0130 = 3,             /* Medfield */
 };
 
-#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
-#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
-#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
-#define IS_CDV(dev) (((dev)->pci_device & 0xfff0) == 0x0be0)
+#define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
+#define IS_MRST(dev) (((dev)->pdev->device & 0xfffc) == 0x4100)
+#define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
+#define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
 
 /*
  * Driver definitions
@@ -837,7 +837,6 @@ extern const struct drm_connector_helper_funcs
 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 
 /* gem.c */
-extern int psb_gem_init_object(struct drm_gem_object *obj);
 extern void psb_gem_free_object(struct drm_gem_object *obj);
 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
                         struct drm_file *file);
diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c
index 029eccf30137..ba4830342d34 100644
--- a/drivers/gpu/drm/gma500/psb_irq.c
+++ b/drivers/gpu/drm/gma500/psb_irq.c
@@ -271,15 +271,15 @@ void psb_irq_preinstall(struct drm_device *dev)
 
         if (gma_power_is_on(dev))
                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
-        if (dev->vblank_enabled[0])
+        if (dev->vblank[0].enabled)
                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
-        if (dev->vblank_enabled[1])
+        if (dev->vblank[1].enabled)
                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 
         /* FIXME: Handle Medfield irq mask
-        if (dev->vblank_enabled[1])
+        if (dev->vblank[1].enabled)
                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
-        if (dev->vblank_enabled[2])
+        if (dev->vblank[2].enabled)
                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
         */
 
@@ -305,17 +305,17 @@ int psb_irq_postinstall(struct drm_device *dev)
         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 
-        if (dev->vblank_enabled[0])
+        if (dev->vblank[0].enabled)
                 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
         else
                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 
-        if (dev->vblank_enabled[1])
+        if (dev->vblank[1].enabled)
                 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
         else
                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 
-        if (dev->vblank_enabled[2])
+        if (dev->vblank[2].enabled)
                 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
         else
                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
@@ -339,13 +339,13 @@ void psb_irq_uninstall(struct drm_device *dev)
 
         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 
-        if (dev->vblank_enabled[0])
+        if (dev->vblank[0].enabled)
                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 
-        if (dev->vblank_enabled[1])
+        if (dev->vblank[1].enabled)
                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 
-        if (dev->vblank_enabled[2])
+        if (dev->vblank[2].enabled)
                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 
         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
@@ -456,7 +456,7 @@ static int psb_vblank_do_wait(struct drm_device *dev,
 {
         unsigned int cur_vblank;
         int ret = 0;
-        DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
+        DRM_WAIT_ON(ret, dev->vblank.queue, 3 * DRM_HZ,
                     (((cur_vblank = atomic_read(counter))
                       - *sequence) <= (1 << 23)));
         *sequence = cur_vblank;
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index ab1892eb1074..249fdff305c6 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -944,8 +944,6 @@ static int i810_dma_vertex(struct drm_device *dev, void *data,
                                  dma->buflist[vertex->idx],
                                  vertex->discard, vertex->used);
 
-        atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
-        atomic_inc(&dev->counts[_DRM_STAT_DMA]);
         sarea_priv->last_enqueue = dev_priv->counter - 1;
         sarea_priv->last_dispatch = (int)hw_status[5];
 
@@ -1105,8 +1103,6 @@ static int i810_dma_mc(struct drm_device *dev, void *data,
         i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
                              mc->last_render);
 
-        atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
-        atomic_inc(&dev->counts[_DRM_STAT_DMA]);
         sarea_priv->last_enqueue = dev_priv->counter - 1;
         sarea_priv->last_dispatch = (int)hw_status[5];
 
@@ -1197,13 +1193,6 @@ static int i810_flip_bufs(struct drm_device *dev, void *data,
 
 int i810_driver_load(struct drm_device *dev, unsigned long flags)
 {
-        /* i810 has 4 more counters */
-        dev->counters += 4;
-        dev->types[6] = _DRM_STAT_IRQ;
-        dev->types[7] = _DRM_STAT_PRIMARY;
-        dev->types[8] = _DRM_STAT_SECONDARY;
-        dev->types[9] = _DRM_STAT_DMA;
-
         pci_set_master(dev->pdev);
 
         return 0;
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b8449a84a0dc..65e60d26891b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -21,6 +21,9 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
           intel_display.o \
           intel_crt.o \
           intel_lvds.o \
+          intel_dsi.o \
+          intel_dsi_cmd.o \
+          intel_dsi_pll.o \
           intel_bios.o \
           intel_ddi.o \
           intel_dp.o \
diff --git a/drivers/gpu/drm/i915/dvo.h b/drivers/gpu/drm/i915/dvo.h
index 33a62ad80100..312163379db9 100644
--- a/drivers/gpu/drm/i915/dvo.h
+++ b/drivers/gpu/drm/i915/dvo.h
@@ -77,17 +77,6 @@ struct intel_dvo_dev_ops {
                           struct drm_display_mode *mode);
 
         /*
-         * Callback to adjust the mode to be set in the CRTC.
-         *
-         * This allows an output to adjust the clock or even the entire set of
-         * timings, which is used for panels with fixed timings or for
-         * buses with clock limitations.
-         */
-        bool (*mode_fixup)(struct intel_dvo_device *dvo,
-                           const struct drm_display_mode *mode,
-                           struct drm_display_mode *adjusted_mode);
-
-        /*
          * Callback for preparing mode changes on an output
          */
         void (*prepare)(struct intel_dvo_device *dvo);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a6f4cb5af185..61fd61969e21 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -145,6 +145,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
                 seq_printf(m, " (%s)", obj->ring->name);
 }
 
+static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
+{
+        seq_putc(m, ctx->is_initialized ? 'I' : 'i');
+        seq_putc(m, ctx->remap_slice ? 'R' : 'r');
+        seq_putc(m, ' ');
+}
+
 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 {
         struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1442,6 +1449,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
         struct drm_device *dev = node->minor->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
         struct intel_ring_buffer *ring;
+        struct i915_hw_context *ctx;
         int ret, i;
 
         ret = mutex_lock_interruptible(&dev->mode_config.mutex);
@@ -1460,12 +1468,15 @@ static int i915_context_status(struct seq_file *m, void *unused)
                 seq_putc(m, '\n');
         }
 
-        for_each_ring(ring, dev_priv, i) {
-                if (ring->default_context) {
-                        seq_printf(m, "HW default context %s ring ", ring->name);
-                        describe_obj(m, ring->default_context->obj);
-                        seq_putc(m, '\n');
-                }
+        list_for_each_entry(ctx, &dev_priv->context_list, link) {
+                seq_puts(m, "HW context ");
+                describe_ctx(m, ctx);
+                for_each_ring(ring, dev_priv, i)
+                        if (ring->default_context == ctx)
+                                seq_printf(m, "(default context %s) ", ring->name);
+
+                describe_obj(m, ctx->obj);
+                seq_putc(m, '\n');
         }
 
         mutex_unlock(&dev->mode_config.mutex);
@@ -1610,27 +1621,27 @@ static int i915_dpio_info(struct seq_file *m, void *data)
         seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
 
         seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_DIV_A));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
         seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_DIV_B));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
 
         seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
         seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
 
         seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
         seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
 
         seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
         seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
+                   vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
 
         seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
-                   vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+                   vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
 
         mutex_unlock(&dev_priv->dpio_lock);
 
@@ -1655,126 +1666,20 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
         struct drm_info_node *node = m->private;
         struct drm_device *dev = node->minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 psrstat, psrperf;
-
-        if (!IS_HASWELL(dev)) {
-                seq_puts(m, "PSR not supported on this platform\n");
-        } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) {
-                seq_puts(m, "PSR enabled\n");
-        } else {
-                seq_puts(m, "PSR disabled: ");
-                switch (dev_priv->no_psr_reason) {
-                case PSR_NO_SOURCE:
-                        seq_puts(m, "not supported on this platform");
-                        break;
-                case PSR_NO_SINK:
-                        seq_puts(m, "not supported by panel");
-                        break;
-                case PSR_MODULE_PARAM:
-                        seq_puts(m, "disabled by flag");
-                        break;
-                case PSR_CRTC_NOT_ACTIVE:
-                        seq_puts(m, "crtc not active");
-                        break;
-                case PSR_PWR_WELL_ENABLED:
-                        seq_puts(m, "power well enabled");
-                        break;
-                case PSR_NOT_TILED:
-                        seq_puts(m, "not tiled");
-                        break;
-                case PSR_SPRITE_ENABLED:
-                        seq_puts(m, "sprite enabled");
-                        break;
-                case PSR_S3D_ENABLED:
-                        seq_puts(m, "stereo 3d enabled");
-                        break;
-                case PSR_INTERLACED_ENABLED:
-                        seq_puts(m, "interlaced enabled");
-                        break;
-                case PSR_HSW_NOT_DDIA:
-                        seq_puts(m, "HSW ties PSR to DDI A (eDP)");
-                        break;
-                default:
-                        seq_puts(m, "unknown reason");
-                }
-                seq_puts(m, "\n");
-                return 0;
-        }
-
-        psrstat = I915_READ(EDP_PSR_STATUS_CTL);
-
-        seq_puts(m, "PSR Current State: ");
-        switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
-        case EDP_PSR_STATUS_STATE_IDLE:
-                seq_puts(m, "Reset state\n");
-                break;
-        case EDP_PSR_STATUS_STATE_SRDONACK:
-                seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
-                break;
-        case EDP_PSR_STATUS_STATE_SRDENT:
-                seq_puts(m, "SRD entry\n");
-                break;
-        case EDP_PSR_STATUS_STATE_BUFOFF:
-                seq_puts(m, "Wait for buffer turn off\n");
-                break;
-        case EDP_PSR_STATUS_STATE_BUFON:
-                seq_puts(m, "Wait for buffer turn on\n");
-                break;
-        case EDP_PSR_STATUS_STATE_AUXACK:
-                seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n");
-                break;
-        case EDP_PSR_STATUS_STATE_SRDOFFACK:
-                seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
-                break;
-        default:
-                seq_puts(m, "Unknown\n");
-                break;
-        }
-
-        seq_puts(m, "Link Status: ");
-        switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
-        case EDP_PSR_STATUS_LINK_FULL_OFF:
-                seq_puts(m, "Link is fully off\n");
-                break;
-        case EDP_PSR_STATUS_LINK_FULL_ON:
-                seq_puts(m, "Link is fully on\n");
-                break;
-        case EDP_PSR_STATUS_LINK_STANDBY:
-                seq_puts(m, "Link is in standby\n");
-                break;
-        default:
-                seq_puts(m, "Unknown\n");
-                break;
-        }
-
-        seq_printf(m, "PSR Entry Count: %u\n",
-                   psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
-                   EDP_PSR_STATUS_COUNT_MASK);
-
-        seq_printf(m, "Max Sleep Timer Counter: %u\n",
-                   psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
-                   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
-
-        seq_printf(m, "Had AUX error: %s\n",
-                   yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
-
-        seq_printf(m, "Sending AUX: %s\n",
-                   yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
-
-        seq_printf(m, "Sending Idle: %s\n",
-                   yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
-
-        seq_printf(m, "Sending TP2 TP3: %s\n",
-                   yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
+        u32 psrperf = 0;
+        bool enabled = false;
 
-        seq_printf(m, "Sending TP1: %s\n",
-                   yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
+        seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
+        seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
 
-        seq_printf(m, "Idle Count: %u\n",
-                   psrstat & EDP_PSR_STATUS_IDLE_MASK);
+        enabled = HAS_PSR(dev) &&
+                I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+        seq_printf(m, "Enabled: %s\n", yesno(enabled));
 
-        psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
-        seq_printf(m, "Performance Counter: %u\n", psrperf);
+        if (HAS_PSR(dev))
+                psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
+                        EDP_PSR_PERF_CNT_MASK;
+        seq_printf(m, "Performance_Counter: %u\n", psrperf);
 
         return 0;
 }
@@ -1885,6 +1790,72 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
                         i915_ring_stop_get, i915_ring_stop_set,
                         "0x%08llx\n");
 
+static int
+i915_ring_missed_irq_get(void *data, u64 *val)
+{
+        struct drm_device *dev = data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        *val = dev_priv->gpu_error.missed_irq_rings;
+        return 0;
+}
+
+static int
+i915_ring_missed_irq_set(void *data, u64 val)
+{
+        struct drm_device *dev = data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int ret;
+
+        /* Lock against concurrent debugfs callers */
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
+        dev_priv->gpu_error.missed_irq_rings = val;
+        mutex_unlock(&dev->struct_mutex);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
+                        i915_ring_missed_irq_get, i915_ring_missed_irq_set,
+                        "0x%08llx\n");
+
+static int
+i915_ring_test_irq_get(void *data, u64 *val)
+{
+        struct drm_device *dev = data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        *val = dev_priv->gpu_error.test_irq_rings;
+
+        return 0;
+}
+
+static int
+i915_ring_test_irq_set(void *data, u64 val)
+{
+        struct drm_device *dev = data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int ret;
+
+        DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
+
+        /* Lock against concurrent debugfs callers */
+        ret = mutex_lock_interruptible(&dev->struct_mutex);
+        if (ret)
+                return ret;
+
+        dev_priv->gpu_error.test_irq_rings = val;
+        mutex_unlock(&dev->struct_mutex);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
+                        i915_ring_test_irq_get, i915_ring_test_irq_set,
+                        "0x%08llx\n");
+
 #define DROP_UNBOUND 0x1
 #define DROP_BOUND 0x2
 #define DROP_RETIRE 0x4
@@ -2145,7 +2116,7 @@ drm_add_fake_info_node(struct drm_minor *minor,
 {
         struct drm_info_node *node;
 
-        node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
+        node = kmalloc(sizeof(*node), GFP_KERNEL);
         if (node == NULL) {
                 debugfs_remove(ent);
                 return -ENOMEM;
@@ -2278,6 +2249,8 @@ static struct i915_debugfs_files {
         {"i915_min_freq", &i915_min_freq_fops},
         {"i915_cache_sharing", &i915_cache_sharing_fops},
         {"i915_ring_stop", &i915_ring_stop_fops},
+        {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
+        {"i915_ring_test_irq", &i915_ring_test_irq_fops},
         {"i915_gem_drop_caches", &i915_drop_caches_fops},
         {"i915_error_state", &i915_error_state_fops},
         {"i915_next_seqno", &i915_next_seqno_fops},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c27a21034a5e..b3873c945d1b 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -52,7 +52,7 @@
         intel_ring_emit(LP_RING(dev_priv), x)
 
 #define ADVANCE_LP_RING() \
-        intel_ring_advance(LP_RING(dev_priv))
+        __intel_ring_advance(LP_RING(dev_priv))
 
 /**
  * Lock test for when it's just for synchronization of ring access.
@@ -641,7 +641,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
 
         if (batch->num_cliprects) {
                 cliprects = kcalloc(batch->num_cliprects,
-                                    sizeof(struct drm_clip_rect),
+                                    sizeof(*cliprects),
                                     GFP_KERNEL);
                 if (cliprects == NULL)
                         return -ENOMEM;
@@ -703,7 +703,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
 
         if (cmdbuf->num_cliprects) {
                 cliprects = kcalloc(cmdbuf->num_cliprects,
-                                    sizeof(struct drm_clip_rect), GFP_KERNEL);
+                                    sizeof(*cliprects), GFP_KERNEL);
                 if (cliprects == NULL) {
                         ret = -ENOMEM;
                         goto fail_batch_free;
@@ -931,7 +931,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
                 value = READ_BREADCRUMB(dev_priv);
                 break;
         case I915_PARAM_CHIPSET_ID:
-                value = dev->pci_device;
+                value = dev->pdev->device;
                 break;
         case I915_PARAM_HAS_GEM:
                 value = 1;
@@ -1314,13 +1314,18 @@ static int i915_load_modeset_init(struct drm_device *dev)
         if (ret)
                 goto cleanup_gem_stolen;
 
+        intel_init_power_well(dev);
+
+        /* Keep VGA alive until i915_disable_vga_mem() */
+        intel_display_power_get(dev, POWER_DOMAIN_VGA);
+
         /* Important: The output setup functions called by modeset_init need
          * working irqs for e.g. gmbus and dp aux transfers. */
         intel_modeset_init(dev);
 
         ret = i915_gem_init(dev);
         if (ret)
-                goto cleanup_irq;
+                goto cleanup_power;
 
         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
 
@@ -1328,9 +1333,11 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
         /* Always safe in the mode setting case. */
         /* FIXME: do pre/post-mode set stuff in core KMS code */
-        dev->vblank_disable_allowed = 1;
-        if (INTEL_INFO(dev)->num_pipes == 0)
+        dev->vblank_disable_allowed = true;
+        if (INTEL_INFO(dev)->num_pipes == 0) {
+                intel_display_power_put(dev, POWER_DOMAIN_VGA);
                 return 0;
+        }
 
         ret = intel_fbdev_init(dev);
         if (ret)
@@ -1356,6 +1363,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
          * vgacon_save_screen() works during the handover.
          */
         i915_disable_vga_mem(dev);
+        intel_display_power_put(dev, POWER_DOMAIN_VGA);
 
         /* Only enable hotplug handling once the fbdev is fully set up. */
         dev_priv->enable_hotplug_processing = true;
@@ -1371,7 +1379,8 @@ cleanup_gem:
         mutex_unlock(&dev->struct_mutex);
         i915_gem_cleanup_aliasing_ppgtt(dev);
         drm_mm_takedown(&dev_priv->gtt.base.mm);
-cleanup_irq:
+cleanup_power:
+        intel_display_power_put(dev, POWER_DOMAIN_VGA);
         drm_irq_uninstall(dev);
 cleanup_gem_stolen:
         i915_gem_cleanup_stolen(dev);
@@ -1471,14 +1480,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
                 return -ENODEV;
 
-        /* i915 has 4 more counters */
-        dev->counters += 4;
-        dev->types[6] = _DRM_STAT_IRQ;
-        dev->types[7] = _DRM_STAT_PRIMARY;
-        dev->types[8] = _DRM_STAT_SECONDARY;
-        dev->types[9] = _DRM_STAT_DMA;
-
-        dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
+        dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
         if (dev_priv == NULL)
                 return -ENOMEM;
 
@@ -1552,7 +1554,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         ret = i915_gem_gtt_init(dev);
         if (ret)
-                goto put_bridge;
+                goto out_regs;
 
         if (drm_core_check_feature(dev, DRIVER_MODESET))
                 i915_kick_out_firmware_fb(dev_priv);
@@ -1581,7 +1583,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                                      aperture_size);
         if (dev_priv->gtt.mappable == NULL) {
                 ret = -EIO;
-                goto out_rmmap;
+                goto out_gtt;
         }
 
         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
@@ -1655,7 +1657,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                 ret = i915_load_modeset_init(dev);
                 if (ret < 0) {
                         DRM_ERROR("failed to init modeset\n");
-                        goto out_gem_unload;
+                        goto out_power_well;
                 }
         } else {
                 /* Start out suspended in ums mode. */
@@ -1675,6 +1677,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         return 0;
 
+out_power_well:
+        if (HAS_POWER_WELL(dev))
+                i915_remove_power_well(dev);
+        drm_vblank_cleanup(dev);
 out_gem_unload:
         if (dev_priv->mm.inactive_shrinker.scan_objects)
                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
@@ -1688,12 +1694,17 @@ out_gem_unload:
 out_mtrrfree:
         arch_phys_wc_del(dev_priv->gtt.mtrr);
         io_mapping_free(dev_priv->gtt.mappable);
+out_gtt:
+        list_del(&dev_priv->gtt.base.global_link);
+        drm_mm_takedown(&dev_priv->gtt.base.mm);
         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
-out_rmmap:
+out_regs:
         pci_iounmap(dev->pdev, dev_priv->regs);
 put_bridge:
         pci_dev_put(dev_priv->bridge_dev);
 free_priv:
+        if (dev_priv->slab)
+                kmem_cache_destroy(dev_priv->slab);
         kfree(dev_priv);
         return ret;
 }
@@ -1783,8 +1794,8 @@ int i915_driver_unload(struct drm_device *dev)
         list_del(&dev_priv->gtt.base.global_link);
         WARN_ON(!list_empty(&dev_priv->vm_list));
         drm_mm_takedown(&dev_priv->gtt.base.mm);
-        if (dev_priv->regs != NULL)
-                pci_iounmap(dev->pdev, dev_priv->regs);
+
+        drm_vblank_cleanup(dev);
 
         intel_teardown_gmbus(dev);
         intel_teardown_mchbar(dev);
@@ -1794,6 +1805,10 @@ int i915_driver_unload(struct drm_device *dev)
 
         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
 
+        intel_uncore_fini(dev);
+        if (dev_priv->regs != NULL)
+                pci_iounmap(dev->pdev, dev_priv->regs);
+
         if (dev_priv->slab)
                 kmem_cache_destroy(dev_priv->slab);
 
@@ -1805,19 +1820,11 @@ int i915_driver_unload(struct drm_device *dev)
 
 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 {
-        struct drm_i915_file_private *file_priv;
-
-        DRM_DEBUG_DRIVER("\n");
-        file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
-        if (!file_priv)
-                return -ENOMEM;
-
-        file->driver_priv = file_priv;
-
-        spin_lock_init(&file_priv->mm.lock);
-        INIT_LIST_HEAD(&file_priv->mm.request_list);
+        int ret;
 
-        idr_init(&file_priv->context_idr);
+        ret = i915_gem_open(dev, file);
+        if (ret)
+                return ret;
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 69d8ed5416c3..96f230497cbe 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -416,7 +416,7 @@ void intel_detect_pch(struct drm_device *dev)
                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
                                 /* PantherPoint is CPT compatible */
                                 dev_priv->pch_type = PCH_CPT;
-                                DRM_DEBUG_KMS("Found PatherPoint PCH\n");
+                                DRM_DEBUG_KMS("Found PantherPoint PCH\n");
                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_LPT;
@@ -576,11 +576,24 @@ static void intel_resume_hotplug(struct drm_device *dev)
         drm_helper_hpd_irq_event(dev);
 }
 
-static int __i915_drm_thaw(struct drm_device *dev)
+static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         int error = 0;
 
+        intel_uncore_early_sanitize(dev);
+
+        intel_uncore_sanitize(dev);
+
+        if (drm_core_check_feature(dev, DRIVER_MODESET) &&
+            restore_gtt_mappings) {
+                mutex_lock(&dev->struct_mutex);
+                i915_gem_restore_gtt_mappings(dev);
+                mutex_unlock(&dev->struct_mutex);
+        }
+
+        intel_init_power_well(dev);
+
         i915_restore_state(dev);
         intel_opregion_setup(dev);
 
@@ -640,19 +653,7 @@ static int __i915_drm_thaw(struct drm_device *dev)
 
 static int i915_drm_thaw(struct drm_device *dev)
 {
-        int error = 0;
-
-        intel_uncore_sanitize(dev);
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                mutex_lock(&dev->struct_mutex);
-                i915_gem_restore_gtt_mappings(dev);
-                mutex_unlock(&dev->struct_mutex);
-        }
-
-        __i915_drm_thaw(dev);
-
-        return error;
+        return __i915_drm_thaw(dev, true);
 }
 
 int i915_resume(struct drm_device *dev)
@@ -668,20 +669,12 @@ int i915_resume(struct drm_device *dev)
 
         pci_set_master(dev->pdev);
 
-        intel_uncore_sanitize(dev);
-
         /*
          * Platforms with opregion should have sane BIOS, older ones (gen3 and
-         * earlier) need this since the BIOS might clear all our scratch PTEs.
+         * earlier) need to restore the GTT mappings since the BIOS might clear
+         * all our scratch PTEs.
          */
-        if (drm_core_check_feature(dev, DRIVER_MODESET) &&
-            !dev_priv->opregion.header) {
-                mutex_lock(&dev->struct_mutex);
-                i915_gem_restore_gtt_mappings(dev);
-                mutex_unlock(&dev->struct_mutex);
-        }
-
-        ret = __i915_drm_thaw(dev);
+        ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
         if (ret)
                 return ret;
 
@@ -719,24 +712,19 @@ int i915_reset(struct drm_device *dev)
 
         simulated = dev_priv->gpu_error.stop_rings != 0;
 
-        if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) {
-                DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
-                ret = -ENODEV;
-        } else {
-                ret = intel_gpu_reset(dev);
-
-                /* Also reset the gpu hangman. */
-                if (simulated) {
-                        DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
-                        dev_priv->gpu_error.stop_rings = 0;
-                        if (ret == -ENODEV) {
-                                DRM_ERROR("Reset not implemented, but ignoring "
-                                          "error for simulated gpu hangs\n");
-                                ret = 0;
-                        }
-                } else
-                        dev_priv->gpu_error.last_reset = get_seconds();
+        ret = intel_gpu_reset(dev);
+
+        /* Also reset the gpu hangman. */
+        if (simulated) {
+                DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
+                dev_priv->gpu_error.stop_rings = 0;
+                if (ret == -ENODEV) {
+                        DRM_ERROR("Reset not implemented, but ignoring "
+                                  "error for simulated gpu hangs\n");
+                        ret = 0;
+                }
         }
+
         if (ret) {
                 DRM_ERROR("Failed to reset chip.\n");
                 mutex_unlock(&dev->struct_mutex);
@@ -799,6 +787,12 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         struct intel_device_info *intel_info =
                 (struct intel_device_info *) ent->driver_data;
 
+        if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
+                DRM_INFO("This hardware requires preliminary hardware support.\n"
+                         "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
+                return -ENODEV;
+        }
+
         /* Only bind to function 0 of the device. Early generations
          * used function 1 as a placeholder for multi-head. This causes
          * us confusion instead, especially on the systems where both
@@ -946,7 +940,6 @@ static struct drm_driver driver = {
         .debugfs_init = i915_debugfs_init,
         .debugfs_cleanup = i915_debugfs_cleanup,
 #endif
-        .gem_init_object = i915_gem_init_object,
         .gem_free_object = i915_gem_free_object,
         .gem_vm_ops = &i915_gem_vm_ops,
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35874b3a86dc..6a5b7ab0c3fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -99,6 +99,7 @@ enum intel_display_power_domain {
         POWER_DOMAIN_TRANSCODER_B,
         POWER_DOMAIN_TRANSCODER_C,
         POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
+        POWER_DOMAIN_VGA,
 };
 
 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
@@ -225,6 +226,8 @@ struct intel_opregion {
         struct opregion_header __iomem *header;
         struct opregion_acpi __iomem *acpi;
         struct opregion_swsci __iomem *swsci;
+        u32 swsci_gbda_sub_functions;
+        u32 swsci_sbcb_sub_functions;
         struct opregion_asle __iomem *asle;
         void __iomem *vbt;
         u32 __iomem *lid_state;
@@ -321,11 +324,13 @@ struct drm_i915_error_state {
                 u32 dirty:1;
                 u32 purgeable:1;
                 s32 ring:4;
-                u32 cache_level:2;
+                u32 cache_level:3;
         } **active_bo, **pinned_bo;
         u32 *active_bo_count, *pinned_bo_count;
         struct intel_overlay_error_state *overlay;
         struct intel_display_error_state *display;
+        int hangcheck_score[I915_NUM_RINGS];
+        enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
 };
 
 struct intel_crtc_config;
@@ -357,7 +362,7 @@ struct drm_i915_display_funcs {
                           int target, int refclk,
                           struct dpll *match_clock,
                           struct dpll *best_clock);
-        void (*update_wm)(struct drm_device *dev);
+        void (*update_wm)(struct drm_crtc *crtc);
         void (*update_sprite_wm)(struct drm_plane *plane,
                                  struct drm_crtc *crtc,
                                  uint32_t sprite_width, int pixel_size,
@@ -367,7 +372,6 @@ struct drm_i915_display_funcs {
          * fills out the pipe-config with the hw state. */
         bool (*get_pipe_config)(struct intel_crtc *,
                                 struct intel_crtc_config *);
-        void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
         int (*crtc_mode_set)(struct drm_crtc *crtc,
                              int x, int y,
                              struct drm_framebuffer *old_fb);
@@ -404,6 +408,8 @@ struct intel_uncore {
 
         unsigned fifo_count;
         unsigned forcewake_count;
+
+        struct delayed_work force_wake_work;
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
@@ -420,6 +426,7 @@ struct intel_uncore {
         func(is_ivybridge) sep \
         func(is_valleyview) sep \
         func(is_haswell) sep \
+        func(is_preliminary) sep \
         func(has_force_wake) sep \
         func(has_fbc) sep \
         func(has_pipe_cxsr) sep \
@@ -568,6 +575,13 @@ struct i915_vma {
         /** This vma's place in the batchbuffer or on the eviction list */
         struct list_head exec_list;
 
+        /**
+         * Used for performing relocations during execbuffer insertion.
+         */
+        struct hlist_node exec_node;
+        unsigned long exec_handle;
+        struct drm_i915_gem_exec_object2 *exec_entry;
+
 };
 
 struct i915_ctx_hang_stats {
@@ -576,6 +590,12 @@ struct i915_ctx_hang_stats {
 
         /* This context had batch active when hang was declared */
         unsigned batch_active;
+
+        /* Time when this context was last blamed for a GPU reset */
+        unsigned long guilty_ts;
+
+        /* This context is banned to submit more work */
+        bool banned;
 };
 
 /* This must match up with the value previously used for execbuf2.rsvd1. */
@@ -584,10 +604,13 @@ struct i915_hw_context {
         struct kref ref;
         int id;
         bool is_initialized;
+        uint8_t remap_slice;
         struct drm_i915_file_private *file_priv;
         struct intel_ring_buffer *ring;
         struct drm_i915_gem_object *obj;
         struct i915_ctx_hang_stats hang_stats;
+
+        struct list_head link;
 };
 
 struct i915_fbc {
@@ -621,17 +644,9 @@ struct i915_fbc {
         } no_fbc_reason;
 };
 
-enum no_psr_reason {
-        PSR_NO_SOURCE, /* Not supported on platform */
-        PSR_NO_SINK, /* Not supported by panel */
-        PSR_MODULE_PARAM,
-        PSR_CRTC_NOT_ACTIVE,
-        PSR_PWR_WELL_ENABLED,
-        PSR_NOT_TILED,
-        PSR_SPRITE_ENABLED,
-        PSR_S3D_ENABLED,
-        PSR_INTERLACED_ENABLED,
-        PSR_HSW_NOT_DDIA,
+struct i915_psr {
+        bool sink_support;
+        bool source_ok;
 };
 
 enum intel_pch {
@@ -821,17 +836,19 @@ struct intel_gen6_power_mgmt {
         struct work_struct work;
         u32 pm_iir;
 
-        /* On vlv we need to manually drop to Vmin with a delayed work. */
-        struct delayed_work vlv_work;
-
         /* The below variables an all the rps hw state are protected by
          * dev->struct mutext. */
         u8 cur_delay;
         u8 min_delay;
         u8 max_delay;
         u8 rpe_delay;
+        u8 rp1_delay;
+        u8 rp0_delay;
         u8 hw_max;
 
+        int last_adj;
+        enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
+
         struct delayed_work delayed_resume_work;
 
         /*
@@ -900,9 +917,11 @@ struct i915_ums_state {
         int mm_suspended;
 };
 
+#define MAX_L3_SLICES 2
 struct intel_l3_parity {
-        u32 *remap_info;
+        u32 *remap_info[MAX_L3_SLICES];
         struct work_struct error_work;
+        int which_slice;
 };
 
 struct i915_gem_mm {
@@ -940,6 +959,15 @@ struct i915_gem_mm {
         struct delayed_work retire_work;
 
         /**
+         * When we detect an idle GPU, we want to turn on
+         * powersaving features. So once we see that there
+         * are no more requests outstanding and no more
+         * arrive within a small period of time, we fire
+         * off the idle_work.
+         */
+        struct delayed_work idle_work;
+
+        /**
          * Are we in a non-interruptible section of code like
          * modesetting?
          */
@@ -977,6 +1005,9 @@ struct i915_gpu_error {
         /* For hangcheck timer */
 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
+        /* Hang gpu twice in this window and your context gets banned */
+#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
+
         struct timer_list hangcheck_timer;
 
         /* For reset and error_state handling. */
@@ -985,7 +1016,8 @@ struct i915_gpu_error {
         struct drm_i915_error_state *first_error;
         struct work_struct work;
 
-        unsigned long last_reset;
+
+        unsigned long missed_irq_rings;
 
         /**
          * State variable and reset counter controlling the reset flow
@@ -1025,6 +1057,9 @@ struct i915_gpu_error {
 
         /* For gpu hang simulation. */
         unsigned int stop_rings;
+
+        /* For missed irq/seqno simulation. */
+        unsigned int test_irq_rings;
 };
 
 enum modeset_restore {
@@ -1033,6 +1068,14 @@ enum modeset_restore {
         MODESET_SUSPENDED,
 };
 
+struct ddi_vbt_port_info {
+        uint8_t hdmi_level_shift;
+
+        uint8_t supports_dvi:1;
+        uint8_t supports_hdmi:1;
+        uint8_t supports_dp:1;
+};
+
 struct intel_vbt_data {
         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1058,10 +1101,17 @@ struct intel_vbt_data {
         int edp_bpp;
         struct edp_power_seq edp_pps;
 
+        /* MIPI DSI */
+        struct {
+                u16 panel_id;
+        } dsi;
+
         int crt_ddc_pin;
 
         int child_dev_num;
-        struct child_device_config *child_dev;
+        union child_device_config *child_dev;
+
+        struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 };
 
 enum intel_ddb_partitioning {
@@ -1298,7 +1348,7 @@ typedef struct drm_i915_private {
         /* Haswell power well */
         struct i915_power_well power_well;
 
-        enum no_psr_reason no_psr_reason;
+        struct i915_psr psr;
 
         struct i915_gpu_error gpu_error;
 
@@ -1318,6 +1368,7 @@ typedef struct drm_i915_private {
 
         bool hw_contexts_disabled;
         uint32_t hw_context_size;
+        struct list_head context_list;
 
         u32 fdi_rx_config;
 
@@ -1398,8 +1449,6 @@ struct drm_i915_gem_object {
         struct list_head ring_list;
         /** Used in execbuf to temporarily hold a ref */
         struct list_head obj_exec_link;
-        /** This object's place in the batchbuffer or on the eviction list */
-        struct list_head exec_list;
 
         /**
          * This is set if the object is on the active lists (has pending
@@ -1485,13 +1534,6 @@ struct drm_i915_gem_object {
         void *dma_buf_vmapping;
         int vmapping_count;
 
-        /**
-         * Used for performing relocations during execbuffer insertion.
-         */
-        struct hlist_node exec_node;
-        unsigned long exec_handle;
-        struct drm_i915_gem_exec_object2 *exec_entry;
-
         struct intel_ring_buffer *ring;
 
         /** Breadcrumb of last rendering to the buffer. */
@@ -1558,48 +1600,55 @@ struct drm_i915_gem_request {
 };
 
 struct drm_i915_file_private {
+        struct drm_i915_private *dev_priv;
+
         struct {
                 spinlock_t lock;
                 struct list_head request_list;
+                struct delayed_work idle_work;
         } mm;
         struct idr context_idr;
 
         struct i915_ctx_hang_stats hang_stats;
+        atomic_t rps_wait_boost;
 };
 
 #define INTEL_INFO(dev) (to_i915(dev)->info)
 
-#define IS_I830(dev)            ((dev)->pci_device == 0x3577)
-#define IS_845G(dev)            ((dev)->pci_device == 0x2562)
+#define IS_I830(dev)            ((dev)->pdev->device == 0x3577)
+#define IS_845G(dev)            ((dev)->pdev->device == 0x2562)
 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
-#define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
+#define IS_I865G(dev)           ((dev)->pdev->device == 0x2572)
 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
-#define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
-#define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
+#define IS_I915GM(dev)          ((dev)->pdev->device == 0x2592)
+#define IS_I945G(dev)           ((dev)->pdev->device == 0x2772)
 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
-#define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
+#define IS_GM45(dev)            ((dev)->pdev->device == 0x2A42)
 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
-#define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
-#define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
+#define IS_PINEVIEW_G(dev)      ((dev)->pdev->device == 0xa001)
+#define IS_PINEVIEW_M(dev)      ((dev)->pdev->device == 0xa011)
 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
-#define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
+#define IS_IRONLAKE_M(dev)      ((dev)->pdev->device == 0x0046)
 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
-#define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
-                                 (dev)->pci_device == 0x0152 || \
-                                 (dev)->pci_device == 0x015a)
-#define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
-                                 (dev)->pci_device == 0x0106 || \
-                                 (dev)->pci_device == 0x010A)
+#define IS_IVB_GT1(dev)         ((dev)->pdev->device == 0x0156 || \
+                                 (dev)->pdev->device == 0x0152 || \
+                                 (dev)->pdev->device == 0x015a)
+#define IS_SNB_GT1(dev)         ((dev)->pdev->device == 0x0102 || \
+                                 (dev)->pdev->device == 0x0106 || \
+                                 (dev)->pdev->device == 0x010A)
 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
-                                 ((dev)->pci_device & 0xFF00) == 0x0C00)
+                                 ((dev)->pdev->device & 0xFF00) == 0x0C00)
 #define IS_ULT(dev)             (IS_HASWELL(dev) && \
-                                 ((dev)->pci_device & 0xFF00) == 0x0A00)
+                                 ((dev)->pdev->device & 0xFF00) == 0x0A00)
+#define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
+                                 ((dev)->pdev->device & 0x00F0) == 0x0020)
+#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
 
 /*
  * The genX designation typically refers to the render engine, so render
@@ -1638,7 +1687,6 @@ struct drm_i915_file_private {
 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
-#define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 
@@ -1651,6 +1699,7 @@ struct drm_i915_file_private {
 #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
 #define HAS_POWER_WELL(dev)     (IS_HASWELL(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
+#define HAS_PSR(dev)            (IS_HASWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
@@ -1668,7 +1717,9 @@ struct drm_i915_file_private {
 
 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
 
-#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+/* DPF == dynamic parity feature */
+#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
 
@@ -1765,6 +1816,7 @@ extern void intel_uncore_early_sanitize(struct drm_device *dev);
 extern void intel_uncore_init(struct drm_device *dev);
 extern void intel_uncore_clear_errors(struct drm_device *dev);
 extern void intel_uncore_check_errors(struct drm_device *dev);
+extern void intel_uncore_fini(struct drm_device *dev);
 
 void
 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
@@ -1822,14 +1874,11 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
 void i915_gem_load(struct drm_device *dev);
 void *i915_gem_object_alloc(struct drm_device *dev);
 void i915_gem_object_free(struct drm_i915_gem_object *obj);
-int i915_gem_init_object(struct drm_gem_object *obj);
 void i915_gem_object_init(struct drm_i915_gem_object *obj,
                          const struct drm_i915_gem_object_ops *ops);
 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
                                                   size_t size);
 void i915_gem_free_object(struct drm_gem_object *obj);
-struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
-                                     struct i915_address_space *vm);
 void i915_gem_vma_destroy(struct i915_vma *vma);
 
 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
@@ -1868,9 +1917,8 @@ static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
                          struct intel_ring_buffer *to);
-void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
-                                    struct intel_ring_buffer *ring);
-
+void i915_vma_move_to_active(struct i915_vma *vma,
+                             struct intel_ring_buffer *ring);
 int i915_gem_dumb_create(struct drm_file *file_priv,
                          struct drm_device *dev,
                          struct drm_mode_create_dumb *args);
@@ -1911,7 +1959,7 @@ i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
         }
 }
 
-void i915_gem_retire_requests(struct drm_device *dev);
+bool i915_gem_retire_requests(struct drm_device *dev);
 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
                                       bool interruptible);
@@ -1931,7 +1979,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init(struct drm_device *dev);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
-void i915_gem_l3_remap(struct drm_device *dev);
+int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
 void i915_gem_init_swizzling(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 int __must_check i915_gpu_idle(struct drm_device *dev);
@@ -1962,6 +2010,7 @@ int i915_gem_attach_phys_object(struct drm_device *dev,
 void i915_gem_detach_phys_object(struct drm_device *dev,
                                  struct drm_i915_gem_object *obj);
 void i915_gem_free_all_phys_object(struct drm_device *dev);
+int i915_gem_open(struct drm_device *dev, struct drm_file *file);
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 
 uint32_t
@@ -1993,6 +2042,9 @@ struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
 struct i915_vma *
 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
                                   struct i915_address_space *vm);
+
+struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
+
 /* Some GGTT VM helpers */
 #define obj_to_ggtt(obj) \
         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
@@ -2029,7 +2081,6 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
         return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
                                    map_and_fenceable, nonblocking);
 }
-#undef obj_to_ggtt
 
 /* i915_gem_context.c */
 void i915_gem_context_init(struct drm_device *dev);
@@ -2090,6 +2141,7 @@ int __must_check i915_gem_evict_something(struct drm_device *dev,
                                           unsigned cache_level,
                                           bool mappable,
                                           bool nonblock);
+int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
 int i915_gem_evict_everything(struct drm_device *dev);
 
 /* i915_gem_stolen.c */
@@ -2182,15 +2234,30 @@ static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
 extern void intel_i2c_reset(struct drm_device *dev);
 
 /* intel_opregion.c */
+struct intel_encoder;
 extern int intel_opregion_setup(struct drm_device *dev);
 #ifdef CONFIG_ACPI
 extern void intel_opregion_init(struct drm_device *dev);
 extern void intel_opregion_fini(struct drm_device *dev);
 extern void intel_opregion_asle_intr(struct drm_device *dev);
+extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
+                                         bool enable);
+extern int intel_opregion_notify_adapter(struct drm_device *dev,
+                                         pci_power_t state);
 #else
 static inline void intel_opregion_init(struct drm_device *dev) { return; }
 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
+static inline int
+intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
+{
+        return 0;
+}
+static inline int
+intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
+{
+        return 0;
+}
 #endif
 
 /* intel_acpi.c */
@@ -2252,8 +2319,16 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
+u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
                    enum intel_sbi_destination destination);
 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cdfb9da0e4ce..13c885d66383 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -41,6 +41,9 @@ static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *o
 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
                                                    bool force);
 static __must_check int
+i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
+                               bool readonly);
+static __must_check int
 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
                            struct i915_address_space *vm,
                            unsigned alignment,
@@ -432,11 +435,9 @@ i915_gem_shmem_pread(struct drm_device *dev,
                  * optimizes for the case when the gpu will dirty the data
                  * anyway again before the next pread happens. */
                 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
-                if (i915_gem_obj_bound_any(obj)) {
-                        ret = i915_gem_object_set_to_gtt_domain(obj, false);
-                        if (ret)
-                                return ret;
-                }
+                ret = i915_gem_object_wait_rendering(obj, true);
+                if (ret)
+                        return ret;
         }
 
         ret = i915_gem_object_get_pages(obj);
@@ -748,11 +749,9 @@ i915_gem_shmem_pwrite(struct drm_device *dev,
                  * optimizes for the case when the gpu will use the data
                  * right away and we therefore have to clflush anyway. */
                 needs_clflush_after = cpu_write_needs_clflush(obj);
-                if (i915_gem_obj_bound_any(obj)) {
-                        ret = i915_gem_object_set_to_gtt_domain(obj, true);
-                        if (ret)
-                                return ret;
-                }
+                ret = i915_gem_object_wait_rendering(obj, false);
+                if (ret)
+                        return ret;
         }
         /* Same trick applies to invalidate partially written cachelines read
          * before writing. */
@@ -966,12 +965,31 @@ i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 
         ret = 0;
-        if (seqno == ring->outstanding_lazy_request)
+        if (seqno == ring->outstanding_lazy_seqno)
                 ret = i915_add_request(ring, NULL);
 
         return ret;
 }
 
+static void fake_irq(unsigned long data)
+{
+        wake_up_process((struct task_struct *)data);
+}
+
+static bool missed_irq(struct drm_i915_private *dev_priv,
+                       struct intel_ring_buffer *ring)
+{
+        return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
+}
+
+static bool can_wait_boost(struct drm_i915_file_private *file_priv)
+{
+        if (file_priv == NULL)
+                return true;
+
+        return !atomic_xchg(&file_priv->rps_wait_boost, true);
+}
+
 /**
  * __wait_seqno - wait until execution of seqno has finished
  * @ring: the ring expected to report seqno
@@ -992,13 +1010,14 @@ i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
  */
 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
                         unsigned reset_counter,
-                        bool interruptible, struct timespec *timeout)
+                        bool interruptible,
+                        struct timespec *timeout,
+                        struct drm_i915_file_private *file_priv)
 {
         drm_i915_private_t *dev_priv = ring->dev->dev_private;
-        struct timespec before, now, wait_time={1,0};
-        unsigned long timeout_jiffies;
-        long end;
-        bool wait_forever = true;
+        struct timespec before, now;
+        DEFINE_WAIT(wait);
+        long timeout_jiffies;
         int ret;
 
         WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
@@ -1006,51 +1025,79 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
                 return 0;
 
-        trace_i915_gem_request_wait_begin(ring, seqno);
+        timeout_jiffies = timeout ? timespec_to_jiffies_timeout(timeout) : 1;
 
-        if (timeout != NULL) {
-                wait_time = *timeout;
-                wait_forever = false;
+        if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {
+                gen6_rps_boost(dev_priv);
+                if (file_priv)
+                        mod_delayed_work(dev_priv->wq,
+                                         &file_priv->mm.idle_work,
+                                         msecs_to_jiffies(100));
         }
 
-        timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
-
-        if (WARN_ON(!ring->irq_get(ring)))
+        if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)) &&
+            WARN_ON(!ring->irq_get(ring)))
                 return -ENODEV;
 
-        /* Record current time in case interrupted by signal, or wedged * */
+        /* Record current time in case interrupted by signal, or wedged */
+        trace_i915_gem_request_wait_begin(ring, seqno);
         getrawmonotonic(&before);
+        for (;;) {
+                struct timer_list timer;
+                unsigned long expire;
 
-#define EXIT_COND \
-        (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
-         i915_reset_in_progress(&dev_priv->gpu_error) || \
-         reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
-        do {
-                if (interruptible)
-                        end = wait_event_interruptible_timeout(ring->irq_queue,
-                                                               EXIT_COND,
-                                                               timeout_jiffies);
-                else
-                        end = wait_event_timeout(ring->irq_queue, EXIT_COND,
-                                                 timeout_jiffies);
+                prepare_to_wait(&ring->irq_queue, &wait,
+                                interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 
                 /* We need to check whether any gpu reset happened in between
                  * the caller grabbing the seqno and now ... */
-                if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
-                        end = -EAGAIN;
+                if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
+                        /* ... but upgrade the -EAGAIN to an -EIO if the gpu
+                         * is truely gone. */
+                        ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
+                        if (ret == 0)
+                                ret = -EAGAIN;
+                        break;
+                }
 
-                /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
-                 * gone. */
-                ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
-                if (ret)
-                        end = ret;
-        } while (end == 0 && wait_forever);
+                if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
+                        ret = 0;
+                        break;
+                }
+
+                if (interruptible && signal_pending(current)) {
+                        ret = -ERESTARTSYS;
+                        break;
+                }
+
+                if (timeout_jiffies <= 0) {
+                        ret = -ETIME;
+                        break;
+                }
+
+                timer.function = NULL;
+                if (timeout || missed_irq(dev_priv, ring)) {
+                        setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
+                        expire = jiffies + (missed_irq(dev_priv, ring) ? 1: timeout_jiffies);
+                        mod_timer(&timer, expire);
+                }
+
+                schedule();
 
+                if (timeout)
+                        timeout_jiffies = expire - jiffies;
+
+                if (timer.function) {
+                        del_singleshot_timer_sync(&timer);
+                        destroy_timer_on_stack(&timer);
+                }
+        }
         getrawmonotonic(&now);
+        trace_i915_gem_request_wait_end(ring, seqno);
 
         ring->irq_put(ring);
-        trace_i915_gem_request_wait_end(ring, seqno);
-#undef EXIT_COND
+
+        finish_wait(&ring->irq_queue, &wait);
 
         if (timeout) {
                 struct timespec sleep_time = timespec_sub(now, before);
@@ -1059,17 +1106,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
                         set_normalized_timespec(timeout, 0, 0);
         }
 
-        switch (end) {
-        case -EIO:
-        case -EAGAIN: /* Wedged */
-        case -ERESTARTSYS: /* Signal */
-                return (int)end;
-        case 0: /* Timeout */
-                return -ETIME;
-        default: /* Completed */
-                WARN_ON(end < 0); /* We're not aware of other errors */
-                return 0;
-        }
+        return ret;
 }
 
 /**
@@ -1097,7 +1134,7 @@ i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
 
         return __wait_seqno(ring, seqno,
                             atomic_read(&dev_priv->gpu_error.reset_counter),
-                            interruptible, NULL);
+                            interruptible, NULL, NULL);
 }
 
 static int
@@ -1147,6 +1184,7 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  */
 static __must_check int
 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
+                                            struct drm_file *file,
                                             bool readonly)
 {
         struct drm_device *dev = obj->base.dev;
@@ -1173,7 +1211,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
 
         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
         mutex_unlock(&dev->struct_mutex);
-        ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
+        ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv);
         mutex_lock(&dev->struct_mutex);
         if (ret)
                 return ret;
@@ -1222,7 +1260,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
          * We will repeat the flush holding the lock in the normal manner
          * to catch cases where we are gazumped.
          */
-        ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
+        ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain);
         if (ret)
                 goto unref;
 
@@ -1918,7 +1956,7 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
         return 0;
 }
 
-void
+static void
 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
                                struct intel_ring_buffer *ring)
 {
@@ -1957,6 +1995,13 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
         }
 }
 
+void i915_vma_move_to_active(struct i915_vma *vma,
+                             struct intel_ring_buffer *ring)
+{
+        list_move_tail(&vma->mm_list, &vma->vm->active_list);
+        return i915_gem_object_move_to_active(vma->obj, ring);
+}
+
 static void
 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
 {
@@ -2078,11 +2123,10 @@ int __i915_add_request(struct intel_ring_buffer *ring,
         if (ret)
                 return ret;
 
-        request = kmalloc(sizeof(*request), GFP_KERNEL);
-        if (request == NULL)
+        request = ring->preallocated_lazy_request;
+        if (WARN_ON(request == NULL))
                 return -ENOMEM;
 
-
         /* Record the position of the start of the request so that
          * should we detect the updated seqno part-way through the
          * GPU processing the request, we never over-estimate the
@@ -2091,17 +2135,13 @@ int __i915_add_request(struct intel_ring_buffer *ring,
         request_ring_position = intel_ring_get_tail(ring);
 
         ret = ring->add_request(ring);
-        if (ret) {
-                kfree(request);
+        if (ret)
                 return ret;
-        }
 
         request->seqno = intel_ring_get_seqno(ring);
         request->ring = ring;
         request->head = request_start;
         request->tail = request_ring_position;
-        request->ctx = ring->last_context;
-        request->batch_obj = obj;
 
         /* Whilst this request exists, batch_obj will be on the
          * active_list, and so will hold the active reference. Only when this
@@ -2109,7 +2149,12 @@ int __i915_add_request(struct intel_ring_buffer *ring,
          * inactive_list and lose its active reference. Hence we do not need
          * to explicitly hold another reference here.
          */
+        request->batch_obj = obj;
 
+        /* Hold a reference to the current context so that we can inspect
+         * it later in case a hangcheck error event fires.
+         */
+        request->ctx = ring->last_context;
         if (request->ctx)
                 i915_gem_context_reference(request->ctx);
 
@@ -2129,12 +2174,14 @@ int __i915_add_request(struct intel_ring_buffer *ring,
         }
 
         trace_i915_gem_request_add(ring, request->seqno);
-        ring->outstanding_lazy_request = 0;
+        ring->outstanding_lazy_seqno = 0;
+        ring->preallocated_lazy_request = NULL;
 
         if (!dev_priv->ums.mm_suspended) {
                 i915_queue_hangcheck(ring->dev);
 
                 if (was_empty) {
+                        cancel_delayed_work_sync(&dev_priv->mm.idle_work);
                         queue_delayed_work(dev_priv->wq,
                                            &dev_priv->mm.retire_work,
                                            round_jiffies_up_relative(HZ));
@@ -2156,10 +2203,8 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
                 return;
 
         spin_lock(&file_priv->mm.lock);
-        if (request->file_priv) {
-                list_del(&request->client_list);
-                request->file_priv = NULL;
-        }
+        list_del(&request->client_list);
+        request->file_priv = NULL;
         spin_unlock(&file_priv->mm.lock);
 }
 
@@ -2224,6 +2269,21 @@ static bool i915_request_guilty(struct drm_i915_gem_request *request,
         return false;
 }
 
+static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
+{
+        const unsigned long elapsed = get_seconds() - hs->guilty_ts;
+
+        if (hs->banned)
+                return true;
+
+        if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
+                DRM_ERROR("context hanging too fast, declaring banned!\n");
+                return true;
+        }
+
+        return false;
+}
+
 static void i915_set_reset_status(struct intel_ring_buffer *ring,
                                   struct drm_i915_gem_request *request,
                                   u32 acthd)
@@ -2260,10 +2320,13 @@ static void i915_set_reset_status(struct intel_ring_buffer *ring,
                 hs = &request->file_priv->hang_stats;
 
         if (hs) {
-                if (guilty)
+                if (guilty) {
+                        hs->banned = i915_context_is_banned(hs);
                         hs->batch_active++;
-                else
+                        hs->guilty_ts = get_seconds();
+                } else {
                         hs->batch_pending++;
+                }
         }
 }
 
@@ -2405,57 +2468,53 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
         WARN_ON(i915_verify_lists(ring->dev));
 }
 
-void
+bool
 i915_gem_retire_requests(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
         struct intel_ring_buffer *ring;
+        bool idle = true;
         int i;
 
-        for_each_ring(ring, dev_priv, i)
+        for_each_ring(ring, dev_priv, i) {
                 i915_gem_retire_requests_ring(ring);
+                idle &= list_empty(&ring->request_list);
+        }
+
+        if (idle)
+                mod_delayed_work(dev_priv->wq,
+                                   &dev_priv->mm.idle_work,
+                                   msecs_to_jiffies(100));
+
+        return idle;
 }
 
 static void
 i915_gem_retire_work_handler(struct work_struct *work)
 {
-        drm_i915_private_t *dev_priv;
-        struct drm_device *dev;
-        struct intel_ring_buffer *ring;
+        struct drm_i915_private *dev_priv =
+                container_of(work, typeof(*dev_priv), mm.retire_work.work);
+        struct drm_device *dev = dev_priv->dev;
         bool idle;
-        int i;
-
-        dev_priv = container_of(work, drm_i915_private_t,
-                                mm.retire_work.work);
-        dev = dev_priv->dev;
 
         /* Come back later if the device is busy... */
-        if (!mutex_trylock(&dev->struct_mutex)) {
-                queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
-                                   round_jiffies_up_relative(HZ));
-                return;
-        }
-
-        i915_gem_retire_requests(dev);
-
-        /* Send a periodic flush down the ring so we don't hold onto GEM
-         * objects indefinitely.
-         */
-        idle = true;
-        for_each_ring(ring, dev_priv, i) {
-                if (ring->gpu_caches_dirty)
-                        i915_add_request(ring, NULL);
-
-                idle &= list_empty(&ring->request_list);
+        idle = false;
+        if (mutex_trylock(&dev->struct_mutex)) {
+                idle = i915_gem_retire_requests(dev);
+                mutex_unlock(&dev->struct_mutex);
         }
-
-        if (!dev_priv->ums.mm_suspended && !idle)
+        if (!idle)
                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
                                    round_jiffies_up_relative(HZ));
-        if (idle)
-                intel_mark_idle(dev);
+}
 
-        mutex_unlock(&dev->struct_mutex);
+static void
+i915_gem_idle_work_handler(struct work_struct *work)
+{
+        struct drm_i915_private *dev_priv =
+                container_of(work, typeof(*dev_priv), mm.idle_work.work);
+
+        intel_mark_idle(dev_priv->dev);
 }
 
 /**
@@ -2553,7 +2612,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
         mutex_unlock(&dev->struct_mutex);
 
-        ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
+        ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
         if (timeout)
                 args->timeout_ns = timespec_to_ns(timeout);
         return ret;
@@ -2600,6 +2659,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
         if (ret)
                 return ret;
 
+        trace_i915_gem_ring_sync_to(from, to, seqno);
         ret = to->sync_to(to, from, seqno);
         if (!ret)
                 /* We use last_read_seqno because sync_to()
@@ -2641,11 +2701,17 @@ int i915_vma_unbind(struct i915_vma *vma)
         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
         int ret;
 
+        /* For now we only ever use 1 vma per object */
+        WARN_ON(!list_is_singular(&obj->vma_list));
+
         if (list_empty(&vma->vma_link))
                 return 0;
 
-        if (!drm_mm_node_allocated(&vma->node))
-                goto destroy;
+        if (!drm_mm_node_allocated(&vma->node)) {
+                i915_gem_vma_destroy(vma);
+
+                return 0;
+        }
 
         if (obj->pin_count)
                 return -EBUSY;
@@ -2685,13 +2751,10 @@ int i915_vma_unbind(struct i915_vma *vma)
 
         drm_mm_remove_node(&vma->node);
 
-destroy:
         i915_gem_vma_destroy(vma);
 
         /* Since the unbound list is global, only move to that list if
-         * no more VMAs exist.
-         * NB: Until we have real VMAs there will only ever be one */
-        WARN_ON(!list_empty(&obj->vma_list));
+         * no more VMAs exist. */
         if (list_empty(&obj->vma_list))
                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
 
@@ -3389,8 +3452,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
 
         /* And bump the LRU for this access */
         if (i915_gem_object_is_inactive(obj)) {
-                struct i915_vma *vma = i915_gem_obj_to_vma(obj,
-                                                           &dev_priv->gtt.base);
+                struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
                 if (vma)
                         list_move_tail(&vma->mm_list,
                                        &dev_priv->gtt.base.inactive_list);
@@ -3761,7 +3823,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
         if (seqno == 0)
                 return 0;
 
-        ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
+        ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
         if (ret == 0)
                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
 
@@ -4015,7 +4077,6 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
 {
         INIT_LIST_HEAD(&obj->global_list);
         INIT_LIST_HEAD(&obj->ring_list);
-        INIT_LIST_HEAD(&obj->exec_list);
         INIT_LIST_HEAD(&obj->obj_exec_link);
         INIT_LIST_HEAD(&obj->vma_list);
 
@@ -4087,13 +4148,6 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
         return obj;
 }
 
-int i915_gem_init_object(struct drm_gem_object *obj)
-{
-        BUG();
-
-        return 0;
-}
-
 void i915_gem_free_object(struct drm_gem_object *gem_obj)
 {
         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
@@ -4147,9 +4201,20 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
         i915_gem_object_free(obj);
 }
 
-struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
+struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
                                      struct i915_address_space *vm)
 {
+        struct i915_vma *vma;
+        list_for_each_entry(vma, &obj->vma_list, vma_link)
+                if (vma->vm == vm)
+                        return vma;
+
+        return NULL;
+}
+
+static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
+                                              struct i915_address_space *vm)
+{
         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
         if (vma == NULL)
                 return ERR_PTR(-ENOMEM);
@@ -4169,10 +4234,29 @@ struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
         return vma;
 }
 
+struct i915_vma *
+i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
+                                  struct i915_address_space *vm)
+{
+        struct i915_vma *vma;
+
+        vma = i915_gem_obj_to_vma(obj, vm);
+        if (!vma)
+                vma = __i915_gem_vma_create(obj, vm);
+
+        return vma;
+}
+
 void i915_gem_vma_destroy(struct i915_vma *vma)
 {
         WARN_ON(vma->node.allocated);
+
+        /* Keep the vma as a placeholder in the execbuffer reservation lists */
+        if (!list_empty(&vma->exec_list))
+                return;
+
         list_del(&vma->vma_link);
+
         kfree(vma);
 }
 
@@ -4182,16 +4266,13 @@ i915_gem_idle(struct drm_device *dev)
         drm_i915_private_t *dev_priv = dev->dev_private;
         int ret;
 
-        if (dev_priv->ums.mm_suspended) {
-                mutex_unlock(&dev->struct_mutex);
+        if (dev_priv->ums.mm_suspended)
                 return 0;
-        }
 
         ret = i915_gpu_idle(dev);
-        if (ret) {
-                mutex_unlock(&dev->struct_mutex);
+        if (ret)
                 return ret;
-        }
+
         i915_gem_retire_requests(dev);
 
         /* Under UMS, be paranoid and evict. */
@@ -4205,40 +4286,40 @@ i915_gem_idle(struct drm_device *dev)
 
         /* Cancel the retire work handler, which should be idle now. */
         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
+        cancel_delayed_work_sync(&dev_priv->mm.idle_work);
 
         return 0;
 }
 
-void i915_gem_l3_remap(struct drm_device *dev)
+int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
 {
+        struct drm_device *dev = ring->dev;
         drm_i915_private_t *dev_priv = dev->dev_private;
-        u32 misccpctl;
-        int i;
+        u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
+        u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
+        int i, ret;
 
-        if (!HAS_L3_GPU_CACHE(dev))
-                return;
-
-        if (!dev_priv->l3_parity.remap_info)
-                return;
+        if (!HAS_L3_DPF(dev) || !remap_info)
+                return 0;
 
-        misccpctl = I915_READ(GEN7_MISCCPCTL);
-        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-        POSTING_READ(GEN7_MISCCPCTL);
+        ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
+        if (ret)
+                return ret;
 
+        /*
+         * Note: We do not worry about the concurrent register cacheline hang
+         * here because no other code should access these registers other than
+         * at initialization time.
+         */
         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
-                u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
-                if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
-                        DRM_DEBUG("0x%x was already programmed to %x\n",
-                                  GEN7_L3LOG_BASE + i, remap);
-                if (remap && !dev_priv->l3_parity.remap_info[i/4])
-                        DRM_DEBUG_DRIVER("Clearing remapped register\n");
-                I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
+                intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+                intel_ring_emit(ring, reg_base + i);
+                intel_ring_emit(ring, remap_info[i/4]);
         }
 
-        /* Make sure all the writes land before disabling dop clock gating */
-        POSTING_READ(GEN7_L3LOG_BASE);
+        intel_ring_advance(ring);
 
-        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+        return ret;
 }
 
 void i915_gem_init_swizzling(struct drm_device *dev)
@@ -4330,7 +4411,7 @@ int
 i915_gem_init_hw(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        int ret;
+        int ret, i;
 
         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
                 return -EIO;
@@ -4338,20 +4419,26 @@ i915_gem_init_hw(struct drm_device *dev)
         if (dev_priv->ellc_size)
                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
+        if (IS_HSW_GT3(dev))
+                I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
+        else
+                I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
+
         if (HAS_PCH_NOP(dev)) {
                 u32 temp = I915_READ(GEN7_MSG_CTL);
                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
                 I915_WRITE(GEN7_MSG_CTL, temp);
         }
 
-        i915_gem_l3_remap(dev);
-
         i915_gem_init_swizzling(dev);
 
         ret = i915_gem_init_rings(dev);
         if (ret)
                 return ret;
 
+        for (i = 0; i < NUM_L3_SLICES(dev); i++)
+                i915_gem_l3_remap(&dev_priv->ring[RCS], i);
+
         /*
          * XXX: There was some w/a described somewhere suggesting loading
          * contexts before PPGTT.
@@ -4523,6 +4610,7 @@ i915_gem_load(struct drm_device *dev)
         INIT_LIST_HEAD(&dev_priv->vm_list);
         i915_init_vm(dev_priv, &dev_priv->gtt.base);
 
+        INIT_LIST_HEAD(&dev_priv->context_list);
         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
@@ -4532,6 +4620,8 @@ i915_gem_load(struct drm_device *dev)
                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
                           i915_gem_retire_work_handler);
+        INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
+                          i915_gem_idle_work_handler);
         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
 
         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
@@ -4582,7 +4672,7 @@ static int i915_gem_init_phys_object(struct drm_device *dev,
         if (dev_priv->mm.phys_objs[id - 1] || !size)
                 return 0;
 
-        phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
+        phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
         if (!phys_obj)
                 return -ENOMEM;
 
@@ -4756,6 +4846,8 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file)
 {
         struct drm_i915_file_private *file_priv = file->driver_priv;
 
+        cancel_delayed_work_sync(&file_priv->mm.idle_work);
+
         /* Clean up our request list when the client is going away, so that
          * later retire_requests won't dereference our soon-to-be-gone
          * file_priv.
@@ -4773,6 +4865,38 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file)
         spin_unlock(&file_priv->mm.lock);
 }
 
+static void
+i915_gem_file_idle_work_handler(struct work_struct *work)
+{
+        struct drm_i915_file_private *file_priv =
+                container_of(work, typeof(*file_priv), mm.idle_work.work);
+
+        atomic_set(&file_priv->rps_wait_boost, false);
+}
+
+int i915_gem_open(struct drm_device *dev, struct drm_file *file)
+{
+        struct drm_i915_file_private *file_priv;
+
+        DRM_DEBUG_DRIVER("\n");
+
+        file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
+        if (!file_priv)
+                return -ENOMEM;
+
+        file->driver_priv = file_priv;
+        file_priv->dev_priv = dev->dev_private;
+
+        spin_lock_init(&file_priv->mm.lock);
+        INIT_LIST_HEAD(&file_priv->mm.request_list);
+        INIT_DELAYED_WORK(&file_priv->mm.idle_work,
+                          i915_gem_file_idle_work_handler);
+
+        idr_init(&file_priv->context_idr);
+
+        return 0;
+}
+
 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
 {
         if (!mutex_is_locked(mutex))
@@ -4859,11 +4983,10 @@ bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
 
 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
 {
-        struct drm_i915_private *dev_priv = o->base.dev->dev_private;
-        struct i915_address_space *vm;
+        struct i915_vma *vma;
 
-        list_for_each_entry(vm, &dev_priv->vm_list, global_link)
-                if (i915_gem_obj_bound(o, vm))
+        list_for_each_entry(vma, &o->vma_list, vma_link)
+                if (drm_mm_node_allocated(&vma->node))
                         return true;
 
         return false;
@@ -4921,26 +5044,16 @@ i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
         return freed;
 }
 
-struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
-                                     struct i915_address_space *vm)
+struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
 {
         struct i915_vma *vma;
-        list_for_each_entry(vma, &obj->vma_list, vma_link)
-                if (vma->vm == vm)
-                        return vma;
-
-        return NULL;
-}
 
-struct i915_vma *
-i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
-                                  struct i915_address_space *vm)
-{
-        struct i915_vma *vma;
+        if (WARN_ON(list_empty(&obj->vma_list)))
+                return NULL;
 
-        vma = i915_gem_obj_to_vma(obj, vm);
-        if (!vma)
-                vma = i915_gem_vma_create(obj, vm);
+        vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
+        if (WARN_ON(vma->vm != obj_to_ggtt(obj)))
+                return NULL;
 
         return vma;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 403309c2a7d6..1a877a547290 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -73,7 +73,7 @@
  *
  * There are two confusing terms used above:
  *  The "current context" means the context which is currently running on the
- *  GPU. The GPU has loaded it's state already and has stored away the gtt
+ *  GPU. The GPU has loaded its state already and has stored away the gtt
  *  offset of the BO. The GPU is not actively referencing the data at this
  *  offset, but it will on the next context switch. The only way to avoid this
  *  is to do a GPU reset.
@@ -129,6 +129,7 @@ void i915_gem_context_free(struct kref *ctx_ref)
         struct i915_hw_context *ctx = container_of(ctx_ref,
                                                    typeof(*ctx), ref);
 
+        list_del(&ctx->link);
         drm_gem_object_unreference(&ctx->obj->base);
         kfree(ctx);
 }
@@ -147,6 +148,7 @@ create_hw_context(struct drm_device *dev,
 
         kref_init(&ctx->ref);
         ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
+        INIT_LIST_HEAD(&ctx->link);
         if (ctx->obj == NULL) {
                 kfree(ctx);
                 DRM_DEBUG_DRIVER("Context object allocated failed\n");
@@ -166,6 +168,7 @@ create_hw_context(struct drm_device *dev,
          * assertion in the context switch code.
          */
         ctx->ring = &dev_priv->ring[RCS];
+        list_add_tail(&ctx->link, &dev_priv->context_list);
 
         /* Default context will never have a file_priv */
         if (file_priv == NULL)
@@ -178,6 +181,10 @@ create_hw_context(struct drm_device *dev,
 
         ctx->file_priv = file_priv;
         ctx->id = ret;
+        /* NB: Mark all slices as needing a remap so that when the context first
+         * loads it will restore whatever remap state already exists. If there
+         * is no remap info, it will be a NOP. */
+        ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
 
         return ctx;
 
@@ -393,11 +400,11 @@ static int do_switch(struct i915_hw_context *to)
         struct intel_ring_buffer *ring = to->ring;
         struct i915_hw_context *from = ring->last_context;
         u32 hw_flags = 0;
-        int ret;
+        int ret, i;
 
         BUG_ON(from != NULL && from->obj != NULL && from->obj->pin_count == 0);
 
-        if (from == to)
+        if (from == to && !to->remap_slice)
                 return 0;
 
         ret = i915_gem_obj_ggtt_pin(to->obj, CONTEXT_ALIGN, false, false);
@@ -420,8 +427,6 @@ static int do_switch(struct i915_hw_context *to)
 
         if (!to->is_initialized || is_default_context(to))
                 hw_flags |= MI_RESTORE_INHIBIT;
-        else if (WARN_ON_ONCE(from == to)) /* not yet expected */
-                hw_flags |= MI_FORCE_RESTORE;
 
         ret = mi_set_context(ring, to, hw_flags);
         if (ret) {
@@ -429,6 +434,18 @@ static int do_switch(struct i915_hw_context *to)
                 return ret;
         }
 
+        for (i = 0; i < MAX_L3_SLICES; i++) {
+                if (!(to->remap_slice & (1<<i)))
+                        continue;
+
+                ret = i915_gem_l3_remap(ring, i);
+                /* If it failed, try again next round */
+                if (ret)
+                        DRM_DEBUG_DRIVER("L3 remapping failed\n");
+                else
+                        to->remap_slice &= ~(1<<i);
+        }
+
         /* The backing object for the context is done after switching to the
          * *next* context. Therefore we cannot retire the previous context until
          * the next context has already started running. In fact, the below code
@@ -436,11 +453,8 @@ static int do_switch(struct i915_hw_context *to)
          * MI_SET_CONTEXT instead of when the next seqno has completed.
          */
         if (from != NULL) {
-                struct drm_i915_private *dev_priv = from->obj->base.dev->dev_private;
-                struct i915_address_space *ggtt = &dev_priv->gtt.base;
                 from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-                list_move_tail(&i915_gem_obj_to_vma(from->obj, ggtt)->mm_list, &ggtt->active_list);
-                i915_gem_object_move_to_active(from->obj, ring);
+                i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
                 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
                  * whole damn pipeline, we don't need to explicitly mark the
                  * object dirty. The only exception is that the context must be
@@ -451,17 +465,7 @@ static int do_switch(struct i915_hw_context *to)
                 from->obj->dirty = 1;
                 BUG_ON(from->obj->ring != ring);
 
-                ret = i915_add_request(ring, NULL);
-                if (ret) {
-                        /* Too late, we've already scheduled a context switch.
-                         * Try to undo the change so that the hw state is
-                         * consistent with out tracking. In case of emergency,
-                         * scream.
-                         */
-                        WARN_ON(mi_set_context(ring, from, MI_RESTORE_INHIBIT));
-                        return ret;
-                }
-
+                /* obj is kept alive until the next request by its active ref */
                 i915_gem_object_unpin(from->obj);
                 i915_gem_context_unreference(from);
         }
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index 91b700155850..b7376533633d 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -37,6 +37,9 @@ mark_free(struct i915_vma *vma, struct list_head *unwind)
         if (vma->obj->pin_count)
                 return false;
 
+        if (WARN_ON(!list_empty(&vma->exec_list)))
+                return false;
+
         list_add(&vma->exec_list, unwind);
         return drm_mm_scan_add_block(&vma->node);
 }
@@ -113,7 +116,7 @@ none:
         }
 
         /* We expect the caller to unpin, evict all and try again, or give up.
-         * So calling i915_gem_evict_everything() is unnecessary.
+         * So calling i915_gem_evict_vm() is unnecessary.
          */
         return -ENOSPC;
 
@@ -152,12 +155,48 @@ found:
         return ret;
 }
 
+/**
+ * i915_gem_evict_vm - Try to free up VM space
+ *
+ * @vm: Address space to evict from
+ * @do_idle: Boolean directing whether to idle first.
+ *
+ * VM eviction is about freeing up virtual address space. If one wants fine
+ * grained eviction, they should see evict something for more details. In terms
+ * of freeing up actual system memory, this function may not accomplish the
+ * desired result. An object may be shared in multiple address space, and this
+ * function will not assert those objects be freed.
+ *
+ * Using do_idle will result in a more complete eviction because it retires, and
+ * inactivates current BOs.
+ */
+int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle)
+{
+        struct i915_vma *vma, *next;
+        int ret;
+
+        trace_i915_gem_evict_vm(vm);
+
+        if (do_idle) {
+                ret = i915_gpu_idle(vm->dev);
+                if (ret)
+                        return ret;
+
+                i915_gem_retire_requests(vm->dev);
+        }
+
+        list_for_each_entry_safe(vma, next, &vm->inactive_list, mm_list)
+                if (vma->obj->pin_count == 0)
+                        WARN_ON(i915_vma_unbind(vma));
+
+        return 0;
+}
+
 int
 i915_gem_evict_everything(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
         struct i915_address_space *vm;
-        struct i915_vma *vma, *next;
         bool lists_empty = true;
         int ret;
 
@@ -184,11 +223,8 @@ i915_gem_evict_everything(struct drm_device *dev)
         i915_gem_retire_requests(dev);
 
         /* Having flushed everything, unbind() should never raise an error */
-        list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
-                list_for_each_entry_safe(vma, next, &vm->inactive_list, mm_list)
-                        if (vma->obj->pin_count == 0)
-                                WARN_ON(i915_vma_unbind(vma));
-        }
+        list_for_each_entry(vm, &dev_priv->vm_list, global_link)
+                WARN_ON(i915_gem_evict_vm(vm, false));
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index bf345777ae9f..0ce0d47e4b0f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -33,35 +33,35 @@
 #include "intel_drv.h"
 #include <linux/dma_remapping.h>
 
-struct eb_objects {
-        struct list_head objects;
+struct eb_vmas {
+        struct list_head vmas;
         int and;
         union {
-                struct drm_i915_gem_object *lut[0];
+                struct i915_vma *lut[0];
                 struct hlist_head buckets[0];
         };
 };
 
-static struct eb_objects *
-eb_create(struct drm_i915_gem_execbuffer2 *args)
+static struct eb_vmas *
+eb_create(struct drm_i915_gem_execbuffer2 *args, struct i915_address_space *vm)
 {
-        struct eb_objects *eb = NULL;
+        struct eb_vmas *eb = NULL;
 
         if (args->flags & I915_EXEC_HANDLE_LUT) {
-                int size = args->buffer_count;
-                size *= sizeof(struct drm_i915_gem_object *);
-                size += sizeof(struct eb_objects);
+                unsigned size = args->buffer_count;
+                size *= sizeof(struct i915_vma *);
+                size += sizeof(struct eb_vmas);
                 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
         }
 
         if (eb == NULL) {
-                int size = args->buffer_count;
-                int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
+                unsigned size = args->buffer_count;
+                unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
                 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
                 while (count > 2*size)
                         count >>= 1;
                 eb = kzalloc(count*sizeof(struct hlist_head) +
-                             sizeof(struct eb_objects),
+                             sizeof(struct eb_vmas),
                              GFP_TEMPORARY);
                 if (eb == NULL)
                         return eb;
@@ -70,64 +70,102 @@ eb_create(struct drm_i915_gem_execbuffer2 *args)
         } else
                 eb->and = -args->buffer_count;
 
-        INIT_LIST_HEAD(&eb->objects);
+        INIT_LIST_HEAD(&eb->vmas);
         return eb;
 }
 
 static void
-eb_reset(struct eb_objects *eb)
+eb_reset(struct eb_vmas *eb)
 {
         if (eb->and >= 0)
                 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 }
 
 static int
-eb_lookup_objects(struct eb_objects *eb,
-                  struct drm_i915_gem_exec_object2 *exec,
-                  const struct drm_i915_gem_execbuffer2 *args,
-                  struct drm_file *file)
+eb_lookup_vmas(struct eb_vmas *eb,
+               struct drm_i915_gem_exec_object2 *exec,
+               const struct drm_i915_gem_execbuffer2 *args,
+               struct i915_address_space *vm,
+               struct drm_file *file)
 {
-        int i;
+        struct drm_i915_gem_object *obj;
+        struct list_head objects;
+        int i, ret = 0;
 
+        INIT_LIST_HEAD(&objects);
         spin_lock(&file->table_lock);
+        /* Grab a reference to the object and release the lock so we can lookup
+         * or create the VMA without using GFP_ATOMIC */
         for (i = 0; i < args->buffer_count; i++) {
-                struct drm_i915_gem_object *obj;
-
                 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
                 if (obj == NULL) {
                         spin_unlock(&file->table_lock);
                         DRM_DEBUG("Invalid object handle %d at index %d\n",
                                    exec[i].handle, i);
-                        return -ENOENT;
+                        ret = -ENOENT;
+                        goto out;
                 }
 
-                if (!list_empty(&obj->exec_list)) {
+                if (!list_empty(&obj->obj_exec_link)) {
                         spin_unlock(&file->table_lock);
                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
                                    obj, exec[i].handle, i);
-                        return -EINVAL;
+                        ret = -EINVAL;
+                        goto out;
                 }
 
                 drm_gem_object_reference(&obj->base);
-                list_add_tail(&obj->exec_list, &eb->objects);
+                list_add_tail(&obj->obj_exec_link, &objects);
+        }
+        spin_unlock(&file->table_lock);
+
+        i = 0;
+        list_for_each_entry(obj, &objects, obj_exec_link) {
+                struct i915_vma *vma;
 
-                obj->exec_entry = &exec[i];
+                /*
+                 * NOTE: We can leak any vmas created here when something fails
+                 * later on. But that's no issue since vma_unbind can deal with
+                 * vmas which are not actually bound. And since only
+                 * lookup_or_create exists as an interface to get at the vma
+                 * from the (obj, vm) we don't run the risk of creating
+                 * duplicated vmas for the same vm.
+                 */
+                vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
+                if (IS_ERR(vma)) {
+                        DRM_DEBUG("Failed to lookup VMA\n");
+                        ret = PTR_ERR(vma);
+                        goto out;
+                }
+
+                list_add_tail(&vma->exec_list, &eb->vmas);
+
+                vma->exec_entry = &exec[i];
                 if (eb->and < 0) {
-                        eb->lut[i] = obj;
+                        eb->lut[i] = vma;
                 } else {
                         uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
-                        obj->exec_handle = handle;
-                        hlist_add_head(&obj->exec_node,
+                        vma->exec_handle = handle;
+                        hlist_add_head(&vma->exec_node,
                                        &eb->buckets[handle & eb->and]);
                 }
+                ++i;
         }
-        spin_unlock(&file->table_lock);
 
-        return 0;
+
+out:
+        while (!list_empty(&objects)) {
+                obj = list_first_entry(&objects,
+                                       struct drm_i915_gem_object,
+                                       obj_exec_link);
+                list_del_init(&obj->obj_exec_link);
+                if (ret)
+                        drm_gem_object_unreference(&obj->base);
+        }
+        return ret;
 }
 
-static struct drm_i915_gem_object *
-eb_get_object(struct eb_objects *eb, unsigned long handle)
+static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
 {
         if (eb->and < 0) {
                 if (handle >= -eb->and)
@@ -139,34 +177,33 @@ eb_get_object(struct eb_objects *eb, unsigned long handle)
 
                 head = &eb->buckets[handle & eb->and];
                 hlist_for_each(node, head) {
-                        struct drm_i915_gem_object *obj;
+                        struct i915_vma *vma;
 
-                        obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
-                        if (obj->exec_handle == handle)
-                                return obj;
+                        vma = hlist_entry(node, struct i915_vma, exec_node);
+                        if (vma->exec_handle == handle)
+                                return vma;
                 }
                 return NULL;
         }
 }
 
-static void
-eb_destroy(struct eb_objects *eb)
-{
-        while (!list_empty(&eb->objects)) {
-                struct drm_i915_gem_object *obj;
+static void eb_destroy(struct eb_vmas *eb) {
+        while (!list_empty(&eb->vmas)) {
+                struct i915_vma *vma;
 
-                obj = list_first_entry(&eb->objects,
-                                       struct drm_i915_gem_object,
+                vma = list_first_entry(&eb->vmas,
+                                       struct i915_vma,
                                        exec_list);
-                list_del_init(&obj->exec_list);
-                drm_gem_object_unreference(&obj->base);
+                list_del_init(&vma->exec_list);
+                drm_gem_object_unreference(&vma->obj->base);
         }
         kfree(eb);
 }
 
 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 {
-        return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
+        return (HAS_LLC(obj->base.dev) ||
+                obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
                 !obj->map_and_fenceable ||
                 obj->cache_level != I915_CACHE_NONE);
 }
@@ -179,7 +216,7 @@ relocate_entry_cpu(struct drm_i915_gem_object *obj,
         char *vaddr;
         int ret = -EINVAL;
 
-        ret = i915_gem_object_set_to_cpu_domain(obj, 1);
+        ret = i915_gem_object_set_to_cpu_domain(obj, true);
         if (ret)
                 return ret;
 
@@ -223,22 +260,24 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj,
 
 static int
 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
-                                   struct eb_objects *eb,
+                                   struct eb_vmas *eb,
                                    struct drm_i915_gem_relocation_entry *reloc,
                                    struct i915_address_space *vm)
 {
         struct drm_device *dev = obj->base.dev;
         struct drm_gem_object *target_obj;
         struct drm_i915_gem_object *target_i915_obj;
+        struct i915_vma *target_vma;
         uint32_t target_offset;
         int ret = -EINVAL;
 
         /* we've already hold a reference to all valid objects */
-        target_obj = &eb_get_object(eb, reloc->target_handle)->base;
-        if (unlikely(target_obj == NULL))
+        target_vma = eb_get_vma(eb, reloc->target_handle);
+        if (unlikely(target_vma == NULL))
                 return -ENOENT;
+        target_i915_obj = target_vma->obj;
+        target_obj = &target_vma->obj->base;
 
-        target_i915_obj = to_intel_bo(target_obj);
         target_offset = i915_gem_obj_ggtt_offset(target_i915_obj);
 
         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
@@ -320,14 +359,13 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 }
 
 static int
-i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
-                                    struct eb_objects *eb,
-                                    struct i915_address_space *vm)
+i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
+                                 struct eb_vmas *eb)
 {
 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
         struct drm_i915_gem_relocation_entry __user *user_relocs;
-        struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
+        struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
         int remain, ret;
 
         user_relocs = to_user_ptr(entry->relocs_ptr);
@@ -346,8 +384,8 @@ i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
                 do {
                         u64 offset = r->presumed_offset;
 
-                        ret = i915_gem_execbuffer_relocate_entry(obj, eb, r,
-                                                                 vm);
+                        ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r,
+                                                                 vma->vm);
                         if (ret)
                                 return ret;
 
@@ -368,17 +406,16 @@ i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
 }
 
 static int
-i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
-                                         struct eb_objects *eb,
-                                         struct drm_i915_gem_relocation_entry *relocs,
-                                         struct i915_address_space *vm)
+i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
+                                      struct eb_vmas *eb,
+                                      struct drm_i915_gem_relocation_entry *relocs)
 {
-        const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
+        const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
         int i, ret;
 
         for (i = 0; i < entry->relocation_count; i++) {
-                ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i],
-                                                         vm);
+                ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i],
+                                                         vma->vm);
                 if (ret)
                         return ret;
         }
@@ -387,10 +424,10 @@ i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
 }
 
 static int
-i915_gem_execbuffer_relocate(struct eb_objects *eb,
+i915_gem_execbuffer_relocate(struct eb_vmas *eb,
                              struct i915_address_space *vm)
 {
-        struct drm_i915_gem_object *obj;
+        struct i915_vma *vma;
         int ret = 0;
 
         /* This is the fast path and we cannot handle a pagefault whilst
@@ -401,8 +438,8 @@ i915_gem_execbuffer_relocate(struct eb_objects *eb,
          * lockdep complains vehemently.
          */
         pagefault_disable();
-        list_for_each_entry(obj, &eb->objects, exec_list) {
-                ret = i915_gem_execbuffer_relocate_object(obj, eb, vm);
+        list_for_each_entry(vma, &eb->vmas, exec_list) {
+                ret = i915_gem_execbuffer_relocate_vma(vma, eb);
                 if (ret)
                         break;
         }
@@ -415,31 +452,32 @@ i915_gem_execbuffer_relocate(struct eb_objects *eb,
 #define  __EXEC_OBJECT_HAS_FENCE (1<<30)
 
 static int
-need_reloc_mappable(struct drm_i915_gem_object *obj)
+need_reloc_mappable(struct i915_vma *vma)
 {
-        struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
-        return entry->relocation_count && !use_cpu_reloc(obj);
+        struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
+        return entry->relocation_count && !use_cpu_reloc(vma->obj) &&
+                i915_is_ggtt(vma->vm);
 }
 
 static int
-i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
-                                   struct intel_ring_buffer *ring,
-                                   struct i915_address_space *vm,
-                                   bool *need_reloc)
+i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
+                                struct intel_ring_buffer *ring,
+                                bool *need_reloc)
 {
-        struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-        struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
+        struct drm_i915_private *dev_priv = ring->dev->dev_private;
+        struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
         bool need_fence, need_mappable;
+        struct drm_i915_gem_object *obj = vma->obj;
         int ret;
 
         need_fence =
                 has_fenced_gpu_access &&
                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
                 obj->tiling_mode != I915_TILING_NONE;
-        need_mappable = need_fence || need_reloc_mappable(obj);
+        need_mappable = need_fence || need_reloc_mappable(vma);
 
-        ret = i915_gem_object_pin(obj, vm, entry->alignment, need_mappable,
+        ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable,
                                   false);
         if (ret)
                 return ret;
@@ -467,8 +505,8 @@ i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
                 obj->has_aliasing_ppgtt_mapping = 1;
         }
 
-        if (entry->offset != i915_gem_obj_offset(obj, vm)) {
-                entry->offset = i915_gem_obj_offset(obj, vm);
+        if (entry->offset != vma->node.start) {
+                entry->offset = vma->node.start;
                 *need_reloc = true;
         }
 
@@ -485,14 +523,15 @@ i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
 }
 
 static void
-i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
+i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
 {
         struct drm_i915_gem_exec_object2 *entry;
+        struct drm_i915_gem_object *obj = vma->obj;
 
-        if (!i915_gem_obj_bound_any(obj))
+        if (!drm_mm_node_allocated(&vma->node))
                 return;
 
-        entry = obj->exec_entry;
+        entry = vma->exec_entry;
 
         if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
                 i915_gem_object_unpin_fence(obj);
@@ -505,41 +544,46 @@ i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
 
 static int
 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
-                            struct list_head *objects,
-                            struct i915_address_space *vm,
+                            struct list_head *vmas,
                             bool *need_relocs)
 {
         struct drm_i915_gem_object *obj;
-        struct list_head ordered_objects;
+        struct i915_vma *vma;
+        struct i915_address_space *vm;
+        struct list_head ordered_vmas;
         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
         int retry;
 
-        INIT_LIST_HEAD(&ordered_objects);
-        while (!list_empty(objects)) {
+        if (list_empty(vmas))
+                return 0;
+
+        vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
+
+        INIT_LIST_HEAD(&ordered_vmas);
+        while (!list_empty(vmas)) {
                 struct drm_i915_gem_exec_object2 *entry;
                 bool need_fence, need_mappable;
 
-                obj = list_first_entry(objects,
-                                       struct drm_i915_gem_object,
-                                       exec_list);
-                entry = obj->exec_entry;
+                vma = list_first_entry(vmas, struct i915_vma, exec_list);
+                obj = vma->obj;
+                entry = vma->exec_entry;
 
                 need_fence =
                         has_fenced_gpu_access &&
                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
                         obj->tiling_mode != I915_TILING_NONE;
-                need_mappable = need_fence || need_reloc_mappable(obj);
+                need_mappable = need_fence || need_reloc_mappable(vma);
 
                 if (need_mappable)
-                        list_move(&obj->exec_list, &ordered_objects);
+                        list_move(&vma->exec_list, &ordered_vmas);
                 else
-                        list_move_tail(&obj->exec_list, &ordered_objects);
+                        list_move_tail(&vma->exec_list, &ordered_vmas);
 
                 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
                 obj->base.pending_write_domain = 0;
                 obj->pending_fenced_gpu_access = false;
         }
-        list_splice(&ordered_objects, objects);
+        list_splice(&ordered_vmas, vmas);
 
         /* Attempt to pin all of the buffers into the GTT.
          * This is done in 3 phases:
@@ -558,52 +602,52 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
                 int ret = 0;
 
                 /* Unbind any ill-fitting objects or pin. */
-                list_for_each_entry(obj, objects, exec_list) {
-                        struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
+                list_for_each_entry(vma, vmas, exec_list) {
+                        struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
                         bool need_fence, need_mappable;
-                        u32 obj_offset;
 
-                        if (!i915_gem_obj_bound(obj, vm))
+                        obj = vma->obj;
+
+                        if (!drm_mm_node_allocated(&vma->node))
                                 continue;
 
-                        obj_offset = i915_gem_obj_offset(obj, vm);
                         need_fence =
                                 has_fenced_gpu_access &&
                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
                                 obj->tiling_mode != I915_TILING_NONE;
-                        need_mappable = need_fence || need_reloc_mappable(obj);
+                        need_mappable = need_fence || need_reloc_mappable(vma);
 
                         WARN_ON((need_mappable || need_fence) &&
-                                !i915_is_ggtt(vm));
+                               !i915_is_ggtt(vma->vm));
 
                         if ((entry->alignment &&
-                             obj_offset & (entry->alignment - 1)) ||
+                             vma->node.start & (entry->alignment - 1)) ||
                             (need_mappable && !obj->map_and_fenceable))
-                                ret = i915_vma_unbind(i915_gem_obj_to_vma(obj, vm));
+                                ret = i915_vma_unbind(vma);
                         else
-                                ret = i915_gem_execbuffer_reserve_object(obj, ring, vm, need_relocs);
+                                ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
                         if (ret)
                                 goto err;
                 }
 
                 /* Bind fresh objects */
-                list_for_each_entry(obj, objects, exec_list) {
-                        if (i915_gem_obj_bound(obj, vm))
+                list_for_each_entry(vma, vmas, exec_list) {
+                        if (drm_mm_node_allocated(&vma->node))
                                 continue;
 
-                        ret = i915_gem_execbuffer_reserve_object(obj, ring, vm, need_relocs);
+                        ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
                         if (ret)
                                 goto err;
                 }
 
 err:            /* Decrement pin count for bound objects */
-                list_for_each_entry(obj, objects, exec_list)
-                        i915_gem_execbuffer_unreserve_object(obj);
+                list_for_each_entry(vma, vmas, exec_list)
+                        i915_gem_execbuffer_unreserve_vma(vma);
 
                 if (ret != -ENOSPC || retry++)
                         return ret;
 
-                ret = i915_gem_evict_everything(ring->dev);
+                ret = i915_gem_evict_vm(vm, true);
                 if (ret)
                         return ret;
         } while (1);
@@ -614,24 +658,27 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
                                   struct drm_i915_gem_execbuffer2 *args,
                                   struct drm_file *file,
                                   struct intel_ring_buffer *ring,
-                                  struct eb_objects *eb,
-                                  struct drm_i915_gem_exec_object2 *exec,
-                                  struct i915_address_space *vm)
+                                  struct eb_vmas *eb,
+                                  struct drm_i915_gem_exec_object2 *exec)
 {
         struct drm_i915_gem_relocation_entry *reloc;
-        struct drm_i915_gem_object *obj;
+        struct i915_address_space *vm;
+        struct i915_vma *vma;
         bool need_relocs;
         int *reloc_offset;
         int i, total, ret;
-        int count = args->buffer_count;
+        unsigned count = args->buffer_count;
+
+        if (WARN_ON(list_empty(&eb->vmas)))
+                return 0;
+
+        vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
 
         /* We may process another execbuffer during the unlock... */
-        while (!list_empty(&eb->objects)) {
-                obj = list_first_entry(&eb->objects,
-                                       struct drm_i915_gem_object,
-                                       exec_list);
-                list_del_init(&obj->exec_list);
-                drm_gem_object_unreference(&obj->base);
+        while (!list_empty(&eb->vmas)) {
+                vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
+                list_del_init(&vma->exec_list);
+                drm_gem_object_unreference(&vma->obj->base);
         }
 
         mutex_unlock(&dev->struct_mutex);
@@ -695,20 +742,19 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 
         /* reacquire the objects */
         eb_reset(eb);
-        ret = eb_lookup_objects(eb, exec, args, file);
+        ret = eb_lookup_vmas(eb, exec, args, vm, file);
         if (ret)
                 goto err;
 
         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
-        ret = i915_gem_execbuffer_reserve(ring, &eb->objects, vm, &need_relocs);
+        ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
         if (ret)
                 goto err;
 
-        list_for_each_entry(obj, &eb->objects, exec_list) {
-                int offset = obj->exec_entry - exec;
-                ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
-                                                               reloc + reloc_offset[offset],
-                                                               vm);
+        list_for_each_entry(vma, &eb->vmas, exec_list) {
+                int offset = vma->exec_entry - exec;
+                ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
+                                                            reloc + reloc_offset[offset]);
                 if (ret)
                         goto err;
         }
@@ -727,14 +773,15 @@ err:
 
 static int
 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
-                                struct list_head *objects)
+                                struct list_head *vmas)
 {
-        struct drm_i915_gem_object *obj;
+        struct i915_vma *vma;
         uint32_t flush_domains = 0;
         bool flush_chipset = false;
         int ret;
 
-        list_for_each_entry(obj, objects, exec_list) {
+        list_for_each_entry(vma, vmas, exec_list) {
+                struct drm_i915_gem_object *obj = vma->obj;
                 ret = i915_gem_object_sync(obj, ring);
                 if (ret)
                         return ret;
@@ -771,8 +818,8 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
                    int count)
 {
         int i;
-        int relocs_total = 0;
-        int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
+        unsigned relocs_total = 0;
+        unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
 
         for (i = 0; i < count; i++) {
                 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
@@ -809,13 +856,13 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 }
 
 static void
-i915_gem_execbuffer_move_to_active(struct list_head *objects,
-                                   struct i915_address_space *vm,
+i915_gem_execbuffer_move_to_active(struct list_head *vmas,
                                    struct intel_ring_buffer *ring)
 {
-        struct drm_i915_gem_object *obj;
+        struct i915_vma *vma;
 
-        list_for_each_entry(obj, objects, exec_list) {
+        list_for_each_entry(vma, vmas, exec_list) {
+                struct drm_i915_gem_object *obj = vma->obj;
                 u32 old_read = obj->base.read_domains;
                 u32 old_write = obj->base.write_domain;
 
@@ -825,9 +872,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
                 obj->base.read_domains = obj->base.pending_read_domains;
                 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
 
-                /* FIXME: This lookup gets fixed later <-- danvet */
-                list_move_tail(&i915_gem_obj_to_vma(obj, vm)->mm_list, &vm->active_list);
-                i915_gem_object_move_to_active(obj, ring);
+                i915_vma_move_to_active(vma, ring);
                 if (obj->base.write_domain) {
                         obj->dirty = 1;
                         obj->last_write_seqno = intel_ring_get_seqno(ring);
@@ -885,10 +930,11 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                        struct i915_address_space *vm)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        struct eb_objects *eb;
+        struct eb_vmas *eb;
         struct drm_i915_gem_object *batch_obj;
         struct drm_clip_rect *cliprects = NULL;
         struct intel_ring_buffer *ring;
+        struct i915_ctx_hang_stats *hs;
         u32 ctx_id = i915_execbuffer2_get_context_id(*args);
         u32 exec_start, exec_len;
         u32 mask, flags;
@@ -1000,7 +1046,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                         return -EINVAL;
                 }
 
-                cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
+                cliprects = kcalloc(args->num_cliprects,
+                                    sizeof(*cliprects),
                                     GFP_KERNEL);
                 if (cliprects == NULL) {
                         ret = -ENOMEM;
@@ -1025,7 +1072,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                 goto pre_mutex_err;
         }
 
-        eb = eb_create(args);
+        eb = eb_create(args, vm);
         if (eb == NULL) {
                 mutex_unlock(&dev->struct_mutex);
                 ret = -ENOMEM;
@@ -1033,18 +1080,16 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         }
 
         /* Look up object handles */
-        ret = eb_lookup_objects(eb, exec, args, file);
+        ret = eb_lookup_vmas(eb, exec, args, vm, file);
         if (ret)
                 goto err;
 
         /* take note of the batch buffer before we might reorder the lists */
-        batch_obj = list_entry(eb->objects.prev,
-                               struct drm_i915_gem_object,
-                               exec_list);
+        batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj;
 
         /* Move the objects en-masse into the GTT, evicting if necessary. */
         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
-        ret = i915_gem_execbuffer_reserve(ring, &eb->objects, vm, &need_relocs);
+        ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
         if (ret)
                 goto err;
 
@@ -1054,7 +1099,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         if (ret) {
                 if (ret == -EFAULT) {
                         ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
-                                                                eb, exec, vm);
+                                                                eb, exec);
                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
                 }
                 if (ret)
@@ -1076,10 +1121,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
                 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
 
-        ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
+        ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas);
         if (ret)
                 goto err;
 
+        hs = i915_gem_context_get_hang_stats(dev, file, ctx_id);
+        if (IS_ERR(hs)) {
+                ret = PTR_ERR(hs);
+                goto err;
+        }
+
+        if (hs->banned) {
+                ret = -EIO;
+                goto err;
+        }
+
         ret = i915_switch_context(ring, file, ctx_id);
         if (ret)
                 goto err;
@@ -1131,7 +1187,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 
         trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
 
-        i915_gem_execbuffer_move_to_active(&eb->objects, vm, ring);
+        i915_gem_execbuffer_move_to_active(&eb->vmas, ring);
         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 
 err:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 212f6d8c35ec..e999496532c6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -336,7 +336,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
-        ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
+        ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
                                   GFP_KERNEL);
         if (!ppgtt->pt_pages)
                 return -ENOMEM;
@@ -347,7 +347,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
                         goto err_pt_alloc;
         }
 
-        ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
+        ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
                                      GFP_KERNEL);
         if (!ppgtt->pt_dma_addr)
                 goto err_pt_alloc;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index e15a1d90037d..d284d892ed94 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -395,7 +395,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
         if (gtt_offset == I915_GTT_OFFSET_NONE)
                 return obj;
 
-        vma = i915_gem_vma_create(obj, ggtt);
+        vma = i915_gem_obj_lookup_or_create_vma(obj, ggtt);
         if (IS_ERR(vma)) {
                 ret = PTR_ERR(vma);
                 goto err_out;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 032e9ef9c896..ac9ebe98f8b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -393,7 +393,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
         /* Try to preallocate memory required to save swizzling on put-pages */
         if (i915_gem_object_needs_bit17_swizzle(obj)) {
                 if (obj->bit_17 == NULL) {
-                        obj->bit_17 = kmalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT) *
+                        obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
                                               sizeof(long), GFP_KERNEL);
                 }
         } else {
@@ -504,8 +504,8 @@ i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
         int i;
 
         if (obj->bit_17 == NULL) {
-                obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
-                                           sizeof(long), GFP_KERNEL);
+                obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
+                                      sizeof(long), GFP_KERNEL);
                 if (obj->bit_17 == NULL) {
                         DRM_ERROR("Failed to allocate memory for bit 17 "
                                   "record\n");
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index dae364f0028c..915c8ca08969 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -215,6 +215,24 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
         }
 }
 
+static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
+{
+        switch (a) {
+        case HANGCHECK_IDLE:
+                return "idle";
+        case HANGCHECK_WAIT:
+                return "wait";
+        case HANGCHECK_ACTIVE:
+                return "active";
+        case HANGCHECK_KICK:
+                return "kick";
+        case HANGCHECK_HUNG:
+                return "hung";
+        }
+
+        return "unknown";
+}
+
 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
                                   struct drm_device *dev,
                                   struct drm_i915_error_state *error,
@@ -255,6 +273,9 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
         err_printf(m, "  waiting: %s\n", yesno(error->waiting[ring]));
         err_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
         err_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
+        err_printf(m, "  hangcheck: %s [%d]\n",
+                   hangcheck_action_to_str(error->hangcheck_action[ring]),
+                   error->hangcheck_score[ring]);
 }
 
 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
@@ -283,13 +304,14 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
         err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
                    error->time.tv_usec);
         err_printf(m, "Kernel: " UTS_RELEASE "\n");
-        err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
+        err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
         err_printf(m, "EIR: 0x%08x\n", error->eir);
         err_printf(m, "IER: 0x%08x\n", error->ier);
         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
         err_printf(m, "CCID: 0x%08x\n", error->ccid);
+        err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 
         for (i = 0; i < dev_priv->num_fence_regs; i++)
                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
@@ -720,6 +742,9 @@ static void i915_record_ring_state(struct drm_device *dev,
 
         error->cpu_ring_head[ring->id] = ring->head;
         error->cpu_ring_tail[ring->id] = ring->tail;
+
+        error->hangcheck_score[ring->id] = ring->hangcheck.score;
+        error->hangcheck_action[ring->id] = ring->hangcheck.action;
 }
 
 
@@ -769,7 +794,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
 
                 error->ring[i].num_requests = count;
                 error->ring[i].requests =
-                        kmalloc(count*sizeof(struct drm_i915_error_request),
+                        kcalloc(count, sizeof(*error->ring[i].requests),
                                 GFP_ATOMIC);
                 if (error->ring[i].requests == NULL) {
                         error->ring[i].num_requests = 0;
@@ -811,7 +836,7 @@ static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
         error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
 
         if (i) {
-                active_bo = kmalloc(sizeof(*active_bo)*i, GFP_ATOMIC);
+                active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
                 if (active_bo)
                         pinned_bo = active_bo + error->active_bo_count[ndx];
         }
@@ -988,6 +1013,7 @@ const char *i915_cache_level_str(int type)
         case I915_CACHE_NONE: return " uncached";
         case I915_CACHE_LLC: return " snooped or LLC";
         case I915_CACHE_L3_LLC: return " L3+LLC";
+        case I915_CACHE_WT: return " WT";
         default: return "";
         }
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b91228fd9bd..d1739d3bdae9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -665,7 +665,8 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
                                                      crtc);
 }
 
-static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
+static bool intel_hpd_irq_event(struct drm_device *dev,
+                                struct drm_connector *connector)
 {
         enum drm_connector_status old_status;
 
@@ -673,11 +674,16 @@ static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *con
         old_status = connector->status;
 
         connector->status = connector->funcs->detect(connector, false);
-        DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
+        if (old_status == connector->status)
+                return false;
+
+        DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
                       connector->base.id,
                       drm_get_connector_name(connector),
-                      old_status, connector->status);
-        return (old_status != connector->status);
+                      drm_get_connector_status_name(old_status),
+                      drm_get_connector_status_name(connector->status));
+
+        return true;
 }
 
 /*
@@ -801,7 +807,7 @@ static void notify_ring(struct drm_device *dev,
         if (ring->obj == NULL)
                 return;
 
-        trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
+        trace_i915_gem_request_complete(ring);
 
         wake_up_all(&ring->irq_queue);
         i915_queue_hangcheck(dev);
@@ -812,7 +818,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
                                                     rps.work);
         u32 pm_iir;
-        u8 new_delay;
+        int new_delay, adj;
 
         spin_lock_irq(&dev_priv->irq_lock);
         pm_iir = dev_priv->rps.pm_iir;
@@ -829,40 +835,49 @@ static void gen6_pm_rps_work(struct work_struct *work)
 
         mutex_lock(&dev_priv->rps.hw_lock);
 
+        adj = dev_priv->rps.last_adj;
         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
-                new_delay = dev_priv->rps.cur_delay + 1;
+                if (adj > 0)
+                        adj *= 2;
+                else
+                        adj = 1;
+                new_delay = dev_priv->rps.cur_delay + adj;
 
                 /*
                  * For better performance, jump directly
                  * to RPe if we're below it.
                  */
-                if (IS_VALLEYVIEW(dev_priv->dev) &&
-                    dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
+                if (new_delay < dev_priv->rps.rpe_delay)
                         new_delay = dev_priv->rps.rpe_delay;
-        } else
-                new_delay = dev_priv->rps.cur_delay - 1;
+        } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
+                if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
+                        new_delay = dev_priv->rps.rpe_delay;
+                else
+                        new_delay = dev_priv->rps.min_delay;
+                adj = 0;
+        } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
+                if (adj < 0)
+                        adj *= 2;
+                else
+                        adj = -1;
+                new_delay = dev_priv->rps.cur_delay + adj;
+        } else { /* unknown event */
+                new_delay = dev_priv->rps.cur_delay;
+        }
 
         /* sysfs frequency interfaces may have snuck in while servicing the
          * interrupt
          */
-        if (new_delay >= dev_priv->rps.min_delay &&
-            new_delay <= dev_priv->rps.max_delay) {
-                if (IS_VALLEYVIEW(dev_priv->dev))
-                        valleyview_set_rps(dev_priv->dev, new_delay);
-                else
-                        gen6_set_rps(dev_priv->dev, new_delay);
-        }
-
-        if (IS_VALLEYVIEW(dev_priv->dev)) {
-                /*
-                 * On VLV, when we enter RC6 we may not be at the minimum
-                 * voltage level, so arm a timer to check.  It should only
-                 * fire when there's activity or once after we've entered
-                 * RC6, and then won't be re-armed until the next RPS interrupt.
-                 */
-                mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
-                                 msecs_to_jiffies(100));
-        }
+        if (new_delay < (int)dev_priv->rps.min_delay)
+                new_delay = dev_priv->rps.min_delay;
+        if (new_delay > (int)dev_priv->rps.max_delay)
+                new_delay = dev_priv->rps.max_delay;
+        dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
+
+        if (IS_VALLEYVIEW(dev_priv->dev))
+                valleyview_set_rps(dev_priv->dev, new_delay);
+        else
+                gen6_set_rps(dev_priv->dev, new_delay);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -882,9 +897,10 @@ static void ivybridge_parity_work(struct work_struct *work)
         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
                                                     l3_parity.error_work);
         u32 error_status, row, bank, subbank;
-        char *parity_event[5];
+        char *parity_event[6];
         uint32_t misccpctl;
         unsigned long flags;
+        uint8_t slice = 0;
 
         /* We must turn off DOP level clock gating to access the L3 registers.
          * In order to prevent a get/put style interface, acquire struct mutex
@@ -892,55 +908,81 @@ static void ivybridge_parity_work(struct work_struct *work)
          */
         mutex_lock(&dev_priv->dev->struct_mutex);
 
+        /* If we've screwed up tracking, just let the interrupt fire again */
+        if (WARN_ON(!dev_priv->l3_parity.which_slice))
+                goto out;
+
         misccpctl = I915_READ(GEN7_MISCCPCTL);
         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
         POSTING_READ(GEN7_MISCCPCTL);
 
-        error_status = I915_READ(GEN7_L3CDERRST1);
-        row = GEN7_PARITY_ERROR_ROW(error_status);
-        bank = GEN7_PARITY_ERROR_BANK(error_status);
-        subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
+        while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
+                u32 reg;
 
-        I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
-                                    GEN7_L3CDERRST1_ENABLE);
-        POSTING_READ(GEN7_L3CDERRST1);
+                slice--;
+                if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
+                        break;
 
-        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+                dev_priv->l3_parity.which_slice &= ~(1<<slice);
 
-        spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
-        spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+                reg = GEN7_L3CDERRST1 + (slice * 0x200);
 
-        mutex_unlock(&dev_priv->dev->struct_mutex);
+                error_status = I915_READ(reg);
+                row = GEN7_PARITY_ERROR_ROW(error_status);
+                bank = GEN7_PARITY_ERROR_BANK(error_status);
+                subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
+
+                I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
+                POSTING_READ(reg);
 
-        parity_event[0] = I915_L3_PARITY_UEVENT "=1";
-        parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
-        parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
-        parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
-        parity_event[4] = NULL;
+                parity_event[0] = I915_L3_PARITY_UEVENT "=1";
+                parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
+                parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
+                parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
+                parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
+                parity_event[5] = NULL;
 
-        kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
-                           KOBJ_CHANGE, parity_event);
+                kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
+                                   KOBJ_CHANGE, parity_event);
 
-        DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
-                  row, bank, subbank);
+                DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
+                          slice, row, bank, subbank);
 
-        kfree(parity_event[3]);
-        kfree(parity_event[2]);
-        kfree(parity_event[1]);
+                kfree(parity_event[4]);
+                kfree(parity_event[3]);
+                kfree(parity_event[2]);
+                kfree(parity_event[1]);
+        }
+
+        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+
+out:
+        WARN_ON(dev_priv->l3_parity.which_slice);
+        spin_lock_irqsave(&dev_priv->irq_lock, flags);
+        ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
+        spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+
+        mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 
-static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
+static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-        if (!HAS_L3_GPU_CACHE(dev))
+        if (!HAS_L3_DPF(dev))
                 return;
 
         spin_lock(&dev_priv->irq_lock);
-        ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+        ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
         spin_unlock(&dev_priv->irq_lock);
 
+        iir &= GT_PARITY_ERROR(dev);
+        if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
+                dev_priv->l3_parity.which_slice |= 1 << 1;
+
+        if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
+                dev_priv->l3_parity.which_slice |= 1 << 0;
+
         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 }
 
@@ -975,8 +1017,8 @@ static void snb_gt_irq_handler(struct drm_device *dev,
                 i915_handle_error(dev, false);
         }
 
-        if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
-                ivybridge_parity_error_irq_handler(dev);
+        if (gt_iir & GT_PARITY_ERROR(dev))
+                ivybridge_parity_error_irq_handler(dev, gt_iir);
 }
 
 #define HPD_STORM_DETECT_PERIOD 1000
@@ -1388,7 +1430,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
         irqreturn_t ret = IRQ_NONE;
-        bool err_int_reenable = false;
 
         atomic_inc(&dev_priv->irq_received);
 
@@ -1412,17 +1453,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
                 POSTING_READ(SDEIER);
         }
 
-        /* On Haswell, also mask ERR_INT because we don't want to risk
-         * generating "unclaimed register" interrupts from inside the interrupt
-         * handler. */
-        if (IS_HASWELL(dev)) {
-                spin_lock(&dev_priv->irq_lock);
-                err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB;
-                if (err_int_reenable)
-                        ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
-                spin_unlock(&dev_priv->irq_lock);
-        }
-
         gt_iir = I915_READ(GTIIR);
         if (gt_iir) {
                 if (INTEL_INFO(dev)->gen >= 6)
@@ -1452,13 +1482,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
                 }
         }
 
-        if (err_int_reenable) {
-                spin_lock(&dev_priv->irq_lock);
-                if (ivb_can_enable_err_int(dev))
-                        ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
-                spin_unlock(&dev_priv->irq_lock);
-        }
-
         I915_WRITE(DEIER, de_ier);
         POSTING_READ(DEIER);
         if (!HAS_PCH_NOP(dev)) {
@@ -1516,7 +1539,7 @@ static void i915_error_work_func(struct work_struct *work)
         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
         int ret;
 
-        kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
+        kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
 
         /*
          * Note that there's only one work item which does gpu resets, so we
@@ -1530,7 +1553,7 @@ static void i915_error_work_func(struct work_struct *work)
          */
         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
                 DRM_DEBUG_DRIVER("resetting chip\n");
-                kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
+                kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
                                    reset_event);
 
                 /*
@@ -1557,7 +1580,7 @@ static void i915_error_work_func(struct work_struct *work)
                         smp_mb__before_atomic_inc();
                         atomic_inc(&dev_priv->gpu_error.reset_counter);
 
-                        kobject_uevent_env(&dev->primary->kdev.kobj,
+                        kobject_uevent_env(&dev->primary->kdev->kobj,
                                            KOBJ_CHANGE, reset_done_event);
                 } else {
                         atomic_set(&error->reset_counter, I915_WEDGED);
@@ -2021,12 +2044,17 @@ static void i915_hangcheck_elapsed(unsigned long data)
 
                 if (ring->hangcheck.seqno == seqno) {
                         if (ring_idle(ring, seqno)) {
+                                ring->hangcheck.action = HANGCHECK_IDLE;
+
                                 if (waitqueue_active(&ring->irq_queue)) {
                                         /* Issue a wake-up to catch stuck h/w. */
-                                        DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
-                                                  ring->name);
-                                        wake_up_all(&ring->irq_queue);
-                                        ring->hangcheck.score += HUNG;
+                                        if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
+                                                DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
+                                                          ring->name);
+                                                wake_up_all(&ring->irq_queue);
+                                        }
+                                        /* Safeguard against driver failure */
+                                        ring->hangcheck.score += BUSY;
                                 } else
                                         busy = false;
                         } else {
@@ -2049,6 +2077,7 @@ static void i915_hangcheck_elapsed(unsigned long data)
                                                                     acthd);
 
                                 switch (ring->hangcheck.action) {
+                                case HANGCHECK_IDLE:
                                 case HANGCHECK_WAIT:
                                         break;
                                 case HANGCHECK_ACTIVE:
@@ -2064,6 +2093,8 @@ static void i915_hangcheck_elapsed(unsigned long data)
                                 }
                         }
                 } else {
+                        ring->hangcheck.action = HANGCHECK_ACTIVE;
+
                         /* Gradually reduce the count so that we catch DoS
                          * attempts across multiple batches.
                          */
@@ -2254,10 +2285,10 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
         pm_irqs = gt_irqs = 0;
 
         dev_priv->gt_irq_mask = ~0;
-        if (HAS_L3_GPU_CACHE(dev)) {
+        if (HAS_L3_DPF(dev)) {
                 /* L3 parity interrupt is always unmasked. */
-                dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
-                gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+                dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
+                gt_irqs |= GT_PARITY_ERROR(dev);
         }
 
         gt_irqs |= GT_RENDER_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c159e1a6810f..95385023e0ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -264,6 +264,11 @@
 #define  MI_SEMAPHORE_SYNC_VVE      (1<<16) /* VECS wait for VCS  (VEVSYNC) */
 #define  MI_SEMAPHORE_SYNC_RVE      (2<<16) /* VECS wait for RCS  (VERSYNC) */
 #define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)
+
+#define MI_PREDICATE_RESULT_2   (0x2214)
+#define  LOWER_SLICE_ENABLED    (1<<0)
+#define  LOWER_SLICE_DISABLED   (0<<0)
+
 /*
  * 3D instructions used by the kernel
  */
@@ -346,12 +351,25 @@
 #define   IOSF_PORT_PUNIT                       0x4
 #define   IOSF_PORT_NC                          0x11
 #define   IOSF_PORT_DPIO                        0x12
+#define   IOSF_PORT_GPIO_NC                     0x13
+#define   IOSF_PORT_CCK                         0x14
+#define   IOSF_PORT_CCU                         0xA9
+#define   IOSF_PORT_GPS_CORE                    0x48
 #define VLV_IOSF_DATA                           (VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR                           (VLV_DISPLAY_BASE + 0x2108)
 
 #define PUNIT_OPCODE_REG_READ                   6
 #define PUNIT_OPCODE_REG_WRITE                  7
 
+#define PUNIT_REG_PWRGT_CTRL                    0x60
+#define PUNIT_REG_PWRGT_STATUS                  0x61
+#define   PUNIT_CLK_GATE                        1
+#define   PUNIT_PWR_RESET                       2
+#define   PUNIT_PWR_GATE                        3
+#define   RENDER_PWRGT                          (PUNIT_PWR_GATE << 0)
+#define   MEDIA_PWRGT                           (PUNIT_PWR_GATE << 2)
+#define   DISP2D_PWRGT                          (PUNIT_PWR_GATE << 6)
+
 #define PUNIT_REG_GPU_LFM                       0xd3
 #define PUNIT_REG_GPU_FREQ_REQ                  0xd4
 #define PUNIT_REG_GPU_FREQ_STS                  0xd8
@@ -372,6 +390,40 @@
 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT            27
 #define   FB_FMAX_VMIN_FREQ_LO_MASK             0xf8000000
 
+/* vlv2 north clock has */
+#define CCK_FUSE_REG                            0x8
+#define  CCK_FUSE_HPLL_FREQ_MASK                0x3
+#define CCK_REG_DSI_PLL_FUSE                    0x44
+#define CCK_REG_DSI_PLL_CONTROL                 0x48
+#define  DSI_PLL_VCO_EN                         (1 << 31)
+#define  DSI_PLL_LDO_GATE                       (1 << 30)
+#define  DSI_PLL_P1_POST_DIV_SHIFT              17
+#define  DSI_PLL_P1_POST_DIV_MASK               (0x1ff << 17)
+#define  DSI_PLL_P2_MUX_DSI0_DIV2               (1 << 13)
+#define  DSI_PLL_P3_MUX_DSI1_DIV2               (1 << 12)
+#define  DSI_PLL_MUX_MASK                       (3 << 9)
+#define  DSI_PLL_MUX_DSI0_DSIPLL                (0 << 10)
+#define  DSI_PLL_MUX_DSI0_CCK                   (1 << 10)
+#define  DSI_PLL_MUX_DSI1_DSIPLL                (0 << 9)
+#define  DSI_PLL_MUX_DSI1_CCK                   (1 << 9)
+#define  DSI_PLL_CLK_GATE_MASK                  (0xf << 5)
+#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL           (1 << 8)
+#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL           (1 << 7)
+#define  DSI_PLL_CLK_GATE_DSI0_CCK              (1 << 6)
+#define  DSI_PLL_CLK_GATE_DSI1_CCK              (1 << 5)
+#define  DSI_PLL_LOCK                           (1 << 0)
+#define CCK_REG_DSI_PLL_DIVIDER                 0x4c
+#define  DSI_PLL_LFSR                           (1 << 31)
+#define  DSI_PLL_FRACTION_EN                    (1 << 30)
+#define  DSI_PLL_FRAC_COUNTER_SHIFT             27
+#define  DSI_PLL_FRAC_COUNTER_MASK              (7 << 27)
+#define  DSI_PLL_USYNC_CNT_SHIFT                18
+#define  DSI_PLL_USYNC_CNT_MASK                 (0x1ff << 18)
+#define  DSI_PLL_N1_DIV_SHIFT                   16
+#define  DSI_PLL_N1_DIV_MASK                    (3 << 16)
+#define  DSI_PLL_M1_DIV_SHIFT                   0
+#define  DSI_PLL_M1_DIV_MASK                    (0x1ff << 0)
+
 /*
  * DPIO - a special bus for various display related registers to hide behind
  *
@@ -387,7 +439,7 @@
 #define  DPIO_MODSEL1                   (1<<3) /* if ref clk b == 27 */
 #define  DPIO_MODSEL0                   (1<<2) /* if ref clk a == 27 */
 #define  DPIO_SFR_BYPASS                (1<<1)
-#define  DPIO_RESET                     (1<<0)
+#define  DPIO_CMNRST                    (1<<0)
 
 #define _DPIO_TX3_SWING_CTL4_A          0x690
 #define _DPIO_TX3_SWING_CTL4_B          0x2a90
@@ -886,6 +938,7 @@
 #define GT_BLT_USER_INTERRUPT                   (1 << 22)
 #define GT_BSD_CS_ERROR_INTERRUPT               (1 << 15)
 #define GT_BSD_USER_INTERRUPT                   (1 << 12)
+#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1  (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT     (1 <<  5) /* !snb */
 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT      (1 <<  4)
 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT     (1 <<  3)
@@ -896,6 +949,10 @@
 #define PM_VEBOX_CS_ERROR_INTERRUPT             (1 << 12) /* hsw+ */
 #define PM_VEBOX_USER_INTERRUPT                 (1 << 10) /* hsw+ */
 
+#define GT_PARITY_ERROR(dev) \
+        (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
+         (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
+
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT                          (1<<5)
 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT              (1<<18)
@@ -1383,6 +1440,12 @@
 
 #define MI_ARB_VLV              (VLV_DISPLAY_BASE + 0x6504)
 
+#define CZCLK_CDCLK_FREQ_RATIO  (VLV_DISPLAY_BASE + 0x6508)
+#define   CDCLK_FREQ_SHIFT      4
+#define   CDCLK_FREQ_MASK       (0x1f << CDCLK_FREQ_SHIFT)
+#define   CZCLK_FREQ_MASK       0xf
+#define GMBUSFREQ_VLV           (VLV_DISPLAY_BASE + 0x6510)
+
 /*
  * Palette regs
  */
@@ -1400,6 +1463,8 @@
  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
  * every way.  It is not accessible from the CP register read instructions.
  *
+ * Starting from Haswell, you can't write registers using the MCHBAR mirror,
+ * just read.
  */
 #define MCHBAR_MIRROR_BASE      0x10000
 
@@ -1749,6 +1814,9 @@
  */
 #define HSW_CXT_TOTAL_SIZE              (17 * PAGE_SIZE)
 
+#define VLV_CLK_CTL2                    0x101104
+#define   CLK_CTL2_CZCOUNT_30NS_SHIFT   28
+
 /*
  * Overlay regs
  */
@@ -1800,7 +1868,8 @@
 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
 /* HSW eDP PSR registers */
-#define EDP_PSR_CTL                             0x64800
+#define EDP_PSR_BASE(dev)                       0x64800
+#define EDP_PSR_CTL(dev)                        (EDP_PSR_BASE(dev) + 0)
 #define   EDP_PSR_ENABLE                        (1<<31)
 #define   EDP_PSR_LINK_DISABLE                  (0<<27)
 #define   EDP_PSR_LINK_STANDBY                  (1<<27)
@@ -1823,16 +1892,16 @@
 #define   EDP_PSR_TP1_TIME_0us                  (3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT              0
 
-#define EDP_PSR_AUX_CTL                 0x64810
-#define EDP_PSR_AUX_DATA1               0x64814
+#define EDP_PSR_AUX_CTL(dev)                    (EDP_PSR_BASE(dev) + 0x10)
+#define EDP_PSR_AUX_DATA1(dev)                  (EDP_PSR_BASE(dev) + 0x14)
 #define   EDP_PSR_DPCD_COMMAND          0x80060000
-#define EDP_PSR_AUX_DATA2               0x64818
+#define EDP_PSR_AUX_DATA2(dev)                  (EDP_PSR_BASE(dev) + 0x18)
 #define   EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
-#define EDP_PSR_AUX_DATA3               0x6481c
-#define EDP_PSR_AUX_DATA4               0x64820
-#define EDP_PSR_AUX_DATA5               0x64824
+#define EDP_PSR_AUX_DATA3(dev)                  (EDP_PSR_BASE(dev) + 0x1c)
+#define EDP_PSR_AUX_DATA4(dev)                  (EDP_PSR_BASE(dev) + 0x20)
+#define EDP_PSR_AUX_DATA5(dev)                  (EDP_PSR_BASE(dev) + 0x24)
 
-#define EDP_PSR_STATUS_CTL                      0x64840
+#define EDP_PSR_STATUS_CTL(dev)                 (EDP_PSR_BASE(dev) + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK             (7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE             (0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK         (1<<29)
@@ -1856,10 +1925,10 @@
 #define   EDP_PSR_STATUS_SENDING_TP1            (1<<4)
 #define   EDP_PSR_STATUS_IDLE_MASK              0xf
 
-#define EDP_PSR_PERF_CNT                0x64844
+#define EDP_PSR_PERF_CNT(dev)           (EDP_PSR_BASE(dev) + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK         0xffffff
 
-#define EDP_PSR_DEBUG_CTL               0x64860
+#define EDP_PSR_DEBUG_CTL(dev)          (EDP_PSR_BASE(dev) + 0x60)
 #define   EDP_PSR_DEBUG_MASK_LPSP       (1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP      (1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD        (1<<25)
@@ -2030,6 +2099,7 @@
 
 /* Gen 4 SDVO/HDMI bits: */
 #define   SDVO_COLOR_FORMAT_8bpc                (0 << 26)
+#define   SDVO_COLOR_FORMAT_MASK                (7 << 26)
 #define   SDVO_ENCODING_SDVO                    (0 << 10)
 #define   SDVO_ENCODING_HDMI                    (2 << 10)
 #define   HDMI_MODE_SELECT_HDMI                 (1 << 9) /* HDMI only */
@@ -2982,6 +3052,7 @@
 #define   PIPECONF_DISABLE      0
 #define   PIPECONF_DOUBLE_WIDE  (1<<30)
 #define   I965_PIPECONF_ACTIVE  (1<<30)
+#define   PIPECONF_DSI_PLL_LOCKED       (1<<29) /* vlv & pipe A only */
 #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
 #define   PIPECONF_SINGLE_WIDE  0
 #define   PIPECONF_PIPE_UNLOCKED 0
@@ -4407,6 +4478,8 @@
 #define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
 #define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
 #define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
+#define  PANEL_PORT_SELECT_DPB_VLV      (1 << 30)
+#define  PANEL_PORT_SELECT_DPC_VLV      (2 << 30)
 #define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
 #define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
 
@@ -4438,7 +4511,6 @@
 #define  PANEL_PORT_SELECT_MASK (3 << 30)
 #define  PANEL_PORT_SELECT_LVDS (0 << 30)
 #define  PANEL_PORT_SELECT_DPA  (1 << 30)
-#define  EDP_PANEL              (1 << 30)
 #define  PANEL_PORT_SELECT_DPC  (2 << 30)
 #define  PANEL_PORT_SELECT_DPD  (3 << 30)
 #define  PANEL_POWER_UP_DELAY_MASK      (0x1fff0000)
@@ -4447,11 +4519,6 @@
 #define  PANEL_LIGHT_ON_DELAY_SHIFT     0
 
 #define PCH_PP_OFF_DELAYS       0xc720c
-#define  PANEL_POWER_PORT_SELECT_MASK   (0x3 << 30)
-#define  PANEL_POWER_PORT_LVDS          (0 << 30)
-#define  PANEL_POWER_PORT_DP_A          (1 << 30)
-#define  PANEL_POWER_PORT_DP_C          (2 << 30)
-#define  PANEL_POWER_PORT_DP_D          (3 << 30)
 #define  PANEL_POWER_DOWN_DELAY_MASK    (0x1fff0000)
 #define  PANEL_POWER_DOWN_DELAY_SHIFT   16
 #define  PANEL_LIGHT_OFF_DELAY_MASK     (0x1fff)
@@ -4629,7 +4696,7 @@
 #define   GEN6_RP_UP_IDLE_MIN                   (0x1<<3)
 #define   GEN6_RP_UP_BUSY_AVG                   (0x2<<3)
 #define   GEN6_RP_UP_BUSY_CONT                  (0x4<<3)
-#define   GEN7_RP_DOWN_IDLE_AVG                 (0x2<<0)
+#define   GEN6_RP_DOWN_IDLE_AVG                 (0x2<<0)
 #define   GEN6_RP_DOWN_IDLE_CONT                (0x1<<0)
 #define GEN6_RP_UP_THRESHOLD                    0xA02C
 #define GEN6_RP_DOWN_THRESHOLD                  0xA030
@@ -4674,6 +4741,10 @@
                                                  GEN6_PM_RP_DOWN_TIMEOUT)
 
 #define GEN6_GT_GFX_RC6_LOCKED                  0x138104
+#define VLV_COUNTER_CONTROL                     0x138104
+#define   VLV_COUNT_RANGE_HIGH                  (1<<15)
+#define   VLV_MEDIA_RC6_COUNT_EN                (1<<1)
+#define   VLV_RENDER_RC6_COUNT_EN               (1<<0)
 #define GEN6_GT_GFX_RC6                         0x138108
 #define GEN6_GT_GFX_RC6p                        0x13810C
 #define GEN6_GT_GFX_RC6pp                       0x138110
@@ -4685,6 +4756,8 @@
 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
 #define   GEN6_PCODE_WRITE_RC6VIDS              0x4
 #define   GEN6_PCODE_READ_RC6VIDS               0x5
+#define   GEN6_PCODE_READ_D_COMP                0x10
+#define   GEN6_PCODE_WRITE_D_COMP               0x11
 #define   GEN6_ENCODE_RC6_VID(mv)               (((mv) - 245) / 5)
 #define   GEN6_DECODE_RC6_VID(vids)             (((vids) * 5) + 245)
 #define GEN6_PCODE_DATA                         0x138128
@@ -4704,6 +4777,7 @@
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1                 0xB008 /* L3CD Error Status 1 */
+#define HSW_L3CDERRST11                 0xB208 /* L3CD Error Status register 1 slice 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK      (0x7ff<<14)
 #define   GEN7_PARITY_ERROR_VALID       (1<<13)
 #define   GEN7_L3CDERRST1_BANK_MASK     (3<<11)
@@ -4717,6 +4791,7 @@
 #define   GEN7_L3CDERRST1_ENABLE        (1<<7)
 
 #define GEN7_L3LOG_BASE                 0xB070
+#define HSW_L3LOG_BASE_SLICE1           0xB270
 #define GEN7_L3LOG_SIZE                 0x80
 
 #define GEN7_HALF_SLICE_CHICKEN1        0xe100 /* IVB GT1 + VLV */
@@ -5116,4 +5191,414 @@
 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
 
+/* VLV MIPI registers */
+
+#define _MIPIA_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61190)
+#define _MIPIB_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61700)
+#define MIPI_PORT_CTRL(pipe)            _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
+#define  DPI_ENABLE                                     (1 << 31) /* A + B */
+#define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT              27
+#define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 27)
+#define  DUAL_LINK_MODE_MASK                            (1 << 26)
+#define  DUAL_LINK_MODE_FRONT_BACK                      (0 << 26)
+#define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE               (1 << 26)
+#define  DITHERING_ENABLE                               (1 << 25) /* A + B */
+#define  FLOPPED_HSTX                                   (1 << 23)
+#define  DE_INVERT                                      (1 << 19) /* XXX */
+#define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT                18
+#define  MIPIA_FLISDSI_DELAY_COUNT_MASK                 (0xf << 18)
+#define  AFE_LATCHOUT                                   (1 << 17)
+#define  LP_OUTPUT_HOLD                                 (1 << 16)
+#define  MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT           15
+#define  MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK            (1 << 15)
+#define  MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT              11
+#define  MIPIB_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 11)
+#define  CSB_SHIFT                                      9
+#define  CSB_MASK                                       (3 << 9)
+#define  CSB_20MHZ                                      (0 << 9)
+#define  CSB_10MHZ                                      (1 << 9)
+#define  CSB_40MHZ                                      (2 << 9)
+#define  BANDGAP_MASK                                   (1 << 8)
+#define  BANDGAP_PNW_CIRCUIT                            (0 << 8)
+#define  BANDGAP_LNC_CIRCUIT                            (1 << 8)
+#define  MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT            5
+#define  MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK             (7 << 5)
+#define  TEARING_EFFECT_DELAY                           (1 << 4) /* A + B */
+#define  TEARING_EFFECT_SHIFT                           2 /* A + B */
+#define  TEARING_EFFECT_MASK                            (3 << 2)
+#define  TEARING_EFFECT_OFF                             (0 << 2)
+#define  TEARING_EFFECT_DSI                             (1 << 2)
+#define  TEARING_EFFECT_GPIO                            (2 << 2)
+#define  LANE_CONFIGURATION_SHIFT                       0
+#define  LANE_CONFIGURATION_MASK                        (3 << 0)
+#define  LANE_CONFIGURATION_4LANE                       (0 << 0)
+#define  LANE_CONFIGURATION_DUAL_LINK_A                 (1 << 0)
+#define  LANE_CONFIGURATION_DUAL_LINK_B                 (2 << 0)
+
+#define _MIPIA_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61194)
+#define _MIPIB_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61704)
+#define MIPI_TEARING_CTRL(pipe)         _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
+#define  TEARING_EFFECT_DELAY_SHIFT                     0
+#define  TEARING_EFFECT_DELAY_MASK                      (0xffff << 0)
+
+/* XXX: all bits reserved */
+#define _MIPIA_AUTOPWG                          (VLV_DISPLAY_BASE + 0x611a0)
+
+/* MIPI DSI Controller and D-PHY registers */
+
+#define _MIPIA_DEVICE_READY                     (VLV_DISPLAY_BASE + 0xb000)
+#define _MIPIB_DEVICE_READY                     (VLV_DISPLAY_BASE + 0xb800)
+#define MIPI_DEVICE_READY(pipe)         _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
+#define  BUS_POSSESSION                                 (1 << 3) /* set to give bus to receiver */
+#define  ULPS_STATE_MASK                                (3 << 1)
+#define  ULPS_STATE_ENTER                               (2 << 1)
+#define  ULPS_STATE_EXIT                                (1 << 1)
+#define  ULPS_STATE_NORMAL_OPERATION                    (0 << 1)
+#define  DEVICE_READY                                   (1 << 0)
+
+#define _MIPIA_INTR_STAT                        (VLV_DISPLAY_BASE + 0xb004)
+#define _MIPIB_INTR_STAT                        (VLV_DISPLAY_BASE + 0xb804)
+#define MIPI_INTR_STAT(pipe)            _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
+#define _MIPIA_INTR_EN                          (VLV_DISPLAY_BASE + 0xb008)
+#define _MIPIB_INTR_EN                          (VLV_DISPLAY_BASE + 0xb808)
+#define MIPI_INTR_EN(pipe)              _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
+#define  TEARING_EFFECT                                 (1 << 31)
+#define  SPL_PKT_SENT_INTERRUPT                         (1 << 30)
+#define  GEN_READ_DATA_AVAIL                            (1 << 29)
+#define  LP_GENERIC_WR_FIFO_FULL                        (1 << 28)
+#define  HS_GENERIC_WR_FIFO_FULL                        (1 << 27)
+#define  RX_PROT_VIOLATION                              (1 << 26)
+#define  RX_INVALID_TX_LENGTH                           (1 << 25)
+#define  ACK_WITH_NO_ERROR                              (1 << 24)
+#define  TURN_AROUND_ACK_TIMEOUT                        (1 << 23)
+#define  LP_RX_TIMEOUT                                  (1 << 22)
+#define  HS_TX_TIMEOUT                                  (1 << 21)
+#define  DPI_FIFO_UNDERRUN                              (1 << 20)
+#define  LOW_CONTENTION                                 (1 << 19)
+#define  HIGH_CONTENTION                                (1 << 18)
+#define  TXDSI_VC_ID_INVALID                            (1 << 17)
+#define  TXDSI_DATA_TYPE_NOT_RECOGNISED                 (1 << 16)
+#define  TXCHECKSUM_ERROR                               (1 << 15)
+#define  TXECC_MULTIBIT_ERROR                           (1 << 14)
+#define  TXECC_SINGLE_BIT_ERROR                         (1 << 13)
+#define  TXFALSE_CONTROL_ERROR                          (1 << 12)
+#define  RXDSI_VC_ID_INVALID                            (1 << 11)
+#define  RXDSI_DATA_TYPE_NOT_REGOGNISED                 (1 << 10)
+#define  RXCHECKSUM_ERROR                               (1 << 9)
+#define  RXECC_MULTIBIT_ERROR                           (1 << 8)
+#define  RXECC_SINGLE_BIT_ERROR                         (1 << 7)
+#define  RXFALSE_CONTROL_ERROR                          (1 << 6)
+#define  RXHS_RECEIVE_TIMEOUT_ERROR                     (1 << 5)
+#define  RX_LP_TX_SYNC_ERROR                            (1 << 4)
+#define  RXEXCAPE_MODE_ENTRY_ERROR                      (1 << 3)
+#define  RXEOT_SYNC_ERROR                               (1 << 2)
+#define  RXSOT_SYNC_ERROR                               (1 << 1)
+#define  RXSOT_ERROR                                    (1 << 0)
+
+#define _MIPIA_DSI_FUNC_PRG                     (VLV_DISPLAY_BASE + 0xb00c)
+#define _MIPIB_DSI_FUNC_PRG                     (VLV_DISPLAY_BASE + 0xb80c)
+#define MIPI_DSI_FUNC_PRG(pipe)         _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
+#define  CMD_MODE_DATA_WIDTH_MASK                       (7 << 13)
+#define  CMD_MODE_NOT_SUPPORTED                         (0 << 13)
+#define  CMD_MODE_DATA_WIDTH_16_BIT                     (1 << 13)
+#define  CMD_MODE_DATA_WIDTH_9_BIT                      (2 << 13)
+#define  CMD_MODE_DATA_WIDTH_8_BIT                      (3 << 13)
+#define  CMD_MODE_DATA_WIDTH_OPTION1                    (4 << 13)
+#define  CMD_MODE_DATA_WIDTH_OPTION2                    (5 << 13)
+#define  VID_MODE_FORMAT_MASK                           (0xf << 7)
+#define  VID_MODE_NOT_SUPPORTED                         (0 << 7)
+#define  VID_MODE_FORMAT_RGB565                         (1 << 7)
+#define  VID_MODE_FORMAT_RGB666                         (2 << 7)
+#define  VID_MODE_FORMAT_RGB666_LOOSE                   (3 << 7)
+#define  VID_MODE_FORMAT_RGB888                         (4 << 7)
+#define  CMD_MODE_CHANNEL_NUMBER_SHIFT                  5
+#define  CMD_MODE_CHANNEL_NUMBER_MASK                   (3 << 5)
+#define  VID_MODE_CHANNEL_NUMBER_SHIFT                  3
+#define  VID_MODE_CHANNEL_NUMBER_MASK                   (3 << 3)
+#define  DATA_LANES_PRG_REG_SHIFT                       0
+#define  DATA_LANES_PRG_REG_MASK                        (7 << 0)
+
+#define _MIPIA_HS_TX_TIMEOUT                    (VLV_DISPLAY_BASE + 0xb010)
+#define _MIPIB_HS_TX_TIMEOUT                    (VLV_DISPLAY_BASE + 0xb810)
+#define MIPI_HS_TX_TIMEOUT(pipe)        _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
+#define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK             0xffffff
+
+#define _MIPIA_LP_RX_TIMEOUT                    (VLV_DISPLAY_BASE + 0xb014)
+#define _MIPIB_LP_RX_TIMEOUT                    (VLV_DISPLAY_BASE + 0xb814)
+#define MIPI_LP_RX_TIMEOUT(pipe)        _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
+#define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK              0xffffff
+
+#define _MIPIA_TURN_AROUND_TIMEOUT              (VLV_DISPLAY_BASE + 0xb018)
+#define _MIPIB_TURN_AROUND_TIMEOUT              (VLV_DISPLAY_BASE + 0xb818)
+#define MIPI_TURN_AROUND_TIMEOUT(pipe)  _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
+#define  TURN_AROUND_TIMEOUT_MASK                       0x3f
+
+#define _MIPIA_DEVICE_RESET_TIMER               (VLV_DISPLAY_BASE + 0xb01c)
+#define _MIPIB_DEVICE_RESET_TIMER               (VLV_DISPLAY_BASE + 0xb81c)
+#define MIPI_DEVICE_RESET_TIMER(pipe)   _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
+#define  DEVICE_RESET_TIMER_MASK                        0xffff
+
+#define _MIPIA_DPI_RESOLUTION                   (VLV_DISPLAY_BASE + 0xb020)
+#define _MIPIB_DPI_RESOLUTION                   (VLV_DISPLAY_BASE + 0xb820)
+#define MIPI_DPI_RESOLUTION(pipe)       _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
+#define  VERTICAL_ADDRESS_SHIFT                         16
+#define  VERTICAL_ADDRESS_MASK                          (0xffff << 16)
+#define  HORIZONTAL_ADDRESS_SHIFT                       0
+#define  HORIZONTAL_ADDRESS_MASK                        0xffff
+
+#define _MIPIA_DBI_FIFO_THROTTLE                (VLV_DISPLAY_BASE + 0xb024)
+#define _MIPIB_DBI_FIFO_THROTTLE                (VLV_DISPLAY_BASE + 0xb824)
+#define MIPI_DBI_FIFO_THROTTLE(pipe)    _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
+#define  DBI_FIFO_EMPTY_HALF                            (0 << 0)
+#define  DBI_FIFO_EMPTY_QUARTER                         (1 << 0)
+#define  DBI_FIFO_EMPTY_7_LOCATIONS                     (2 << 0)
+
+/* regs below are bits 15:0 */
+#define _MIPIA_HSYNC_PADDING_COUNT              (VLV_DISPLAY_BASE + 0xb028)
+#define _MIPIB_HSYNC_PADDING_COUNT              (VLV_DISPLAY_BASE + 0xb828)
+#define MIPI_HSYNC_PADDING_COUNT(pipe)  _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
+
+#define _MIPIA_HBP_COUNT                        (VLV_DISPLAY_BASE + 0xb02c)
+#define _MIPIB_HBP_COUNT                        (VLV_DISPLAY_BASE + 0xb82c)
+#define MIPI_HBP_COUNT(pipe)            _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
+
+#define _MIPIA_HFP_COUNT                        (VLV_DISPLAY_BASE + 0xb030)
+#define _MIPIB_HFP_COUNT                        (VLV_DISPLAY_BASE + 0xb830)
+#define MIPI_HFP_COUNT(pipe)            _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
+
+#define _MIPIA_HACTIVE_AREA_COUNT               (VLV_DISPLAY_BASE + 0xb034)
+#define _MIPIB_HACTIVE_AREA_COUNT               (VLV_DISPLAY_BASE + 0xb834)
+#define MIPI_HACTIVE_AREA_COUNT(pipe)   _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
+
+#define _MIPIA_VSYNC_PADDING_COUNT              (VLV_DISPLAY_BASE + 0xb038)
+#define _MIPIB_VSYNC_PADDING_COUNT              (VLV_DISPLAY_BASE + 0xb838)
+#define MIPI_VSYNC_PADDING_COUNT(pipe)  _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
+
+#define _MIPIA_VBP_COUNT                        (VLV_DISPLAY_BASE + 0xb03c)
+#define _MIPIB_VBP_COUNT                        (VLV_DISPLAY_BASE + 0xb83c)
+#define MIPI_VBP_COUNT(pipe)            _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
+
+#define _MIPIA_VFP_COUNT                        (VLV_DISPLAY_BASE + 0xb040)
+#define _MIPIB_VFP_COUNT                        (VLV_DISPLAY_BASE + 0xb840)
+#define MIPI_VFP_COUNT(pipe)            _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
+
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT            (VLV_DISPLAY_BASE + 0xb044)
+#define _MIPIB_HIGH_LOW_SWITCH_COUNT            (VLV_DISPLAY_BASE + 0xb844)
+#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe)        _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
+/* regs above are bits 15:0 */
+
+#define _MIPIA_DPI_CONTROL                      (VLV_DISPLAY_BASE + 0xb048)
+#define _MIPIB_DPI_CONTROL                      (VLV_DISPLAY_BASE + 0xb848)
+#define MIPI_DPI_CONTROL(pipe)          _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
+#define  DPI_LP_MODE                                    (1 << 6)
+#define  BACKLIGHT_OFF                                  (1 << 5)
+#define  BACKLIGHT_ON                                   (1 << 4)
+#define  COLOR_MODE_OFF                                 (1 << 3)
+#define  COLOR_MODE_ON                                  (1 << 2)
+#define  TURN_ON                                        (1 << 1)
+#define  SHUTDOWN                                       (1 << 0)
+
+#define _MIPIA_DPI_DATA                         (VLV_DISPLAY_BASE + 0xb04c)
+#define _MIPIB_DPI_DATA                         (VLV_DISPLAY_BASE + 0xb84c)
+#define MIPI_DPI_DATA(pipe)             _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
+#define  COMMAND_BYTE_SHIFT                             0
+#define  COMMAND_BYTE_MASK                              (0x3f << 0)
+
+#define _MIPIA_INIT_COUNT                       (VLV_DISPLAY_BASE + 0xb050)
+#define _MIPIB_INIT_COUNT                       (VLV_DISPLAY_BASE + 0xb850)
+#define MIPI_INIT_COUNT(pipe)           _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
+#define  MASTER_INIT_TIMER_SHIFT                        0
+#define  MASTER_INIT_TIMER_MASK                         (0xffff << 0)
+
+#define _MIPIA_MAX_RETURN_PKT_SIZE              (VLV_DISPLAY_BASE + 0xb054)
+#define _MIPIB_MAX_RETURN_PKT_SIZE              (VLV_DISPLAY_BASE + 0xb854)
+#define MIPI_MAX_RETURN_PKT_SIZE(pipe)  _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
+#define  MAX_RETURN_PKT_SIZE_SHIFT                      0
+#define  MAX_RETURN_PKT_SIZE_MASK                       (0x3ff << 0)
+
+#define _MIPIA_VIDEO_MODE_FORMAT                (VLV_DISPLAY_BASE + 0xb058)
+#define _MIPIB_VIDEO_MODE_FORMAT                (VLV_DISPLAY_BASE + 0xb858)
+#define MIPI_VIDEO_MODE_FORMAT(pipe)    _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
+#define  RANDOM_DPI_DISPLAY_RESOLUTION                  (1 << 4)
+#define  DISABLE_VIDEO_BTA                              (1 << 3)
+#define  IP_TG_CONFIG                                   (1 << 2)
+#define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE           (1 << 0)
+#define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS          (2 << 0)
+#define  VIDEO_MODE_BURST                               (3 << 0)
+
+#define _MIPIA_EOT_DISABLE                      (VLV_DISPLAY_BASE + 0xb05c)
+#define _MIPIB_EOT_DISABLE                      (VLV_DISPLAY_BASE + 0xb85c)
+#define MIPI_EOT_DISABLE(pipe)          _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
+#define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 7)
+#define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 6)
+#define  LOW_CONTENTION_RECOVERY_DISABLE                (1 << 5)
+#define  HIGH_CONTENTION_RECOVERY_DISABLE               (1 << 4)
+#define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
+#define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE          (1 << 2)
+#define  CLOCKSTOP                                      (1 << 1)
+#define  EOT_DISABLE                                    (1 << 0)
+
+#define _MIPIA_LP_BYTECLK                       (VLV_DISPLAY_BASE + 0xb060)
+#define _MIPIB_LP_BYTECLK                       (VLV_DISPLAY_BASE + 0xb860)
+#define MIPI_LP_BYTECLK(pipe)           _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
+#define  LP_BYTECLK_SHIFT                               0
+#define  LP_BYTECLK_MASK                                (0xffff << 0)
+
+/* bits 31:0 */
+#define _MIPIA_LP_GEN_DATA                      (VLV_DISPLAY_BASE + 0xb064)
+#define _MIPIB_LP_GEN_DATA                      (VLV_DISPLAY_BASE + 0xb864)
+#define MIPI_LP_GEN_DATA(pipe)          _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
+
+/* bits 31:0 */
+#define _MIPIA_HS_GEN_DATA                      (VLV_DISPLAY_BASE + 0xb068)
+#define _MIPIB_HS_GEN_DATA                      (VLV_DISPLAY_BASE + 0xb868)
+#define MIPI_HS_GEN_DATA(pipe)          _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
+
+#define _MIPIA_LP_GEN_CTRL                      (VLV_DISPLAY_BASE + 0xb06c)
+#define _MIPIB_LP_GEN_CTRL                      (VLV_DISPLAY_BASE + 0xb86c)
+#define MIPI_LP_GEN_CTRL(pipe)          _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
+#define _MIPIA_HS_GEN_CTRL                      (VLV_DISPLAY_BASE + 0xb070)
+#define _MIPIB_HS_GEN_CTRL                      (VLV_DISPLAY_BASE + 0xb870)
+#define MIPI_HS_GEN_CTRL(pipe)          _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
+#define  LONG_PACKET_WORD_COUNT_SHIFT                   8
+#define  LONG_PACKET_WORD_COUNT_MASK                    (0xffff << 8)
+#define  SHORT_PACKET_PARAM_SHIFT                       8
+#define  SHORT_PACKET_PARAM_MASK                        (0xffff << 8)
+#define  VIRTUAL_CHANNEL_SHIFT                          6
+#define  VIRTUAL_CHANNEL_MASK                           (3 << 6)
+#define  DATA_TYPE_SHIFT                                0
+#define  DATA_TYPE_MASK                                 (3f << 0)
+/* data type values, see include/video/mipi_display.h */
+
+#define _MIPIA_GEN_FIFO_STAT                    (VLV_DISPLAY_BASE + 0xb074)
+#define _MIPIB_GEN_FIFO_STAT                    (VLV_DISPLAY_BASE + 0xb874)
+#define MIPI_GEN_FIFO_STAT(pipe)        _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
+#define  DPI_FIFO_EMPTY                                 (1 << 28)
+#define  DBI_FIFO_EMPTY                                 (1 << 27)
+#define  LP_CTRL_FIFO_EMPTY                             (1 << 26)
+#define  LP_CTRL_FIFO_HALF_EMPTY                        (1 << 25)
+#define  LP_CTRL_FIFO_FULL                              (1 << 24)
+#define  HS_CTRL_FIFO_EMPTY                             (1 << 18)
+#define  HS_CTRL_FIFO_HALF_EMPTY                        (1 << 17)
+#define  HS_CTRL_FIFO_FULL                              (1 << 16)
+#define  LP_DATA_FIFO_EMPTY                             (1 << 10)
+#define  LP_DATA_FIFO_HALF_EMPTY                        (1 << 9)
+#define  LP_DATA_FIFO_FULL                              (1 << 8)
+#define  HS_DATA_FIFO_EMPTY                             (1 << 2)
+#define  HS_DATA_FIFO_HALF_EMPTY                        (1 << 1)
+#define  HS_DATA_FIFO_FULL                              (1 << 0)
+
+#define _MIPIA_HS_LS_DBI_ENABLE                 (VLV_DISPLAY_BASE + 0xb078)
+#define _MIPIB_HS_LS_DBI_ENABLE                 (VLV_DISPLAY_BASE + 0xb878)
+#define MIPI_HS_LP_DBI_ENABLE(pipe)     _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
+#define  DBI_HS_LP_MODE_MASK                            (1 << 0)
+#define  DBI_LP_MODE                                    (1 << 0)
+#define  DBI_HS_MODE                                    (0 << 0)
+
+#define _MIPIA_DPHY_PARAM                       (VLV_DISPLAY_BASE + 0xb080)
+#define _MIPIB_DPHY_PARAM                       (VLV_DISPLAY_BASE + 0xb880)
+#define MIPI_DPHY_PARAM(pipe)           _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
+#define  EXIT_ZERO_COUNT_SHIFT                          24
+#define  EXIT_ZERO_COUNT_MASK                           (0x3f << 24)
+#define  TRAIL_COUNT_SHIFT                              16
+#define  TRAIL_COUNT_MASK                               (0x1f << 16)
+#define  CLK_ZERO_COUNT_SHIFT                           8
+#define  CLK_ZERO_COUNT_MASK                            (0xff << 8)
+#define  PREPARE_COUNT_SHIFT                            0
+#define  PREPARE_COUNT_MASK                             (0x3f << 0)
+
+/* bits 31:0 */
+#define _MIPIA_DBI_BW_CTRL                      (VLV_DISPLAY_BASE + 0xb084)
+#define _MIPIB_DBI_BW_CTRL                      (VLV_DISPLAY_BASE + 0xb884)
+#define MIPI_DBI_BW_CTRL(pipe)          _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
+
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT         (VLV_DISPLAY_BASE + 0xb088)
+#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT         (VLV_DISPLAY_BASE + 0xb888)
+#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe)     _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
+#define  LP_HS_SSW_CNT_SHIFT                            16
+#define  LP_HS_SSW_CNT_MASK                             (0xffff << 16)
+#define  HS_LP_PWR_SW_CNT_SHIFT                         0
+#define  HS_LP_PWR_SW_CNT_MASK                          (0xffff << 0)
+
+#define _MIPIA_STOP_STATE_STALL                 (VLV_DISPLAY_BASE + 0xb08c)
+#define _MIPIB_STOP_STATE_STALL                 (VLV_DISPLAY_BASE + 0xb88c)
+#define MIPI_STOP_STATE_STALL(pipe)     _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
+#define  STOP_STATE_STALL_COUNTER_SHIFT                 0
+#define  STOP_STATE_STALL_COUNTER_MASK                  (0xff << 0)
+
+#define _MIPIA_INTR_STAT_REG_1                  (VLV_DISPLAY_BASE + 0xb090)
+#define _MIPIB_INTR_STAT_REG_1                  (VLV_DISPLAY_BASE + 0xb890)
+#define MIPI_INTR_STAT_REG_1(pipe)      _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
+#define _MIPIA_INTR_EN_REG_1                    (VLV_DISPLAY_BASE + 0xb094)
+#define _MIPIB_INTR_EN_REG_1                    (VLV_DISPLAY_BASE + 0xb894)
+#define MIPI_INTR_EN_REG_1(pipe)        _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
+#define  RX_CONTENTION_DETECTED                         (1 << 0)
+
+/* XXX: only pipe A ?!? */
+#define MIPIA_DBI_TYPEC_CTRL                    (VLV_DISPLAY_BASE + 0xb100)
+#define  DBI_TYPEC_ENABLE                               (1 << 31)
+#define  DBI_TYPEC_WIP                                  (1 << 30)
+#define  DBI_TYPEC_OPTION_SHIFT                         28
+#define  DBI_TYPEC_OPTION_MASK                          (3 << 28)
+#define  DBI_TYPEC_FREQ_SHIFT                           24
+#define  DBI_TYPEC_FREQ_MASK                            (0xf << 24)
+#define  DBI_TYPEC_OVERRIDE                             (1 << 8)
+#define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT               0
+#define  DBI_TYPEC_OVERRIDE_COUNTER_MASK                (0xff << 0)
+
+
+/* MIPI adapter registers */
+
+#define _MIPIA_CTRL                             (VLV_DISPLAY_BASE + 0xb104)
+#define _MIPIB_CTRL                             (VLV_DISPLAY_BASE + 0xb904)
+#define MIPI_CTRL(pipe)                 _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
+#define  ESCAPE_CLOCK_DIVIDER_SHIFT                     5 /* A only */
+#define  ESCAPE_CLOCK_DIVIDER_MASK                      (3 << 5)
+#define  ESCAPE_CLOCK_DIVIDER_1                         (0 << 5)
+#define  ESCAPE_CLOCK_DIVIDER_2                         (1 << 5)
+#define  ESCAPE_CLOCK_DIVIDER_4                         (2 << 5)
+#define  READ_REQUEST_PRIORITY_SHIFT                    3
+#define  READ_REQUEST_PRIORITY_MASK                     (3 << 3)
+#define  READ_REQUEST_PRIORITY_LOW                      (0 << 3)
+#define  READ_REQUEST_PRIORITY_HIGH                     (3 << 3)
+#define  RGB_FLIP_TO_BGR                                (1 << 2)
+
+#define _MIPIA_DATA_ADDRESS                     (VLV_DISPLAY_BASE + 0xb108)
+#define _MIPIB_DATA_ADDRESS                     (VLV_DISPLAY_BASE + 0xb908)
+#define MIPI_DATA_ADDRESS(pipe)         _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
+#define  DATA_MEM_ADDRESS_SHIFT                         5
+#define  DATA_MEM_ADDRESS_MASK                          (0x7ffffff << 5)
+#define  DATA_VALID                                     (1 << 0)
+
+#define _MIPIA_DATA_LENGTH                      (VLV_DISPLAY_BASE + 0xb10c)
+#define _MIPIB_DATA_LENGTH                      (VLV_DISPLAY_BASE + 0xb90c)
+#define MIPI_DATA_LENGTH(pipe)          _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
+#define  DATA_LENGTH_SHIFT                              0
+#define  DATA_LENGTH_MASK                               (0xfffff << 0)
+
+#define _MIPIA_COMMAND_ADDRESS                  (VLV_DISPLAY_BASE + 0xb110)
+#define _MIPIB_COMMAND_ADDRESS                  (VLV_DISPLAY_BASE + 0xb910)
+#define MIPI_COMMAND_ADDRESS(pipe)      _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
+#define  COMMAND_MEM_ADDRESS_SHIFT                      5
+#define  COMMAND_MEM_ADDRESS_MASK                       (0x7ffffff << 5)
+#define  AUTO_PWG_ENABLE                                (1 << 2)
+#define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING          (1 << 1)
+#define  COMMAND_VALID                                  (1 << 0)
+
+#define _MIPIA_COMMAND_LENGTH                   (VLV_DISPLAY_BASE + 0xb114)
+#define _MIPIB_COMMAND_LENGTH                   (VLV_DISPLAY_BASE + 0xb914)
+#define MIPI_COMMAND_LENGTH(pipe)       _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
+#define  COMMAND_LENGTH_SHIFT(n)                        (8 * (n)) /* n: 0...3 */
+#define  COMMAND_LENGTH_MASK(n)                         (0xff << (8 * (n)))
+
+#define _MIPIA_READ_DATA_RETURN0                (VLV_DISPLAY_BASE + 0xb118)
+#define _MIPIB_READ_DATA_RETURN0                (VLV_DISPLAY_BASE + 0xb918)
+#define MIPI_READ_DATA_RETURN(pipe, n) \
+        (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
+
+#define _MIPIA_READ_DATA_VALID                  (VLV_DISPLAY_BASE + 0xb138)
+#define _MIPIB_READ_DATA_VALID                  (VLV_DISPLAY_BASE + 0xb938)
+#define MIPI_READ_DATA_VALID(pipe)      _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
+#define  READ_DATA_VALID(n)                             (1 << (n))
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 70db618989c4..3538370e3a47 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -340,7 +340,9 @@ int i915_save_state(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int i;
 
-        pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
+        if (INTEL_INFO(dev)->gen <= 4)
+                pci_read_config_byte(dev->pdev, LBB,
+                                     &dev_priv->regfile.saveLBB);
 
         mutex_lock(&dev->struct_mutex);
 
@@ -390,7 +392,9 @@ int i915_restore_state(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int i;
 
-        pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
+        if (INTEL_INFO(dev)->gen <= 4)
+                pci_write_config_byte(dev->pdev, LBB,
+                                      dev_priv->regfile.saveLBB);
 
         mutex_lock(&dev->struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index c8c4112de110..1beec51b8e26 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -32,30 +32,50 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+#define dev_to_drm_minor(d) dev_get_drvdata((d))
+
 #ifdef CONFIG_PM
 static u32 calc_residency(struct drm_device *dev, const u32 reg)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u64 raw_time; /* 32b value may overflow during fixed point math */
+        u64 units = 128ULL, div = 100000ULL, bias = 100ULL;
 
         if (!intel_enable_rc6(dev))
                 return 0;
 
-        raw_time = I915_READ(reg) * 128ULL;
-        return DIV_ROUND_UP_ULL(raw_time, 100000);
+        /* On VLV, residency time is in CZ units rather than 1.28us */
+        if (IS_VALLEYVIEW(dev)) {
+                u32 clkctl2;
+
+                clkctl2 = I915_READ(VLV_CLK_CTL2) >>
+                        CLK_CTL2_CZCOUNT_30NS_SHIFT;
+                if (!clkctl2) {
+                        WARN(!clkctl2, "bogus CZ count value");
+                        return 0;
+                }
+                units = DIV_ROUND_UP_ULL(30ULL * bias, (u64)clkctl2);
+                if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
+                        units <<= 8;
+
+                div = 1000000ULL * bias;
+        }
+
+        raw_time = I915_READ(reg) * units;
+        return DIV_ROUND_UP_ULL(raw_time, div);
 }
 
 static ssize_t
 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *dminor = dev_to_drm_minor(kdev);
         return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
 }
 
 static ssize_t
 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *dminor = dev_get_drvdata(kdev);
         u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
 }
@@ -63,16 +83,20 @@ show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 static ssize_t
 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *dminor = dev_to_drm_minor(kdev);
         u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
+        if (IS_VALLEYVIEW(dminor->dev))
+                rc6p_residency = 0;
         return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
 }
 
 static ssize_t
 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *dminor = dev_to_drm_minor(kdev);
         u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
+        if (IS_VALLEYVIEW(dminor->dev))
+                rc6pp_residency = 0;
         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
 }
 
@@ -97,7 +121,7 @@ static struct attribute_group rc6_attr_group = {
 
 static int l3_access_valid(struct drm_device *dev, loff_t offset)
 {
-        if (!HAS_L3_GPU_CACHE(dev))
+        if (!HAS_L3_DPF(dev))
                 return -EPERM;
 
         if (offset % 4 != 0)
@@ -115,31 +139,34 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
              loff_t offset, size_t count)
 {
         struct device *dev = container_of(kobj, struct device, kobj);
-        struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+        struct drm_minor *dminor = dev_to_drm_minor(dev);
         struct drm_device *drm_dev = dminor->dev;
         struct drm_i915_private *dev_priv = drm_dev->dev_private;
-        uint32_t misccpctl;
-        int i, ret;
+        int slice = (int)(uintptr_t)attr->private;
+        int ret;
+
+        count = round_down(count, 4);
 
         ret = l3_access_valid(drm_dev, offset);
         if (ret)
                 return ret;
 
+        count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
+
         ret = i915_mutex_lock_interruptible(drm_dev);
         if (ret)
                 return ret;
 
-        misccpctl = I915_READ(GEN7_MISCCPCTL);
-        I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-
-        for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
-                *((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
-
-        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+        if (dev_priv->l3_parity.remap_info[slice])
+                memcpy(buf,
+                       dev_priv->l3_parity.remap_info[slice] + (offset/4),
+                       count);
+        else
+                memset(buf, 0, count);
 
         mutex_unlock(&drm_dev->struct_mutex);
 
-        return i - offset;
+        return count;
 }
 
 static ssize_t
@@ -148,21 +175,26 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
               loff_t offset, size_t count)
 {
         struct device *dev = container_of(kobj, struct device, kobj);
-        struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
+        struct drm_minor *dminor = dev_to_drm_minor(dev);
         struct drm_device *drm_dev = dminor->dev;
         struct drm_i915_private *dev_priv = drm_dev->dev_private;
+        struct i915_hw_context *ctx;
         u32 *temp = NULL; /* Just here to make handling failures easy */
+        int slice = (int)(uintptr_t)attr->private;
         int ret;
 
         ret = l3_access_valid(drm_dev, offset);
         if (ret)
                 return ret;
 
+        if (dev_priv->hw_contexts_disabled)
+                return -ENXIO;
+
         ret = i915_mutex_lock_interruptible(drm_dev);
         if (ret)
                 return ret;
 
-        if (!dev_priv->l3_parity.remap_info) {
+        if (!dev_priv->l3_parity.remap_info[slice]) {
                 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
                 if (!temp) {
                         mutex_unlock(&drm_dev->struct_mutex);
@@ -182,13 +214,13 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
          * at this point it is left as a TODO.
         */
         if (temp)
-                dev_priv->l3_parity.remap_info = temp;
+                dev_priv->l3_parity.remap_info[slice] = temp;
 
-        memcpy(dev_priv->l3_parity.remap_info + (offset/4),
-               buf + (offset/4),
-               count);
+        memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
 
-        i915_gem_l3_remap(drm_dev);
+        /* NB: We defer the remapping until we switch to the context */
+        list_for_each_entry(ctx, &dev_priv->context_list, link)
+                ctx->remap_slice |= (1<<slice);
 
         mutex_unlock(&drm_dev->struct_mutex);
 
@@ -200,13 +232,23 @@ static struct bin_attribute dpf_attrs = {
         .size = GEN7_L3LOG_SIZE,
         .read = i915_l3_read,
         .write = i915_l3_write,
-        .mmap = NULL
+        .mmap = NULL,
+        .private = (void *)0
+};
+
+static struct bin_attribute dpf_attrs_1 = {
+        .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
+        .size = GEN7_L3LOG_SIZE,
+        .read = i915_l3_read,
+        .write = i915_l3_write,
+        .mmap = NULL,
+        .private = (void *)1
 };
 
 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
                                     struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int ret;
@@ -227,7 +269,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
                                      struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -238,7 +280,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 
 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int ret;
@@ -257,7 +299,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
                                      struct device_attribute *attr,
                                      const char *buf, size_t count)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
@@ -310,7 +352,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int ret;
@@ -329,7 +371,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
                                      struct device_attribute *attr,
                                      const char *buf, size_t count)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 val, rp_state_cap, hw_max, hw_min;
@@ -388,7 +430,7 @@ static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 /* For now we have a static number of RP states */
 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 val, rp_state_cap;
@@ -436,7 +478,7 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 {
 
         struct device *kdev = container_of(kobj, struct device, kobj);
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct i915_error_state_file_priv error_priv;
         struct drm_i915_error_state_buf error_str;
@@ -471,7 +513,7 @@ static ssize_t error_state_write(struct file *file, struct kobject *kobj,
                                  loff_t off, size_t count)
 {
         struct device *kdev = container_of(kobj, struct device, kobj);
-        struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+        struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         int ret;
 
@@ -501,27 +543,34 @@ void i915_setup_sysfs(struct drm_device *dev)
 
 #ifdef CONFIG_PM
         if (INTEL_INFO(dev)->gen >= 6) {
-                ret = sysfs_merge_group(&dev->primary->kdev.kobj,
+                ret = sysfs_merge_group(&dev->primary->kdev->kobj,
                                         &rc6_attr_group);
                 if (ret)
                         DRM_ERROR("RC6 residency sysfs setup failed\n");
         }
 #endif
-        if (HAS_L3_GPU_CACHE(dev)) {
-                ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
+        if (HAS_L3_DPF(dev)) {
+                ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
                 if (ret)
                         DRM_ERROR("l3 parity sysfs setup failed\n");
+
+                if (NUM_L3_SLICES(dev) > 1) {
+                        ret = device_create_bin_file(dev->primary->kdev,
+                                                     &dpf_attrs_1);
+                        if (ret)
+                                DRM_ERROR("l3 parity slice 1 setup failed\n");
+                }
         }
 
         ret = 0;
         if (IS_VALLEYVIEW(dev))
-                ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
+                ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
         else if (INTEL_INFO(dev)->gen >= 6)
-                ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
+                ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
         if (ret)
                 DRM_ERROR("RPS sysfs setup failed\n");
 
-        ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
+        ret = sysfs_create_bin_file(&dev->primary->kdev->kobj,
                                     &error_state_attr);
         if (ret)
                 DRM_ERROR("error_state sysfs setup failed\n");
@@ -529,13 +578,14 @@ void i915_setup_sysfs(struct drm_device *dev)
 
 void i915_teardown_sysfs(struct drm_device *dev)
 {
-        sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
+        sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
         if (IS_VALLEYVIEW(dev))
-                sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
+                sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
         else
-                sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
-        device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
+                sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
+        device_remove_bin_file(dev->primary->kdev,  &dpf_attrs_1);
+        device_remove_bin_file(dev->primary->kdev,  &dpf_attrs);
 #ifdef CONFIG_PM
-        sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
+        sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);
 #endif
 }
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index e2c5ee6f6194..6e580c98dede 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -233,6 +233,47 @@ TRACE_EVENT(i915_gem_evict_everything,
             TP_printk("dev=%d", __entry->dev)
 );
 
+TRACE_EVENT(i915_gem_evict_vm,
+            TP_PROTO(struct i915_address_space *vm),
+            TP_ARGS(vm),
+
+            TP_STRUCT__entry(
+                             __field(struct i915_address_space *, vm)
+                            ),
+
+            TP_fast_assign(
+                           __entry->vm = vm;
+                          ),
+
+            TP_printk("dev=%d, vm=%p", __entry->vm->dev->primary->index, __entry->vm)
+);
+
+TRACE_EVENT(i915_gem_ring_sync_to,
+            TP_PROTO(struct intel_ring_buffer *from,
+                     struct intel_ring_buffer *to,
+                     u32 seqno),
+            TP_ARGS(from, to, seqno),
+
+            TP_STRUCT__entry(
+                             __field(u32, dev)
+                             __field(u32, sync_from)
+                             __field(u32, sync_to)
+                             __field(u32, seqno)
+                             ),
+
+            TP_fast_assign(
+                           __entry->dev = from->dev->primary->index;
+                           __entry->sync_from = from->id;
+                           __entry->sync_to = to->id;
+                           __entry->seqno = seqno;
+                           ),
+
+            TP_printk("dev=%u, sync-from=%u, sync-to=%u, seqno=%u",
+                      __entry->dev,
+                      __entry->sync_from, __entry->sync_to,
+                      __entry->seqno)
+);
+
 TRACE_EVENT(i915_gem_ring_dispatch,
             TP_PROTO(struct intel_ring_buffer *ring, u32 seqno, u32 flags),
             TP_ARGS(ring, seqno, flags),
@@ -304,9 +345,24 @@ DEFINE_EVENT(i915_gem_request, i915_gem_request_add,
             TP_ARGS(ring, seqno)
 );
 
-DEFINE_EVENT(i915_gem_request, i915_gem_request_complete,
-            TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
-            TP_ARGS(ring, seqno)
+TRACE_EVENT(i915_gem_request_complete,
+            TP_PROTO(struct intel_ring_buffer *ring),
+            TP_ARGS(ring),
+
+            TP_STRUCT__entry(
+                             __field(u32, dev)
+                             __field(u32, ring)
+                             __field(u32, seqno)
+                             ),
+
+            TP_fast_assign(
+                           __entry->dev = ring->dev->primary->index;
+                           __entry->ring = ring->id;
+                           __entry->seqno = ring->get_seqno(ring, false);
+                           ),
+
+            TP_printk("dev=%u, ring=%u, seqno=%u",
+                      __entry->dev, __entry->ring, __entry->seqno)
 );
 
 DEFINE_EVENT(i915_gem_request, i915_gem_request_retire,
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 53f2bed8bc5f..e29bcae1ef81 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -389,7 +389,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
 {
         struct sdvo_device_mapping *p_mapping;
         struct bdb_general_definitions *p_defs;
-        struct child_device_config *p_child;
+        union child_device_config *p_child;
         int i, child_device_num, count;
         u16     block_size;
 
@@ -416,36 +416,36 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
         count = 0;
         for (i = 0; i < child_device_num; i++) {
                 p_child = &(p_defs->devices[i]);
-                if (!p_child->device_type) {
+                if (!p_child->old.device_type) {
                         /* skip the device block if device type is invalid */
                         continue;
                 }
-                if (p_child->slave_addr != SLAVE_ADDR1 &&
-                        p_child->slave_addr != SLAVE_ADDR2) {
+                if (p_child->old.slave_addr != SLAVE_ADDR1 &&
+                        p_child->old.slave_addr != SLAVE_ADDR2) {
                         /*
                          * If the slave address is neither 0x70 nor 0x72,
                          * it is not a SDVO device. Skip it.
                          */
                         continue;
                 }
-                if (p_child->dvo_port != DEVICE_PORT_DVOB &&
-                        p_child->dvo_port != DEVICE_PORT_DVOC) {
+                if (p_child->old.dvo_port != DEVICE_PORT_DVOB &&
+                        p_child->old.dvo_port != DEVICE_PORT_DVOC) {
                         /* skip the incorrect SDVO port */
                         DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
                         continue;
                 }
                 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
                                 " %s port\n",
-                                p_child->slave_addr,
-                                (p_child->dvo_port == DEVICE_PORT_DVOB) ?
+                                p_child->old.slave_addr,
+                                (p_child->old.dvo_port == DEVICE_PORT_DVOB) ?
                                         "SDVOB" : "SDVOC");
-                p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);
+                p_mapping = &(dev_priv->sdvo_mappings[p_child->old.dvo_port - 1]);
                 if (!p_mapping->initialized) {
-                        p_mapping->dvo_port = p_child->dvo_port;
-                        p_mapping->slave_addr = p_child->slave_addr;
-                        p_mapping->dvo_wiring = p_child->dvo_wiring;
-                        p_mapping->ddc_pin = p_child->ddc_pin;
-                        p_mapping->i2c_pin = p_child->i2c_pin;
+                        p_mapping->dvo_port = p_child->old.dvo_port;
+                        p_mapping->slave_addr = p_child->old.slave_addr;
+                        p_mapping->dvo_wiring = p_child->old.dvo_wiring;
+                        p_mapping->ddc_pin = p_child->old.ddc_pin;
+                        p_mapping->i2c_pin = p_child->old.i2c_pin;
                         p_mapping->initialized = 1;
                         DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
                                       p_mapping->dvo_port,
@@ -457,7 +457,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
                         DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
                                          "two SDVO device.\n");
                 }
-                if (p_child->slave2_addr) {
+                if (p_child->old.slave2_addr) {
                         /* Maybe this is a SDVO device with multiple inputs */
                         /* And the mapping info is not added */
                         DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
@@ -477,15 +477,13 @@ static void
 parse_driver_features(struct drm_i915_private *dev_priv,
                        struct bdb_header *bdb)
 {
-        struct drm_device *dev = dev_priv->dev;
         struct bdb_driver_features *driver;
 
         driver = find_section(bdb, BDB_DRIVER_FEATURES);
         if (!driver)
                 return;
 
-        if (SUPPORTS_EDP(dev) &&
-            driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
+        if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
                 dev_priv->vbt.edp_support = 1;
 
         if (driver->dual_frequency)
@@ -501,7 +499,7 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
 
         edp = find_section(bdb, BDB_EDP);
         if (!edp) {
-                if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->vbt.edp_support)
+                if (dev_priv->vbt.edp_support)
                         DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
                 return;
         }
@@ -569,11 +567,149 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
 }
 
 static void
+parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+{
+        struct bdb_mipi *mipi;
+
+        mipi = find_section(bdb, BDB_MIPI);
+        if (!mipi) {
+                DRM_DEBUG_KMS("No MIPI BDB found");
+                return;
+        }
+
+        /* XXX: add more info */
+        dev_priv->vbt.dsi.panel_id = mipi->panel_id;
+}
+
+static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
+                           struct bdb_header *bdb)
+{
+        union child_device_config *it, *child = NULL;
+        struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
+        uint8_t hdmi_level_shift;
+        int i, j;
+        bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
+        uint8_t aux_channel;
+        /* Each DDI port can have more than one value on the "DVO Port" field,
+         * so look for all the possible values for each port and abort if more
+         * than one is found. */
+        int dvo_ports[][2] = {
+                {DVO_PORT_HDMIA, DVO_PORT_DPA},
+                {DVO_PORT_HDMIB, DVO_PORT_DPB},
+                {DVO_PORT_HDMIC, DVO_PORT_DPC},
+                {DVO_PORT_HDMID, DVO_PORT_DPD},
+                {DVO_PORT_CRT, -1 /* Port E can only be DVO_PORT_CRT */ },
+        };
+
+        /* Find the child device to use, abort if more than one found. */
+        for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
+                it = dev_priv->vbt.child_dev + i;
+
+                for (j = 0; j < 2; j++) {
+                        if (dvo_ports[port][j] == -1)
+                                break;
+
+                        if (it->common.dvo_port == dvo_ports[port][j]) {
+                                if (child) {
+                                        DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n",
+                                                      port_name(port));
+                                        return;
+                                }
+                                child = it;
+                        }
+                }
+        }
+        if (!child)
+                return;
+
+        aux_channel = child->raw[25];
+
+        is_dvi = child->common.device_type & (1 << 4);
+        is_dp = child->common.device_type & (1 << 2);
+        is_crt = child->common.device_type & (1 << 0);
+        is_hdmi = is_dvi && (child->common.device_type & (1 << 11)) == 0;
+        is_edp = is_dp && (child->common.device_type & (1 << 12));
+
+        info->supports_dvi = is_dvi;
+        info->supports_hdmi = is_hdmi;
+        info->supports_dp = is_dp;
+
+        DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n",
+                      port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt);
+
+        if (is_edp && is_dvi)
+                DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
+                              port_name(port));
+        if (is_crt && port != PORT_E)
+                DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
+        if (is_crt && (is_dvi || is_dp))
+                DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
+                              port_name(port));
+        if (is_dvi && (port == PORT_A || port == PORT_E))
+                DRM_DEBUG_KMS("Port %c is TMDS compabile\n", port_name(port));
+        if (!is_dvi && !is_dp && !is_crt)
+                DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
+                              port_name(port));
+        if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
+                DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
+
+        if (is_dvi) {
+                if (child->common.ddc_pin == 0x05 && port != PORT_B)
+                        DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
+                if (child->common.ddc_pin == 0x04 && port != PORT_C)
+                        DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
+                if (child->common.ddc_pin == 0x06 && port != PORT_D)
+                        DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
+        }
+
+        if (is_dp) {
+                if (aux_channel == 0x40 && port != PORT_A)
+                        DRM_DEBUG_KMS("Unexpected AUX channel for port A\n");
+                if (aux_channel == 0x10 && port != PORT_B)
+                        DRM_DEBUG_KMS("Unexpected AUX channel for port B\n");
+                if (aux_channel == 0x20 && port != PORT_C)
+                        DRM_DEBUG_KMS("Unexpected AUX channel for port C\n");
+                if (aux_channel == 0x30 && port != PORT_D)
+                        DRM_DEBUG_KMS("Unexpected AUX channel for port D\n");
+        }
+
+        if (bdb->version >= 158) {
+                /* The VBT HDMI level shift values match the table we have. */
+                hdmi_level_shift = child->raw[7] & 0xF;
+                if (hdmi_level_shift < 0xC) {
+                        DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
+                                      port_name(port),
+                                      hdmi_level_shift);
+                        info->hdmi_level_shift = hdmi_level_shift;
+                }
+        }
+}
+
+static void parse_ddi_ports(struct drm_i915_private *dev_priv,
+                            struct bdb_header *bdb)
+{
+        struct drm_device *dev = dev_priv->dev;
+        enum port port;
+
+        if (!HAS_DDI(dev))
+                return;
+
+        if (!dev_priv->vbt.child_dev_num)
+                return;
+
+        if (bdb->version < 155)
+                return;
+
+        for (port = PORT_A; port < I915_MAX_PORTS; port++)
+                parse_ddi_port(dev_priv, port, bdb);
+}
+
+static void
 parse_device_mapping(struct drm_i915_private *dev_priv,
                        struct bdb_header *bdb)
 {
         struct bdb_general_definitions *p_defs;
-        struct child_device_config *p_child, *child_dev_ptr;
+        union child_device_config *p_child, *child_dev_ptr;
         int i, child_device_num, count;
         u16     block_size;
 
@@ -601,7 +737,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
         /* get the number of child device that is present */
         for (i = 0; i < child_device_num; i++) {
                 p_child = &(p_defs->devices[i]);
-                if (!p_child->device_type) {
+                if (!p_child->common.device_type) {
                         /* skip the device block if device type is invalid */
                         continue;
                 }
@@ -621,7 +757,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
         count = 0;
         for (i = 0; i < child_device_num; i++) {
                 p_child = &(p_defs->devices[i]);
-                if (!p_child->device_type) {
+                if (!p_child->common.device_type) {
                         /* skip the device block if device type is invalid */
                         continue;
                 }
@@ -637,6 +773,7 @@ static void
 init_vbt_defaults(struct drm_i915_private *dev_priv)
 {
         struct drm_device *dev = dev_priv->dev;
+        enum port port;
 
         dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
 
@@ -655,6 +792,18 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
         dev_priv->vbt.lvds_use_ssc = 1;
         dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
         DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
+
+        for (port = PORT_A; port < I915_MAX_PORTS; port++) {
+                struct ddi_vbt_port_info *info =
+                        &dev_priv->vbt.ddi_port_info[port];
+
+                /* Recommended BSpec default: 800mV 0dB. */
+                info->hdmi_level_shift = 6;
+
+                info->supports_dvi = (port != PORT_A && port != PORT_E);
+                info->supports_hdmi = info->supports_dvi;
+                info->supports_dp = (port != PORT_E);
+        }
 }
 
 static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
@@ -745,6 +894,8 @@ intel_parse_bios(struct drm_device *dev)
         parse_device_mapping(dev_priv, bdb);
         parse_driver_features(dev_priv, bdb);
         parse_edp(dev_priv, bdb);
+        parse_mipi(dev_priv, bdb);
+        parse_ddi_ports(dev_priv, bdb);
 
         if (bios)
                 pci_unmap_rom(pdev, bios);
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index e088d6f0956a..287cc5a21c2e 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -104,6 +104,7 @@ struct vbios_data {
 #define BDB_LVDS_LFP_DATA        42
 #define BDB_LVDS_BACKLIGHT       43
 #define BDB_LVDS_POWER           44
+#define BDB_MIPI                 50
 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 
 struct bdb_general_features {
@@ -201,7 +202,10 @@ struct bdb_general_features {
 #define DEVICE_PORT_DVOB        0x01
 #define DEVICE_PORT_DVOC        0x02
 
-struct child_device_config {
+/* We used to keep this struct but without any version control. We should avoid
+ * using it in the future, but it should be safe to keep using it in the old
+ * code. */
+struct old_child_dev_config {
         u16 handle;
         u16 device_type;
         u8  device_id[10]; /* ascii string */
@@ -223,6 +227,32 @@ struct child_device_config {
         u8  dvo_function;
 } __attribute__((packed));
 
+/* This one contains field offsets that are known to be common for all BDB
+ * versions. Notice that the meaning of the contents contents may still change,
+ * but at least the offsets are consistent. */
+struct common_child_dev_config {
+        u16 handle;
+        u16 device_type;
+        u8 not_common1[12];
+        u8 dvo_port;
+        u8 not_common2[2];
+        u8 ddc_pin;
+        u16 edid_ptr;
+} __attribute__((packed));
+
+/* This field changes depending on the BDB version, so the most reliable way to
+ * read it is by checking the BDB version and reading the raw pointer. */
+union child_device_config {
+        /* This one is safe to be used anywhere, but the code should still check
+         * the BDB version. */
+        u8 raw[33];
+        /* This one should only be kept for legacy code. */
+        struct old_child_dev_config old;
+        /* This one should also be safe to use anywhere, even without version
+         * checks. */
+        struct common_child_dev_config common;
+};
+
 struct bdb_general_definitions {
         /* DDC GPIO */
         u8 crt_ddc_gmbus_pin;
@@ -248,7 +278,7 @@ struct bdb_general_definitions {
          * number = (block_size - sizeof(bdb_general_definitions))/
          *           sizeof(child_device_config);
          */
-        struct child_device_config devices[0];
+        union child_device_config devices[0];
 } __attribute__((packed));
 
 struct bdb_lvds_options {
@@ -618,4 +648,57 @@ int intel_parse_bios(struct drm_device *dev);
 #define         PORT_IDPC       8
 #define         PORT_IDPD       9
 
+/* Possible values for the "DVO Port" field for versions >= 155: */
+#define DVO_PORT_HDMIA  0
+#define DVO_PORT_HDMIB  1
+#define DVO_PORT_HDMIC  2
+#define DVO_PORT_HDMID  3
+#define DVO_PORT_LVDS   4
+#define DVO_PORT_TV     5
+#define DVO_PORT_CRT    6
+#define DVO_PORT_DPB    7
+#define DVO_PORT_DPC    8
+#define DVO_PORT_DPD    9
+#define DVO_PORT_DPA    10
+
+/* MIPI DSI panel info */
+struct bdb_mipi {
+        u16 panel_id;
+        u16 bridge_revision;
+
+        /* General params */
+        u32 dithering:1;
+        u32 bpp_pixel_format:1;
+        u32 rsvd1:1;
+        u32 dphy_valid:1;
+        u32 resvd2:28;
+
+        u16 port_info;
+        u16 rsvd3:2;
+        u16 num_lanes:2;
+        u16 rsvd4:12;
+
+        /* DSI config */
+        u16 virt_ch_num:2;
+        u16 vtm:2;
+        u16 rsvd5:12;
+
+        u32 dsi_clock;
+        u32 bridge_ref_clk;
+        u16 rsvd_pwr;
+
+        /* Dphy Params */
+        u32 prepare_cnt:5;
+        u32 rsvd6:3;
+        u32 clk_zero_cnt:8;
+        u32 trail_cnt:5;
+        u32 rsvd7:3;
+        u32 exit_zero_cnt:6;
+        u32 rsvd8:2;
+
+        u32 hl_switch_cnt;
+        u32 lp_byte_clk;
+        u32 clk_lane_switch_cnt;
+} __attribute__((packed));
+
 #endif /* _I830_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index ea9022ef15d5..942b9acb0d8e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -83,8 +83,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
         return true;
 }
 
-static void intel_crt_get_config(struct intel_encoder *encoder,
-                                 struct intel_crtc_config *pipe_config)
+static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 {
         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
         struct intel_crt *crt = intel_encoder_to_crt(encoder);
@@ -102,7 +101,35 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
         else
                 flags |= DRM_MODE_FLAG_NVSYNC;
 
-        pipe_config->adjusted_mode.flags |= flags;
+        return flags;
+}
+
+static void intel_crt_get_config(struct intel_encoder *encoder,
+                                 struct intel_crtc_config *pipe_config)
+{
+        struct drm_device *dev = encoder->base.dev;
+        int dotclock;
+
+        pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
+
+        dotclock = pipe_config->port_clock;
+
+        if (HAS_PCH_SPLIT(dev))
+                ironlake_check_encoder_dotclock(pipe_config, dotclock);
+
+        pipe_config->adjusted_mode.crtc_clock = dotclock;
+}
+
+static void hsw_crt_get_config(struct intel_encoder *encoder,
+                               struct intel_crtc_config *pipe_config)
+{
+        intel_ddi_get_config(encoder, pipe_config);
+
+        pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
+                                              DRM_MODE_FLAG_NHSYNC |
+                                              DRM_MODE_FLAG_PVSYNC |
+                                              DRM_MODE_FLAG_NVSYNC);
+        pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
 }
 
 /* Note: The caller is required to filter out dpms modes not supported by the
@@ -349,9 +376,6 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 
         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 
-        /* FIXME: debug force function and remove */
-        ret = true;
-
         return ret;
 }
 
@@ -653,7 +677,6 @@ intel_crt_detect(struct drm_connector *connector, bool force)
 
 static void intel_crt_destroy(struct drm_connector *connector)
 {
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(connector);
 }
@@ -759,7 +782,7 @@ void intel_crt_init(struct drm_device *dev)
         if (!crt)
                 return;
 
-        intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
+        intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
         if (!intel_connector) {
                 kfree(crt);
                 return;
@@ -799,7 +822,10 @@ void intel_crt_init(struct drm_device *dev)
         crt->base.mode_set = intel_crt_mode_set;
         crt->base.disable = intel_disable_crt;
         crt->base.enable = intel_enable_crt;
-        crt->base.get_config = intel_crt_get_config;
+        if (IS_HASWELL(dev))
+                crt->base.get_config = hsw_crt_get_config;
+        else
+                crt->base.get_config = intel_crt_get_config;
         if (I915_HAS_HOTPLUG(dev))
                 crt->base.hpd_pin = HPD_CRT;
         if (HAS_DDI(dev))
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 63de2701b974..6d335f8ca343 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -42,7 +42,6 @@ static const u32 hsw_ddi_translations_dp[] = {
         0x80C30FFF, 0x000B0000,
         0x00FFFFFF, 0x00040006,
         0x80D75FFF, 0x000B0000,
-        0x00FFFFFF, 0x00040006          /* HDMI parameters */
 };
 
 static const u32 hsw_ddi_translations_fdi[] = {
@@ -55,10 +54,25 @@ static const u32 hsw_ddi_translations_fdi[] = {
         0x00C30FFF, 0x001E0000,
         0x00FFFFFF, 0x00060006,
         0x00D75FFF, 0x001E0000,
-        0x00FFFFFF, 0x00040006          /* HDMI parameters */
 };
 
-static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
+static const u32 hsw_ddi_translations_hdmi[] = {
+                                /* Idx  NT mV diff      T mV diff       db  */
+        0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
+        0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
+        0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
+        0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
+        0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
+        0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
+        0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
+        0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
+        0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
+        0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
+        0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
+        0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
+};
+
+enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 {
         struct drm_encoder *encoder = &intel_encoder->base;
         int type = intel_encoder->type;
@@ -92,12 +106,18 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
         const u32 *ddi_translations = (port == PORT_E) ?
                 hsw_ddi_translations_fdi :
                 hsw_ddi_translations_dp;
+        int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
         for (i = 0, reg = DDI_BUF_TRANS(port);
              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
                 I915_WRITE(reg, ddi_translations[i]);
                 reg += 4;
         }
+        /* Entry 9 is for HDMI: */
+        for (i = 0; i < 2; i++) {
+                I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
+                reg += 4;
+        }
 }
 
 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
@@ -296,9 +316,6 @@ static void intel_ddi_mode_set(struct intel_encoder *encoder)
                         DRM_DEBUG_DRIVER("DP audio: write eld information\n");
                         intel_write_eld(&encoder->base, adjusted_mode);
                 }
-
-                intel_dp_init_link_config(intel_dp);
-
         } else if (type == INTEL_OUTPUT_HDMI) {
                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 
@@ -767,9 +784,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
                 BUG();
         }
 
-        if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
+        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
                 temp |= TRANS_DDI_PVSYNC;
-        if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
+        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
                 temp |= TRANS_DDI_PHSYNC;
 
         if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1202,7 +1219,7 @@ void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
 
         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
-        if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+        if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
         I915_WRITE(DP_TP_CTL(port), val);
         POSTING_READ(DP_TP_CTL(port));
@@ -1249,8 +1266,8 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
                 intel_dp_check_link_status(intel_dp);
 }
 
-static void intel_ddi_get_config(struct intel_encoder *encoder,
-                                 struct intel_crtc_config *pipe_config)
+void intel_ddi_get_config(struct intel_encoder *encoder,
+                          struct intel_crtc_config *pipe_config)
 {
         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -1268,6 +1285,37 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
                 flags |= DRM_MODE_FLAG_NVSYNC;
 
         pipe_config->adjusted_mode.flags |= flags;
+
+        switch (temp & TRANS_DDI_BPC_MASK) {
+        case TRANS_DDI_BPC_6:
+                pipe_config->pipe_bpp = 18;
+                break;
+        case TRANS_DDI_BPC_8:
+                pipe_config->pipe_bpp = 24;
+                break;
+        case TRANS_DDI_BPC_10:
+                pipe_config->pipe_bpp = 30;
+                break;
+        case TRANS_DDI_BPC_12:
+                pipe_config->pipe_bpp = 36;
+                break;
+        default:
+                break;
+        }
+
+        switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
+        case TRANS_DDI_MODE_SELECT_HDMI:
+        case TRANS_DDI_MODE_SELECT_DVI:
+        case TRANS_DDI_MODE_SELECT_FDI:
+                break;
+        case TRANS_DDI_MODE_SELECT_DP_SST:
+        case TRANS_DDI_MODE_SELECT_DP_MST:
+                pipe_config->has_dp_encoder = true;
+                intel_dp_get_m_n(intel_crtc, pipe_config);
+                break;
+        default:
+                break;
+        }
 }
 
 static void intel_ddi_destroy(struct drm_encoder *encoder)
@@ -1305,12 +1353,23 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
         struct drm_encoder *encoder;
         struct intel_connector *hdmi_connector = NULL;
         struct intel_connector *dp_connector = NULL;
+        bool init_hdmi, init_dp;
+
+        init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
+                     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
+        init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
+        if (!init_dp && !init_hdmi) {
+                DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
+                              port_name(port));
+                init_hdmi = true;
+                init_dp = true;
+        }
 
-        intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
+        intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
         if (!intel_dig_port)
                 return;
 
-        dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
+        dp_connector = kzalloc(sizeof(*dp_connector), GFP_KERNEL);
         if (!dp_connector) {
                 kfree(intel_dig_port);
                 return;
@@ -1342,19 +1401,20 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
         intel_encoder->cloneable = false;
         intel_encoder->hot_plug = intel_ddi_hot_plug;
 
-        if (!intel_dp_init_connector(intel_dig_port, dp_connector)) {
+        if (init_dp && !intel_dp_init_connector(intel_dig_port, dp_connector)) {
                 drm_encoder_cleanup(encoder);
                 kfree(intel_dig_port);
                 kfree(dp_connector);
                 return;
         }
 
-        if (intel_encoder->type != INTEL_OUTPUT_EDP) {
-                hdmi_connector = kzalloc(sizeof(struct intel_connector),
+        /* In theory we don't need the encoder->type check, but leave it just in
+         * case we have some really bad VBTs... */
+        if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
+                hdmi_connector = kzalloc(sizeof(*hdmi_connector),
                                          GFP_KERNEL);
-                if (!hdmi_connector) {
+                if (!hdmi_connector)
                         return;
-                }
 
                 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
                 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5822e79f912..617b963dfb67 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -41,14 +41,13 @@
 #include <drm/drm_crtc_helper.h>
 #include <linux/dma_remapping.h>
 
-bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 static void intel_increase_pllclock(struct drm_crtc *crtc);
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                 struct intel_crtc_config *pipe_config);
-static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
-                                    struct intel_crtc_config *pipe_config);
+static void ironlake_pch_clock_get(struct intel_crtc *crtc,
+                                   struct intel_crtc_config *pipe_config);
 
 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
                           int x, int y, struct drm_framebuffer *old_fb);
@@ -69,9 +68,6 @@ struct intel_limit {
         intel_p2_t          p2;
 };
 
-/* FDI */
-#define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
-
 int
 intel_pch_rawclk(struct drm_device *dev)
 {
@@ -339,18 +335,20 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
                 .p2_slow = 2, .p2_fast = 20 },
 };
 
-static const intel_limit_t intel_limits_vlv_dp = {
-        .dot = { .min = 25000, .max = 270000 },
-        .vco = { .min = 4000000, .max = 6000000 },
-        .n = { .min = 1, .max = 7 },
-        .m = { .min = 22, .max = 450 },
-        .m1 = { .min = 2, .max = 3 },
-        .m2 = { .min = 11, .max = 156 },
-        .p = { .min = 10, .max = 30 },
-        .p1 = { .min = 1, .max = 3 },
-        .p2 = { .dot_limit = 270000,
-                .p2_slow = 2, .p2_fast = 20 },
-};
+/**
+ * Returns whether any output on the specified pipe is of the specified type
+ */
+static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
+{
+        struct drm_device *dev = crtc->dev;
+        struct intel_encoder *encoder;
+
+        for_each_encoder_on_crtc(dev, crtc, encoder)
+                if (encoder->type == type)
+                        return true;
+
+        return false;
+}
 
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
                                                 int refclk)
@@ -414,10 +412,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
         } else if (IS_VALLEYVIEW(dev)) {
                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
                         limit = &intel_limits_vlv_dac;
-                else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
-                        limit = &intel_limits_vlv_hdmi;
                 else
-                        limit = &intel_limits_vlv_dp;
+                        limit = &intel_limits_vlv_hdmi;
         } else if (!IS_GEN2(dev)) {
                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                         limit = &intel_limits_i9xx_lvds;
@@ -456,21 +452,6 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
         clock->dot = clock->vco / clock->p;
 }
 
-/**
- * Returns whether any output on the specified pipe is of the specified type
- */
-bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
-{
-        struct drm_device *dev = crtc->dev;
-        struct intel_encoder *encoder;
-
-        for_each_encoder_on_crtc(dev, crtc, encoder)
-                if (encoder->type == type)
-                        return true;
-
-        return false;
-}
-
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
@@ -714,29 +695,30 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
                                 p = p1 * p2;
                                 /* based on hardware requirement, prefer bigger m1,m2 values */
                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
-                                        m2 = (((2*(fastclk * p * n / m1 )) +
-                                               refclk) / (2*refclk));
+                                        m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
                                         m = m1 * m2;
                                         vco = updrate * m;
-                                        if (vco >= limit->vco.min && vco < limit->vco.max) {
-                                                ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
-                                                absppm = (ppm > 0) ? ppm : (-ppm);
-                                                if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
-                                                        bestppm = 0;
-                                                        flag = 1;
-                                                }
-                                                if (absppm < bestppm - 10) {
-                                                        bestppm = absppm;
-                                                        flag = 1;
-                                                }
-                                                if (flag) {
-                                                        bestn = n;
-                                                        bestm1 = m1;
-                                                        bestm2 = m2;
-                                                        bestp1 = p1;
-                                                        bestp2 = p2;
-                                                        flag = 0;
-                                                }
+
+                                        if (vco < limit->vco.min || vco >= limit->vco.max)
+                                                continue;
+
+                                        ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
+                                        absppm = (ppm > 0) ? ppm : (-ppm);
+                                        if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
+                                                bestppm = 0;
+                                                flag = 1;
+                                        }
+                                        if (absppm < bestppm - 10) {
+                                                bestppm = absppm;
+                                                flag = 1;
+                                        }
+                                        if (flag) {
+                                                bestn = n;
+                                                bestm1 = m1;
+                                                bestm2 = m2;
+                                                bestp1 = p1;
+                                                bestp2 = p2;
+                                                flag = 0;
                                         }
                                 }
                         }
@@ -751,6 +733,23 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
         return true;
 }
 
+bool intel_crtc_active(struct drm_crtc *crtc)
+{
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+        /* Be paranoid as we can arrive here with only partial
+         * state retrieved from the hardware during setup.
+         *
+         * We can ditch the adjusted_mode.crtc_clock check as soon
+         * as Haswell has gained clock readout/fastboot support.
+         *
+         * We can ditch the crtc->fb check as soon as we can
+         * properly reconstruct framebuffers.
+         */
+        return intel_crtc->active && crtc->fb &&
+                intel_crtc->config.adjusted_mode.crtc_clock;
+}
+
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
                                              enum pipe pipe)
 {
@@ -929,6 +928,24 @@ void assert_pll(struct drm_i915_private *dev_priv,
              state_string(state), state_string(cur_state));
 }
 
+/* XXX: the dsi pll is shared between MIPI DSI ports */
+static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
+{
+        u32 val;
+        bool cur_state;
+
+        mutex_lock(&dev_priv->dpio_lock);
+        val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+        mutex_unlock(&dev_priv->dpio_lock);
+
+        cur_state = val & DSI_PLL_VCO_EN;
+        WARN(cur_state != state,
+             "DSI PLL state assertion failure (expected %s, current %s)\n",
+             state_string(state), state_string(cur_state));
+}
+#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
+#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
+
 struct intel_shared_dpll *
 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 {
@@ -1069,6 +1086,26 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
              pipe_name(pipe));
 }
 
+static void assert_cursor(struct drm_i915_private *dev_priv,
+                          enum pipe pipe, bool state)
+{
+        struct drm_device *dev = dev_priv->dev;
+        bool cur_state;
+
+        if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+                cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
+        else if (IS_845G(dev) || IS_I865G(dev))
+                cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
+        else
+                cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
+
+        WARN(cur_state != state,
+             "cursor on pipe %c assertion failure (expected %s, current %s)\n",
+             pipe_name(pipe), state_string(state), state_string(cur_state));
+}
+#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
+#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
+
 void assert_pipe(struct drm_i915_private *dev_priv,
                  enum pipe pipe, bool state)
 {
@@ -1323,6 +1360,26 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
 }
 
+static void intel_init_dpio(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (!IS_VALLEYVIEW(dev))
+                return;
+
+        /*
+         * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
+         *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
+         *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
+         *   b. The other bits such as sfr settings / modesel may all be set
+         *      to 0.
+         *
+         * This should only be done on init and resume from S3 with both
+         * PLLs disabled, or we risk losing DPIO and PLL synchronization.
+         */
+        I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
+}
+
 static void vlv_enable_pll(struct intel_crtc *crtc)
 {
         struct drm_device *dev = crtc->base.dev;
@@ -1429,6 +1486,20 @@ static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
         POSTING_READ(DPLL(pipe));
 }
 
+static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+        u32 val = 0;
+
+        /* Make sure the pipe isn't still relying on us */
+        assert_pipe_disabled(dev_priv, pipe);
+
+        /* Leave integrated clock source enabled */
+        if (pipe == PIPE_B)
+                val = DPLL_INTEGRATED_CRI_CLK_VLV;
+        I915_WRITE(DPLL(pipe), val);
+        POSTING_READ(DPLL(pipe));
+}
+
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
 {
         u32 port_mask;
@@ -1661,7 +1732,7 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  * returning.
  */
 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
-                              bool pch_port)
+                              bool pch_port, bool dsi)
 {
         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                       pipe);
@@ -1670,6 +1741,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
         u32 val;
 
         assert_planes_disabled(dev_priv, pipe);
+        assert_cursor_disabled(dev_priv, pipe);
         assert_sprites_disabled(dev_priv, pipe);
 
         if (HAS_PCH_LPT(dev_priv->dev))
@@ -1683,7 +1755,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
          * need the check.
          */
         if (!HAS_PCH_SPLIT(dev_priv->dev))
-                assert_pll_enabled(dev_priv, pipe);
+                if (dsi)
+                        assert_dsi_pll_enabled(dev_priv);
+                else
+                        assert_pll_enabled(dev_priv, pipe);
         else {
                 if (pch_port) {
                         /* if driving the PCH, we need FDI enabled */
@@ -1728,6 +1803,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
          * or we might hang the display.
          */
         assert_planes_disabled(dev_priv, pipe);
+        assert_cursor_disabled(dev_priv, pipe);
         assert_sprites_disabled(dev_priv, pipe);
 
         /* Don't disable pipe A or pipe A PLLs if needed */
@@ -2244,11 +2320,26 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                 return ret;
         }
 
-        /* Update pipe size and adjust fitter if needed */
+        /*
+         * Update pipe size and adjust fitter if needed: the reason for this is
+         * that in compute_mode_changes we check the native mode (not the pfit
+         * mode) to see if we can flip rather than do a full mode set. In the
+         * fastboot case, we'll flip, but if we don't update the pipesrc and
+         * pfit state, we'll end up with a big fb scanned out into the wrong
+         * sized surface.
+         *
+         * To fix this properly, we need to hoist the checks up into
+         * compute_mode_changes (or above), check the actual pfit state and
+         * whether the platform allows pfit disable with pipe active, and only
+         * then update the pipesrc and pfit state, even on the flip path.
+         */
         if (i915_fastboot) {
+                const struct drm_display_mode *adjusted_mode =
+                        &intel_crtc->config.adjusted_mode;
+
                 I915_WRITE(PIPESRC(intel_crtc->pipe),
-                           ((crtc->mode.hdisplay - 1) << 16) |
-                           (crtc->mode.vdisplay - 1));
+                           ((adjusted_mode->crtc_hdisplay - 1) << 16) |
+                           (adjusted_mode->crtc_vdisplay - 1));
                 if (!intel_crtc->config.pch_pfit.enabled &&
                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
@@ -2872,6 +2963,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
         u32 divsel, phaseinc, auxdiv, phasedir = 0;
         u32 temp;
 
@@ -2889,14 +2981,14 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
                         SBI_ICLK);
 
         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
-        if (crtc->mode.clock == 20000) {
+        if (clock == 20000) {
                 auxdiv = 1;
                 divsel = 0x41;
                 phaseinc = 0x20;
         } else {
                 /* The iCLK virtual clock root frequency is in MHz,
-                 * but the crtc->mode.clock in in KHz. To get the divisors,
-                 * it is necessary to divide one by another, so we
+                 * but the adjusted_mode->crtc_clock in in KHz. To get the
+                 * divisors, it is necessary to divide one by another, so we
                  * convert the virtual clock precision to KHz here for higher
                  * precision.
                  */
@@ -2904,7 +2996,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
                 u32 iclk_pi_range = 64;
                 u32 desired_divisor, msb_divisor_value, pi_value;
 
-                desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
+                desired_divisor = (iclk_virtual_root_freq / clock);
                 msb_divisor_value = desired_divisor / iclk_pi_range;
                 pi_value = desired_divisor % iclk_pi_range;
 
@@ -2920,7 +3012,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
 
         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-                        crtc->mode.clock,
+                        clock,
                         auxdiv,
                         divsel,
                         phasedir,
@@ -3240,6 +3332,84 @@ static void intel_disable_planes(struct drm_crtc *crtc)
                         intel_plane_disable(&intel_plane->base);
 }
 
+static void hsw_enable_ips(struct intel_crtc *crtc)
+{
+        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+
+        if (!crtc->config.ips_enabled)
+                return;
+
+        /* We can only enable IPS after we enable a plane and wait for a vblank.
+         * We guarantee that the plane is enabled by calling intel_enable_ips
+         * only after intel_enable_plane. And intel_enable_plane already waits
+         * for a vblank, so all we need to do here is to enable the IPS bit. */
+        assert_plane_enabled(dev_priv, crtc->plane);
+        I915_WRITE(IPS_CTL, IPS_ENABLE);
+}
+
+static void hsw_disable_ips(struct intel_crtc *crtc)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (!crtc->config.ips_enabled)
+                return;
+
+        assert_plane_enabled(dev_priv, crtc->plane);
+        I915_WRITE(IPS_CTL, 0);
+        POSTING_READ(IPS_CTL);
+
+        /* We need to wait for a vblank before we can disable the plane. */
+        intel_wait_for_vblank(dev, crtc->pipe);
+}
+
+/** Loads the palette/gamma unit for the CRTC with the prepared values */
+static void intel_crtc_load_lut(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        int palreg = PALETTE(pipe);
+        int i;
+        bool reenable_ips = false;
+
+        /* The clocks have to be on to load the palette. */
+        if (!crtc->enabled || !intel_crtc->active)
+                return;
+
+        if (!HAS_PCH_SPLIT(dev_priv->dev)) {
+                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+                        assert_dsi_pll_enabled(dev_priv);
+                else
+                        assert_pll_enabled(dev_priv, pipe);
+        }
+
+        /* use legacy palette for Ironlake */
+        if (HAS_PCH_SPLIT(dev))
+                palreg = LGC_PALETTE(pipe);
+
+        /* Workaround : Do not read or write the pipe palette/gamma data while
+         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+         */
+        if (intel_crtc->config.ips_enabled &&
+            ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
+             GAMMA_MODE_MODE_SPLIT)) {
+                hsw_disable_ips(intel_crtc);
+                reenable_ips = true;
+        }
+
+        for (i = 0; i < 256; i++) {
+                I915_WRITE(palreg + 4 * i,
+                           (intel_crtc->lut_r[i] << 16) |
+                           (intel_crtc->lut_g[i] << 8) |
+                           intel_crtc->lut_b[i]);
+        }
+
+        if (reenable_ips)
+                hsw_enable_ips(intel_crtc);
+}
+
 static void ironlake_crtc_enable(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
@@ -3259,8 +3429,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
 
-        intel_update_watermarks(dev);
-
         for_each_encoder_on_crtc(dev, crtc, encoder)
                 if (encoder->pre_enable)
                         encoder->pre_enable(encoder);
@@ -3283,8 +3451,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
          */
         intel_crtc_load_lut(crtc);
 
+        intel_update_watermarks(crtc);
         intel_enable_pipe(dev_priv, pipe,
-                          intel_crtc->config.has_pch_encoder);
+                          intel_crtc->config.has_pch_encoder, false);
         intel_enable_plane(dev_priv, plane, pipe);
         intel_enable_planes(crtc);
         intel_crtc_update_cursor(crtc, true);
@@ -3319,34 +3488,74 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
 }
 
-static void hsw_enable_ips(struct intel_crtc *crtc)
+static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
 {
-        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int pipe = intel_crtc->pipe;
+        int plane = intel_crtc->plane;
 
-        if (!crtc->config.ips_enabled)
-                return;
+        intel_enable_plane(dev_priv, plane, pipe);
+        intel_enable_planes(crtc);
+        intel_crtc_update_cursor(crtc, true);
 
-        /* We can only enable IPS after we enable a plane and wait for a vblank.
-         * We guarantee that the plane is enabled by calling intel_enable_ips
-         * only after intel_enable_plane. And intel_enable_plane already waits
-         * for a vblank, so all we need to do here is to enable the IPS bit. */
-        assert_plane_enabled(dev_priv, crtc->plane);
-        I915_WRITE(IPS_CTL, IPS_ENABLE);
+        hsw_enable_ips(intel_crtc);
+
+        mutex_lock(&dev->struct_mutex);
+        intel_update_fbc(dev);
+        mutex_unlock(&dev->struct_mutex);
 }
 
-static void hsw_disable_ips(struct intel_crtc *crtc)
+static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
 {
-        struct drm_device *dev = crtc->base.dev;
+        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int pipe = intel_crtc->pipe;
+        int plane = intel_crtc->plane;
 
-        if (!crtc->config.ips_enabled)
-                return;
+        intel_crtc_wait_for_pending_flips(crtc);
+        drm_vblank_off(dev, pipe);
 
-        assert_plane_enabled(dev_priv, crtc->plane);
-        I915_WRITE(IPS_CTL, 0);
+        /* FBC must be disabled before disabling the plane on HSW. */
+        if (dev_priv->fbc.plane == plane)
+                intel_disable_fbc(dev);
 
-        /* We need to wait for a vblank before we can disable the plane. */
-        intel_wait_for_vblank(dev, crtc->pipe);
+        hsw_disable_ips(intel_crtc);
+
+        intel_crtc_update_cursor(crtc, false);
+        intel_disable_planes(crtc);
+        intel_disable_plane(dev_priv, plane, pipe);
+}
+
+/*
+ * This implements the workaround described in the "notes" section of the mode
+ * set sequence documentation. When going from no pipes or single pipe to
+ * multiple pipes, and planes are enabled after the pipe, we need to wait at
+ * least 2 vblanks on the first pipe before enabling planes on the second pipe.
+ */
+static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct intel_crtc *crtc_it, *other_active_crtc = NULL;
+
+        /* We want to get the other_active_crtc only if there's only 1 other
+         * active crtc. */
+        list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
+                if (!crtc_it->active || crtc_it == crtc)
+                        continue;
+
+                if (other_active_crtc)
+                        return;
+
+                other_active_crtc = crtc_it;
+        }
+        if (!other_active_crtc)
+                return;
+
+        intel_wait_for_vblank(dev, other_active_crtc->pipe);
+        intel_wait_for_vblank(dev, other_active_crtc->pipe);
 }
 
 static void haswell_crtc_enable(struct drm_crtc *crtc)
@@ -3356,7 +3565,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_encoder *encoder;
         int pipe = intel_crtc->pipe;
-        int plane = intel_crtc->plane;
 
         WARN_ON(!crtc->enabled);
 
@@ -3369,8 +3577,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
         if (intel_crtc->config.has_pch_encoder)
                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
 
-        intel_update_watermarks(dev);
-
         if (intel_crtc->config.has_pch_encoder)
                 dev_priv->display.fdi_link_train(crtc);
 
@@ -3391,23 +3597,22 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
         intel_ddi_set_pipe_settings(crtc);
         intel_ddi_enable_transcoder_func(crtc);
 
+        intel_update_watermarks(crtc);
         intel_enable_pipe(dev_priv, pipe,
-                          intel_crtc->config.has_pch_encoder);
-        intel_enable_plane(dev_priv, plane, pipe);
-        intel_enable_planes(crtc);
-        intel_crtc_update_cursor(crtc, true);
-
-        hsw_enable_ips(intel_crtc);
+                          intel_crtc->config.has_pch_encoder, false);
 
         if (intel_crtc->config.has_pch_encoder)
                 lpt_pch_enable(crtc);
 
-        mutex_lock(&dev->struct_mutex);
-        intel_update_fbc(dev);
-        mutex_unlock(&dev->struct_mutex);
-
-        for_each_encoder_on_crtc(dev, crtc, encoder)
+        for_each_encoder_on_crtc(dev, crtc, encoder) {
                 encoder->enable(encoder);
+                intel_opregion_notify_encoder(encoder, true);
+        }
+
+        /* If we change the relative order between pipe/planes enabling, we need
+         * to change the workaround. */
+        haswell_mode_set_planes_workaround(intel_crtc);
+        haswell_crtc_enable_planes(crtc);
 
         /*
          * There seems to be a race in PCH platform hw (at least on some
@@ -3501,7 +3706,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
         }
 
         intel_crtc->active = false;
-        intel_update_watermarks(dev);
+        intel_update_watermarks(crtc);
 
         mutex_lock(&dev->struct_mutex);
         intel_update_fbc(dev);
@@ -3515,27 +3720,17 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_encoder *encoder;
         int pipe = intel_crtc->pipe;
-        int plane = intel_crtc->plane;
         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 
         if (!intel_crtc->active)
                 return;
 
-        for_each_encoder_on_crtc(dev, crtc, encoder)
-                encoder->disable(encoder);
-
-        intel_crtc_wait_for_pending_flips(crtc);
-        drm_vblank_off(dev, pipe);
-
-        /* FBC must be disabled before disabling the plane on HSW. */
-        if (dev_priv->fbc.plane == plane)
-                intel_disable_fbc(dev);
-
-        hsw_disable_ips(intel_crtc);
+        haswell_crtc_disable_planes(crtc);
 
-        intel_crtc_update_cursor(crtc, false);
-        intel_disable_planes(crtc);
-        intel_disable_plane(dev_priv, plane, pipe);
+        for_each_encoder_on_crtc(dev, crtc, encoder) {
+                intel_opregion_notify_encoder(encoder, false);
+                encoder->disable(encoder);
+        }
 
         if (intel_crtc->config.has_pch_encoder)
                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
@@ -3558,7 +3753,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
         }
 
         intel_crtc->active = false;
-        intel_update_watermarks(dev);
+        intel_update_watermarks(crtc);
 
         mutex_lock(&dev->struct_mutex);
         intel_update_fbc(dev);
@@ -3650,6 +3845,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
         struct intel_encoder *encoder;
         int pipe = intel_crtc->pipe;
         int plane = intel_crtc->plane;
+        bool is_dsi;
 
         WARN_ON(!crtc->enabled);
 
@@ -3657,13 +3853,15 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
                 return;
 
         intel_crtc->active = true;
-        intel_update_watermarks(dev);
 
         for_each_encoder_on_crtc(dev, crtc, encoder)
                 if (encoder->pre_pll_enable)
                         encoder->pre_pll_enable(encoder);
 
-        vlv_enable_pll(intel_crtc);
+        is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+        if (!is_dsi)
+                vlv_enable_pll(intel_crtc);
 
         for_each_encoder_on_crtc(dev, crtc, encoder)
                 if (encoder->pre_enable)
@@ -3673,7 +3871,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
         intel_crtc_load_lut(crtc);
 
-        intel_enable_pipe(dev_priv, pipe, false);
+        intel_update_watermarks(crtc);
+        intel_enable_pipe(dev_priv, pipe, false, is_dsi);
         intel_enable_plane(dev_priv, plane, pipe);
         intel_enable_planes(crtc);
         intel_crtc_update_cursor(crtc, true);
@@ -3699,7 +3898,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
                 return;
 
         intel_crtc->active = true;
-        intel_update_watermarks(dev);
 
         for_each_encoder_on_crtc(dev, crtc, encoder)
                 if (encoder->pre_enable)
@@ -3711,7 +3909,8 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
 
         intel_crtc_load_lut(crtc);
 
-        intel_enable_pipe(dev_priv, pipe, false);
+        intel_update_watermarks(crtc);
+        intel_enable_pipe(dev_priv, pipe, false, false);
         intel_enable_plane(dev_priv, plane, pipe);
         intel_enable_planes(crtc);
         /* The fixup needs to happen before cursor is enabled */
@@ -3778,11 +3977,15 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
                 if (encoder->post_disable)
                         encoder->post_disable(encoder);
 
-        i9xx_disable_pll(dev_priv, pipe);
+        if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
+                vlv_disable_pll(dev_priv, pipe);
+        else if (!IS_VALLEYVIEW(dev))
+                i9xx_disable_pll(dev_priv, pipe);
 
         intel_crtc->active = false;
+        intel_update_watermarks(crtc);
+
         intel_update_fbc(dev);
-        intel_update_watermarks(dev);
 }
 
 static void i9xx_crtc_off(struct drm_crtc *crtc)
@@ -3856,6 +4059,7 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
         dev_priv->display.off(crtc);
 
         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
+        assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
 
         if (crtc->fb) {
@@ -4049,8 +4253,7 @@ retry:
          */
         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
 
-        fdi_dotclock = adjusted_mode->clock;
-        fdi_dotclock /= pipe_config->pixel_multiplier;
+        fdi_dotclock = adjusted_mode->crtc_clock;
 
         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
                                            pipe_config->pipe_bpp);
@@ -4092,13 +4295,39 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
         struct drm_device *dev = crtc->base.dev;
         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 
-        if (HAS_PCH_SPLIT(dev)) {
-                /* FDI link clock is fixed at 2.7G */
-                if (pipe_config->requested_mode.clock * 3
-                    > IRONLAKE_FDI_FREQ * 4)
+        /* FIXME should check pixel clock limits on all platforms */
+        if (INTEL_INFO(dev)->gen < 4) {
+                struct drm_i915_private *dev_priv = dev->dev_private;
+                int clock_limit =
+                        dev_priv->display.get_display_clock_speed(dev);
+
+                /*
+                 * Enable pixel doubling when the dot clock
+                 * is > 90% of the (display) core speed.
+                 *
+                 * GDG double wide on either pipe,
+                 * otherwise pipe A only.
+                 */
+                if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
+                    adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
+                        clock_limit *= 2;
+                        pipe_config->double_wide = true;
+                }
+
+                if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
                         return -EINVAL;
         }
 
+        /*
+         * Pipe horizontal size must be even in:
+         * - DVO ganged mode
+         * - LVDS dual channel mode
+         * - Double wide pipe
+         */
+        if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
+             intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
+                pipe_config->pipe_src_w &= ~1;
+
         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
          */
@@ -4262,28 +4491,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
 }
 
-static int vlv_get_refclk(struct drm_crtc *crtc)
-{
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        int refclk = 27000; /* for DP & HDMI */
-
-        return 100000; /* only one validated so far */
-
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
-                refclk = 96000;
-        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
-                if (intel_panel_use_ssc(dev_priv))
-                        refclk = 100000;
-                else
-                        refclk = 96000;
-        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
-                refclk = 100000;
-        }
-
-        return refclk;
-}
-
 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
 {
         struct drm_device *dev = crtc->dev;
@@ -4291,7 +4498,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
         int refclk;
 
         if (IS_VALLEYVIEW(dev)) {
-                refclk = vlv_get_refclk(crtc);
+                refclk = 100000;
         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
@@ -4349,7 +4556,8 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
         }
 }
 
-static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
+                pipe)
 {
         u32 reg_val;
 
@@ -4357,24 +4565,24 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
          * PLLB opamp always calibrates to max value of 0x3f, force enable it
          * and set it to a reasonable value instead.
          */
-        reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
         reg_val &= 0xffffff00;
         reg_val |= 0x00000030;
-        vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
 
-        reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
         reg_val &= 0x8cffffff;
         reg_val = 0x8c000000;
-        vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
 
-        reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
         reg_val &= 0xffffff00;
-        vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
 
-        reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
         reg_val &= 0x00ffffff;
         reg_val |= 0xb0000000;
-        vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
 }
 
 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
@@ -4440,18 +4648,18 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 
         /* PLL B needs special handling */
         if (pipe)
-                vlv_pllb_recal_opamp(dev_priv);
+                vlv_pllb_recal_opamp(dev_priv, pipe);
 
         /* Set up Tx target for periodic Rcomp update */
-        vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
 
         /* Disable target IRef on PLL */
-        reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
+        reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
         reg_val &= 0x00ffffff;
-        vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
 
         /* Disable fast lock */
-        vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
+        vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
 
         /* Set idtafcrecal before PLL is enabled */
         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
@@ -4465,55 +4673,55 @@ static void vlv_update_pll(struct intel_crtc *crtc)
          * Note: don't use the DAC post divider as it seems unstable.
          */
         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
-        vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
 
         mdiv |= DPIO_ENABLE_CALIBRATION;
-        vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
 
         /* Set HBR and RBR LPF coefficients */
         if (crtc->config.port_clock == 162000 ||
             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
-                vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
+                vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
                                  0x009f0003);
         else
-                vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
+                vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
                                  0x00d0000f);
 
         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
                 /* Use SSC source */
                 if (!pipe)
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                          0x0df40000);
                 else
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                          0x0df70000);
         } else { /* HDMI or VGA */
                 /* Use bend source */
                 if (!pipe)
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                          0x0df70000);
                 else
-                        vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
+                        vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
                                          0x0df40000);
         }
 
-        coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
+        coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
                 coreclk |= 0x01000000;
-        vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
+        vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
 
-        vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
 
         /* Enable DPIO clock input */
         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
-        if (pipe)
+        /* We should never disable this, set it here for state tracking */
+        if (pipe == PIPE_B)
                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
         dpll |= DPLL_VCO_ENABLE;
         crtc->config.dpll_hw_state.dpll = dpll;
 
@@ -4651,7 +4859,6 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
         struct drm_display_mode *adjusted_mode =
                 &intel_crtc->config.adjusted_mode;
-        struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
 
         /* We need to be careful not to changed the adjusted mode, for otherwise
@@ -4704,7 +4911,8 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
          * always be the user's requested size.
          */
         I915_WRITE(PIPESRC(pipe),
-                   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
+                   ((intel_crtc->config.pipe_src_w - 1) << 16) |
+                   (intel_crtc->config.pipe_src_h - 1));
 }
 
 static void intel_get_pipe_timings(struct intel_crtc *crtc,
@@ -4742,8 +4950,11 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
         }
 
         tmp = I915_READ(PIPESRC(crtc->pipe));
-        pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
-        pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
+        pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
+        pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
+
+        pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
+        pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
 }
 
 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
@@ -4763,7 +4974,7 @@ static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
 
         crtc->mode.flags = pipe_config->adjusted_mode.flags;
 
-        crtc->mode.clock = pipe_config->adjusted_mode.clock;
+        crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
 }
 
@@ -4779,17 +4990,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
                 pipeconf |= PIPECONF_ENABLE;
 
-        if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
-                /* Enable pixel doubling when the dot clock is > 90% of the (display)
-                 * core speed.
-                 *
-                 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
-                 * pipe == 0 check?
-                 */
-                if (intel_crtc->config.requested_mode.clock >
-                    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
-                        pipeconf |= PIPECONF_DOUBLE_WIDE;
-        }
+        if (intel_crtc->config.double_wide)
+                pipeconf |= PIPECONF_DOUBLE_WIDE;
 
         /* only g4x and later have fancy bpc/dither controls */
         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
@@ -4843,14 +5045,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
         int pipe = intel_crtc->pipe;
         int plane = intel_crtc->plane;
         int refclk, num_connectors = 0;
         intel_clock_t clock, reduced_clock;
         u32 dspcntr;
         bool ok, has_reduced_clock = false;
-        bool is_lvds = false;
+        bool is_lvds = false, is_dsi = false;
         struct intel_encoder *encoder;
         const intel_limit_t *limit;
         int ret;
@@ -4860,42 +5061,49 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                 case INTEL_OUTPUT_LVDS:
                         is_lvds = true;
                         break;
+                case INTEL_OUTPUT_DSI:
+                        is_dsi = true;
+                        break;
                 }
 
                 num_connectors++;
         }
 
-        refclk = i9xx_get_refclk(crtc, num_connectors);
+        if (is_dsi)
+                goto skip_dpll;
 
-        /*
-         * Returns a set of divisors for the desired target clock with the given
-         * refclk, or FALSE.  The returned values represent the clock equation:
-         * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
-         */
-        limit = intel_limit(crtc, refclk);
-        ok = dev_priv->display.find_dpll(limit, crtc,
-                                         intel_crtc->config.port_clock,
-                                         refclk, NULL, &clock);
-        if (!ok && !intel_crtc->config.clock_set) {
-                DRM_ERROR("Couldn't find PLL settings for mode!\n");
-                return -EINVAL;
-        }
+        if (!intel_crtc->config.clock_set) {
+                refclk = i9xx_get_refclk(crtc, num_connectors);
 
-        if (is_lvds && dev_priv->lvds_downclock_avail) {
                 /*
-                 * Ensure we match the reduced clock's P to the target clock.
-                 * If the clocks don't match, we can't switch the display clock
-                 * by using the FP0/FP1. In such case we will disable the LVDS
-                 * downclock feature.
-                */
-                has_reduced_clock =
-                        dev_priv->display.find_dpll(limit, crtc,
-                                                    dev_priv->lvds_downclock,
-                                                    refclk, &clock,
-                                                    &reduced_clock);
-        }
-        /* Compat-code for transition, will disappear. */
-        if (!intel_crtc->config.clock_set) {
+                 * Returns a set of divisors for the desired target clock with
+                 * the given refclk, or FALSE.  The returned values represent
+                 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
+                 * 2) / p1 / p2.
+                 */
+                limit = intel_limit(crtc, refclk);
+                ok = dev_priv->display.find_dpll(limit, crtc,
+                                                 intel_crtc->config.port_clock,
+                                                 refclk, NULL, &clock);
+                if (!ok) {
+                        DRM_ERROR("Couldn't find PLL settings for mode!\n");
+                        return -EINVAL;
+                }
+
+                if (is_lvds && dev_priv->lvds_downclock_avail) {
+                        /*
+                         * Ensure we match the reduced clock's P to the target
+                         * clock.  If the clocks don't match, we can't switch
+                         * the display clock by using the FP0/FP1. In such case
+                         * we will disable the LVDS downclock feature.
+                         */
+                        has_reduced_clock =
+                                dev_priv->display.find_dpll(limit, crtc,
+                                                            dev_priv->lvds_downclock,
+                                                            refclk, &clock,
+                                                            &reduced_clock);
+                }
+                /* Compat-code for transition, will disappear. */
                 intel_crtc->config.dpll.n = clock.n;
                 intel_crtc->config.dpll.m1 = clock.m1;
                 intel_crtc->config.dpll.m2 = clock.m2;
@@ -4903,17 +5111,19 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                 intel_crtc->config.dpll.p2 = clock.p2;
         }
 
-        if (IS_GEN2(dev))
+        if (IS_GEN2(dev)) {
                 i8xx_update_pll(intel_crtc,
                                 has_reduced_clock ? &reduced_clock : NULL,
                                 num_connectors);
-        else if (IS_VALLEYVIEW(dev))
+        } else if (IS_VALLEYVIEW(dev)) {
                 vlv_update_pll(intel_crtc);
-        else
+        } else {
                 i9xx_update_pll(intel_crtc,
                                 has_reduced_clock ? &reduced_clock : NULL,
                                 num_connectors);
+        }
 
+skip_dpll:
         /* Set up the display plane register */
         dspcntr = DISPPLANE_GAMMA_ENABLE;
 
@@ -4930,8 +5140,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
          * which should always be the user's requested size.
          */
         I915_WRITE(DSPSIZE(plane),
-                   ((mode->vdisplay - 1) << 16) |
-                   (mode->hdisplay - 1));
+                   ((intel_crtc->config.pipe_src_h - 1) << 16) |
+                   (intel_crtc->config.pipe_src_w - 1));
         I915_WRITE(DSPPOS(plane), 0);
 
         i9xx_set_pipeconf(intel_crtc);
@@ -4941,8 +5151,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
         ret = intel_pipe_set_base(crtc, x, y, fb);
 
-        intel_update_watermarks(dev);
-
         return ret;
 }
 
@@ -4973,6 +5181,32 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
 }
 
+static void vlv_crtc_clock_get(struct intel_crtc *crtc,
+                               struct intel_crtc_config *pipe_config)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int pipe = pipe_config->cpu_transcoder;
+        intel_clock_t clock;
+        u32 mdiv;
+        int refclk = 100000;
+
+        mutex_lock(&dev_priv->dpio_lock);
+        mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
+        mutex_unlock(&dev_priv->dpio_lock);
+
+        clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
+        clock.m2 = mdiv & DPIO_M2DIV_MASK;
+        clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
+        clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
+        clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+
+        clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
+        clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
+
+        pipe_config->port_clock = clock.dot / 10;
+}
+
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                                  struct intel_crtc_config *pipe_config)
 {
@@ -4987,6 +5221,25 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
         if (!(tmp & PIPECONF_ENABLE))
                 return false;
 
+        if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+                switch (tmp & PIPECONF_BPC_MASK) {
+                case PIPECONF_6BPC:
+                        pipe_config->pipe_bpp = 18;
+                        break;
+                case PIPECONF_8BPC:
+                        pipe_config->pipe_bpp = 24;
+                        break;
+                case PIPECONF_10BPC:
+                        pipe_config->pipe_bpp = 30;
+                        break;
+                default:
+                        break;
+                }
+        }
+
+        if (INTEL_INFO(dev)->gen < 4)
+                pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
+
         intel_get_pipe_timings(crtc, pipe_config);
 
         i9xx_get_pfit_config(crtc, pipe_config);
@@ -5019,6 +5272,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                                                      DPLL_PORTB_READY_MASK);
         }
 
+        if (IS_VALLEYVIEW(dev))
+                vlv_crtc_clock_get(crtc, pipe_config);
+        else
+                i9xx_crtc_clock_get(crtc, pipe_config);
+
         return true;
 }
 
@@ -5826,25 +6084,67 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
         ret = intel_pipe_set_base(crtc, x, y, fb);
 
-        intel_update_watermarks(dev);
-
         return ret;
 }
 
-static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
-                                        struct intel_crtc_config *pipe_config)
+static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
+                                         struct intel_link_m_n *m_n)
 {
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        enum transcoder transcoder = pipe_config->cpu_transcoder;
+        enum pipe pipe = crtc->pipe;
+
+        m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
+        m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
+        m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
+                & ~TU_SIZE_MASK;
+        m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
+        m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
+                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+}
+
+static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
+                                         enum transcoder transcoder,
+                                         struct intel_link_m_n *m_n)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        enum pipe pipe = crtc->pipe;
+
+        if (INTEL_INFO(dev)->gen >= 5) {
+                m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
+                m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
+                m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
+                        & ~TU_SIZE_MASK;
+                m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
+                m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
+                            & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+        } else {
+                m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
+                m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
+                m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
+                        & ~TU_SIZE_MASK;
+                m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
+                m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
+                            & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+        }
+}
 
-        pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
-        pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
-        pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
-                                        & ~TU_SIZE_MASK;
-        pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
-        pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
-                                   & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+void intel_dp_get_m_n(struct intel_crtc *crtc,
+                      struct intel_crtc_config *pipe_config)
+{
+        if (crtc->config.has_pch_encoder)
+                intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
+        else
+                intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+                                             &pipe_config->dp_m_n);
+}
+
+static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
+                                        struct intel_crtc_config *pipe_config)
+{
+        intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
+                                     &pipe_config->fdi_m_n);
 }
 
 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
@@ -5885,6 +6185,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
         if (!(tmp & PIPECONF_ENABLE))
                 return false;
 
+        switch (tmp & PIPECONF_BPC_MASK) {
+        case PIPECONF_6BPC:
+                pipe_config->pipe_bpp = 18;
+                break;
+        case PIPECONF_8BPC:
+                pipe_config->pipe_bpp = 24;
+                break;
+        case PIPECONF_10BPC:
+                pipe_config->pipe_bpp = 30;
+                break;
+        case PIPECONF_12BPC:
+                pipe_config->pipe_bpp = 36;
+                break;
+        default:
+                break;
+        }
+
         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
                 struct intel_shared_dpll *pll;
 
@@ -5916,6 +6233,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
                 pipe_config->pixel_multiplier =
                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+
+                ironlake_pch_clock_get(crtc, pipe_config);
         } else {
                 pipe_config->pixel_multiplier = 1;
         }
@@ -5972,8 +6291,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  * register. Callers should take care of disabling all the display engine
  * functions, doing the mode unset, fixing interrupts, etc.
  */
-void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
-                       bool switch_to_fclk, bool allow_power_down)
+static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
+                              bool switch_to_fclk, bool allow_power_down)
 {
         uint32_t val;
 
@@ -6001,7 +6320,10 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
 
         val = I915_READ(D_COMP);
         val |= D_COMP_COMP_DISABLE;
-        I915_WRITE(D_COMP, val);
+        mutex_lock(&dev_priv->rps.hw_lock);
+        if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+                DRM_ERROR("Failed to disable D_COMP\n");
+        mutex_unlock(&dev_priv->rps.hw_lock);
         POSTING_READ(D_COMP);
         ndelay(100);
 
@@ -6020,7 +6342,7 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  * source.
  */
-void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
+static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
 {
         uint32_t val;
 
@@ -6043,7 +6365,10 @@ void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
         val = I915_READ(D_COMP);
         val |= D_COMP_COMP_FORCE;
         val &= ~D_COMP_COMP_DISABLE;
-        I915_WRITE(D_COMP, val);
+        mutex_lock(&dev_priv->rps.hw_lock);
+        if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+                DRM_ERROR("Failed to enable D_COMP\n");
+        mutex_unlock(&dev_priv->rps.hw_lock);
         POSTING_READ(D_COMP);
 
         val = I915_READ(LCPLL_CTL);
@@ -6280,8 +6605,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 
         ret = intel_pipe_set_base(crtc, x, y, fb);
 
-        intel_update_watermarks(dev);
-
         return ret;
 }
 
@@ -6644,49 +6967,6 @@ void intel_write_eld(struct drm_encoder *encoder,
                 dev_priv->display.write_eld(connector, crtc);
 }
 
-/** Loads the palette/gamma unit for the CRTC with the prepared values */
-void intel_crtc_load_lut(struct drm_crtc *crtc)
-{
-        struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        enum pipe pipe = intel_crtc->pipe;
-        int palreg = PALETTE(pipe);
-        int i;
-        bool reenable_ips = false;
-
-        /* The clocks have to be on to load the palette. */
-        if (!crtc->enabled || !intel_crtc->active)
-                return;
-
-        if (!HAS_PCH_SPLIT(dev_priv->dev))
-                assert_pll_enabled(dev_priv, pipe);
-
-        /* use legacy palette for Ironlake */
-        if (HAS_PCH_SPLIT(dev))
-                palreg = LGC_PALETTE(pipe);
-
-        /* Workaround : Do not read or write the pipe palette/gamma data while
-         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
-         */
-        if (intel_crtc->config.ips_enabled &&
-            ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
-             GAMMA_MODE_MODE_SPLIT)) {
-                hsw_disable_ips(intel_crtc);
-                reenable_ips = true;
-        }
-
-        for (i = 0; i < 256; i++) {
-                I915_WRITE(palreg + 4 * i,
-                           (intel_crtc->lut_r[i] << 16) |
-                           (intel_crtc->lut_g[i] << 8) |
-                           intel_crtc->lut_b[i]);
-        }
-
-        if (reenable_ips)
-                hsw_enable_ips(intel_crtc);
-}
-
 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 {
         struct drm_device *dev = crtc->dev;
@@ -6782,23 +7062,20 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
         int pipe = intel_crtc->pipe;
         int x = intel_crtc->cursor_x;
         int y = intel_crtc->cursor_y;
-        u32 base, pos;
+        u32 base = 0, pos = 0;
         bool visible;
 
-        pos = 0;
-
-        if (on && crtc->enabled && crtc->fb) {
+        if (on)
                 base = intel_crtc->cursor_addr;
-                if (x > (int) crtc->fb->width)
-                        base = 0;
 
-                if (y > (int) crtc->fb->height)
-                        base = 0;
-        } else
+        if (x >= intel_crtc->config.pipe_src_w)
+                base = 0;
+
+        if (y >= intel_crtc->config.pipe_src_h)
                 base = 0;
 
         if (x < 0) {
-                if (x + intel_crtc->cursor_width < 0)
+                if (x + intel_crtc->cursor_width <= 0)
                         base = 0;
 
                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
@@ -6807,7 +7084,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
         pos |= x << CURSOR_X_SHIFT;
 
         if (y < 0) {
-                if (y + intel_crtc->cursor_height < 0)
+                if (y + intel_crtc->cursor_height <= 0)
                         base = 0;
 
                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
@@ -6959,27 +7236,6 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
         return 0;
 }
 
-/** Sets the color ramps on behalf of RandR */
-void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
-                                 u16 blue, int regno)
-{
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-        intel_crtc->lut_r[regno] = red >> 8;
-        intel_crtc->lut_g[regno] = green >> 8;
-        intel_crtc->lut_b[regno] = blue >> 8;
-}
-
-void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
-                             u16 *blue, int regno)
-{
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-        *red = intel_crtc->lut_r[regno] << 8;
-        *green = intel_crtc->lut_g[regno] << 8;
-        *blue = intel_crtc->lut_b[regno] << 8;
-}
-
 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                                  u16 *blue, uint32_t start, uint32_t size)
 {
@@ -7228,6 +7484,22 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
         mutex_unlock(&crtc->mutex);
 }
 
+static int i9xx_pll_refclk(struct drm_device *dev,
+                           const struct intel_crtc_config *pipe_config)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 dpll = pipe_config->dpll_hw_state.dpll;
+
+        if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
+                return dev_priv->vbt.lvds_ssc_freq * 1000;
+        else if (HAS_PCH_SPLIT(dev))
+                return 120000;
+        else if (!IS_GEN2(dev))
+                return 96000;
+        else
+                return 48000;
+}
+
 /* Returns the clock of the currently programmed mode of the given pipe. */
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                 struct intel_crtc_config *pipe_config)
@@ -7235,14 +7507,15 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int pipe = pipe_config->cpu_transcoder;
-        u32 dpll = I915_READ(DPLL(pipe));
+        u32 dpll = pipe_config->dpll_hw_state.dpll;
         u32 fp;
         intel_clock_t clock;
+        int refclk = i9xx_pll_refclk(dev, pipe_config);
 
         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
-                fp = I915_READ(FP0(pipe));
+                fp = pipe_config->dpll_hw_state.fp0;
         else
-                fp = I915_READ(FP1(pipe));
+                fp = pipe_config->dpll_hw_state.fp1;
 
         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
         if (IS_PINEVIEW(dev)) {
@@ -7273,14 +7546,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                 default:
                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
-                        pipe_config->adjusted_mode.clock = 0;
                         return;
                 }
 
                 if (IS_PINEVIEW(dev))
-                        pineview_clock(96000, &clock);
+                        pineview_clock(refclk, &clock);
                 else
-                        i9xx_clock(96000, &clock);
+                        i9xx_clock(refclk, &clock);
         } else {
                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
 
@@ -7288,13 +7560,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
                         clock.p2 = 14;
-
-                        if ((dpll & PLL_REF_INPUT_MASK) ==
-                            PLLB_REF_INPUT_SPREADSPECTRUMIN) {
-                                /* XXX: might not be 66MHz */
-                                i9xx_clock(66000, &clock);
-                        } else
-                                i9xx_clock(48000, &clock);
                 } else {
                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
                                 clock.p1 = 2;
@@ -7306,59 +7571,55 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                 clock.p2 = 4;
                         else
                                 clock.p2 = 2;
-
-                        i9xx_clock(48000, &clock);
                 }
+
+                i9xx_clock(refclk, &clock);
         }
 
-        pipe_config->adjusted_mode.clock = clock.dot;
+        /*
+         * This value includes pixel_multiplier. We will use
+         * port_clock to compute adjusted_mode.crtc_clock in the
+         * encoder's get_config() function.
+         */
+        pipe_config->port_clock = clock.dot;
 }
 
-static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
-                                    struct intel_crtc_config *pipe_config)
+int intel_dotclock_calculate(int link_freq,
+                             const struct intel_link_m_n *m_n)
 {
-        struct drm_device *dev = crtc->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-        int link_freq, repeat;
-        u64 clock;
-        u32 link_m, link_n;
-
-        repeat = pipe_config->pixel_multiplier;
-
         /*
          * The calculation for the data clock is:
-         * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
+         * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
          * But we want to avoid losing precison if possible, so:
-         * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
+         * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
          *
          * and the link clock is simpler:
-         * link_clock = (m * link_clock * repeat) / n
+         * link_clock = (m * link_clock) / n
          */
 
-        /*
-         * We need to get the FDI or DP link clock here to derive
-         * the M/N dividers.
-         *
-         * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
-         * For DP, it's either 1.62GHz or 2.7GHz.
-         * We do our calculations in 10*MHz since we don't need much precison.
-         */
-        if (pipe_config->has_pch_encoder)
-                link_freq = intel_fdi_link_freq(dev) * 10000;
-        else
-                link_freq = pipe_config->port_clock;
+        if (!m_n->link_n)
+                return 0;
 
-        link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
-        link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
+        return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
+}
 
-        if (!link_m || !link_n)
-                return;
+static void ironlake_pch_clock_get(struct intel_crtc *crtc,
+                                   struct intel_crtc_config *pipe_config)
+{
+        struct drm_device *dev = crtc->base.dev;
 
-        clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
-        do_div(clock, link_n);
+        /* read out port_clock from the DPLL */
+        i9xx_crtc_clock_get(crtc, pipe_config);
 
-        pipe_config->adjusted_mode.clock = clock;
+        /*
+         * This value does not include pixel_multiplier.
+         * We will check that port_clock and adjusted_mode.crtc_clock
+         * agree once we know their relationship in the encoder's
+         * get_config() function.
+         */
+        pipe_config->adjusted_mode.crtc_clock =
+                intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
+                                         &pipe_config->fdi_m_n);
 }
 
 /** Returns the currently programmed mode of the given pipe. */
@@ -7374,6 +7635,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
         int hsync = I915_READ(HSYNC(cpu_transcoder));
         int vtot = I915_READ(VTOTAL(cpu_transcoder));
         int vsync = I915_READ(VSYNC(cpu_transcoder));
+        enum pipe pipe = intel_crtc->pipe;
 
         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
         if (!mode)
@@ -7386,11 +7648,14 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
          * to use a real value here instead.
          */
-        pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
+        pipe_config.cpu_transcoder = (enum transcoder) pipe;
         pipe_config.pixel_multiplier = 1;
+        pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
+        pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
+        pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
 
-        mode->clock = pipe_config.adjusted_mode.clock;
+        mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
         mode->hdisplay = (htot & 0xffff) + 1;
         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
         mode->hsync_start = (hsync & 0xffff) + 1;
@@ -7496,6 +7761,9 @@ void intel_mark_idle(struct drm_device *dev)
 
                 intel_decrease_pllclock(crtc);
         }
+
+        if (dev_priv->info->gen >= 6)
+                gen6_rps_idle(dev->dev_private);
 }
 
 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
@@ -7684,7 +7952,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
         intel_ring_emit(ring, 0); /* aux display base address, unused */
 
         intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
         return 0;
 
 err_unpin:
@@ -7726,7 +7994,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
         intel_ring_emit(ring, MI_NOOP);
 
         intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
         return 0;
 
 err_unpin:
@@ -7775,7 +8043,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
         intel_ring_emit(ring, pf | pipesrc);
 
         intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
         return 0;
 
 err_unpin:
@@ -7820,7 +8088,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
         intel_ring_emit(ring, pf | pipesrc);
 
         intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
         return 0;
 
 err_unpin:
@@ -7899,7 +8167,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
         intel_ring_emit(ring, (MI_NOOP));
 
         intel_mark_page_flip_active(intel_crtc);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
         return 0;
 
 err_unpin:
@@ -7944,7 +8212,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
              fb->pitches[0] != crtc->fb->pitches[0]))
                 return -EINVAL;
 
-        work = kzalloc(sizeof *work, GFP_KERNEL);
+        work = kzalloc(sizeof(*work), GFP_KERNEL);
         if (work == NULL)
                 return -ENOMEM;
 
@@ -8179,6 +8447,17 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
         return bpp;
 }
 
+static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
+{
+        DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
+                        "type: 0x%x flags: 0x%x\n",
+                mode->crtc_clock,
+                mode->crtc_hdisplay, mode->crtc_hsync_start,
+                mode->crtc_hsync_end, mode->crtc_htotal,
+                mode->crtc_vdisplay, mode->crtc_vsync_start,
+                mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
+}
+
 static void intel_dump_pipe_config(struct intel_crtc *crtc,
                                    struct intel_crtc_config *pipe_config,
                                    const char *context)
@@ -8195,10 +8474,19 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
                       pipe_config->fdi_m_n.tu);
+        DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+                      pipe_config->has_dp_encoder,
+                      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
+                      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
+                      pipe_config->dp_m_n.tu);
         DRM_DEBUG_KMS("requested mode:\n");
         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
         DRM_DEBUG_KMS("adjusted mode:\n");
         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
+        intel_dump_crtc_timings(&pipe_config->adjusted_mode);
+        DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
+        DRM_DEBUG_KMS("pipe src size: %dx%d\n",
+                      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
                       pipe_config->gmch_pfit.control,
                       pipe_config->gmch_pfit.pgm_ratios,
@@ -8208,6 +8496,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                       pipe_config->pch_pfit.size,
                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
+        DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 }
 
 static bool check_encoder_cloning(struct drm_crtc *crtc)
@@ -8251,6 +8540,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
 
         drm_mode_copy(&pipe_config->adjusted_mode, mode);
         drm_mode_copy(&pipe_config->requested_mode, mode);
+
         pipe_config->cpu_transcoder =
                 (enum transcoder) to_intel_crtc(crtc)->pipe;
         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
@@ -8277,13 +8567,25 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
         if (plane_bpp < 0)
                 goto fail;
 
+        /*
+         * Determine the real pipe dimensions. Note that stereo modes can
+         * increase the actual pipe size due to the frame doubling and
+         * insertion of additional space for blanks between the frame. This
+         * is stored in the crtc timings. We use the requested mode to do this
+         * computation to clearly distinguish it from the adjusted mode, which
+         * can be changed by the connectors in the below retry loop.
+         */
+        drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
+        pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
+        pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
+
 encoder_retry:
         /* Ensure the port clock defaults are reset when retrying. */
         pipe_config->port_clock = 0;
         pipe_config->pixel_multiplier = 1;
 
         /* Fill in default crtc timings, allow encoders to overwrite them. */
-        drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
+        drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
 
         /* Pass our mode to the connectors and the CRTC to give them a chance to
          * adjust it according to limitations or connector properties, and also
@@ -8304,7 +8606,8 @@ encoder_retry:
         /* Set default port clock if not overwritten by the encoder. Needs to be
          * done afterwards in case the encoder adjusts the mode. */
         if (!pipe_config->port_clock)
-                pipe_config->port_clock = pipe_config->adjusted_mode.clock;
+                pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
+                        * pipe_config->pixel_multiplier;
 
         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
         if (ret < 0) {
@@ -8491,13 +8794,9 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
 
 }
 
-static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
-                                    struct intel_crtc_config *new)
+static bool intel_fuzzy_clock_check(int clock1, int clock2)
 {
-        int clock1, clock2, diff;
-
-        clock1 = cur->adjusted_mode.clock;
-        clock2 = new->adjusted_mode.clock;
+        int diff;
 
         if (clock1 == clock2)
                 return true;
@@ -8551,6 +8850,15 @@ intel_pipe_config_compare(struct drm_device *dev,
                 return false; \
         }
 
+#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
+        if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
+                DRM_ERROR("mismatch in " #name " " \
+                          "(expected %i, found %i)\n", \
+                          current_config->name, \
+                          pipe_config->name); \
+                return false; \
+        }
+
 #define PIPE_CONF_QUIRK(quirk)  \
         ((current_config->quirks | pipe_config->quirks) & (quirk))
 
@@ -8564,6 +8872,13 @@ intel_pipe_config_compare(struct drm_device *dev,
         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
         PIPE_CONF_CHECK_I(fdi_m_n.tu);
 
+        PIPE_CONF_CHECK_I(has_dp_encoder);
+        PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
+        PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
+        PIPE_CONF_CHECK_I(dp_m_n.link_m);
+        PIPE_CONF_CHECK_I(dp_m_n.link_n);
+        PIPE_CONF_CHECK_I(dp_m_n.tu);
+
         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
@@ -8594,8 +8909,8 @@ intel_pipe_config_compare(struct drm_device *dev,
                                       DRM_MODE_FLAG_NVSYNC);
         }
 
-        PIPE_CONF_CHECK_I(requested_mode.hdisplay);
-        PIPE_CONF_CHECK_I(requested_mode.vdisplay);
+        PIPE_CONF_CHECK_I(pipe_src_w);
+        PIPE_CONF_CHECK_I(pipe_src_h);
 
         PIPE_CONF_CHECK_I(gmch_pfit.control);
         /* pfit ratios are autocomputed by the hw on gen4+ */
@@ -8610,26 +8925,28 @@ intel_pipe_config_compare(struct drm_device *dev,
 
         PIPE_CONF_CHECK_I(ips_enabled);
 
+        PIPE_CONF_CHECK_I(double_wide);
+
         PIPE_CONF_CHECK_I(shared_dpll);
         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
 
+        if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
+                PIPE_CONF_CHECK_I(pipe_bpp);
+
+        if (!IS_HASWELL(dev)) {
+                PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
+                PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+        }
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_FLAGS
+#undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_QUIRK
 
-        if (!IS_HASWELL(dev)) {
-                if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
-                        DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
-                                  current_config->adjusted_mode.clock,
-                                  pipe_config->adjusted_mode.clock);
-                        return false;
-                }
-        }
-
         return true;
 }
 
@@ -8761,9 +9078,6 @@ check_crtc_state(struct drm_device *dev)
                                 encoder->get_config(encoder, &pipe_config);
                 }
 
-                if (dev_priv->display.get_clock)
-                        dev_priv->display.get_clock(crtc, &pipe_config);
-
                 WARN(crtc->active != active,
                      "crtc active state doesn't match with hw state "
                      "(expected %i, found %i)\n", crtc->active, active);
@@ -8838,6 +9152,18 @@ intel_modeset_check_state(struct drm_device *dev)
         check_shared_dpll_state(dev);
 }
 
+void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
+                                     int dotclock)
+{
+        /*
+         * FDI already provided one idea for the dotclock.
+         * Yell if the encoder disagrees.
+         */
+        WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
+             "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
+             pipe_config->adjusted_mode.crtc_clock, dotclock);
+}
+
 static int __intel_set_mode(struct drm_crtc *crtc,
                             struct drm_display_mode *mode,
                             int x, int y, struct drm_framebuffer *fb)
@@ -8850,7 +9176,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
         unsigned disable_pipes, prepare_pipes, modeset_pipes;
         int ret = 0;
 
-        saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
+        saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
         if (!saved_mode)
                 return -ENOMEM;
         saved_hwmode = saved_mode + 1;
@@ -9389,7 +9715,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
         struct intel_crtc *intel_crtc;
         int i;
 
-        intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
+        intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
         if (intel_crtc == NULL)
                 return;
 
@@ -9555,6 +9881,8 @@ static void intel_setup_outputs(struct drm_device *dev)
                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
                 }
+
+                intel_dsi_init(dev);
         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
                 bool found = false;
 
@@ -9787,7 +10115,6 @@ static void intel_init_display(struct drm_device *dev)
                 dev_priv->display.update_plane = ironlake_update_plane;
         } else if (HAS_PCH_SPLIT(dev)) {
                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
-                dev_priv->display.get_clock = ironlake_crtc_clock_get;
                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
@@ -9795,7 +10122,6 @@ static void intel_init_display(struct drm_device *dev)
                 dev_priv->display.update_plane = ironlake_update_plane;
         } else if (IS_VALLEYVIEW(dev)) {
                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-                dev_priv->display.get_clock = i9xx_crtc_clock_get;
                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -9803,7 +10129,6 @@ static void intel_init_display(struct drm_device *dev)
                 dev_priv->display.update_plane = i9xx_update_plane;
         } else {
                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-                dev_priv->display.get_clock = i9xx_crtc_clock_get;
                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -9989,20 +10314,11 @@ static struct intel_quirk intel_quirks[] = {
         /* Sony Vaio Y cannot use SSC on LVDS */
         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
 
-        /* Acer Aspire 5734Z must invert backlight brightness */
-        { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
-
-        /* Acer/eMachines G725 */
-        { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
-
-        /* Acer/eMachines e725 */
-        { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
-
-        /* Acer/Packard Bell NCL20 */
-        { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
-
-        /* Acer Aspire 4736Z */
-        { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
+        /*
+         * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
+         * seem to use inverted backlight PWM.
+         */
+        { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
 
         /* Dell XPS13 HD Sandy Bridge */
         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
@@ -10078,12 +10394,19 @@ void i915_disable_vga_mem(struct drm_device *dev)
 
 void intel_modeset_init_hw(struct drm_device *dev)
 {
-        intel_init_power_well(dev);
+        struct drm_i915_private *dev_priv = dev->dev_private;
 
         intel_prepare_ddi(dev);
 
         intel_init_clock_gating(dev);
 
+        /* Enable the CRI clock source so we can get at the display */
+        if (IS_VALLEYVIEW(dev))
+                I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
+                           DPLL_INTEGRATED_CRI_CLK_VLV);
+
+        intel_init_dpio(dev);
+
         mutex_lock(&dev->struct_mutex);
         intel_enable_gt_powersave(dev);
         mutex_unlock(&dev->struct_mutex);
@@ -10422,15 +10745,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                               pipe);
         }
 
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list,
-                            base.head) {
-                if (!crtc->active)
-                        continue;
-                if (dev_priv->display.get_clock)
-                        dev_priv->display.get_clock(crtc,
-                                                    &crtc->config);
-        }
-
         list_for_each_entry(connector, &dev->mode_config.connector_list,
                             base.head) {
                 if (connector->get_hw_state(connector)) {
@@ -10455,7 +10769,6 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         enum pipe pipe;
-        struct drm_plane *plane;
         struct intel_crtc *crtc;
         struct intel_encoder *encoder;
         int i;
@@ -10503,6 +10816,8 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
         }
 
         if (force_restore) {
+                i915_redisable_vga(dev);
+
                 /*
                  * We need to use raw interfaces for restoring state to avoid
                  * checking (bogus) intermediate states.
@@ -10514,10 +10829,6 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
                                          crtc->fb);
                 }
-                list_for_each_entry(plane, &dev->mode_config.plane_list, head)
-                        intel_plane_restore(plane);
-
-                i915_redisable_vga(dev);
         } else {
                 intel_modeset_update_staged_output_state(dev);
         }
@@ -10540,6 +10851,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_crtc *crtc;
+        struct drm_connector *connector;
 
         /*
          * Interrupts and polling as the first thing to avoid creating havoc.
@@ -10582,6 +10894,10 @@ void intel_modeset_cleanup(struct drm_device *dev)
         /* destroy backlight, if any, before the connectors */
         intel_panel_destroy_backlight(dev);
 
+        /* destroy the sysfs files before encoders/connectors */
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head)
+                drm_sysfs_connector_remove(connector);
+
         drm_mode_config_cleanup(dev);
 
         intel_cleanup_overlay(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 79c14e298ba6..d5bd349105e5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,6 +38,32 @@
 
 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
 
+struct dp_link_dpll {
+        int link_bw;
+        struct dpll dpll;
+};
+
+static const struct dp_link_dpll gen4_dpll[] = {
+        { DP_LINK_BW_1_62,
+                { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
+        { DP_LINK_BW_2_7,
+                { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
+};
+
+static const struct dp_link_dpll pch_dpll[] = {
+        { DP_LINK_BW_1_62,
+                { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
+        { DP_LINK_BW_2_7,
+                { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
+};
+
+static const struct dp_link_dpll vlv_dpll[] = {
+        { DP_LINK_BW_1_62,
+                { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
+        { DP_LINK_BW_2_7,
+                { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
+};
+
 /**
  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  * @intel_dp: DP struct
@@ -211,24 +237,77 @@ intel_hrawclk(struct drm_device *dev)
         }
 }
 
+static void
+intel_dp_init_panel_power_sequencer(struct drm_device *dev,
+                                    struct intel_dp *intel_dp,
+                                    struct edp_power_seq *out);
+static void
+intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
+                                              struct intel_dp *intel_dp,
+                                              struct edp_power_seq *out);
+
+static enum pipe
+vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
+{
+        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+        struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
+        struct drm_device *dev = intel_dig_port->base.base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        enum port port = intel_dig_port->port;
+        enum pipe pipe;
+
+        /* modeset should have pipe */
+        if (crtc)
+                return to_intel_crtc(crtc)->pipe;
+
+        /* init time, try to find a pipe with this port selected */
+        for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
+                u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
+                        PANEL_PORT_SELECT_MASK;
+                if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
+                        return pipe;
+                if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
+                        return pipe;
+        }
+
+        /* shrug */
+        return PIPE_A;
+}
+
+static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
+{
+        struct drm_device *dev = intel_dp_to_dev(intel_dp);
+
+        if (HAS_PCH_SPLIT(dev))
+                return PCH_PP_CONTROL;
+        else
+                return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
+}
+
+static u32 _pp_stat_reg(struct intel_dp *intel_dp)
+{
+        struct drm_device *dev = intel_dp_to_dev(intel_dp);
+
+        if (HAS_PCH_SPLIT(dev))
+                return PCH_PP_STATUS;
+        else
+                return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
+}
+
 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 pp_stat_reg;
 
-        pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
-        return (I915_READ(pp_stat_reg) & PP_ON) != 0;
+        return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 pp_ctrl_reg;
 
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
-        return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
+        return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 }
 
 static void
@@ -236,19 +315,15 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 pp_stat_reg, pp_ctrl_reg;
 
         if (!is_edp(intel_dp))
                 return;
 
-        pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
-
         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
-                                I915_READ(pp_stat_reg),
-                                I915_READ(pp_ctrl_reg));
+                              I915_READ(_pp_stat_reg(intel_dp)),
+                              I915_READ(_pp_ctrl_reg(intel_dp)));
         }
 }
 
@@ -361,6 +436,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
                 goto out;
         }
 
+        /* Only 5 data registers! */
+        if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
+                ret = -E2BIG;
+                goto out;
+        }
+
         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
                 /* Must try at least 3 times according to DP spec */
                 for (try = 0; try < 5; try++) {
@@ -451,9 +532,10 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
         int msg_bytes;
         uint8_t ack;
 
+        if (WARN_ON(send_bytes > 16))
+                return -E2BIG;
+
         intel_dp_check_edp(intel_dp);
-        if (send_bytes > 16)
-                return -1;
         msg[0] = AUX_NATIVE_WRITE << 4;
         msg[1] = address >> 8;
         msg[2] = address & 0xff;
@@ -494,6 +576,9 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
         uint8_t ack;
         int ret;
 
+        if (WARN_ON(recv_bytes > 19))
+                return -E2BIG;
+
         intel_dp_check_edp(intel_dp);
         msg[0] = AUX_NATIVE_READ << 4;
         msg[1] = address >> 8;
@@ -569,7 +654,12 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
                 break;
         }
 
-        for (retry = 0; retry < 5; retry++) {
+        /*
+         * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
+         * required to retry at least seven times upon receiving AUX_DEFER
+         * before giving up the AUX transaction.
+         */
+        for (retry = 0; retry < 7; retry++) {
                 ret = intel_dp_aux_ch(intel_dp,
                                       msg, msg_bytes,
                                       reply, reply_bytes);
@@ -647,7 +737,7 @@ intel_dp_i2c_init(struct intel_dp *intel_dp,
         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
         intel_dp->adapter.algo_data = &intel_dp->algo;
-        intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
+        intel_dp->adapter.dev.parent = intel_connector->base.kdev;
 
         ironlake_edp_panel_vdd_on(intel_dp);
         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
@@ -660,41 +750,30 @@ intel_dp_set_clock(struct intel_encoder *encoder,
                    struct intel_crtc_config *pipe_config, int link_bw)
 {
         struct drm_device *dev = encoder->base.dev;
+        const struct dp_link_dpll *divisor = NULL;
+        int i, count = 0;
 
         if (IS_G4X(dev)) {
-                if (link_bw == DP_LINK_BW_1_62) {
-                        pipe_config->dpll.p1 = 2;
-                        pipe_config->dpll.p2 = 10;
-                        pipe_config->dpll.n = 2;
-                        pipe_config->dpll.m1 = 23;
-                        pipe_config->dpll.m2 = 8;
-                } else {
-                        pipe_config->dpll.p1 = 1;
-                        pipe_config->dpll.p2 = 10;
-                        pipe_config->dpll.n = 1;
-                        pipe_config->dpll.m1 = 14;
-                        pipe_config->dpll.m2 = 2;
-                }
-                pipe_config->clock_set = true;
+                divisor = gen4_dpll;
+                count = ARRAY_SIZE(gen4_dpll);
         } else if (IS_HASWELL(dev)) {
                 /* Haswell has special-purpose DP DDI clocks. */
         } else if (HAS_PCH_SPLIT(dev)) {
-                if (link_bw == DP_LINK_BW_1_62) {
-                        pipe_config->dpll.n = 1;
-                        pipe_config->dpll.p1 = 2;
-                        pipe_config->dpll.p2 = 10;
-                        pipe_config->dpll.m1 = 12;
-                        pipe_config->dpll.m2 = 9;
-                } else {
-                        pipe_config->dpll.n = 2;
-                        pipe_config->dpll.p1 = 1;
-                        pipe_config->dpll.p2 = 10;
-                        pipe_config->dpll.m1 = 14;
-                        pipe_config->dpll.m2 = 8;
-                }
-                pipe_config->clock_set = true;
+                divisor = pch_dpll;
+                count = ARRAY_SIZE(pch_dpll);
         } else if (IS_VALLEYVIEW(dev)) {
-                /* FIXME: Need to figure out optimized DP clocks for vlv. */
+                divisor = vlv_dpll;
+                count = ARRAY_SIZE(vlv_dpll);
+        }
+
+        if (divisor && count) {
+                for (i = 0; i < count; i++) {
+                        if (link_bw == divisor[i].link_bw) {
+                                pipe_config->dpll = divisor[i].dpll;
+                                pipe_config->clock_set = true;
+                                break;
+                        }
+                }
         }
 }
 
@@ -737,7 +816,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
         DRM_DEBUG_KMS("DP link computation with max lane count %i "
                       "max bw %02x pixel clock %iKHz\n",
-                      max_lane_count, bws[max_clock], adjusted_mode->clock);
+                      max_lane_count, bws[max_clock],
+                      adjusted_mode->crtc_clock);
 
         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
          * bpc in between. */
@@ -749,7 +829,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
         }
 
         for (; bpp >= 6*3; bpp -= 2*3) {
-                mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
+                mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
+                                                   bpp);
 
                 for (clock = 0; clock <= max_clock; clock++) {
                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
@@ -794,7 +875,8 @@ found:
                       mode_rate, link_avail);
 
         intel_link_compute_m_n(bpp, lane_count,
-                               adjusted_mode->clock, pipe_config->port_clock,
+                               adjusted_mode->crtc_clock,
+                               pipe_config->port_clock,
                                &pipe_config->dp_m_n);
 
         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
@@ -802,21 +884,6 @@ found:
         return true;
 }
 
-void intel_dp_init_link_config(struct intel_dp *intel_dp)
-{
-        memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
-        intel_dp->link_configuration[0] = intel_dp->link_bw;
-        intel_dp->link_configuration[1] = intel_dp->lane_count;
-        intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
-        /*
-         * Check for DPCD version > 1.1 and enhanced framing support
-         */
-        if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
-            (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
-                intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
-        }
-}
-
 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 {
         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -889,8 +956,6 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
                 intel_write_eld(&encoder->base, adjusted_mode);
         }
 
-        intel_dp_init_link_config(intel_dp);
-
         /* Split out the IBX/CPU vs CPT settings */
 
         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
@@ -900,7 +965,7 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
                         intel_dp->DP |= DP_SYNC_VS_HIGH;
                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 
-                if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 
                 intel_dp->DP |= crtc->pipe << 29;
@@ -914,7 +979,7 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
                         intel_dp->DP |= DP_SYNC_VS_HIGH;
                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 
-                if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 
                 if (crtc->pipe == 1)
@@ -944,8 +1009,8 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 pp_stat_reg, pp_ctrl_reg;
 
-        pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+        pp_stat_reg = _pp_stat_reg(intel_dp);
+        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 
         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
                         mask, value,
@@ -987,11 +1052,8 @@ static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 control;
-        u32 pp_ctrl_reg;
-
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
-        control = I915_READ(pp_ctrl_reg);
 
+        control = I915_READ(_pp_ctrl_reg(intel_dp));
         control &= ~PANEL_UNLOCK_MASK;
         control |= PANEL_UNLOCK_REGS;
         return control;
@@ -1024,8 +1086,8 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
         pp = ironlake_get_pp_control(intel_dp);
         pp |= EDP_FORCE_VDD;
 
-        pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+        pp_stat_reg = _pp_stat_reg(intel_dp);
+        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 
         I915_WRITE(pp_ctrl_reg, pp);
         POSTING_READ(pp_ctrl_reg);
@@ -1053,8 +1115,8 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
                 pp = ironlake_get_pp_control(intel_dp);
                 pp &= ~EDP_FORCE_VDD;
 
-                pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
-                pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+                pp_stat_reg = _pp_ctrl_reg(intel_dp);
+                pp_ctrl_reg = _pp_stat_reg(intel_dp);
 
                 I915_WRITE(pp_ctrl_reg, pp);
                 POSTING_READ(pp_ctrl_reg);
@@ -1119,20 +1181,19 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 
         ironlake_wait_panel_power_cycle(intel_dp);
 
+        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
         pp = ironlake_get_pp_control(intel_dp);
         if (IS_GEN5(dev)) {
                 /* ILK workaround: disable reset around power sequence */
                 pp &= ~PANEL_POWER_RESET;
-                I915_WRITE(PCH_PP_CONTROL, pp);
-                POSTING_READ(PCH_PP_CONTROL);
+                I915_WRITE(pp_ctrl_reg, pp);
+                POSTING_READ(pp_ctrl_reg);
         }
 
         pp |= POWER_TARGET_ON;
         if (!IS_GEN5(dev))
                 pp |= PANEL_POWER_RESET;
 
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
-
         I915_WRITE(pp_ctrl_reg, pp);
         POSTING_READ(pp_ctrl_reg);
 
@@ -1140,8 +1201,8 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
 
         if (IS_GEN5(dev)) {
                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
-                I915_WRITE(PCH_PP_CONTROL, pp);
-                POSTING_READ(PCH_PP_CONTROL);
+                I915_WRITE(pp_ctrl_reg, pp);
+                POSTING_READ(pp_ctrl_reg);
         }
 }
 
@@ -1164,7 +1225,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
          * panels get very unhappy and cease to work. */
         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
 
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 
         I915_WRITE(pp_ctrl_reg, pp);
         POSTING_READ(pp_ctrl_reg);
@@ -1197,7 +1258,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
         pp = ironlake_get_pp_control(intel_dp);
         pp |= EDP_BLC_ENABLE;
 
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 
         I915_WRITE(pp_ctrl_reg, pp);
         POSTING_READ(pp_ctrl_reg);
@@ -1221,7 +1282,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
         pp = ironlake_get_pp_control(intel_dp);
         pp &= ~EDP_BLC_ENABLE;
 
-        pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
+        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 
         I915_WRITE(pp_ctrl_reg, pp);
         POSTING_READ(pp_ctrl_reg);
@@ -1368,6 +1429,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
         struct drm_i915_private *dev_priv = dev->dev_private;
         enum port port = dp_to_dig_port(intel_dp)->port;
         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+        int dotclock;
 
         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
                 tmp = I915_READ(intel_dp->output_reg);
@@ -1395,28 +1457,41 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 
         pipe_config->adjusted_mode.flags |= flags;
 
-        if (dp_to_dig_port(intel_dp)->port == PORT_A) {
+        pipe_config->has_dp_encoder = true;
+
+        intel_dp_get_m_n(crtc, pipe_config);
+
+        if (port == PORT_A) {
                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
                         pipe_config->port_clock = 162000;
                 else
                         pipe_config->port_clock = 270000;
         }
+
+        dotclock = intel_dotclock_calculate(pipe_config->port_clock,
+                                            &pipe_config->dp_m_n);
+
+        if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
+                ironlake_check_encoder_dotclock(pipe_config, dotclock);
+
+        pipe_config->adjusted_mode.crtc_clock = dotclock;
 }
 
-static bool is_edp_psr(struct intel_dp *intel_dp)
+static bool is_edp_psr(struct drm_device *dev)
 {
-        return is_edp(intel_dp) &&
-                intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        return dev_priv->psr.sink_support;
 }
 
 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (!IS_HASWELL(dev))
+        if (!HAS_PSR(dev))
                 return false;
 
-        return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
+        return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
 }
 
 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
@@ -1466,7 +1541,7 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp)
         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
 
         /* Avoid continuous PSR exit by masking memup and hpd */
-        I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
+        I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
                    EDP_PSR_DEBUG_MASK_HPD);
 
         intel_dp->psr_setup_done = true;
@@ -1491,9 +1566,9 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
                                             DP_PSR_MAIN_LINK_ACTIVE);
 
         /* Setup AUX registers */
-        I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
-        I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
-        I915_WRITE(EDP_PSR_AUX_CTL,
+        I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
+        I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
+        I915_WRITE(EDP_PSR_AUX_CTL(dev),
                    DP_AUX_CH_CTL_TIME_OUT_400us |
                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
@@ -1516,7 +1591,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
         } else
                 val |= EDP_PSR_LINK_DISABLE;
 
-        I915_WRITE(EDP_PSR_CTL, val |
+        I915_WRITE(EDP_PSR_CTL(dev), val |
                    EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
@@ -1533,42 +1608,33 @@ static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
 
-        if (!IS_HASWELL(dev)) {
+        dev_priv->psr.source_ok = false;
+
+        if (!HAS_PSR(dev)) {
                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
-                dev_priv->no_psr_reason = PSR_NO_SOURCE;
                 return false;
         }
 
         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
             (dig_port->port != PORT_A)) {
                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
-                dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
-                return false;
-        }
-
-        if (!is_edp_psr(intel_dp)) {
-                DRM_DEBUG_KMS("PSR not supported by this panel\n");
-                dev_priv->no_psr_reason = PSR_NO_SINK;
                 return false;
         }
 
         if (!i915_enable_psr) {
                 DRM_DEBUG_KMS("PSR disable by flag\n");
-                dev_priv->no_psr_reason = PSR_MODULE_PARAM;
                 return false;
         }
 
         crtc = dig_port->base.base.crtc;
         if (crtc == NULL) {
                 DRM_DEBUG_KMS("crtc not active for PSR\n");
-                dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
                 return false;
         }
 
         intel_crtc = to_intel_crtc(crtc);
-        if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
+        if (!intel_crtc_active(crtc)) {
                 DRM_DEBUG_KMS("crtc not active for PSR\n");
-                dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
                 return false;
         }
 
@@ -1576,29 +1642,26 @@ static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
         if (obj->tiling_mode != I915_TILING_X ||
             obj->fence_reg == I915_FENCE_REG_NONE) {
                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
-                dev_priv->no_psr_reason = PSR_NOT_TILED;
                 return false;
         }
 
         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
-                dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
                 return false;
         }
 
         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
             S3D_ENABLE) {
                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
-                dev_priv->no_psr_reason = PSR_S3D_ENABLED;
                 return false;
         }
 
-        if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
+        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
-                dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
                 return false;
         }
 
+        dev_priv->psr.source_ok = true;
         return true;
 }
 
@@ -1637,10 +1700,11 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
         if (!intel_edp_is_psr_enabled(dev))
                 return;
 
-        I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
+        I915_WRITE(EDP_PSR_CTL(dev),
+                   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
 
         /* Wait till PSR is idle */
-        if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
+        if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
 }
@@ -1654,7 +1718,7 @@ void intel_edp_psr_update(struct drm_device *dev)
                 if (encoder->type == INTEL_OUTPUT_EDP) {
                         intel_dp = enc_to_intel_dp(&encoder->base);
 
-                        if (!is_edp_psr(intel_dp))
+                        if (!is_edp_psr(dev))
                                 return;
 
                         if (!intel_edp_psr_match_conditions(intel_dp))
@@ -1713,14 +1777,24 @@ static void intel_enable_dp(struct intel_encoder *encoder)
         ironlake_edp_panel_vdd_off(intel_dp, true);
         intel_dp_complete_link_train(intel_dp);
         intel_dp_stop_link_train(intel_dp);
+}
+
+static void g4x_enable_dp(struct intel_encoder *encoder)
+{
+        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+        intel_enable_dp(encoder);
         ironlake_edp_backlight_on(intel_dp);
 }
 
 static void vlv_enable_dp(struct intel_encoder *encoder)
 {
+        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+        ironlake_edp_backlight_on(intel_dp);
 }
 
-static void intel_pre_enable_dp(struct intel_encoder *encoder)
+static void g4x_pre_enable_dp(struct intel_encoder *encoder)
 {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
@@ -1738,53 +1812,59 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
         int port = vlv_dport_to_channel(dport);
         int pipe = intel_crtc->pipe;
+        struct edp_power_seq power_seq;
         u32 val;
 
         mutex_lock(&dev_priv->dpio_lock);
 
-        val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
+        val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
         val = 0;
         if (pipe)
                 val |= (1<<21);
         else
                 val &= ~(1<<21);
         val |= 0x001000c4;
-        vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
 
         mutex_unlock(&dev_priv->dpio_lock);
 
+        /* init power sequencer on this pipe and port */
+        intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
+        intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
+                                                      &power_seq);
+
         intel_enable_dp(encoder);
 
         vlv_wait_port_ready(dev_priv, port);
 }
 
-static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
+static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 {
         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
         struct drm_device *dev = encoder->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(encoder->base.crtc);
         int port = vlv_dport_to_channel(dport);
-
-        if (!IS_VALLEYVIEW(dev))
-                return;
+        int pipe = intel_crtc->pipe;
 
         /* Program Tx lane resets to default */
         mutex_lock(&dev_priv->dpio_lock);
-        vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
                          DPIO_PCS_TX_LANE2_RESET |
                          DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
                                  DPIO_PCS_CLK_SOFT_RESET);
 
         /* Fix up inter-pair skew failure */
-        vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
-        vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
-        vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
         mutex_unlock(&dev_priv->dpio_lock);
 }
 
@@ -1919,10 +1999,13 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(dport->base.base.crtc);
         unsigned long demph_reg_value, preemph_reg_value,
                 uniqtranscale_reg_value;
         uint8_t train_set = intel_dp->train_set[0];
         int port = vlv_dport_to_channel(dport);
+        int pipe = intel_crtc->pipe;
 
         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
         case DP_TRAIN_PRE_EMPHASIS_0:
@@ -1998,14 +2081,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
         }
 
         mutex_lock(&dev_priv->dpio_lock);
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
                          uniqtranscale_reg_value);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
-        vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
         mutex_unlock(&dev_priv->dpio_lock);
 
         return 0;
@@ -2207,7 +2290,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
-                        uint32_t dp_reg_value,
+                        uint32_t *DP,
                         uint8_t dp_train_pat)
 {
         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -2243,50 +2326,51 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
                 I915_WRITE(DP_TP_CTL(port), temp);
 
         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
-                dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
+                *DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
                 case DP_TRAINING_PATTERN_DISABLE:
-                        dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
+                        *DP |= DP_LINK_TRAIN_OFF_CPT;
                         break;
                 case DP_TRAINING_PATTERN_1:
-                        dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
+                        *DP |= DP_LINK_TRAIN_PAT_1_CPT;
                         break;
                 case DP_TRAINING_PATTERN_2:
-                        dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
+                        *DP |= DP_LINK_TRAIN_PAT_2_CPT;
                         break;
                 case DP_TRAINING_PATTERN_3:
                         DRM_ERROR("DP training pattern 3 not supported\n");
-                        dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
+                        *DP |= DP_LINK_TRAIN_PAT_2_CPT;
                         break;
                 }
 
         } else {
-                dp_reg_value &= ~DP_LINK_TRAIN_MASK;
+                *DP &= ~DP_LINK_TRAIN_MASK;
 
                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
                 case DP_TRAINING_PATTERN_DISABLE:
-                        dp_reg_value |= DP_LINK_TRAIN_OFF;
+                        *DP |= DP_LINK_TRAIN_OFF;
                         break;
                 case DP_TRAINING_PATTERN_1:
-                        dp_reg_value |= DP_LINK_TRAIN_PAT_1;
+                        *DP |= DP_LINK_TRAIN_PAT_1;
                         break;
                 case DP_TRAINING_PATTERN_2:
-                        dp_reg_value |= DP_LINK_TRAIN_PAT_2;
+                        *DP |= DP_LINK_TRAIN_PAT_2;
                         break;
                 case DP_TRAINING_PATTERN_3:
                         DRM_ERROR("DP training pattern 3 not supported\n");
-                        dp_reg_value |= DP_LINK_TRAIN_PAT_2;
+                        *DP |= DP_LINK_TRAIN_PAT_2;
                         break;
                 }
         }
 
-        I915_WRITE(intel_dp->output_reg, dp_reg_value);
+        I915_WRITE(intel_dp->output_reg, *DP);
         POSTING_READ(intel_dp->output_reg);
 
-        intel_dp_aux_native_write_1(intel_dp,
-                                    DP_TRAINING_PATTERN_SET,
-                                    dp_train_pat);
+        ret = intel_dp_aux_native_write_1(intel_dp, DP_TRAINING_PATTERN_SET,
+                                          dp_train_pat);
+        if (ret != 1)
+                return false;
 
         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
             DP_TRAINING_PATTERN_DISABLE) {
@@ -2301,6 +2385,37 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
         return true;
 }
 
+static bool
+intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
+                        uint8_t dp_train_pat)
+{
+        memset(intel_dp->train_set, 0, 4);
+        intel_dp_set_signal_levels(intel_dp, DP);
+        return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
+}
+
+static bool
+intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
+                           uint8_t link_status[DP_LINK_STATUS_SIZE])
+{
+        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+        struct drm_device *dev = intel_dig_port->base.base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int ret;
+
+        intel_get_adjust_train(intel_dp, link_status);
+        intel_dp_set_signal_levels(intel_dp, DP);
+
+        I915_WRITE(intel_dp->output_reg, *DP);
+        POSTING_READ(intel_dp->output_reg);
+
+        ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
+                                        intel_dp->train_set,
+                                        intel_dp->lane_count);
+
+        return ret == intel_dp->lane_count;
+}
+
 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 {
         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -2342,32 +2457,37 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
         uint8_t voltage;
         int voltage_tries, loop_tries;
         uint32_t DP = intel_dp->DP;
+        uint8_t link_config[2];
 
         if (HAS_DDI(dev))
                 intel_ddi_prepare_link_retrain(encoder);
 
         /* Write the link configuration data */
-        intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
-                                  intel_dp->link_configuration,
-                                  DP_LINK_CONFIGURATION_SIZE);
+        link_config[0] = intel_dp->link_bw;
+        link_config[1] = intel_dp->lane_count;
+        if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+                link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+        intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
+
+        link_config[0] = 0;
+        link_config[1] = DP_SET_ANSI_8B10B;
+        intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
 
         DP |= DP_PORT_EN;
 
-        memset(intel_dp->train_set, 0, 4);
+        /* clock recovery */
+        if (!intel_dp_reset_link_train(intel_dp, &DP,
+                                       DP_TRAINING_PATTERN_1 |
+                                       DP_LINK_SCRAMBLING_DISABLE)) {
+                DRM_ERROR("failed to enable link training\n");
+                return;
+        }
+
         voltage = 0xff;
         voltage_tries = 0;
         loop_tries = 0;
         for (;;) {
-                /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
-                uint8_t     link_status[DP_LINK_STATUS_SIZE];
-
-                intel_dp_set_signal_levels(intel_dp, &DP);
-
-                /* Set training pattern 1 */
-                if (!intel_dp_set_link_train(intel_dp, DP,
-                                             DP_TRAINING_PATTERN_1 |
-                                             DP_LINK_SCRAMBLING_DISABLE))
-                        break;
+                uint8_t link_status[DP_LINK_STATUS_SIZE];
 
                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
@@ -2390,7 +2510,9 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                                 DRM_DEBUG_KMS("too many full retries, give up\n");
                                 break;
                         }
-                        memset(intel_dp->train_set, 0, 4);
+                        intel_dp_reset_link_train(intel_dp, &DP,
+                                                  DP_TRAINING_PATTERN_1 |
+                                                  DP_LINK_SCRAMBLING_DISABLE);
                         voltage_tries = 0;
                         continue;
                 }
@@ -2406,8 +2528,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                         voltage_tries = 0;
                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
-                /* Compute new intel_dp->train_set as requested by target */
-                intel_get_adjust_train(intel_dp, link_status);
+                /* Update training set as requested by target */
+                if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
+                        DRM_ERROR("failed to update link training\n");
+                        break;
+                }
         }
 
         intel_dp->DP = DP;
@@ -2421,11 +2546,18 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
         uint32_t DP = intel_dp->DP;
 
         /* channel equalization */
+        if (!intel_dp_set_link_train(intel_dp, &DP,
+                                     DP_TRAINING_PATTERN_2 |
+                                     DP_LINK_SCRAMBLING_DISABLE)) {
+                DRM_ERROR("failed to start channel equalization\n");
+                return;
+        }
+
         tries = 0;
         cr_tries = 0;
         channel_eq = false;
         for (;;) {
-                uint8_t     link_status[DP_LINK_STATUS_SIZE];
+                uint8_t link_status[DP_LINK_STATUS_SIZE];
 
                 if (cr_tries > 5) {
                         DRM_ERROR("failed to train DP, aborting\n");
@@ -2433,21 +2565,18 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                         break;
                 }
 
-                intel_dp_set_signal_levels(intel_dp, &DP);
-
-                /* channel eq pattern */
-                if (!intel_dp_set_link_train(intel_dp, DP,
-                                             DP_TRAINING_PATTERN_2 |
-                                             DP_LINK_SCRAMBLING_DISABLE))
-                        break;
-
                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
-                if (!intel_dp_get_link_status(intel_dp, link_status))
+                if (!intel_dp_get_link_status(intel_dp, link_status)) {
+                        DRM_ERROR("failed to get link status\n");
                         break;
+                }
 
                 /* Make sure clock is still ok */
                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
                         intel_dp_start_link_train(intel_dp);
+                        intel_dp_set_link_train(intel_dp, &DP,
+                                                DP_TRAINING_PATTERN_2 |
+                                                DP_LINK_SCRAMBLING_DISABLE);
                         cr_tries++;
                         continue;
                 }
@@ -2461,13 +2590,19 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                 if (tries > 5) {
                         intel_dp_link_down(intel_dp);
                         intel_dp_start_link_train(intel_dp);
+                        intel_dp_set_link_train(intel_dp, &DP,
+                                                DP_TRAINING_PATTERN_2 |
+                                                DP_LINK_SCRAMBLING_DISABLE);
                         tries = 0;
                         cr_tries++;
                         continue;
                 }
 
-                /* Compute new intel_dp->train_set as requested by target */
-                intel_get_adjust_train(intel_dp, link_status);
+                /* Update training set as requested by target */
+                if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
+                        DRM_ERROR("failed to update link training\n");
+                        break;
+                }
                 ++tries;
         }
 
@@ -2482,7 +2617,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 {
-        intel_dp_set_link_train(intel_dp, intel_dp->DP,
+        intel_dp_set_link_train(intel_dp, &intel_dp->DP,
                                 DP_TRAINING_PATTERN_DISABLE);
 }
 
@@ -2569,6 +2704,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 static bool
 intel_dp_get_dpcd(struct intel_dp *intel_dp)
 {
+        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+        struct drm_device *dev = dig_port->base.base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
 
         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
@@ -2584,11 +2723,16 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 
         /* Check if the panel supports PSR */
         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
-        intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
-                                       intel_dp->psr_dpcd,
-                                       sizeof(intel_dp->psr_dpcd));
-        if (is_edp_psr(intel_dp))
-                DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
+        if (is_edp(intel_dp)) {
+                intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
+                                               intel_dp->psr_dpcd,
+                                               sizeof(intel_dp->psr_dpcd));
+                if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
+                        dev_priv->psr.sink_support = true;
+                        DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
+                }
+        }
+
         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
               DP_DWN_STRM_PORT_PRESENT))
                 return true; /* native DP sink */
@@ -2708,7 +2852,6 @@ static enum drm_connector_status
 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
 {
         uint8_t *dpcd = intel_dp->dpcd;
-        bool hpd;
         uint8_t type;
 
         if (!intel_dp_get_dpcd(intel_dp))
@@ -2719,8 +2862,8 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
                 return connector_status_connected;
 
         /* If we're HPD-aware, SINK_COUNT changes dynamically */
-        hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
-        if (hpd) {
+        if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+            intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
                 uint8_t reg;
                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
                                                     &reg, 1))
@@ -2734,9 +2877,18 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
                 return connector_status_connected;
 
         /* Well we tried, say unknown for unreliable port types */
-        type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
-        if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
-                return connector_status_unknown;
+        if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+                type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+                if (type == DP_DS_PORT_TYPE_VGA ||
+                    type == DP_DS_PORT_TYPE_NON_EDID)
+                        return connector_status_unknown;
+        } else {
+                type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+                        DP_DWN_STRM_PORT_TYPE_MASK;
+                if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
+                    type == DP_DWN_STRM_PORT_TYPE_OTHER)
+                        return connector_status_unknown;
+        }
 
         /* Anything else is out of spec, warn and ignore */
         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
@@ -2810,19 +2962,11 @@ intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
 
         /* use cached edid if we have one */
         if (intel_connector->edid) {
-                struct edid *edid;
-                int size;
-
                 /* invalid edid */
                 if (IS_ERR(intel_connector->edid))
                         return NULL;
 
-                size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
-                edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
-                if (!edid)
-                        return NULL;
-
-                return edid;
+                return drm_edid_duplicate(intel_connector->edid);
         }
 
         return drm_get_edid(connector, adapter);
@@ -3030,7 +3174,6 @@ intel_dp_connector_destroy(struct drm_connector *connector)
         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
                 intel_panel_fini(&intel_connector->panel);
 
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(connector);
 }
@@ -3101,7 +3244,7 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc)
 bool intel_dpd_is_edp(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct child_device_config *p_child;
+        union child_device_config *p_child;
         int i;
 
         if (!dev_priv->vbt.child_dev_num)
@@ -3110,8 +3253,8 @@ bool intel_dpd_is_edp(struct drm_device *dev)
         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
                 p_child = dev_priv->vbt.child_dev + i;
 
-                if (p_child->dvo_port == PORT_IDPD &&
-                    p_child->device_type == DEVICE_TYPE_eDP)
+                if (p_child->common.dvo_port == PORT_IDPD &&
+                    p_child->common.device_type == DEVICE_TYPE_eDP)
                         return true;
         }
         return false;
@@ -3144,24 +3287,26 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct edp_power_seq cur, vbt, spec, final;
         u32 pp_on, pp_off, pp_div, pp;
-        int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
+        int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
 
         if (HAS_PCH_SPLIT(dev)) {
-                pp_control_reg = PCH_PP_CONTROL;
+                pp_ctrl_reg = PCH_PP_CONTROL;
                 pp_on_reg = PCH_PP_ON_DELAYS;
                 pp_off_reg = PCH_PP_OFF_DELAYS;
                 pp_div_reg = PCH_PP_DIVISOR;
         } else {
-                pp_control_reg = PIPEA_PP_CONTROL;
-                pp_on_reg = PIPEA_PP_ON_DELAYS;
-                pp_off_reg = PIPEA_PP_OFF_DELAYS;
-                pp_div_reg = PIPEA_PP_DIVISOR;
+                enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+
+                pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+                pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
+                pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
+                pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
         }
 
         /* Workaround: Need to write PP_CONTROL with the unlock key as
          * the very first thing. */
         pp = ironlake_get_pp_control(intel_dp);
-        I915_WRITE(pp_control_reg, pp);
+        I915_WRITE(pp_ctrl_reg, pp);
 
         pp_on = I915_READ(pp_on_reg);
         pp_off = I915_READ(pp_off_reg);
@@ -3249,9 +3394,11 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
                 pp_off_reg = PCH_PP_OFF_DELAYS;
                 pp_div_reg = PCH_PP_DIVISOR;
         } else {
-                pp_on_reg = PIPEA_PP_ON_DELAYS;
-                pp_off_reg = PIPEA_PP_OFF_DELAYS;
-                pp_div_reg = PIPEA_PP_DIVISOR;
+                enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+
+                pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
+                pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
+                pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
         }
 
         /* And finally store the new values in the power sequencer. */
@@ -3268,12 +3415,15 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
         /* Haswell doesn't have any port selection bits for the panel
          * power sequencer any more. */
         if (IS_VALLEYVIEW(dev)) {
-                port_sel = I915_READ(pp_on_reg) & 0xc0000000;
+                if (dp_to_dig_port(intel_dp)->port == PORT_B)
+                        port_sel = PANEL_PORT_SELECT_DPB_VLV;
+                else
+                        port_sel = PANEL_PORT_SELECT_DPC_VLV;
         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
-                        port_sel = PANEL_POWER_PORT_DP_A;
+                        port_sel = PANEL_PORT_SELECT_DPA;
                 else
-                        port_sel = PANEL_POWER_PORT_DP_D;
+                        port_sel = PANEL_PORT_SELECT_DPD;
         }
 
         pp_on |= port_sel;
@@ -3516,11 +3666,11 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
         struct drm_encoder *encoder;
         struct intel_connector *intel_connector;
 
-        intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
+        intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
         if (!intel_dig_port)
                 return;
 
-        intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
+        intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
         if (!intel_connector) {
                 kfree(intel_dig_port);
                 return;
@@ -3539,12 +3689,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
         intel_encoder->get_hw_state = intel_dp_get_hw_state;
         intel_encoder->get_config = intel_dp_get_config;
         if (IS_VALLEYVIEW(dev)) {
-                intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
+                intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
                 intel_encoder->pre_enable = vlv_pre_enable_dp;
                 intel_encoder->enable = vlv_enable_dp;
         } else {
-                intel_encoder->pre_enable = intel_pre_enable_dp;
-                intel_encoder->enable = intel_enable_dp;
+                intel_encoder->pre_enable = g4x_pre_enable_dp;
+                intel_encoder->enable = g4x_enable_dp;
         }
 
         intel_dig_port->port = port;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 28cae80495e2..eaf0003ddfd9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -77,7 +77,6 @@
 /* the i915, i945 have a single sDVO i2c bus - which is different */
 #define MAX_OUTPUTS 6
 /* maximum connectors per crtcs in the mode set */
-#define INTELFB_CONN_LIMIT 4
 
 #define INTEL_I2C_BUS_DVO 1
 #define INTEL_I2C_BUS_SDVO 2
@@ -93,13 +92,17 @@
 #define INTEL_OUTPUT_HDMI 6
 #define INTEL_OUTPUT_DISPLAYPORT 7
 #define INTEL_OUTPUT_EDP 8
-#define INTEL_OUTPUT_UNKNOWN 9
+#define INTEL_OUTPUT_DSI 9
+#define INTEL_OUTPUT_UNKNOWN 10
 
 #define INTEL_DVO_CHIP_NONE 0
 #define INTEL_DVO_CHIP_LVDS 1
 #define INTEL_DVO_CHIP_TMDS 2
 #define INTEL_DVO_CHIP_TVOUT 4
 
+#define INTEL_DSI_COMMAND_MODE  0
+#define INTEL_DSI_VIDEO_MODE    1
+
 struct intel_framebuffer {
         struct drm_framebuffer base;
         struct drm_i915_gem_object *obj;
@@ -207,8 +210,21 @@ struct intel_crtc_config {
 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
         unsigned long quirks;
 
+        /* User requested mode, only valid as a starting point to
+         * compute adjusted_mode, except in the case of (S)DVO where
+         * it's also for the output timings of the (S)DVO chip.
+         * adjusted_mode will then correspond to the S(DVO) chip's
+         * preferred input timings. */
         struct drm_display_mode requested_mode;
+        /* Actual pipe timings ie. what we program into the pipe timing
+         * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
         struct drm_display_mode adjusted_mode;
+
+        /* Pipe source size (ie. panel fitter input size)
+         * All planes will be positioned inside this space,
+         * and get clipped at the edges. */
+        int pipe_src_w, pipe_src_h;
+
         /* Whether to set up the PCH/FDI. Note that we never allow sharing
          * between pch encoders and cpu encoders. */
         bool has_pch_encoder;
@@ -262,7 +278,8 @@ struct intel_crtc_config {
 
         /*
          * Frequence the dpll for the port should run at. Differs from the
-         * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
+         * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
+         * already multiplied by pixel_multiplier.
          */
         int port_clock;
 
@@ -288,6 +305,8 @@ struct intel_crtc_config {
         struct intel_link_m_n fdi_m_n;
 
         bool ips_enabled;
+
+        bool double_wide;
 };
 
 struct intel_crtc {
@@ -417,13 +436,11 @@ struct intel_hdmi {
 };
 
 #define DP_MAX_DOWNSTREAM_PORTS         0x10
-#define DP_LINK_CONFIGURATION_SIZE      9
 
 struct intel_dp {
         uint32_t output_reg;
         uint32_t aux_ch_ctl_reg;
         uint32_t DP;
-        uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
         bool has_audio;
         enum hdmi_force_audio force_audio;
         uint32_t color_range;
@@ -495,80 +512,6 @@ struct intel_unpin_work {
         bool enable_stall_check;
 };
 
-int intel_pch_rawclk(struct drm_device *dev);
-
-int intel_connector_update_modes(struct drm_connector *connector,
-                                struct edid *edid);
-int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
-
-extern void intel_attach_force_audio_property(struct drm_connector *connector);
-extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
-
-extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
-extern void intel_crt_init(struct drm_device *dev);
-extern void intel_hdmi_init(struct drm_device *dev,
-                            int hdmi_reg, enum port port);
-extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
-                                      struct intel_connector *intel_connector);
-extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
-extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
-                                      struct intel_crtc_config *pipe_config);
-extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
-                            bool is_sdvob);
-extern void intel_dvo_init(struct drm_device *dev);
-extern void intel_tv_init(struct drm_device *dev);
-extern void intel_mark_busy(struct drm_device *dev);
-extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
-                               struct intel_ring_buffer *ring);
-extern void intel_mark_idle(struct drm_device *dev);
-extern void intel_lvds_init(struct drm_device *dev);
-extern bool intel_is_dual_link_lvds(struct drm_device *dev);
-extern void intel_dp_init(struct drm_device *dev, int output_reg,
-                          enum port port);
-extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
-                                    struct intel_connector *intel_connector);
-extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
-extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
-extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
-extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
-extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
-extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
-extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
-extern bool intel_dp_compute_config(struct intel_encoder *encoder,
-                                    struct intel_crtc_config *pipe_config);
-extern bool intel_dpd_is_edp(struct drm_device *dev);
-extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
-extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
-extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
-extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
-extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
-extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
-extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
-extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
-                                      enum plane plane);
-
-/* intel_panel.c */
-extern int intel_panel_init(struct intel_panel *panel,
-                            struct drm_display_mode *fixed_mode);
-extern void intel_panel_fini(struct intel_panel *panel);
-
-extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
-                                   struct drm_display_mode *adjusted_mode);
-extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
-                                    struct intel_crtc_config *pipe_config,
-                                    int fitting_mode);
-extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
-                                     struct intel_crtc_config *pipe_config,
-                                     int fitting_mode);
-extern void intel_panel_set_backlight(struct drm_device *dev,
-                                      u32 level, u32 max);
-extern int intel_panel_setup_backlight(struct drm_connector *connector);
-extern void intel_panel_enable_backlight(struct drm_device *dev,
-                                         enum pipe pipe);
-extern void intel_panel_disable_backlight(struct drm_device *dev);
-extern void intel_panel_destroy_backlight(struct drm_device *dev);
-extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
-
 struct intel_set_config {
         struct drm_encoder **save_connector_encoders;
         struct drm_crtc **save_encoder_crtcs;
@@ -577,18 +520,14 @@ struct intel_set_config {
         bool mode_changed;
 };
 
-extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
-extern void intel_crtc_load_lut(struct drm_crtc *crtc);
-extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
-extern void intel_encoder_destroy(struct drm_encoder *encoder);
-extern void intel_connector_dpms(struct drm_connector *, int mode);
-extern bool intel_connector_get_hw_state(struct intel_connector *connector);
-extern void intel_modeset_check_state(struct drm_device *dev);
-extern void intel_plane_restore(struct drm_plane *plane);
-extern void intel_plane_disable(struct drm_plane *plane);
-
+struct intel_load_detect_pipe {
+        struct drm_framebuffer *release_fb;
+        bool load_detect_temp;
+        int dpms_mode;
+};
 
-static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
+static inline struct intel_encoder *
+intel_attached_encoder(struct drm_connector *connector)
 {
         return to_intel_connector(connector)->encoder;
 }
@@ -616,73 +555,94 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 }
 
+
+/* i915_irq.c */
+bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
+                                           enum pipe pipe, bool enable);
+bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
+                                           enum transcoder pch_transcoder,
+                                           bool enable);
+void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
+void hsw_pc8_disable_interrupts(struct drm_device *dev);
+void hsw_pc8_restore_interrupts(struct drm_device *dev);
+
+
+/* intel_crt.c */
+void intel_crt_init(struct drm_device *dev);
+
+
+/* intel_ddi.c */
+void intel_prepare_ddi(struct drm_device *dev);
+void hsw_fdi_link_train(struct drm_crtc *crtc);
+void intel_ddi_init(struct drm_device *dev, enum port port);
+enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
+bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
+int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
+void intel_ddi_pll_init(struct drm_device *dev);
+void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
+void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
+                                       enum transcoder cpu_transcoder);
+void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
+void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
+void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
+bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
+void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
+void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
+void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
+bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
+void intel_ddi_fdi_disable(struct drm_crtc *crtc);
+void intel_ddi_get_config(struct intel_encoder *encoder,
+                          struct intel_crtc_config *pipe_config);
+
+
+/* intel_display.c */
+int intel_pch_rawclk(struct drm_device *dev);
+void intel_mark_busy(struct drm_device *dev);
+void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
+                        struct intel_ring_buffer *ring);
+void intel_mark_idle(struct drm_device *dev);
+void intel_crtc_restore_mode(struct drm_crtc *crtc);
+void intel_crtc_update_dpms(struct drm_crtc *crtc);
+void intel_encoder_destroy(struct drm_encoder *encoder);
+void intel_connector_dpms(struct drm_connector *, int mode);
+bool intel_connector_get_hw_state(struct intel_connector *connector);
+void intel_modeset_check_state(struct drm_device *dev);
 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
                                 struct intel_digital_port *port);
-
-extern void intel_connector_attach_encoder(struct intel_connector *connector,
-                                           struct intel_encoder *encoder);
-extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
-
-extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
-                                                    struct drm_crtc *crtc);
+void intel_connector_attach_encoder(struct intel_connector *connector,
+                                    struct intel_encoder *encoder);
+struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
+struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
+                                             struct drm_crtc *crtc);
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
                                 struct drm_file *file_priv);
-extern enum transcoder
-intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
-                             enum pipe pipe);
-extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
-extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
-extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
-extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
-
-struct intel_load_detect_pipe {
-        struct drm_framebuffer *release_fb;
-        bool load_detect_temp;
-        int dpms_mode;
-};
-extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
-                                       struct drm_display_mode *mode,
-                                       struct intel_load_detect_pipe *old);
-extern void intel_release_load_detect_pipe(struct drm_connector *connector,
-                                           struct intel_load_detect_pipe *old);
-
-extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
-                                    u16 blue, int regno);
-extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
-                                    u16 *blue, int regno);
-
-extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
-                                      struct drm_i915_gem_object *obj,
-                                      struct intel_ring_buffer *pipelined);
-extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
-
-extern int intel_framebuffer_init(struct drm_device *dev,
-                                  struct intel_framebuffer *ifb,
-                                  struct drm_mode_fb_cmd2 *mode_cmd,
-                                  struct drm_i915_gem_object *obj);
-extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
-extern int intel_fbdev_init(struct drm_device *dev);
-extern void intel_fbdev_initial_config(struct drm_device *dev);
-extern void intel_fbdev_fini(struct drm_device *dev);
-extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
-extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
-extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
-extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
-
-extern void intel_setup_overlay(struct drm_device *dev);
-extern void intel_cleanup_overlay(struct drm_device *dev);
-extern int intel_overlay_switch_off(struct intel_overlay *overlay);
-extern int intel_overlay_put_image(struct drm_device *dev, void *data,
-                                   struct drm_file *file_priv);
-extern int intel_overlay_attrs(struct drm_device *dev, void *data,
-                               struct drm_file *file_priv);
-
-extern void intel_fb_output_poll_changed(struct drm_device *dev);
-extern void intel_fb_restore_mode(struct drm_device *dev);
-
-struct intel_shared_dpll *
-intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
-
+enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
+                                             enum pipe pipe);
+void intel_wait_for_vblank(struct drm_device *dev, int pipe);
+void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
+int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
+void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
+bool intel_get_load_detect_pipe(struct drm_connector *connector,
+                                struct drm_display_mode *mode,
+                                struct intel_load_detect_pipe *old);
+void intel_release_load_detect_pipe(struct drm_connector *connector,
+                                    struct intel_load_detect_pipe *old);
+int intel_pin_and_fence_fb_obj(struct drm_device *dev,
+                               struct drm_i915_gem_object *obj,
+                               struct intel_ring_buffer *pipelined);
+void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
+int intel_framebuffer_init(struct drm_device *dev,
+                           struct intel_framebuffer *ifb,
+                           struct drm_mode_fb_cmd2 *mode_cmd,
+                           struct drm_i915_gem_object *obj);
+void intel_framebuffer_fini(struct intel_framebuffer *fb);
+void intel_prepare_page_flip(struct drm_device *dev, int plane);
+void intel_finish_page_flip(struct drm_device *dev, int pipe);
+void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
+struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 void assert_shared_dpll(struct drm_i915_private *dev_priv,
                         struct intel_shared_dpll *pll,
                         bool state);
@@ -696,103 +656,173 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
                        enum pipe pipe, bool state);
 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
-extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
-                        bool state);
+void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
+void intel_write_eld(struct drm_encoder *encoder,
+                     struct drm_display_mode *mode);
+unsigned long intel_gen4_compute_page_offset(int *x, int *y,
+                                             unsigned int tiling_mode,
+                                             unsigned int bpp,
+                                             unsigned int pitch);
+void intel_display_handle_reset(struct drm_device *dev);
+void hsw_enable_pc8_work(struct work_struct *__work);
+void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
+void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
+void intel_dp_get_m_n(struct intel_crtc *crtc,
+                      struct intel_crtc_config *pipe_config);
+int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
+void
+ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
+                                int dotclock);
+bool intel_crtc_active(struct drm_crtc *crtc);
+void i915_disable_vga_mem(struct drm_device *dev);
+
+
+/* intel_dp.c */
+void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
+bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
+                             struct intel_connector *intel_connector);
+void intel_dp_start_link_train(struct intel_dp *intel_dp);
+void intel_dp_complete_link_train(struct intel_dp *intel_dp);
+void intel_dp_stop_link_train(struct intel_dp *intel_dp);
+void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_encoder_destroy(struct drm_encoder *encoder);
+void intel_dp_check_link_status(struct intel_dp *intel_dp);
+bool intel_dp_compute_config(struct intel_encoder *encoder,
+                             struct intel_crtc_config *pipe_config);
+bool intel_dpd_is_edp(struct drm_device *dev);
+void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
+void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
+void ironlake_edp_panel_on(struct intel_dp *intel_dp);
+void ironlake_edp_panel_off(struct intel_dp *intel_dp);
+void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
+void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
+void intel_edp_psr_enable(struct intel_dp *intel_dp);
+void intel_edp_psr_disable(struct intel_dp *intel_dp);
+void intel_edp_psr_update(struct drm_device *dev);
+
+
+/* intel_dsi.c */
+bool intel_dsi_init(struct drm_device *dev);
+
+
+/* intel_dvo.c */
+void intel_dvo_init(struct drm_device *dev);
+
+
+/* intel_fb.c */
+int intel_fbdev_init(struct drm_device *dev);
+void intel_fbdev_initial_config(struct drm_device *dev);
+void intel_fbdev_fini(struct drm_device *dev);
+void intel_fbdev_set_suspend(struct drm_device *dev, int state);
+void intel_fb_output_poll_changed(struct drm_device *dev);
+void intel_fb_restore_mode(struct drm_device *dev);
+
+
+/* intel_hdmi.c */
+void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
+void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
+                               struct intel_connector *intel_connector);
+struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
+bool intel_hdmi_compute_config(struct intel_encoder *encoder,
+                               struct intel_crtc_config *pipe_config);
+
+
+/* intel_lvds.c */
+void intel_lvds_init(struct drm_device *dev);
+bool intel_is_dual_link_lvds(struct drm_device *dev);
+
+
+/* intel_modes.c */
+int intel_connector_update_modes(struct drm_connector *connector,
+                                 struct edid *edid);
+int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
+void intel_attach_force_audio_property(struct drm_connector *connector);
+void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 
-extern void intel_init_clock_gating(struct drm_device *dev);
-extern void intel_suspend_hw(struct drm_device *dev);
-extern void intel_write_eld(struct drm_encoder *encoder,
-                            struct drm_display_mode *mode);
-extern void intel_prepare_ddi(struct drm_device *dev);
-extern void hsw_fdi_link_train(struct drm_crtc *crtc);
-extern void intel_ddi_init(struct drm_device *dev, enum port port);
-
-/* For use by IVB LP watermark workaround in intel_sprite.c */
-extern void intel_update_watermarks(struct drm_device *dev);
-extern void intel_update_sprite_watermarks(struct drm_plane *plane,
-                                           struct drm_crtc *crtc,
-                                           uint32_t sprite_width, int pixel_size,
-                                           bool enabled, bool scaled);
-
-extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-                                                    unsigned int tiling_mode,
-                                                    unsigned int bpp,
-                                                    unsigned int pitch);
-
-extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
-                                     struct drm_file *file_priv);
-extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
-                                     struct drm_file *file_priv);
-
-/* Power-related functions, located in intel_pm.c */
-extern void intel_init_pm(struct drm_device *dev);
-/* FBC */
-extern bool intel_fbc_enabled(struct drm_device *dev);
-extern void intel_update_fbc(struct drm_device *dev);
-/* IPS */
-extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
-extern void intel_gpu_ips_teardown(void);
-
-/* Power well */
-extern int i915_init_power_well(struct drm_device *dev);
-extern void i915_remove_power_well(struct drm_device *dev);
-
-extern bool intel_display_power_enabled(struct drm_device *dev,
-                                        enum intel_display_power_domain domain);
-extern void intel_init_power_well(struct drm_device *dev);
-extern void intel_set_power_well(struct drm_device *dev, bool enable);
-extern void intel_enable_gt_powersave(struct drm_device *dev);
-extern void intel_disable_gt_powersave(struct drm_device *dev);
-extern void ironlake_teardown_rc6(struct drm_device *dev);
+
+/* intel_overlay.c */
+void intel_setup_overlay(struct drm_device *dev);
+void intel_cleanup_overlay(struct drm_device *dev);
+int intel_overlay_switch_off(struct intel_overlay *overlay);
+int intel_overlay_put_image(struct drm_device *dev, void *data,
+                            struct drm_file *file_priv);
+int intel_overlay_attrs(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+
+
+/* intel_panel.c */
+int intel_panel_init(struct intel_panel *panel,
+                     struct drm_display_mode *fixed_mode);
+void intel_panel_fini(struct intel_panel *panel);
+void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
+                            struct drm_display_mode *adjusted_mode);
+void intel_pch_panel_fitting(struct intel_crtc *crtc,
+                             struct intel_crtc_config *pipe_config,
+                             int fitting_mode);
+void intel_gmch_panel_fitting(struct intel_crtc *crtc,
+                              struct intel_crtc_config *pipe_config,
+                              int fitting_mode);
+void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max);
+int intel_panel_setup_backlight(struct drm_connector *connector);
+void intel_panel_enable_backlight(struct drm_device *dev, enum pipe pipe);
+void intel_panel_disable_backlight(struct drm_device *dev);
+void intel_panel_destroy_backlight(struct drm_device *dev);
+enum drm_connector_status intel_panel_detect(struct drm_device *dev);
+
+
+/* intel_pm.c */
+void intel_init_clock_gating(struct drm_device *dev);
+void intel_suspend_hw(struct drm_device *dev);
+void intel_update_watermarks(struct drm_crtc *crtc);
+void intel_update_sprite_watermarks(struct drm_plane *plane,
+                                    struct drm_crtc *crtc,
+                                    uint32_t sprite_width, int pixel_size,
+                                    bool enabled, bool scaled);
+void intel_init_pm(struct drm_device *dev);
+bool intel_fbc_enabled(struct drm_device *dev);
+void intel_update_fbc(struct drm_device *dev);
+void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
+void intel_gpu_ips_teardown(void);
+int i915_init_power_well(struct drm_device *dev);
+void i915_remove_power_well(struct drm_device *dev);
+bool intel_display_power_enabled(struct drm_device *dev,
+                                 enum intel_display_power_domain domain);
+void intel_display_power_get(struct drm_device *dev,
+                             enum intel_display_power_domain domain);
+void intel_display_power_put(struct drm_device *dev,
+                             enum intel_display_power_domain domain);
+void intel_init_power_well(struct drm_device *dev);
+void intel_set_power_well(struct drm_device *dev, bool enable);
+void intel_enable_gt_powersave(struct drm_device *dev);
+void intel_disable_gt_powersave(struct drm_device *dev);
+void ironlake_teardown_rc6(struct drm_device *dev);
 void gen6_update_ring_freq(struct drm_device *dev);
+void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
+void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
+
+
+/* intel_sdvo.c */
+bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
+
+
+/* intel_sprite.c */
+int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
+void intel_flush_display_plane(struct drm_i915_private *dev_priv,
+                               enum plane plane);
+void intel_plane_restore(struct drm_plane *plane);
+void intel_plane_disable(struct drm_plane *plane);
+int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
+                              struct drm_file *file_priv);
+int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
+                              struct drm_file *file_priv);
+
+
+/* intel_tv.c */
+void intel_tv_init(struct drm_device *dev);
 
-extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
-                                   enum pipe *pipe);
-extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
-extern void intel_ddi_pll_init(struct drm_device *dev);
-extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
-extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
-                                              enum transcoder cpu_transcoder);
-extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
-extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
-extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
-extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
-extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
-extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
-extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
-extern bool
-intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
-extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
-
-extern void intel_display_handle_reset(struct drm_device *dev);
-extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
-                                                  enum pipe pipe,
-                                                  bool enable);
-extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
-                                                 enum transcoder pch_transcoder,
-                                                 bool enable);
-
-extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
-extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
-extern void intel_edp_psr_update(struct drm_device *dev);
-extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
-                              bool switch_to_fclk, bool allow_power_down);
-extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
-extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
-                               uint32_t mask);
-extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
-extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
-                               uint32_t mask);
-extern void hsw_enable_pc8_work(struct work_struct *__work);
-extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
-extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
-extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
-extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
-extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
-extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
-extern void i915_disable_vga_mem(struct drm_device *dev);
+void gen6_rps_idle(struct drm_i915_private *dev_priv);
+void gen6_rps_boost(struct drm_i915_private *dev_priv);
 
 #endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
new file mode 100644
index 000000000000..9a2fdd2a7e34
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -0,0 +1,620 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+#include <drm/i915_drm.h>
+#include <linux/slab.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+#include "intel_dsi_cmd.h"
+
+/* the sub-encoders aka panel drivers */
+static const struct intel_dsi_device intel_dsi_devices[] = {
+};
+
+
+static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
+                           u32 mask)
+{
+        u32 tmp = vlv_cck_read(dev_priv, reg);
+        tmp &= ~mask;
+        tmp |= val;
+        vlv_cck_write(dev_priv, reg, tmp);
+}
+
+static void band_gap_wa(struct drm_i915_private *dev_priv)
+{
+        mutex_lock(&dev_priv->dpio_lock);
+
+        /* Enable bandgap fix in GOP driver */
+        vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);
+        msleep(20);
+        vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);
+        msleep(20);
+        vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);
+        msleep(20);
+        vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);
+        msleep(20);
+        vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);
+        msleep(20);
+
+        /* Turn Display Trunk on */
+        vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);
+        msleep(20);
+
+        vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);
+        msleep(20);
+
+        vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);
+        msleep(20);
+        vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);
+        msleep(20);
+        vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);
+
+        mutex_unlock(&dev_priv->dpio_lock);
+
+        /* Need huge delay, otherwise clock is not stable */
+        msleep(100);
+}
+
+static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
+{
+        return container_of(intel_attached_encoder(connector),
+                            struct intel_dsi, base);
+}
+
+static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
+{
+        return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
+}
+
+static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
+{
+        return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
+}
+
+static void intel_dsi_hot_plug(struct intel_encoder *encoder)
+{
+        DRM_DEBUG_KMS("\n");
+}
+
+static bool intel_dsi_compute_config(struct intel_encoder *encoder,
+                                     struct intel_crtc_config *config)
+{
+        struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+                                                   base);
+        struct intel_connector *intel_connector = intel_dsi->attached_connector;
+        struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+        struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
+        struct drm_display_mode *mode = &config->requested_mode;
+
+        DRM_DEBUG_KMS("\n");
+
+        if (fixed_mode)
+                intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+
+        if (intel_dsi->dev.dev_ops->mode_fixup)
+                return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
+                                                          mode, adjusted_mode);
+
+        return true;
+}
+
+static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
+{
+        DRM_DEBUG_KMS("\n");
+
+        vlv_enable_dsi_pll(encoder);
+}
+
+static void intel_dsi_pre_enable(struct intel_encoder *encoder)
+{
+        DRM_DEBUG_KMS("\n");
+}
+
+static void intel_dsi_enable(struct intel_encoder *encoder)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+        struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+        int pipe = intel_crtc->pipe;
+        u32 temp;
+
+        DRM_DEBUG_KMS("\n");
+
+        temp = I915_READ(MIPI_DEVICE_READY(pipe));
+        if ((temp & DEVICE_READY) == 0) {
+                temp &= ~ULPS_STATE_MASK;
+                I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
+        } else if (temp & ULPS_STATE_MASK) {
+                temp &= ~ULPS_STATE_MASK;
+                I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
+                /*
+                 * We need to ensure that there is a minimum of 1 ms time
+                 * available before clearing the UPLS exit state.
+                 */
+                msleep(2);
+                I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
+        }
+
+        if (is_cmd_mode(intel_dsi))
+                I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
+
+        if (is_vid_mode(intel_dsi)) {
+                msleep(20); /* XXX */
+                dpi_send_cmd(intel_dsi, TURN_ON);
+                msleep(100);
+
+                /* assert ip_tg_enable signal */
+                temp = I915_READ(MIPI_PORT_CTRL(pipe));
+                I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
+                POSTING_READ(MIPI_PORT_CTRL(pipe));
+        }
+
+        intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
+}
+
+static void intel_dsi_disable(struct intel_encoder *encoder)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+        struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+        int pipe = intel_crtc->pipe;
+        u32 temp;
+
+        DRM_DEBUG_KMS("\n");
+
+        intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
+
+        if (is_vid_mode(intel_dsi)) {
+                dpi_send_cmd(intel_dsi, SHUTDOWN);
+                msleep(10);
+
+                /* de-assert ip_tg_enable signal */
+                temp = I915_READ(MIPI_PORT_CTRL(pipe));
+                I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
+                POSTING_READ(MIPI_PORT_CTRL(pipe));
+
+                msleep(2);
+        }
+
+        temp = I915_READ(MIPI_DEVICE_READY(pipe));
+        if (temp & DEVICE_READY) {
+                temp &= ~DEVICE_READY;
+                temp &= ~ULPS_STATE_MASK;
+                I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
+        }
+}
+
+static void intel_dsi_post_disable(struct intel_encoder *encoder)
+{
+        DRM_DEBUG_KMS("\n");
+
+        vlv_disable_dsi_pll(encoder);
+}
+
+static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
+                                   enum pipe *pipe)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        u32 port, func;
+        enum pipe p;
+
+        DRM_DEBUG_KMS("\n");
+
+        /* XXX: this only works for one DSI output */
+        for (p = PIPE_A; p <= PIPE_B; p++) {
+                port = I915_READ(MIPI_PORT_CTRL(p));
+                func = I915_READ(MIPI_DSI_FUNC_PRG(p));
+
+                if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
+                        if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
+                                *pipe = p;
+                                return true;
+                        }
+                }
+        }
+
+        return false;
+}
+
+static void intel_dsi_get_config(struct intel_encoder *encoder,
+                                 struct intel_crtc_config *pipe_config)
+{
+        DRM_DEBUG_KMS("\n");
+
+        /* XXX: read flags, set to adjusted_mode */
+}
+
+static int intel_dsi_mode_valid(struct drm_connector *connector,
+                                struct drm_display_mode *mode)
+{
+        struct intel_connector *intel_connector = to_intel_connector(connector);
+        struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+        struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
+
+        DRM_DEBUG_KMS("\n");
+
+        if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
+                DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
+                return MODE_NO_DBLESCAN;
+        }
+
+        if (fixed_mode) {
+                if (mode->hdisplay > fixed_mode->hdisplay)
+                        return MODE_PANEL;
+                if (mode->vdisplay > fixed_mode->vdisplay)
+                        return MODE_PANEL;
+        }
+
+        return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
+}
+
+/* return txclkesc cycles in terms of divider and duration in us */
+static u16 txclkesc(u32 divider, unsigned int us)
+{
+        switch (divider) {
+        case ESCAPE_CLOCK_DIVIDER_1:
+        default:
+                return 20 * us;
+        case ESCAPE_CLOCK_DIVIDER_2:
+                return 10 * us;
+        case ESCAPE_CLOCK_DIVIDER_4:
+                return 5 * us;
+        }
+}
+
+/* return pixels in terms of txbyteclkhs */
+static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
+{
+        return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
+}
+
+static void set_dsi_timings(struct drm_encoder *encoder,
+                            const struct drm_display_mode *mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+        int pipe = intel_crtc->pipe;
+        unsigned int bpp = intel_crtc->config.pipe_bpp;
+        unsigned int lane_count = intel_dsi->lane_count;
+
+        u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
+
+        hactive = mode->hdisplay;
+        hfp = mode->hsync_start - mode->hdisplay;
+        hsync = mode->hsync_end - mode->hsync_start;
+        hbp = mode->htotal - mode->hsync_end;
+
+        vfp = mode->vsync_start - mode->vdisplay;
+        vsync = mode->vsync_end - mode->vsync_start;
+        vbp = mode->vtotal - mode->vsync_end;
+
+        /* horizontal values are in terms of high speed byte clock */
+        hactive = txbyteclkhs(hactive, bpp, lane_count);
+        hfp = txbyteclkhs(hfp, bpp, lane_count);
+        hsync = txbyteclkhs(hsync, bpp, lane_count);
+        hbp = txbyteclkhs(hbp, bpp, lane_count);
+
+        I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
+        I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
+
+        /* meaningful for video mode non-burst sync pulse mode only, can be zero
+         * for non-burst sync events and burst modes */
+        I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
+        I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
+
+        /* vertical values are in terms of lines */
+        I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
+        I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
+        I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
+}
+
+static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
+{
+        struct drm_encoder *encoder = &intel_encoder->base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+        struct drm_display_mode *adjusted_mode =
+                &intel_crtc->config.adjusted_mode;
+        int pipe = intel_crtc->pipe;
+        unsigned int bpp = intel_crtc->config.pipe_bpp;
+        u32 val, tmp;
+
+        DRM_DEBUG_KMS("pipe %d\n", pipe);
+
+        /* Update the DSI PLL */
+        vlv_enable_dsi_pll(intel_encoder);
+
+        /* XXX: Location of the call */
+        band_gap_wa(dev_priv);
+
+        /* escape clock divider, 20MHz, shared for A and C. device ready must be
+         * off when doing this! txclkesc? */
+        tmp = I915_READ(MIPI_CTRL(0));
+        tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+        I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
+
+        /* read request priority is per pipe */
+        tmp = I915_READ(MIPI_CTRL(pipe));
+        tmp &= ~READ_REQUEST_PRIORITY_MASK;
+        I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
+
+        /* XXX: why here, why like this? handling in irq handler?! */
+        I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
+        I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
+
+        I915_WRITE(MIPI_DPHY_PARAM(pipe),
+                   0x3c << EXIT_ZERO_COUNT_SHIFT |
+                   0x1f << TRAIL_COUNT_SHIFT |
+                   0xc5 << CLK_ZERO_COUNT_SHIFT |
+                   0x1f << PREPARE_COUNT_SHIFT);
+
+        I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
+                   adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
+                   adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
+
+        set_dsi_timings(encoder, adjusted_mode);
+
+        val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
+        if (is_cmd_mode(intel_dsi)) {
+                val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
+                val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
+        } else {
+                val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
+
+                /* XXX: cross-check bpp vs. pixel format? */
+                val |= intel_dsi->pixel_format;
+        }
+        I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
+
+        /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
+         * stop state. */
+
+        /*
+         * In burst mode, value greater than one DPI line Time in byte clock
+         * (txbyteclkhs) To timeout this timer 1+ of the above said value is
+         * recommended.
+         *
+         * In non-burst mode, Value greater than one DPI frame time in byte
+         * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
+         * is recommended.
+         *
+         * In DBI only mode, value greater than one DBI frame time in byte
+         * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
+         * is recommended.
+         */
+
+        if (is_vid_mode(intel_dsi) &&
+            intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
+                I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
+                           txbyteclkhs(adjusted_mode->htotal, bpp,
+                                       intel_dsi->lane_count) + 1);
+        } else {
+                I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
+                           txbyteclkhs(adjusted_mode->vtotal *
+                                       adjusted_mode->htotal,
+                                       bpp, intel_dsi->lane_count) + 1);
+        }
+        I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */
+        I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */
+        I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */
+
+        /* dphy stuff */
+
+        /* in terms of low power clock */
+        I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
+
+        /* recovery disables */
+        I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
+
+        /* in terms of txbyteclkhs. actual high to low switch +
+         * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
+         *
+         * XXX: write MIPI_STOP_STATE_STALL?
+         */
+        I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
+
+        /* XXX: low power clock equivalence in terms of byte clock. the number
+         * of byte clocks occupied in one low power clock. based on txbyteclkhs
+         * and txclkesc. txclkesc time / txbyteclk time * (105 +
+         * MIPI_STOP_STATE_STALL) / 105.???
+         */
+        I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
+
+        /* the bw essential for transmitting 16 long packets containing 252
+         * bytes meant for dcs write memory command is programmed in this
+         * register in terms of byte clocks. based on dsi transfer rate and the
+         * number of lanes configured the time taken to transmit 16 long packets
+         * in a dsi stream varies. */
+        I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
+
+        I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
+                   0xa << LP_HS_SSW_CNT_SHIFT |
+                   0x14 << HS_LP_PWR_SW_CNT_SHIFT);
+
+        if (is_vid_mode(intel_dsi))
+                I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
+                           intel_dsi->video_mode_format);
+}
+
+static enum drm_connector_status
+intel_dsi_detect(struct drm_connector *connector, bool force)
+{
+        struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
+        DRM_DEBUG_KMS("\n");
+        return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
+}
+
+static int intel_dsi_get_modes(struct drm_connector *connector)
+{
+        struct intel_connector *intel_connector = to_intel_connector(connector);
+        struct drm_display_mode *mode;
+
+        DRM_DEBUG_KMS("\n");
+
+        if (!intel_connector->panel.fixed_mode) {
+                DRM_DEBUG_KMS("no fixed mode\n");
+                return 0;
+        }
+
+        mode = drm_mode_duplicate(connector->dev,
+                                  intel_connector->panel.fixed_mode);
+        if (!mode) {
+                DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
+                return 0;
+        }
+
+        drm_mode_probed_add(connector, mode);
+        return 1;
+}
+
+static void intel_dsi_destroy(struct drm_connector *connector)
+{
+        struct intel_connector *intel_connector = to_intel_connector(connector);
+
+        DRM_DEBUG_KMS("\n");
+        intel_panel_fini(&intel_connector->panel);
+        drm_connector_cleanup(connector);
+        kfree(connector);
+}
+
+static const struct drm_encoder_funcs intel_dsi_funcs = {
+        .destroy = intel_encoder_destroy,
+};
+
+static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
+        .get_modes = intel_dsi_get_modes,
+        .mode_valid = intel_dsi_mode_valid,
+        .best_encoder = intel_best_encoder,
+};
+
+static const struct drm_connector_funcs intel_dsi_connector_funcs = {
+        .dpms = intel_connector_dpms,
+        .detect = intel_dsi_detect,
+        .destroy = intel_dsi_destroy,
+        .fill_modes = drm_helper_probe_single_connector_modes,
+};
+
+bool intel_dsi_init(struct drm_device *dev)
+{
+        struct intel_dsi *intel_dsi;
+        struct intel_encoder *intel_encoder;
+        struct drm_encoder *encoder;
+        struct intel_connector *intel_connector;
+        struct drm_connector *connector;
+        struct drm_display_mode *fixed_mode = NULL;
+        const struct intel_dsi_device *dsi;
+        unsigned int i;
+
+        DRM_DEBUG_KMS("\n");
+
+        intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+        if (!intel_dsi)
+                return false;
+
+        intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
+        if (!intel_connector) {
+                kfree(intel_dsi);
+                return false;
+        }
+
+        intel_encoder = &intel_dsi->base;
+        encoder = &intel_encoder->base;
+        intel_dsi->attached_connector = intel_connector;
+
+        connector = &intel_connector->base;
+
+        drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
+
+        /* XXX: very likely not all of these are needed */
+        intel_encoder->hot_plug = intel_dsi_hot_plug;
+        intel_encoder->compute_config = intel_dsi_compute_config;
+        intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
+        intel_encoder->pre_enable = intel_dsi_pre_enable;
+        intel_encoder->enable = intel_dsi_enable;
+        intel_encoder->mode_set = intel_dsi_mode_set;
+        intel_encoder->disable = intel_dsi_disable;
+        intel_encoder->post_disable = intel_dsi_post_disable;
+        intel_encoder->get_hw_state = intel_dsi_get_hw_state;
+        intel_encoder->get_config = intel_dsi_get_config;
+
+        intel_connector->get_hw_state = intel_connector_get_hw_state;
+
+        for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
+                dsi = &intel_dsi_devices[i];
+                intel_dsi->dev = *dsi;
+
+                if (dsi->dev_ops->init(&intel_dsi->dev))
+                        break;
+        }
+
+        if (i == ARRAY_SIZE(intel_dsi_devices)) {
+                DRM_DEBUG_KMS("no device found\n");
+                goto err;
+        }
+
+        intel_encoder->type = INTEL_OUTPUT_DSI;
+        intel_encoder->crtc_mask = (1 << 0); /* XXX */
+
+        intel_encoder->cloneable = false;
+        drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
+                           DRM_MODE_CONNECTOR_DSI);
+
+        drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
+
+        connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
+        connector->interlace_allowed = false;
+        connector->doublescan_allowed = false;
+
+        intel_connector_attach_encoder(intel_connector, intel_encoder);
+
+        drm_sysfs_connector_add(connector);
+
+        fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
+        if (!fixed_mode) {
+                DRM_DEBUG_KMS("no fixed mode\n");
+                goto err;
+        }
+
+        fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
+        intel_panel_init(&intel_connector->panel, fixed_mode);
+
+        return true;
+
+err:
+        drm_encoder_cleanup(&intel_encoder->base);
+        kfree(intel_dsi);
+        kfree(intel_connector);
+
+        return false;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
new file mode 100644
index 000000000000..c7765f33d524
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _INTEL_DSI_H
+#define _INTEL_DSI_H
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include "intel_drv.h"
+
+struct intel_dsi_device {
+        unsigned int panel_id;
+        const char *name;
+        int type;
+        const struct intel_dsi_dev_ops *dev_ops;
+        void *dev_priv;
+};
+
+struct intel_dsi_dev_ops {
+        bool (*init)(struct intel_dsi_device *dsi);
+
+        /* This callback must be able to assume DSI commands can be sent */
+        void (*enable)(struct intel_dsi_device *dsi);
+
+        /* This callback must be able to assume DSI commands can be sent */
+        void (*disable)(struct intel_dsi_device *dsi);
+
+        int (*mode_valid)(struct intel_dsi_device *dsi,
+                          struct drm_display_mode *mode);
+
+        bool (*mode_fixup)(struct intel_dsi_device *dsi,
+                           const struct drm_display_mode *mode,
+                           struct drm_display_mode *adjusted_mode);
+
+        void (*mode_set)(struct intel_dsi_device *dsi,
+                         struct drm_display_mode *mode,
+                         struct drm_display_mode *adjusted_mode);
+
+        enum drm_connector_status (*detect)(struct intel_dsi_device *dsi);
+
+        bool (*get_hw_state)(struct intel_dsi_device *dev);
+
+        struct drm_display_mode *(*get_modes)(struct intel_dsi_device *dsi);
+
+        void (*destroy) (struct intel_dsi_device *dsi);
+};
+
+struct intel_dsi {
+        struct intel_encoder base;
+
+        struct intel_dsi_device dev;
+
+        struct intel_connector *attached_connector;
+
+        /* if true, use HS mode, otherwise LP */
+        bool hs;
+
+        /* virtual channel */
+        int channel;
+
+        /* number of DSI lanes */
+        unsigned int lane_count;
+
+        /* video mode pixel format for MIPI_DSI_FUNC_PRG register */
+        u32 pixel_format;
+
+        /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
+        u32 video_mode_format;
+
+        /* eot for MIPI_EOT_DISABLE register */
+        u32 eot_disable;
+};
+
+static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
+{
+        return container_of(encoder, struct intel_dsi, base.base);
+}
+
+extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
+extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
+
+#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
new file mode 100644
index 000000000000..7c40f981d2c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ */
+
+#include <linux/export.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <video/mipi_display.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+#include "intel_dsi_cmd.h"
+
+/*
+ * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
+ * MIPI_COMMAND_ADDRESS registers.
+ *
+ * Apparently these registers provide a MIPI adapter level way to send (lots of)
+ * commands and data to the receiver, without having to write the commands and
+ * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
+ *
+ * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
+ * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
+ * framebuffer in command mode displays) these are just an optimization that can
+ * come later.
+ *
+ * For memory writes, these should probably be used for performance.
+ */
+
+static void print_stat(struct intel_dsi *intel_dsi)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 val;
+
+        val = I915_READ(MIPI_INTR_STAT(pipe));
+
+#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
+        DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"
+                      "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
+                      "\n", pipe, val,
+                      STAT_BIT(val, TEARING_EFFECT),
+                      STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
+                      STAT_BIT(val, GEN_READ_DATA_AVAIL),
+                      STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
+                      STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
+                      STAT_BIT(val, RX_PROT_VIOLATION),
+                      STAT_BIT(val, RX_INVALID_TX_LENGTH),
+                      STAT_BIT(val, ACK_WITH_NO_ERROR),
+                      STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
+                      STAT_BIT(val, LP_RX_TIMEOUT),
+                      STAT_BIT(val, HS_TX_TIMEOUT),
+                      STAT_BIT(val, DPI_FIFO_UNDERRUN),
+                      STAT_BIT(val, LOW_CONTENTION),
+                      STAT_BIT(val, HIGH_CONTENTION),
+                      STAT_BIT(val, TXDSI_VC_ID_INVALID),
+                      STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
+                      STAT_BIT(val, TXCHECKSUM_ERROR),
+                      STAT_BIT(val, TXECC_MULTIBIT_ERROR),
+                      STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
+                      STAT_BIT(val, TXFALSE_CONTROL_ERROR),
+                      STAT_BIT(val, RXDSI_VC_ID_INVALID),
+                      STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
+                      STAT_BIT(val, RXCHECKSUM_ERROR),
+                      STAT_BIT(val, RXECC_MULTIBIT_ERROR),
+                      STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
+                      STAT_BIT(val, RXFALSE_CONTROL_ERROR),
+                      STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
+                      STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
+                      STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
+                      STAT_BIT(val, RXEOT_SYNC_ERROR),
+                      STAT_BIT(val, RXSOT_SYNC_ERROR),
+                      STAT_BIT(val, RXSOT_ERROR));
+#undef STAT_BIT
+}
+
+enum dsi_type {
+        DSI_DCS,
+        DSI_GENERIC,
+};
+
+/* enable or disable command mode hs transmissions */
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 temp;
+        u32 mask = DBI_FIFO_EMPTY;
+
+        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
+                DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
+
+        temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
+        temp &= DBI_HS_LP_MODE_MASK;
+        I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
+
+        intel_dsi->hs = enable;
+}
+
+static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
+                             u8 data_type, u16 data)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 ctrl_reg;
+        u32 ctrl;
+        u32 mask;
+
+        DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
+                      channel, data_type, data);
+
+        if (intel_dsi->hs) {
+                ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
+                mask = HS_CTRL_FIFO_FULL;
+        } else {
+                ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
+                mask = LP_CTRL_FIFO_FULL;
+        }
+
+        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
+                DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
+                print_stat(intel_dsi);
+        }
+
+        /*
+         * Note: This function is also used for long packets, with length passed
+         * as data, since SHORT_PACKET_PARAM_SHIFT ==
+         * LONG_PACKET_WORD_COUNT_SHIFT.
+         */
+        ctrl = data << SHORT_PACKET_PARAM_SHIFT |
+                channel << VIRTUAL_CHANNEL_SHIFT |
+                data_type << DATA_TYPE_SHIFT;
+
+        I915_WRITE(ctrl_reg, ctrl);
+
+        return 0;
+}
+
+static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
+                            u8 data_type, const u8 *data, int len)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 data_reg;
+        int i, j, n;
+        u32 mask;
+
+        DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
+                      channel, data_type, len);
+
+        if (intel_dsi->hs) {
+                data_reg = MIPI_HS_GEN_DATA(pipe);
+                mask = HS_DATA_FIFO_FULL;
+        } else {
+                data_reg = MIPI_LP_GEN_DATA(pipe);
+                mask = LP_DATA_FIFO_FULL;
+        }
+
+        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
+                DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
+
+        for (i = 0; i < len; i += n) {
+                u32 val = 0;
+                n = min_t(int, len - i, 4);
+
+                for (j = 0; j < n; j++)
+                        val |= *data++ << 8 * j;
+
+                I915_WRITE(data_reg, val);
+                /* XXX: check for data fifo full, once that is set, write 4
+                 * dwords, then wait for not set, then continue. */
+        }
+
+        return dsi_vc_send_short(intel_dsi, channel, data_type, len);
+}
+
+static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
+                               int channel, const u8 *data, int len,
+                               enum dsi_type type)
+{
+        int ret;
+
+        if (len == 0) {
+                BUG_ON(type == DSI_GENERIC);
+                ret = dsi_vc_send_short(intel_dsi, channel,
+                                        MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
+                                        0);
+        } else if (len == 1) {
+                ret = dsi_vc_send_short(intel_dsi, channel,
+                                        type == DSI_GENERIC ?
+                                        MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
+                                        MIPI_DSI_DCS_SHORT_WRITE, data[0]);
+        } else if (len == 2) {
+                ret = dsi_vc_send_short(intel_dsi, channel,
+                                        type == DSI_GENERIC ?
+                                        MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
+                                        MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                                        (data[1] << 8) | data[0]);
+        } else {
+                ret = dsi_vc_send_long(intel_dsi, channel,
+                                       type == DSI_GENERIC ?
+                                       MIPI_DSI_GENERIC_LONG_WRITE :
+                                       MIPI_DSI_DCS_LONG_WRITE, data, len);
+        }
+
+        return ret;
+}
+
+int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
+                     const u8 *data, int len)
+{
+        return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
+}
+
+int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
+                         const u8 *data, int len)
+{
+        return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
+}
+
+static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
+                                        int channel, u8 dcs_cmd)
+{
+        return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
+                                 dcs_cmd);
+}
+
+static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
+                                            int channel, u8 *reqdata,
+                                            int reqlen)
+{
+        u16 data;
+        u8 data_type;
+
+        switch (reqlen) {
+        case 0:
+                data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
+                data = 0;
+                break;
+        case 1:
+                data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
+                data = reqdata[0];
+                break;
+        case 2:
+                data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
+                data = (reqdata[1] << 8) | reqdata[0];
+                break;
+        default:
+                BUG();
+        }
+
+        return dsi_vc_send_short(intel_dsi, channel, data_type, data);
+}
+
+static int dsi_read_data_return(struct intel_dsi *intel_dsi,
+                                u8 *buf, int buflen)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        int i, len = 0;
+        u32 data_reg, val;
+
+        if (intel_dsi->hs) {
+                data_reg = MIPI_HS_GEN_DATA(pipe);
+        } else {
+                data_reg = MIPI_LP_GEN_DATA(pipe);
+        }
+
+        while (len < buflen) {
+                val = I915_READ(data_reg);
+                for (i = 0; i < 4 && len < buflen; i++, len++)
+                        buf[len] = val >> 8 * i;
+        }
+
+        return len;
+}
+
+int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
+                    u8 *buf, int buflen)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 mask;
+        int ret;
+
+        /*
+         * XXX: should issue multiple read requests and reads if request is
+         * longer than MIPI_MAX_RETURN_PKT_SIZE
+         */
+
+        I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
+
+        ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
+        if (ret)
+                return ret;
+
+        mask = GEN_READ_DATA_AVAIL;
+        if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
+                DRM_ERROR("Timeout waiting for read data.\n");
+
+        ret = dsi_read_data_return(intel_dsi, buf, buflen);
+        if (ret < 0)
+                return ret;
+
+        if (ret != buflen)
+                return -EIO;
+
+        return 0;
+}
+
+int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
+                        u8 *reqdata, int reqlen, u8 *buf, int buflen)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 mask;
+        int ret;
+
+        /*
+         * XXX: should issue multiple read requests and reads if request is
+         * longer than MIPI_MAX_RETURN_PKT_SIZE
+         */
+
+        I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
+
+        ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
+                                               reqlen);
+        if (ret)
+                return ret;
+
+        mask = GEN_READ_DATA_AVAIL;
+        if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
+                DRM_ERROR("Timeout waiting for read data.\n");
+
+        ret = dsi_read_data_return(intel_dsi, buf, buflen);
+        if (ret < 0)
+                return ret;
+
+        if (ret != buflen)
+                return -EIO;
+
+        return 0;
+}
+
+/*
+ * send a video mode command
+ *
+ * XXX: commands with data in MIPI_DPI_DATA?
+ */
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)
+{
+        struct drm_encoder *encoder = &intel_dsi->base.base;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        enum pipe pipe = intel_crtc->pipe;
+        u32 mask;
+
+        /* XXX: pipe, hs */
+        if (intel_dsi->hs)
+                cmd &= ~DPI_LP_MODE;
+        else
+                cmd |= DPI_LP_MODE;
+
+        /* DPI virtual channel?! */
+
+        mask = DPI_FIFO_EMPTY;
+        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
+                DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
+
+        /* clear bit */
+        I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
+
+        /* XXX: old code skips write if control unchanged */
+        if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
+                DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+
+        I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
+
+        mask = SPL_PKT_SENT_INTERRUPT;
+        if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))
+                DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
+
+        return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
new file mode 100644
index 000000000000..54c8a234a2e0
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Jani Nikula <jani.nikula@intel.com>
+ */
+
+#ifndef _INTEL_DSI_DSI_H
+#define _INTEL_DSI_DSI_H
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <video/mipi_display.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+#include "intel_dsi.h"
+
+void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
+
+int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
+                     const u8 *data, int len);
+
+int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
+                         const u8 *data, int len);
+
+int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
+                    u8 *buf, int buflen);
+
+int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
+                        u8 *reqdata, int reqlen, u8 *buf, int buflen);
+
+int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd);
+
+/* XXX: questionable write helpers */
+static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
+                                     int channel, u8 dcs_cmd)
+{
+        return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
+}
+
+static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
+                                     int channel, u8 dcs_cmd, u8 param)
+{
+        u8 buf[2] = { dcs_cmd, param };
+        return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
+}
+
+static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
+                                         int channel)
+{
+        return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
+}
+
+static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
+                                         int channel, u8 param)
+{
+        return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
+}
+
+static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
+                                         int channel, u8 param1, u8 param2)
+{
+        u8 buf[2] = { param1, param2 };
+        return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
+}
+
+/* XXX: questionable read helpers */
+static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
+                                        int channel, u8 *buf, int buflen)
+{
+        return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
+}
+
+static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
+                                        int channel, u8 param, u8 *buf,
+                                        int buflen)
+{
+        return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
+}
+
+static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
+                                        int channel, u8 param1, u8 param2,
+                                        u8 *buf, int buflen)
+{
+        u8 req[2] = { param1, param2 };
+
+        return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
+}
+
+
+#endif /* _INTEL_DSI_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
new file mode 100644
index 000000000000..44279b2ade88
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Shobhit Kumar <shobhit.kumar@intel.com>
+ *      Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include "intel_drv.h"
+#include "i915_drv.h"
+#include "intel_dsi.h"
+
+#define DSI_HSS_PACKET_SIZE             4
+#define DSI_HSE_PACKET_SIZE             4
+#define DSI_HSA_PACKET_EXTRA_SIZE       6
+#define DSI_HBP_PACKET_EXTRA_SIZE       6
+#define DSI_HACTIVE_PACKET_EXTRA_SIZE   6
+#define DSI_HFP_PACKET_EXTRA_SIZE       6
+#define DSI_EOTP_PACKET_SIZE            4
+
+struct dsi_mnp {
+        u32 dsi_pll_ctrl;
+        u32 dsi_pll_div;
+};
+
+static const u32 lfsr_converts[] = {
+        426, 469, 234, 373, 442, 221, 110, 311, 411,            /* 62 - 70 */
+        461, 486, 243, 377, 188, 350, 175, 343, 427, 213,       /* 71 - 80 */
+        106, 53, 282, 397, 354, 227, 113, 56, 284, 142,         /* 81 - 90 */
+        71, 35                                                  /* 91 - 92 */
+};
+
+static u32 dsi_rr_formula(const struct drm_display_mode *mode,
+                          int pixel_format, int video_mode_format,
+                          int lane_count, bool eotp)
+{
+        u32 bpp;
+        u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
+        u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
+        u32 bytes_per_line, bytes_per_frame;
+        u32 num_frames;
+        u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
+        u32 dsi_bit_clock_hz;
+        u32 dsi_clk;
+
+        switch (pixel_format) {
+        default:
+        case VID_MODE_FORMAT_RGB888:
+        case VID_MODE_FORMAT_RGB666_LOOSE:
+                bpp = 24;
+                break;
+        case VID_MODE_FORMAT_RGB666:
+                bpp = 18;
+                break;
+        case VID_MODE_FORMAT_RGB565:
+                bpp = 16;
+                break;
+        }
+
+        hactive = mode->hdisplay;
+        vactive = mode->vdisplay;
+        hfp = mode->hsync_start - mode->hdisplay;
+        hsync = mode->hsync_end - mode->hsync_start;
+        hbp = mode->htotal - mode->hsync_end;
+
+        vfp = mode->vsync_start - mode->vdisplay;
+        vsync = mode->vsync_end - mode->vsync_start;
+        vbp = mode->vtotal - mode->vsync_end;
+
+        hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
+        hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
+        hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
+        hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);
+
+        bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
+                DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
+                hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
+                hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
+                hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;
+
+        /*
+         * XXX: Need to accurately calculate LP to HS transition timeout and add
+         * it to bytes_per_line/bytes_per_frame.
+         */
+
+        if (eotp && video_mode_format == VIDEO_MODE_BURST)
+                bytes_per_line += DSI_EOTP_PACKET_SIZE;
+
+        bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
+                vactive * bytes_per_line + vfp * bytes_per_line;
+
+        if (eotp &&
+            (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ||
+             video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
+                bytes_per_frame += DSI_EOTP_PACKET_SIZE;
+
+        num_frames = drm_mode_vrefresh(mode);
+        bytes_per_x_frames = num_frames * bytes_per_frame;
+
+        bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
+
+        /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
+        dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
+        dsi_clk = dsi_bit_clock_hz / (1000 * 1000);
+
+        if (eotp && video_mode_format == VIDEO_MODE_BURST)
+                dsi_clk *= 2;
+
+        return dsi_clk;
+}
+
+#ifdef MNP_FROM_TABLE
+
+struct dsi_clock_table {
+        u32 freq;
+        u8 m;
+        u8 p;
+};
+
+static const struct dsi_clock_table dsi_clk_tbl[] = {
+        {300, 72, 6}, {313, 75, 6}, {323, 78, 6}, {333, 80, 6},
+        {343, 82, 6}, {353, 85, 6}, {363, 87, 6}, {373, 90, 6},
+        {383, 92, 6}, {390, 78, 5}, {393, 79, 5}, {400, 80, 5},
+        {401, 80, 5}, {402, 80, 5}, {403, 81, 5}, {404, 81, 5},
+        {405, 81, 5}, {406, 81, 5}, {407, 81, 5}, {408, 82, 5},
+        {409, 82, 5}, {410, 82, 5}, {411, 82, 5}, {412, 82, 5},
+        {413, 83, 5}, {414, 83, 5}, {415, 83, 5}, {416, 83, 5},
+        {417, 83, 5}, {418, 84, 5}, {419, 84, 5}, {420, 84, 5},
+        {430, 86, 5}, {440, 88, 5}, {450, 90, 5}, {460, 92, 5},
+        {470, 75, 4}, {480, 77, 4}, {490, 78, 4}, {500, 80, 4},
+        {510, 82, 4}, {520, 83, 4}, {530, 85, 4}, {540, 86, 4},
+        {550, 88, 4}, {560, 90, 4}, {570, 91, 4}, {580, 70, 3},
+        {590, 71, 3}, {600, 72, 3}, {610, 73, 3}, {620, 74, 3},
+        {630, 76, 3}, {640, 77, 3}, {650, 78, 3}, {660, 79, 3},
+        {670, 80, 3}, {680, 82, 3}, {690, 83, 3}, {700, 84, 3},
+        {710, 85, 3}, {720, 86, 3}, {730, 88, 3}, {740, 89, 3},
+        {750, 90, 3}, {760, 91, 3}, {770, 92, 3}, {780, 62, 2},
+        {790, 63, 2}, {800, 64, 2}, {880, 70, 2}, {900, 72, 2},
+        {1000, 80, 2},          /* dsi clock frequency in Mhz*/
+};
+
+static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+{
+        unsigned int i;
+        u8 m;
+        u8 n;
+        u8 p;
+        u32 m_seed;
+
+        if (dsi_clk < 300 || dsi_clk > 1000)
+                return -ECHRNG;
+
+        for (i = 0; i <= ARRAY_SIZE(dsi_clk_tbl); i++) {
+                if (dsi_clk_tbl[i].freq > dsi_clk)
+                        break;
+        }
+
+        m = dsi_clk_tbl[i].m;
+        p = dsi_clk_tbl[i].p;
+        m_seed = lfsr_converts[m - 62];
+        n = 1;
+        dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + p - 2);
+        dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
+                m_seed << DSI_PLL_M1_DIV_SHIFT;
+
+        return 0;
+}
+
+#else
+
+static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+{
+        u32 m, n, p;
+        u32 ref_clk;
+        u32 error;
+        u32 tmp_error;
+        u32 target_dsi_clk;
+        u32 calc_dsi_clk;
+        u32 calc_m;
+        u32 calc_p;
+        u32 m_seed;
+
+        if (dsi_clk < 300 || dsi_clk > 1150) {
+                DRM_ERROR("DSI CLK Out of Range\n");
+                return -ECHRNG;
+        }
+
+        ref_clk = 25000;
+        target_dsi_clk = dsi_clk * 1000;
+        error = 0xFFFFFFFF;
+        calc_m = 0;
+        calc_p = 0;
+
+        for (m = 62; m <= 92; m++) {
+                for (p = 2; p <= 6; p++) {
+
+                        calc_dsi_clk = (m * ref_clk) / p;
+                        if (calc_dsi_clk >= target_dsi_clk) {
+                                tmp_error = calc_dsi_clk - target_dsi_clk;
+                                if (tmp_error < error) {
+                                        error = tmp_error;
+                                        calc_m = m;
+                                        calc_p = p;
+                                }
+                        }
+                }
+        }
+
+        m_seed = lfsr_converts[calc_m - 62];
+        n = 1;
+        dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
+        dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
+                m_seed << DSI_PLL_M1_DIV_SHIFT;
+
+        return 0;
+}
+
+#endif
+
+/*
+ * XXX: The muxing and gating is hard coded for now. Need to add support for
+ * sharing PLLs with two DSI outputs.
+ */
+static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+        const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+        struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+        int ret;
+        struct dsi_mnp dsi_mnp;
+        u32 dsi_clk;
+
+        dsi_clk = dsi_rr_formula(mode, intel_dsi->pixel_format,
+                                 intel_dsi->video_mode_format,
+                                 intel_dsi->lane_count, !intel_dsi->eot_disable);
+
+        ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
+        if (ret) {
+                DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
+                return;
+        }
+
+        dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
+
+        DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
+                      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
+
+        vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
+        vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
+        vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
+}
+
+void vlv_enable_dsi_pll(struct intel_encoder *encoder)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        u32 tmp;
+
+        DRM_DEBUG_KMS("\n");
+
+        mutex_lock(&dev_priv->dpio_lock);
+
+        vlv_configure_dsi_pll(encoder);
+
+        /* wait at least 0.5 us after ungating before enabling VCO */
+        usleep_range(1, 10);
+
+        tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+        tmp |= DSI_PLL_VCO_EN;
+        vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
+
+        mutex_unlock(&dev_priv->dpio_lock);
+
+        if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
+                DRM_ERROR("DSI PLL lock failed\n");
+                return;
+        }
+
+        DRM_DEBUG_KMS("DSI PLL locked\n");
+}
+
+void vlv_disable_dsi_pll(struct intel_encoder *encoder)
+{
+        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        u32 tmp;
+
+        DRM_DEBUG_KMS("\n");
+
+        mutex_lock(&dev_priv->dpio_lock);
+
+        tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
+        tmp &= ~DSI_PLL_VCO_EN;
+        tmp |= DSI_PLL_LDO_GATE;
+        vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
+
+        mutex_unlock(&dev_priv->dpio_lock);
+}
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 7fa7df546c1e..1b64145c669a 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -153,6 +153,8 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
                 flags |= DRM_MODE_FLAG_NVSYNC;
 
         pipe_config->adjusted_mode.flags |= flags;
+
+        pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static void intel_disable_dvo(struct intel_encoder *encoder)
@@ -267,11 +269,6 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder,
                 drm_mode_set_crtcinfo(adjusted_mode, 0);
         }
 
-        if (intel_dvo->dev.dev_ops->mode_fixup)
-                return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev,
-                                                          &pipe_config->requested_mode,
-                                                          adjusted_mode);
-
         return true;
 }
 
@@ -370,7 +367,6 @@ static int intel_dvo_get_modes(struct drm_connector *connector)
 
 static void intel_dvo_destroy(struct drm_connector *connector)
 {
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(connector);
 }
@@ -451,11 +447,11 @@ void intel_dvo_init(struct drm_device *dev)
         int i;
         int encoder_type = DRM_MODE_ENCODER_NONE;
 
-        intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL);
+        intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
         if (!intel_dvo)
                 return;
 
-        intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
+        intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
         if (!intel_connector) {
                 kfree(intel_dvo);
                 return;
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index bc2100007b21..d883b77b1b78 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -184,6 +184,27 @@ out:
         return ret;
 }
 
+/** Sets the color ramps on behalf of RandR */
+static void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
+                                    u16 blue, int regno)
+{
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+        intel_crtc->lut_r[regno] = red >> 8;
+        intel_crtc->lut_g[regno] = green >> 8;
+        intel_crtc->lut_b[regno] = blue >> 8;
+}
+
+static void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+                                    u16 *blue, int regno)
+{
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+        *red = intel_crtc->lut_r[regno] << 8;
+        *green = intel_crtc->lut_g[regno] << 8;
+        *blue = intel_crtc->lut_b[regno] << 8;
+}
+
 static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
         .gamma_set = intel_crtc_fb_gamma_set,
         .gamma_get = intel_crtc_fb_gamma_get,
@@ -216,7 +237,7 @@ int intel_fbdev_init(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int ret;
 
-        ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
+        ifbdev = kzalloc(sizeof(*ifbdev), GFP_KERNEL);
         if (!ifbdev)
                 return -ENOMEM;
 
@@ -225,7 +246,7 @@ int intel_fbdev_init(struct drm_device *dev)
 
         ret = drm_fb_helper_init(dev, &ifbdev->helper,
                                  INTEL_INFO(dev)->num_pipes,
-                                 INTELFB_CONN_LIMIT);
+                                 4);
         if (ret) {
                 kfree(ifbdev);
                 return ret;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4148cc85bf7f..4f4d346db8f0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -713,6 +713,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
         u32 tmp, flags = 0;
+        int dotclock;
 
         tmp = I915_READ(intel_hdmi->hdmi_reg);
 
@@ -727,6 +728,16 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
                 flags |= DRM_MODE_FLAG_NVSYNC;
 
         pipe_config->adjusted_mode.flags |= flags;
+
+        if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
+                dotclock = pipe_config->port_clock * 2 / 3;
+        else
+                dotclock = pipe_config->port_clock;
+
+        if (HAS_PCH_SPLIT(dev_priv->dev))
+                ironlake_check_encoder_dotclock(pipe_config, dotclock);
+
+        pipe_config->adjusted_mode.crtc_clock = dotclock;
 }
 
 static void intel_enable_hdmi(struct intel_encoder *encoder)
@@ -862,7 +873,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
         struct drm_device *dev = encoder->base.dev;
         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
-        int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
+        int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
         int portclock_limit = hdmi_portclock_limit(intel_hdmi);
         int desired_bpp;
 
@@ -904,7 +915,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
                 pipe_config->pipe_bpp = desired_bpp;
         }
 
-        if (adjusted_mode->clock > portclock_limit) {
+        if (adjusted_mode->crtc_clock > portclock_limit) {
                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
                 return false;
         }
@@ -1079,35 +1090,35 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
 
         /* Enable clock channels for this port */
         mutex_lock(&dev_priv->dpio_lock);
-        val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
+        val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
         val = 0;
         if (pipe)
                 val |= (1<<21);
         else
                 val &= ~(1<<21);
         val |= 0x001000c4;
-        vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
 
         /* HDMI 1.0V-2dB */
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port),
                          0x2b245f5f);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
                          0x5578b83a);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port),
                          0x0c782040);
-        vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port),
                          0x2b247878);
-        vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
                          0x00002000);
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
                          DPIO_TX_OCALINIT_EN);
 
         /* Program lane clock */
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port),
                          0x00760018);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port),
                          0x00400888);
         mutex_unlock(&dev_priv->dpio_lock);
 
@@ -1121,30 +1132,33 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
         struct drm_device *dev = encoder->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(encoder->base.crtc);
         int port = vlv_dport_to_channel(dport);
+        int pipe = intel_crtc->pipe;
 
         if (!IS_VALLEYVIEW(dev))
                 return;
 
         /* Program Tx lane resets to default */
         mutex_lock(&dev_priv->dpio_lock);
-        vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
                          DPIO_PCS_TX_LANE2_RESET |
                          DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
                          DPIO_PCS_CLK_SOFT_RESET);
 
         /* Fix up inter-pair skew failure */
-        vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
-        vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
-        vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
 
-        vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
                          0x00002000);
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
                          DPIO_TX_OCALINIT_EN);
         mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -1153,18 +1167,20 @@ static void intel_hdmi_post_disable(struct intel_encoder *encoder)
 {
         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(encoder->base.crtc);
         int port = vlv_dport_to_channel(dport);
+        int pipe = intel_crtc->pipe;
 
         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
         mutex_lock(&dev_priv->dpio_lock);
-        vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060);
         mutex_unlock(&dev_priv->dpio_lock);
 }
 
 static void intel_hdmi_destroy(struct drm_connector *connector)
 {
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(connector);
 }
@@ -1211,6 +1227,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 
         connector->interlace_allowed = 1;
         connector->doublescan_allowed = 0;
+        connector->stereo_allowed = 1;
 
         switch (port) {
         case PORT_B:
@@ -1275,11 +1292,11 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
         struct intel_encoder *intel_encoder;
         struct intel_connector *intel_connector;
 
-        intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
+        intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
         if (!intel_dig_port)
                 return;
 
-        intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
+        intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
         if (!intel_connector) {
                 kfree(intel_dig_port);
                 return;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d1c1e0f7f262..2ca17b14b6c1 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -34,6 +34,11 @@
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 
+enum disp_clk {
+        CDCLK,
+        CZCLK
+};
+
 struct gmbus_port {
         const char *name;
         int reg;
@@ -58,10 +63,69 @@ to_intel_gmbus(struct i2c_adapter *i2c)
         return container_of(i2c, struct intel_gmbus, adapter);
 }
 
+static int get_disp_clk_div(struct drm_i915_private *dev_priv,
+                            enum disp_clk clk)
+{
+        u32 reg_val;
+        int clk_ratio;
+
+        reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
+
+        if (clk == CDCLK)
+                clk_ratio =
+                        ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
+        else
+                clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
+
+        return clk_ratio;
+}
+
+static void gmbus_set_freq(struct drm_i915_private *dev_priv)
+{
+        int vco_freq[] = { 800, 1600, 2000, 2400 };
+        int gmbus_freq = 0, cdclk_div, hpll_freq;
+
+        BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
+
+        /* Skip setting the gmbus freq if BIOS has already programmed it */
+        if (I915_READ(GMBUSFREQ_VLV) != 0xA0)
+                return;
+
+        /* Obtain SKU information */
+        mutex_lock(&dev_priv->dpio_lock);
+        hpll_freq =
+                vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK;
+        mutex_unlock(&dev_priv->dpio_lock);
+
+        /* Get the CDCLK divide ratio */
+        cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
+
+        /*
+         * Program the gmbus_freq based on the cdclk frequency.
+         * BSpec erroneously claims we should aim for 4MHz, but
+         * in fact 1MHz is the correct frequency.
+         */
+        if (cdclk_div)
+                gmbus_freq = (vco_freq[hpll_freq] << 1) / cdclk_div;
+
+        if (WARN_ON(gmbus_freq == 0))
+                return;
+
+        I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
+}
+
 void
 intel_i2c_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
+
+        /*
+         * In BIOS-less system, program the correct gmbus frequency
+         * before reading edid.
+         */
+        if (IS_VALLEYVIEW(dev))
+                gmbus_set_freq(dev_priv);
+
         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
 }
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 831a5c021c4b..ae0c843dd263 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -92,6 +92,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
         struct drm_device *dev = encoder->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 lvds_reg, tmp, flags = 0;
+        int dotclock;
 
         if (HAS_PCH_SPLIT(dev))
                 lvds_reg = PCH_LVDS;
@@ -116,6 +117,13 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 
                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
         }
+
+        dotclock = pipe_config->port_clock;
+
+        if (HAS_PCH_SPLIT(dev_priv->dev))
+                ironlake_check_encoder_dotclock(pipe_config, dotclock);
+
+        pipe_config->adjusted_mode.crtc_clock = dotclock;
 }
 
 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
@@ -466,7 +474,6 @@ static void intel_lvds_destroy(struct drm_connector *connector)
 
         intel_panel_fini(&lvds_connector->base.panel);
 
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(connector);
 }
@@ -786,7 +793,8 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev,
                 return true;
 
         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
-                struct child_device_config *child = dev_priv->vbt.child_dev + i;
+                union child_device_config *uchild = dev_priv->vbt.child_dev + i;
+                struct old_child_dev_config *child = &uchild->old;
 
                 /* If the device type is not LFP, continue.
                  * We have to check both the new identifiers as well as the
@@ -940,11 +948,11 @@ void intel_lvds_init(struct drm_device *dev)
                 }
         }
 
-        lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
+        lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
         if (!lvds_encoder)
                 return;
 
-        lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
+        lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
         if (!lvds_connector) {
                 kfree(lvds_encoder);
                 return;
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 119771ff46ab..2acf5cae20e4 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -36,8 +36,11 @@
 #include "i915_drv.h"
 #include "intel_drv.h"
 
-#define PCI_ASLE 0xe4
-#define PCI_ASLS 0xfc
+#define PCI_ASLE                0xe4
+#define PCI_ASLS                0xfc
+#define PCI_SWSCI               0xe8
+#define PCI_SWSCI_SCISEL        (1 << 15)
+#define PCI_SWSCI_GSSCIE        (1 << 0)
 
 #define OPREGION_HEADER_OFFSET 0
 #define OPREGION_ACPI_OFFSET   0x100
@@ -107,25 +110,38 @@ struct opregion_asle {
         u32 epfm;       /* enabled panel fitting modes */
         u8 plut[74];    /* panel LUT and identifier */
         u32 pfmb;       /* PWM freq and min brightness */
-        u8 rsvd[102];
+        u32 cddv;       /* color correction default values */
+        u32 pcft;       /* power conservation features */
+        u32 srot;       /* supported rotation angles */
+        u32 iuer;       /* IUER events */
+        u8 rsvd[86];
 } __attribute__((packed));
 
 /* Driver readiness indicator */
 #define ASLE_ARDY_READY         (1 << 0)
 #define ASLE_ARDY_NOT_READY     (0 << 0)
 
-/* ASLE irq request bits */
-#define ASLE_SET_ALS_ILLUM     (1 << 0)
-#define ASLE_SET_BACKLIGHT     (1 << 1)
-#define ASLE_SET_PFIT          (1 << 2)
-#define ASLE_SET_PWM_FREQ      (1 << 3)
-#define ASLE_REQ_MSK           0xf
-
-/* response bits of ASLE irq request */
-#define ASLE_ALS_ILLUM_FAILED   (1<<10)
-#define ASLE_BACKLIGHT_FAILED   (1<<12)
-#define ASLE_PFIT_FAILED        (1<<14)
-#define ASLE_PWM_FREQ_FAILED    (1<<16)
+/* ASLE Interrupt Command (ASLC) bits */
+#define ASLC_SET_ALS_ILLUM              (1 << 0)
+#define ASLC_SET_BACKLIGHT              (1 << 1)
+#define ASLC_SET_PFIT                   (1 << 2)
+#define ASLC_SET_PWM_FREQ               (1 << 3)
+#define ASLC_SUPPORTED_ROTATION_ANGLES  (1 << 4)
+#define ASLC_BUTTON_ARRAY               (1 << 5)
+#define ASLC_CONVERTIBLE_INDICATOR      (1 << 6)
+#define ASLC_DOCKING_INDICATOR          (1 << 7)
+#define ASLC_ISCT_STATE_CHANGE          (1 << 8)
+#define ASLC_REQ_MSK                    0x1ff
+/* response bits */
+#define ASLC_ALS_ILLUM_FAILED           (1 << 10)
+#define ASLC_BACKLIGHT_FAILED           (1 << 12)
+#define ASLC_PFIT_FAILED                (1 << 14)
+#define ASLC_PWM_FREQ_FAILED            (1 << 16)
+#define ASLC_ROTATION_ANGLES_FAILED     (1 << 18)
+#define ASLC_BUTTON_ARRAY_FAILED        (1 << 20)
+#define ASLC_CONVERTIBLE_FAILED         (1 << 22)
+#define ASLC_DOCKING_FAILED             (1 << 24)
+#define ASLC_ISCT_STATE_FAILED          (1 << 26)
 
 /* Technology enabled indicator */
 #define ASLE_TCHE_ALS_EN        (1 << 0)
@@ -151,6 +167,60 @@ struct opregion_asle {
 
 #define ASLE_CBLV_VALID         (1<<31)
 
+/* IUER */
+#define ASLE_IUER_DOCKING               (1 << 7)
+#define ASLE_IUER_CONVERTIBLE           (1 << 6)
+#define ASLE_IUER_ROTATION_LOCK_BTN     (1 << 4)
+#define ASLE_IUER_VOLUME_DOWN_BTN       (1 << 3)
+#define ASLE_IUER_VOLUME_UP_BTN         (1 << 2)
+#define ASLE_IUER_WINDOWS_BTN           (1 << 1)
+#define ASLE_IUER_POWER_BTN             (1 << 0)
+
+/* Software System Control Interrupt (SWSCI) */
+#define SWSCI_SCIC_INDICATOR            (1 << 0)
+#define SWSCI_SCIC_MAIN_FUNCTION_SHIFT  1
+#define SWSCI_SCIC_MAIN_FUNCTION_MASK   (0xf << 1)
+#define SWSCI_SCIC_SUB_FUNCTION_SHIFT   8
+#define SWSCI_SCIC_SUB_FUNCTION_MASK    (0xff << 8)
+#define SWSCI_SCIC_EXIT_PARAMETER_SHIFT 8
+#define SWSCI_SCIC_EXIT_PARAMETER_MASK  (0xff << 8)
+#define SWSCI_SCIC_EXIT_STATUS_SHIFT    5
+#define SWSCI_SCIC_EXIT_STATUS_MASK     (7 << 5)
+#define SWSCI_SCIC_EXIT_STATUS_SUCCESS  1
+
+#define SWSCI_FUNCTION_CODE(main, sub) \
+        ((main) << SWSCI_SCIC_MAIN_FUNCTION_SHIFT | \
+         (sub) << SWSCI_SCIC_SUB_FUNCTION_SHIFT)
+
+/* SWSCI: Get BIOS Data (GBDA) */
+#define SWSCI_GBDA                      4
+#define SWSCI_GBDA_SUPPORTED_CALLS      SWSCI_FUNCTION_CODE(SWSCI_GBDA, 0)
+#define SWSCI_GBDA_REQUESTED_CALLBACKS  SWSCI_FUNCTION_CODE(SWSCI_GBDA, 1)
+#define SWSCI_GBDA_BOOT_DISPLAY_PREF    SWSCI_FUNCTION_CODE(SWSCI_GBDA, 4)
+#define SWSCI_GBDA_PANEL_DETAILS        SWSCI_FUNCTION_CODE(SWSCI_GBDA, 5)
+#define SWSCI_GBDA_TV_STANDARD          SWSCI_FUNCTION_CODE(SWSCI_GBDA, 6)
+#define SWSCI_GBDA_INTERNAL_GRAPHICS    SWSCI_FUNCTION_CODE(SWSCI_GBDA, 7)
+#define SWSCI_GBDA_SPREAD_SPECTRUM      SWSCI_FUNCTION_CODE(SWSCI_GBDA, 10)
+
+/* SWSCI: System BIOS Callbacks (SBCB) */
+#define SWSCI_SBCB                      6
+#define SWSCI_SBCB_SUPPORTED_CALLBACKS  SWSCI_FUNCTION_CODE(SWSCI_SBCB, 0)
+#define SWSCI_SBCB_INIT_COMPLETION      SWSCI_FUNCTION_CODE(SWSCI_SBCB, 1)
+#define SWSCI_SBCB_PRE_HIRES_SET_MODE   SWSCI_FUNCTION_CODE(SWSCI_SBCB, 3)
+#define SWSCI_SBCB_POST_HIRES_SET_MODE  SWSCI_FUNCTION_CODE(SWSCI_SBCB, 4)
+#define SWSCI_SBCB_DISPLAY_SWITCH       SWSCI_FUNCTION_CODE(SWSCI_SBCB, 5)
+#define SWSCI_SBCB_SET_TV_FORMAT        SWSCI_FUNCTION_CODE(SWSCI_SBCB, 6)
+#define SWSCI_SBCB_ADAPTER_POWER_STATE  SWSCI_FUNCTION_CODE(SWSCI_SBCB, 7)
+#define SWSCI_SBCB_DISPLAY_POWER_STATE  SWSCI_FUNCTION_CODE(SWSCI_SBCB, 8)
+#define SWSCI_SBCB_SET_BOOT_DISPLAY     SWSCI_FUNCTION_CODE(SWSCI_SBCB, 9)
+#define SWSCI_SBCB_SET_PANEL_DETAILS    SWSCI_FUNCTION_CODE(SWSCI_SBCB, 10)
+#define SWSCI_SBCB_SET_INTERNAL_GFX     SWSCI_FUNCTION_CODE(SWSCI_SBCB, 11)
+#define SWSCI_SBCB_POST_HIRES_TO_DOS_FS SWSCI_FUNCTION_CODE(SWSCI_SBCB, 16)
+#define SWSCI_SBCB_SUSPEND_RESUME       SWSCI_FUNCTION_CODE(SWSCI_SBCB, 17)
+#define SWSCI_SBCB_SET_SPREAD_SPECTRUM  SWSCI_FUNCTION_CODE(SWSCI_SBCB, 18)
+#define SWSCI_SBCB_POST_VBE_PM          SWSCI_FUNCTION_CODE(SWSCI_SBCB, 19)
+#define SWSCI_SBCB_ENABLE_DISABLE_AUDIO SWSCI_FUNCTION_CODE(SWSCI_SBCB, 21)
+
 #define ACPI_OTHER_OUTPUT (0<<8)
 #define ACPI_VGA_OUTPUT (1<<8)
 #define ACPI_TV_OUTPUT (2<<8)
@@ -158,6 +228,169 @@ struct opregion_asle {
 #define ACPI_LVDS_OUTPUT (4<<8)
 
 #ifdef CONFIG_ACPI
+static int swsci(struct drm_device *dev, u32 function, u32 parm, u32 *parm_out)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct opregion_swsci __iomem *swsci = dev_priv->opregion.swsci;
+        u32 main_function, sub_function, scic;
+        u16 pci_swsci;
+        u32 dslp;
+
+        if (!swsci)
+                return -ENODEV;
+
+        main_function = (function & SWSCI_SCIC_MAIN_FUNCTION_MASK) >>
+                SWSCI_SCIC_MAIN_FUNCTION_SHIFT;
+        sub_function = (function & SWSCI_SCIC_SUB_FUNCTION_MASK) >>
+                SWSCI_SCIC_SUB_FUNCTION_SHIFT;
+
+        /* Check if we can call the function. See swsci_setup for details. */
+        if (main_function == SWSCI_SBCB) {
+                if ((dev_priv->opregion.swsci_sbcb_sub_functions &
+                     (1 << sub_function)) == 0)
+                        return -EINVAL;
+        } else if (main_function == SWSCI_GBDA) {
+                if ((dev_priv->opregion.swsci_gbda_sub_functions &
+                     (1 << sub_function)) == 0)
+                        return -EINVAL;
+        }
+
+        /* Driver sleep timeout in ms. */
+        dslp = ioread32(&swsci->dslp);
+        if (!dslp) {
+                dslp = 2;
+        } else if (dslp > 500) {
+                /* Hey bios, trust must be earned. */
+                WARN_ONCE(1, "excessive driver sleep timeout (DSPL) %u\n", dslp);
+                dslp = 500;
+        }
+
+        /* The spec tells us to do this, but we are the only user... */
+        scic = ioread32(&swsci->scic);
+        if (scic & SWSCI_SCIC_INDICATOR) {
+                DRM_DEBUG_DRIVER("SWSCI request already in progress\n");
+                return -EBUSY;
+        }
+
+        scic = function | SWSCI_SCIC_INDICATOR;
+
+        iowrite32(parm, &swsci->parm);
+        iowrite32(scic, &swsci->scic);
+
+        /* Ensure SCI event is selected and event trigger is cleared. */
+        pci_read_config_word(dev->pdev, PCI_SWSCI, &pci_swsci);
+        if (!(pci_swsci & PCI_SWSCI_SCISEL) || (pci_swsci & PCI_SWSCI_GSSCIE)) {
+                pci_swsci |= PCI_SWSCI_SCISEL;
+                pci_swsci &= ~PCI_SWSCI_GSSCIE;
+                pci_write_config_word(dev->pdev, PCI_SWSCI, pci_swsci);
+        }
+
+        /* Use event trigger to tell bios to check the mail. */
+        pci_swsci |= PCI_SWSCI_GSSCIE;
+        pci_write_config_word(dev->pdev, PCI_SWSCI, pci_swsci);
+
+        /* Poll for the result. */
+#define C (((scic = ioread32(&swsci->scic)) & SWSCI_SCIC_INDICATOR) == 0)
+        if (wait_for(C, dslp)) {
+                DRM_DEBUG_DRIVER("SWSCI request timed out\n");
+                return -ETIMEDOUT;
+        }
+
+        scic = (scic & SWSCI_SCIC_EXIT_STATUS_MASK) >>
+                SWSCI_SCIC_EXIT_STATUS_SHIFT;
+
+        /* Note: scic == 0 is an error! */
+        if (scic != SWSCI_SCIC_EXIT_STATUS_SUCCESS) {
+                DRM_DEBUG_DRIVER("SWSCI request error %u\n", scic);
+                return -EIO;
+        }
+
+        if (parm_out)
+                *parm_out = ioread32(&swsci->parm);
+
+        return 0;
+
+#undef C
+}
+
+#define DISPLAY_TYPE_CRT                        0
+#define DISPLAY_TYPE_TV                         1
+#define DISPLAY_TYPE_EXTERNAL_FLAT_PANEL        2
+#define DISPLAY_TYPE_INTERNAL_FLAT_PANEL        3
+
+int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
+                                  bool enable)
+{
+        struct drm_device *dev = intel_encoder->base.dev;
+        u32 parm = 0;
+        u32 type = 0;
+        u32 port;
+
+        /* don't care about old stuff for now */
+        if (!HAS_DDI(dev))
+                return 0;
+
+        port = intel_ddi_get_encoder_port(intel_encoder);
+        if (port == PORT_E) {
+                port = 0;
+        } else {
+                parm |= 1 << port;
+                port++;
+        }
+
+        if (!enable)
+                parm |= 4 << 8;
+
+        switch (intel_encoder->type) {
+        case INTEL_OUTPUT_ANALOG:
+                type = DISPLAY_TYPE_CRT;
+                break;
+        case INTEL_OUTPUT_UNKNOWN:
+        case INTEL_OUTPUT_DISPLAYPORT:
+        case INTEL_OUTPUT_HDMI:
+                type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
+                break;
+        case INTEL_OUTPUT_EDP:
+                type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
+                break;
+        default:
+                WARN_ONCE(1, "unsupported intel_encoder type %d\n",
+                          intel_encoder->type);
+                return -EINVAL;
+        }
+
+        parm |= type << (16 + port * 3);
+
+        return swsci(dev, SWSCI_SBCB_DISPLAY_POWER_STATE, parm, NULL);
+}
+
+static const struct {
+        pci_power_t pci_power_state;
+        u32 parm;
+} power_state_map[] = {
+        { PCI_D0,       0x00 },
+        { PCI_D1,       0x01 },
+        { PCI_D2,       0x02 },
+        { PCI_D3hot,    0x04 },
+        { PCI_D3cold,   0x04 },
+};
+
+int intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
+{
+        int i;
+
+        if (!HAS_DDI(dev))
+                return 0;
+
+        for (i = 0; i < ARRAY_SIZE(power_state_map); i++) {
+                if (state == power_state_map[i].pci_power_state)
+                        return swsci(dev, SWSCI_SBCB_ADAPTER_POWER_STATE,
+                                     power_state_map[i].parm, NULL);
+        }
+
+        return -EINVAL;
+}
+
 static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -166,11 +399,11 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
         DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp);
 
         if (!(bclp & ASLE_BCLP_VALID))
-                return ASLE_BACKLIGHT_FAILED;
+                return ASLC_BACKLIGHT_FAILED;
 
         bclp &= ASLE_BCLP_MSK;
         if (bclp > 255)
-                return ASLE_BACKLIGHT_FAILED;
+                return ASLC_BACKLIGHT_FAILED;
 
         intel_panel_set_backlight(dev, bclp, 255);
         iowrite32(DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID, &asle->cblv);
@@ -183,13 +416,13 @@ static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi)
         /* alsi is the current ALS reading in lux. 0 indicates below sensor
            range, 0xffff indicates above sensor range. 1-0xfffe are valid */
         DRM_DEBUG_DRIVER("Illum is not supported\n");
-        return ASLE_ALS_ILLUM_FAILED;
+        return ASLC_ALS_ILLUM_FAILED;
 }
 
 static u32 asle_set_pwm_freq(struct drm_device *dev, u32 pfmb)
 {
         DRM_DEBUG_DRIVER("PWM freq is not supported\n");
-        return ASLE_PWM_FREQ_FAILED;
+        return ASLC_PWM_FREQ_FAILED;
 }
 
 static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
@@ -197,39 +430,106 @@ static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
         /* Panel fitting is currently controlled by the X code, so this is a
            noop until modesetting support works fully */
         DRM_DEBUG_DRIVER("Pfit is not supported\n");
-        return ASLE_PFIT_FAILED;
+        return ASLC_PFIT_FAILED;
+}
+
+static u32 asle_set_supported_rotation_angles(struct drm_device *dev, u32 srot)
+{
+        DRM_DEBUG_DRIVER("SROT is not supported\n");
+        return ASLC_ROTATION_ANGLES_FAILED;
+}
+
+static u32 asle_set_button_array(struct drm_device *dev, u32 iuer)
+{
+        if (!iuer)
+                DRM_DEBUG_DRIVER("Button array event is not supported (nothing)\n");
+        if (iuer & ASLE_IUER_ROTATION_LOCK_BTN)
+                DRM_DEBUG_DRIVER("Button array event is not supported (rotation lock)\n");
+        if (iuer & ASLE_IUER_VOLUME_DOWN_BTN)
+                DRM_DEBUG_DRIVER("Button array event is not supported (volume down)\n");
+        if (iuer & ASLE_IUER_VOLUME_UP_BTN)
+                DRM_DEBUG_DRIVER("Button array event is not supported (volume up)\n");
+        if (iuer & ASLE_IUER_WINDOWS_BTN)
+                DRM_DEBUG_DRIVER("Button array event is not supported (windows)\n");
+        if (iuer & ASLE_IUER_POWER_BTN)
+                DRM_DEBUG_DRIVER("Button array event is not supported (power)\n");
+
+        return ASLC_BUTTON_ARRAY_FAILED;
+}
+
+static u32 asle_set_convertible(struct drm_device *dev, u32 iuer)
+{
+        if (iuer & ASLE_IUER_CONVERTIBLE)
+                DRM_DEBUG_DRIVER("Convertible is not supported (clamshell)\n");
+        else
+                DRM_DEBUG_DRIVER("Convertible is not supported (slate)\n");
+
+        return ASLC_CONVERTIBLE_FAILED;
+}
+
+static u32 asle_set_docking(struct drm_device *dev, u32 iuer)
+{
+        if (iuer & ASLE_IUER_DOCKING)
+                DRM_DEBUG_DRIVER("Docking is not supported (docked)\n");
+        else
+                DRM_DEBUG_DRIVER("Docking is not supported (undocked)\n");
+
+        return ASLC_DOCKING_FAILED;
+}
+
+static u32 asle_isct_state(struct drm_device *dev)
+{
+        DRM_DEBUG_DRIVER("ISCT is not supported\n");
+        return ASLC_ISCT_STATE_FAILED;
 }
 
 void intel_opregion_asle_intr(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct opregion_asle __iomem *asle = dev_priv->opregion.asle;
-        u32 asle_stat = 0;
-        u32 asle_req;
+        u32 aslc_stat = 0;
+        u32 aslc_req;
 
         if (!asle)
                 return;
 
-        asle_req = ioread32(&asle->aslc) & ASLE_REQ_MSK;
+        aslc_req = ioread32(&asle->aslc);
 
-        if (!asle_req) {
-                DRM_DEBUG_DRIVER("non asle set request??\n");
+        if (!(aslc_req & ASLC_REQ_MSK)) {
+                DRM_DEBUG_DRIVER("No request on ASLC interrupt 0x%08x\n",
+                                 aslc_req);
                 return;
         }
 
-        if (asle_req & ASLE_SET_ALS_ILLUM)
-                asle_stat |= asle_set_als_illum(dev, ioread32(&asle->alsi));
+        if (aslc_req & ASLC_SET_ALS_ILLUM)
+                aslc_stat |= asle_set_als_illum(dev, ioread32(&asle->alsi));
+
+        if (aslc_req & ASLC_SET_BACKLIGHT)
+                aslc_stat |= asle_set_backlight(dev, ioread32(&asle->bclp));
+
+        if (aslc_req & ASLC_SET_PFIT)
+                aslc_stat |= asle_set_pfit(dev, ioread32(&asle->pfit));
+
+        if (aslc_req & ASLC_SET_PWM_FREQ)
+                aslc_stat |= asle_set_pwm_freq(dev, ioread32(&asle->pfmb));
 
-        if (asle_req & ASLE_SET_BACKLIGHT)
-                asle_stat |= asle_set_backlight(dev, ioread32(&asle->bclp));
+        if (aslc_req & ASLC_SUPPORTED_ROTATION_ANGLES)
+                aslc_stat |= asle_set_supported_rotation_angles(dev,
+                                                        ioread32(&asle->srot));
 
-        if (asle_req & ASLE_SET_PFIT)
-                asle_stat |= asle_set_pfit(dev, ioread32(&asle->pfit));
+        if (aslc_req & ASLC_BUTTON_ARRAY)
+                aslc_stat |= asle_set_button_array(dev, ioread32(&asle->iuer));
 
-        if (asle_req & ASLE_SET_PWM_FREQ)
-                asle_stat |= asle_set_pwm_freq(dev, ioread32(&asle->pfmb));
+        if (aslc_req & ASLC_CONVERTIBLE_INDICATOR)
+                aslc_stat |= asle_set_convertible(dev, ioread32(&asle->iuer));
 
-        iowrite32(asle_stat, &asle->aslc);
+        if (aslc_req & ASLC_DOCKING_INDICATOR)
+                aslc_stat |= asle_set_docking(dev, ioread32(&asle->iuer));
+
+        if (aslc_req & ASLC_ISCT_STATE_CHANGE)
+                aslc_stat |= asle_isct_state(dev);
+
+        iowrite32(aslc_stat, &asle->aslc);
 }
 
 #define ACPI_EV_DISPLAY_SWITCH (1<<0)
@@ -446,8 +746,68 @@ void intel_opregion_fini(struct drm_device *dev)
         opregion->swsci = NULL;
         opregion->asle = NULL;
         opregion->vbt = NULL;
+        opregion->lid_state = NULL;
+}
+
+static void swsci_setup(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_opregion *opregion = &dev_priv->opregion;
+        bool requested_callbacks = false;
+        u32 tmp;
+
+        /* Sub-function code 0 is okay, let's allow them. */
+        opregion->swsci_gbda_sub_functions = 1;
+        opregion->swsci_sbcb_sub_functions = 1;
+
+        /* We use GBDA to ask for supported GBDA calls. */
+        if (swsci(dev, SWSCI_GBDA_SUPPORTED_CALLS, 0, &tmp) == 0) {
+                /* make the bits match the sub-function codes */
+                tmp <<= 1;
+                opregion->swsci_gbda_sub_functions |= tmp;
+        }
+
+        /*
+         * We also use GBDA to ask for _requested_ SBCB callbacks. The driver
+         * must not call interfaces that are not specifically requested by the
+         * bios.
+         */
+        if (swsci(dev, SWSCI_GBDA_REQUESTED_CALLBACKS, 0, &tmp) == 0) {
+                /* here, the bits already match sub-function codes */
+                opregion->swsci_sbcb_sub_functions |= tmp;
+                requested_callbacks = true;
+        }
+
+        /*
+         * But we use SBCB to ask for _supported_ SBCB calls. This does not mean
+         * the callback is _requested_. But we still can't call interfaces that
+         * are not requested.
+         */
+        if (swsci(dev, SWSCI_SBCB_SUPPORTED_CALLBACKS, 0, &tmp) == 0) {
+                /* make the bits match the sub-function codes */
+                u32 low = tmp & 0x7ff;
+                u32 high = tmp & ~0xfff; /* bit 11 is reserved */
+                tmp = (high << 4) | (low << 1) | 1;
+
+                /* best guess what to do with supported wrt requested */
+                if (requested_callbacks) {
+                        u32 req = opregion->swsci_sbcb_sub_functions;
+                        if ((req & tmp) != req)
+                                DRM_DEBUG_DRIVER("SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", req, tmp);
+                        /* XXX: for now, trust the requested callbacks */
+                        /* opregion->swsci_sbcb_sub_functions &= tmp; */
+                } else {
+                        opregion->swsci_sbcb_sub_functions |= tmp;
+                }
+        }
+
+        DRM_DEBUG_DRIVER("SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n",
+                         opregion->swsci_gbda_sub_functions,
+                         opregion->swsci_sbcb_sub_functions);
 }
-#endif
+#else /* CONFIG_ACPI */
+static inline void swsci_setup(struct drm_device *dev) {}
+#endif  /* CONFIG_ACPI */
 
 int intel_opregion_setup(struct drm_device *dev)
 {
@@ -490,6 +850,7 @@ int intel_opregion_setup(struct drm_device *dev)
         if (mboxes & MBOX_SWSCI) {
                 DRM_DEBUG_DRIVER("SWSCI supported\n");
                 opregion->swsci = base + OPREGION_SWSCI_OFFSET;
+                swsci_setup(dev);
         }
         if (mboxes & MBOX_ASLE) {
                 DRM_DEBUG_DRIVER("ASLE supported\n");
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index ddfd0aefe0c0..a98a990fbab3 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -821,14 +821,11 @@ int intel_overlay_switch_off(struct intel_overlay *overlay)
 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
                                           struct intel_crtc *crtc)
 {
-        drm_i915_private_t *dev_priv = overlay->dev->dev_private;
-
         if (!crtc->active)
                 return -EINVAL;
 
         /* can't use the overlay with double wide pipe */
-        if (INTEL_INFO(overlay->dev)->gen < 4 &&
-            (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
+        if (crtc->config.double_wide)
                 return -EINVAL;
 
         return 0;
@@ -1056,7 +1053,7 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
                 return ret;
         }
 
-        params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
+        params = kmalloc(sizeof(*params), GFP_KERNEL);
         if (!params)
                 return -ENOMEM;
 
@@ -1323,7 +1320,7 @@ void intel_setup_overlay(struct drm_device *dev)
         if (!HAS_OVERLAY(dev))
                 return;
 
-        overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
+        overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
         if (!overlay)
                 return;
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 293564a2896a..c81020923ee4 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -50,23 +50,22 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
                         struct intel_crtc_config *pipe_config,
                         int fitting_mode)
 {
-        struct drm_display_mode *mode, *adjusted_mode;
+        struct drm_display_mode *adjusted_mode;
         int x, y, width, height;
 
-        mode = &pipe_config->requested_mode;
         adjusted_mode = &pipe_config->adjusted_mode;
 
         x = y = width = height = 0;
 
         /* Native modes don't need fitting */
-        if (adjusted_mode->hdisplay == mode->hdisplay &&
-            adjusted_mode->vdisplay == mode->vdisplay)
+        if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
+            adjusted_mode->vdisplay == pipe_config->pipe_src_h)
                 goto done;
 
         switch (fitting_mode) {
         case DRM_MODE_SCALE_CENTER:
-                width = mode->hdisplay;
-                height = mode->vdisplay;
+                width = pipe_config->pipe_src_w;
+                height = pipe_config->pipe_src_h;
                 x = (adjusted_mode->hdisplay - width + 1)/2;
                 y = (adjusted_mode->vdisplay - height + 1)/2;
                 break;
@@ -74,17 +73,19 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
         case DRM_MODE_SCALE_ASPECT:
                 /* Scale but preserve the aspect ratio */
                 {
-                        u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
-                        u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
+                        u32 scaled_width = adjusted_mode->hdisplay
+                                * pipe_config->pipe_src_h;
+                        u32 scaled_height = pipe_config->pipe_src_w
+                                * adjusted_mode->vdisplay;
                         if (scaled_width > scaled_height) { /* pillar */
-                                width = scaled_height / mode->vdisplay;
+                                width = scaled_height / pipe_config->pipe_src_h;
                                 if (width & 1)
                                         width++;
                                 x = (adjusted_mode->hdisplay - width + 1) / 2;
                                 y = 0;
                                 height = adjusted_mode->vdisplay;
                         } else if (scaled_width < scaled_height) { /* letter */
-                                height = scaled_width / mode->hdisplay;
+                                height = scaled_width / pipe_config->pipe_src_w;
                                 if (height & 1)
                                     height++;
                                 y = (adjusted_mode->vdisplay - height + 1) / 2;
@@ -171,20 +172,96 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
         return (FACTOR * ratio + FACTOR/2) / FACTOR;
 }
 
+static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
+                              u32 *pfit_control)
+{
+        struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+        u32 scaled_width = adjusted_mode->hdisplay *
+                pipe_config->pipe_src_h;
+        u32 scaled_height = pipe_config->pipe_src_w *
+                adjusted_mode->vdisplay;
+
+        /* 965+ is easy, it does everything in hw */
+        if (scaled_width > scaled_height)
+                *pfit_control |= PFIT_ENABLE |
+                        PFIT_SCALING_PILLAR;
+        else if (scaled_width < scaled_height)
+                *pfit_control |= PFIT_ENABLE |
+                        PFIT_SCALING_LETTER;
+        else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
+                *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
+}
+
+static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
+                              u32 *pfit_control, u32 *pfit_pgm_ratios,
+                              u32 *border)
+{
+        struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+        u32 scaled_width = adjusted_mode->hdisplay *
+                pipe_config->pipe_src_h;
+        u32 scaled_height = pipe_config->pipe_src_w *
+                adjusted_mode->vdisplay;
+        u32 bits;
+
+        /*
+         * For earlier chips we have to calculate the scaling
+         * ratio by hand and program it into the
+         * PFIT_PGM_RATIO register
+         */
+        if (scaled_width > scaled_height) { /* pillar */
+                centre_horizontally(adjusted_mode,
+                                    scaled_height /
+                                    pipe_config->pipe_src_h);
+
+                *border = LVDS_BORDER_ENABLE;
+                if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
+                        bits = panel_fitter_scaling(pipe_config->pipe_src_h,
+                                                    adjusted_mode->vdisplay);
+
+                        *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
+                                             bits << PFIT_VERT_SCALE_SHIFT);
+                        *pfit_control |= (PFIT_ENABLE |
+                                          VERT_INTERP_BILINEAR |
+                                          HORIZ_INTERP_BILINEAR);
+                }
+        } else if (scaled_width < scaled_height) { /* letter */
+                centre_vertically(adjusted_mode,
+                                  scaled_width /
+                                  pipe_config->pipe_src_w);
+
+                *border = LVDS_BORDER_ENABLE;
+                if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
+                        bits = panel_fitter_scaling(pipe_config->pipe_src_w,
+                                                    adjusted_mode->hdisplay);
+
+                        *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
+                                             bits << PFIT_VERT_SCALE_SHIFT);
+                        *pfit_control |= (PFIT_ENABLE |
+                                          VERT_INTERP_BILINEAR |
+                                          HORIZ_INTERP_BILINEAR);
+                }
+        } else {
+                /* Aspects match, Let hw scale both directions */
+                *pfit_control |= (PFIT_ENABLE |
+                                  VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
+                                  VERT_INTERP_BILINEAR |
+                                  HORIZ_INTERP_BILINEAR);
+        }
+}
+
 void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
                               struct intel_crtc_config *pipe_config,
                               int fitting_mode)
 {
         struct drm_device *dev = intel_crtc->base.dev;
         u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
-        struct drm_display_mode *mode, *adjusted_mode;
+        struct drm_display_mode *adjusted_mode;
 
-        mode = &pipe_config->requested_mode;
         adjusted_mode = &pipe_config->adjusted_mode;
 
         /* Native modes don't need fitting */
-        if (adjusted_mode->hdisplay == mode->hdisplay &&
-            adjusted_mode->vdisplay == mode->vdisplay)
+        if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
+            adjusted_mode->vdisplay == pipe_config->pipe_src_h)
                 goto out;
 
         switch (fitting_mode) {
@@ -193,81 +270,25 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
                  * For centered modes, we have to calculate border widths &
                  * heights and modify the values programmed into the CRTC.
                  */
-                centre_horizontally(adjusted_mode, mode->hdisplay);
-                centre_vertically(adjusted_mode, mode->vdisplay);
+                centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
+                centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
                 border = LVDS_BORDER_ENABLE;
                 break;
         case DRM_MODE_SCALE_ASPECT:
                 /* Scale but preserve the aspect ratio */
-                if (INTEL_INFO(dev)->gen >= 4) {
-                        u32 scaled_width = adjusted_mode->hdisplay *
-                                mode->vdisplay;
-                        u32 scaled_height = mode->hdisplay *
-                                adjusted_mode->vdisplay;
-
-                        /* 965+ is easy, it does everything in hw */
-                        if (scaled_width > scaled_height)
-                                pfit_control |= PFIT_ENABLE |
-                                        PFIT_SCALING_PILLAR;
-                        else if (scaled_width < scaled_height)
-                                pfit_control |= PFIT_ENABLE |
-                                        PFIT_SCALING_LETTER;
-                        else if (adjusted_mode->hdisplay != mode->hdisplay)
-                                pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
-                } else {
-                        u32 scaled_width = adjusted_mode->hdisplay *
-                                mode->vdisplay;
-                        u32 scaled_height = mode->hdisplay *
-                                adjusted_mode->vdisplay;
-                        /*
-                         * For earlier chips we have to calculate the scaling
-                         * ratio by hand and program it into the
-                         * PFIT_PGM_RATIO register
-                         */
-                        if (scaled_width > scaled_height) { /* pillar */
-                                centre_horizontally(adjusted_mode,
-                                                    scaled_height /
-                                                    mode->vdisplay);
-
-                                border = LVDS_BORDER_ENABLE;
-                                if (mode->vdisplay != adjusted_mode->vdisplay) {
-                                        u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
-                                        pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
-                                                            bits << PFIT_VERT_SCALE_SHIFT);
-                                        pfit_control |= (PFIT_ENABLE |
-                                                         VERT_INTERP_BILINEAR |
-                                                         HORIZ_INTERP_BILINEAR);
-                                }
-                        } else if (scaled_width < scaled_height) { /* letter */
-                                centre_vertically(adjusted_mode,
-                                                  scaled_width /
-                                                  mode->hdisplay);
-
-                                border = LVDS_BORDER_ENABLE;
-                                if (mode->hdisplay != adjusted_mode->hdisplay) {
-                                        u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
-                                        pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
-                                                            bits << PFIT_VERT_SCALE_SHIFT);
-                                        pfit_control |= (PFIT_ENABLE |
-                                                         VERT_INTERP_BILINEAR |
-                                                         HORIZ_INTERP_BILINEAR);
-                                }
-                        } else {
-                                /* Aspects match, Let hw scale both directions */
-                                pfit_control |= (PFIT_ENABLE |
-                                                 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
-                                                 VERT_INTERP_BILINEAR |
-                                                 HORIZ_INTERP_BILINEAR);
-                        }
-                }
+                if (INTEL_INFO(dev)->gen >= 4)
+                        i965_scale_aspect(pipe_config, &pfit_control);
+                else
+                        i9xx_scale_aspect(pipe_config, &pfit_control,
+                                          &pfit_pgm_ratios, &border);
                 break;
         case DRM_MODE_SCALE_FULLSCREEN:
                 /*
                  * Full scaling, even if it changes the aspect ratio.
                  * Fortunately this is all done for us in hw.
                  */
-                if (mode->vdisplay != adjusted_mode->vdisplay ||
-                    mode->hdisplay != adjusted_mode->hdisplay) {
+                if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
+                    pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
                         pfit_control |= PFIT_ENABLE;
                         if (INTEL_INFO(dev)->gen >= 4)
                                 pfit_control |= PFIT_SCALING_AUTO;
@@ -308,7 +329,7 @@ static int is_backlight_combination_mode(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (INTEL_INFO(dev)->gen >= 4)
+        if (IS_GEN4(dev))
                 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
 
         if (IS_GEN2(dev))
@@ -351,6 +372,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
                                 I915_WRITE(BLC_PWM_CTL2,
                                            dev_priv->regfile.saveBLC_PWM_CTL2);
                 }
+
+                if (IS_VALLEYVIEW(dev) && !val)
+                        val = 0x0f42ffff;
         }
 
         return val;
@@ -441,7 +465,8 @@ static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
         I915_WRITE(BLC_PWM_CPU_CTL, val | level);
 }
 
-static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
+static void intel_panel_actually_set_backlight(struct drm_device *dev,
+                                               u32 level)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 tmp;
@@ -607,10 +632,24 @@ set_level:
         spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
 }
 
+/* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */
+static void intel_panel_init_backlight_regs(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (IS_VALLEYVIEW(dev)) {
+                u32 cur_val = I915_READ(BLC_PWM_CTL) &
+                        BACKLIGHT_DUTY_CYCLE_MASK;
+                I915_WRITE(BLC_PWM_CTL, (0xf42 << 16) | cur_val);
+        }
+}
+
 static void intel_panel_init_backlight(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        intel_panel_init_backlight_regs(dev);
+
         dev_priv->backlight.level = intel_panel_get_backlight(dev);
         dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
 }
@@ -637,7 +676,7 @@ intel_panel_detect(struct drm_device *dev)
         }
 }
 
-#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
+#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
 static int intel_panel_update_status(struct backlight_device *bd)
 {
         struct drm_device *dev = bl_get_data(bd);
@@ -683,7 +722,7 @@ int intel_panel_setup_backlight(struct drm_connector *connector)
         }
         dev_priv->backlight.device =
                 backlight_device_register("intel_backlight",
-                                          &connector->kdev, dev,
+                                          connector->kdev, dev,
                                           &intel_panel_bl_ops, &props);
 
         if (IS_ERR(dev_priv->backlight.device)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd176b7296c1..008ec0bb017f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,14 +43,6 @@
  * i915.i915_enable_fbc parameter
  */
 
-static bool intel_crtc_active(struct drm_crtc *crtc)
-{
-        /* Be paranoid as we can arrive here with only partial
-         * state retrieved from the hardware during setup.
-         */
-        return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
-}
-
 static void i8xx_disable_fbc(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -378,7 +370,7 @@ static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 
         intel_cancel_fbc_work(dev_priv);
 
-        work = kzalloc(sizeof *work, GFP_KERNEL);
+        work = kzalloc(sizeof(*work), GFP_KERNEL);
         if (work == NULL) {
                 DRM_ERROR("Failed to allocate FBC work structure\n");
                 dev_priv->display.enable_fbc(crtc, interval);
@@ -458,7 +450,8 @@ void intel_update_fbc(struct drm_device *dev)
         struct drm_framebuffer *fb;
         struct intel_framebuffer *intel_fb;
         struct drm_i915_gem_object *obj;
-        unsigned int max_hdisplay, max_vdisplay;
+        const struct drm_display_mode *adjusted_mode;
+        unsigned int max_width, max_height;
 
         if (!I915_HAS_FBC(dev)) {
                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
@@ -502,6 +495,7 @@ void intel_update_fbc(struct drm_device *dev)
         fb = crtc->fb;
         intel_fb = to_intel_framebuffer(fb);
         obj = intel_fb->obj;
+        adjusted_mode = &intel_crtc->config.adjusted_mode;
 
         if (i915_enable_fbc < 0 &&
             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
@@ -514,8 +508,8 @@ void intel_update_fbc(struct drm_device *dev)
                         DRM_DEBUG_KMS("fbc disabled per module param\n");
                 goto out_disable;
         }
-        if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
-            (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
+        if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
+            (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
                         DRM_DEBUG_KMS("mode incompatible with compression, "
                                       "disabling\n");
@@ -523,14 +517,14 @@ void intel_update_fbc(struct drm_device *dev)
         }
 
         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
-                max_hdisplay = 4096;
-                max_vdisplay = 2048;
+                max_width = 4096;
+                max_height = 2048;
         } else {
-                max_hdisplay = 2048;
-                max_vdisplay = 1536;
+                max_width = 2048;
+                max_height = 1536;
         }
-        if ((crtc->mode.hdisplay > max_hdisplay) ||
-            (crtc->mode.vdisplay > max_vdisplay)) {
+        if (intel_crtc->config.pipe_src_w > max_width ||
+            intel_crtc->config.pipe_src_h > max_height) {
                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
                 goto out_disable;
@@ -1087,8 +1081,9 @@ static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
         return enabled;
 }
 
-static void pineview_update_wm(struct drm_device *dev)
+static void pineview_update_wm(struct drm_crtc *unused_crtc)
 {
+        struct drm_device *dev = unused_crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_crtc *crtc;
         const struct cxsr_latency *latency;
@@ -1105,8 +1100,12 @@ static void pineview_update_wm(struct drm_device *dev)
 
         crtc = single_enabled_crtc(dev);
         if (crtc) {
-                int clock = crtc->mode.clock;
+                const struct drm_display_mode *adjusted_mode;
                 int pixel_size = crtc->fb->bits_per_pixel / 8;
+                int clock;
+
+                adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+                clock = adjusted_mode->crtc_clock;
 
                 /* Display SR */
                 wm = intel_calculate_wm(clock, &pineview_display_wm,
@@ -1166,6 +1165,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
                             int *cursor_wm)
 {
         struct drm_crtc *crtc;
+        const struct drm_display_mode *adjusted_mode;
         int htotal, hdisplay, clock, pixel_size;
         int line_time_us, line_count;
         int entries, tlb_miss;
@@ -1177,9 +1177,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
                 return false;
         }
 
-        htotal = crtc->mode.htotal;
-        hdisplay = crtc->mode.hdisplay;
-        clock = crtc->mode.clock;
+        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+        clock = adjusted_mode->crtc_clock;
+        htotal = adjusted_mode->htotal;
+        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
         pixel_size = crtc->fb->bits_per_pixel / 8;
 
         /* Use the small buffer method to calculate plane watermark */
@@ -1250,6 +1251,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
                              int *display_wm, int *cursor_wm)
 {
         struct drm_crtc *crtc;
+        const struct drm_display_mode *adjusted_mode;
         int hdisplay, htotal, pixel_size, clock;
         unsigned long line_time_us;
         int line_count, line_size;
@@ -1262,9 +1264,10 @@ static bool g4x_compute_srwm(struct drm_device *dev,
         }
 
         crtc = intel_get_crtc_for_plane(dev, plane);
-        hdisplay = crtc->mode.hdisplay;
-        htotal = crtc->mode.htotal;
-        clock = crtc->mode.clock;
+        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+        clock = adjusted_mode->crtc_clock;
+        htotal = adjusted_mode->htotal;
+        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
         pixel_size = crtc->fb->bits_per_pixel / 8;
 
         line_time_us = (htotal * 1000) / clock;
@@ -1303,7 +1306,7 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
         if (!intel_crtc_active(crtc))
                 return false;
 
-        clock = crtc->mode.clock;       /* VESA DOT Clock */
+        clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
 
         entries = (clock / 1000) * pixel_size;
@@ -1365,8 +1368,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
 
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
-static void valleyview_update_wm(struct drm_device *dev)
+static void valleyview_update_wm(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
         static const int sr_latency_ns = 12000;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
@@ -1424,8 +1428,9 @@ static void valleyview_update_wm(struct drm_device *dev)
                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 
-static void g4x_update_wm(struct drm_device *dev)
+static void g4x_update_wm(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
         static const int sr_latency_ns = 12000;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
@@ -1476,8 +1481,9 @@ static void g4x_update_wm(struct drm_device *dev)
                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 
-static void i965_update_wm(struct drm_device *dev)
+static void i965_update_wm(struct drm_crtc *unused_crtc)
 {
+        struct drm_device *dev = unused_crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_crtc *crtc;
         int srwm = 1;
@@ -1488,9 +1494,11 @@ static void i965_update_wm(struct drm_device *dev)
         if (crtc) {
                 /* self-refresh has much higher latency */
                 static const int sr_latency_ns = 12000;
-                int clock = crtc->mode.clock;
-                int htotal = crtc->mode.htotal;
-                int hdisplay = crtc->mode.hdisplay;
+                const struct drm_display_mode *adjusted_mode =
+                        &to_intel_crtc(crtc)->config.adjusted_mode;
+                int clock = adjusted_mode->crtc_clock;
+                int htotal = adjusted_mode->htotal;
+                int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
                 int pixel_size = crtc->fb->bits_per_pixel / 8;
                 unsigned long line_time_us;
                 int entries;
@@ -1541,8 +1549,9 @@ static void i965_update_wm(struct drm_device *dev)
         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 
-static void i9xx_update_wm(struct drm_device *dev)
+static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 {
+        struct drm_device *dev = unused_crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         const struct intel_watermark_params *wm_info;
         uint32_t fwater_lo;
@@ -1562,11 +1571,13 @@ static void i9xx_update_wm(struct drm_device *dev)
         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
         crtc = intel_get_crtc_for_plane(dev, 0);
         if (intel_crtc_active(crtc)) {
+                const struct drm_display_mode *adjusted_mode;
                 int cpp = crtc->fb->bits_per_pixel / 8;
                 if (IS_GEN2(dev))
                         cpp = 4;
 
-                planea_wm = intel_calculate_wm(crtc->mode.clock,
+                adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+                planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
                                                wm_info, fifo_size, cpp,
                                                latency_ns);
                 enabled = crtc;
@@ -1576,11 +1587,13 @@ static void i9xx_update_wm(struct drm_device *dev)
         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
         crtc = intel_get_crtc_for_plane(dev, 1);
         if (intel_crtc_active(crtc)) {
+                const struct drm_display_mode *adjusted_mode;
                 int cpp = crtc->fb->bits_per_pixel / 8;
                 if (IS_GEN2(dev))
                         cpp = 4;
 
-                planeb_wm = intel_calculate_wm(crtc->mode.clock,
+                adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+                planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
                                                wm_info, fifo_size, cpp,
                                                latency_ns);
                 if (enabled == NULL)
@@ -1607,9 +1620,11 @@ static void i9xx_update_wm(struct drm_device *dev)
         if (HAS_FW_BLC(dev) && enabled) {
                 /* self-refresh has much higher latency */
                 static const int sr_latency_ns = 6000;
-                int clock = enabled->mode.clock;
-                int htotal = enabled->mode.htotal;
-                int hdisplay = enabled->mode.hdisplay;
+                const struct drm_display_mode *adjusted_mode =
+                        &to_intel_crtc(enabled)->config.adjusted_mode;
+                int clock = adjusted_mode->crtc_clock;
+                int htotal = adjusted_mode->htotal;
+                int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
                 int pixel_size = enabled->fb->bits_per_pixel / 8;
                 unsigned long line_time_us;
                 int entries;
@@ -1658,10 +1673,12 @@ static void i9xx_update_wm(struct drm_device *dev)
         }
 }
 
-static void i830_update_wm(struct drm_device *dev)
+static void i830_update_wm(struct drm_crtc *unused_crtc)
 {
+        struct drm_device *dev = unused_crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_crtc *crtc;
+        const struct drm_display_mode *adjusted_mode;
         uint32_t fwater_lo;
         int planea_wm;
 
@@ -1669,7 +1686,9 @@ static void i830_update_wm(struct drm_device *dev)
         if (crtc == NULL)
                 return;
 
-        planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
+        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+        planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+                                       &i830_wm_info,
                                        dev_priv->display.get_fifo_size(dev, 0),
                                        4, latency_ns);
         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -1741,6 +1760,7 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
                                   int *fbc_wm, int *display_wm, int *cursor_wm)
 {
         struct drm_crtc *crtc;
+        const struct drm_display_mode *adjusted_mode;
         unsigned long line_time_us;
         int hdisplay, htotal, pixel_size, clock;
         int line_count, line_size;
@@ -1753,9 +1773,10 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
         }
 
         crtc = intel_get_crtc_for_plane(dev, plane);
-        hdisplay = crtc->mode.hdisplay;
-        htotal = crtc->mode.htotal;
-        clock = crtc->mode.clock;
+        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
+        clock = adjusted_mode->crtc_clock;
+        htotal = adjusted_mode->htotal;
+        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
         pixel_size = crtc->fb->bits_per_pixel / 8;
 
         line_time_us = (htotal * 1000) / clock;
@@ -1785,8 +1806,9 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
                                    display, cursor);
 }
 
-static void ironlake_update_wm(struct drm_device *dev)
+static void ironlake_update_wm(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int fbc_wm, plane_wm, cursor_wm;
         unsigned int enabled;
@@ -1868,8 +1890,9 @@ static void ironlake_update_wm(struct drm_device *dev)
          */
 }
 
-static void sandybridge_update_wm(struct drm_device *dev)
+static void sandybridge_update_wm(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
         u32 val;
@@ -1970,8 +1993,9 @@ static void sandybridge_update_wm(struct drm_device *dev)
                    cursor_wm);
 }
 
-static void ivybridge_update_wm(struct drm_device *dev)
+static void ivybridge_update_wm(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
         u32 val;
@@ -2098,7 +2122,7 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         uint32_t pixel_rate;
 
-        pixel_rate = intel_crtc->config.adjusted_mode.clock;
+        pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
 
         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
          * adjust the pixel_rate here. */
@@ -2107,8 +2131,8 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
 
-                pipe_w = intel_crtc->config.requested_mode.hdisplay;
-                pipe_h = intel_crtc->config.requested_mode.vdisplay;
+                pipe_w = intel_crtc->config.pipe_src_w;
+                pipe_h = intel_crtc->config.pipe_src_h;
                 pfit_w = (pfit_size >> 16) & 0xFFFF;
                 pfit_h = pfit_size & 0xFFFF;
                 if (pipe_w < pfit_w)
@@ -2196,7 +2220,7 @@ struct intel_wm_config {
  * For both WM_PIPE and WM_LP.
  * mem_value must be in 0.1us units.
  */
-static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
+static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
                                    uint32_t mem_value,
                                    bool is_lp)
 {
@@ -2225,7 +2249,7 @@ static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
  * For both WM_PIPE and WM_LP.
  * mem_value must be in 0.1us units.
  */
-static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
+static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
                                    uint32_t mem_value)
 {
         uint32_t method1, method2;
@@ -2248,7 +2272,7 @@ static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
  * For both WM_PIPE and WM_LP.
  * mem_value must be in 0.1us units.
  */
-static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
+static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
                                    uint32_t mem_value)
 {
         if (!params->active || !params->cur.enabled)
@@ -2262,7 +2286,7 @@ static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
 }
 
 /* Only for WM_LP. */
-static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
+static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
                                    uint32_t pri_val)
 {
         if (!params->active || !params->pri.enabled)
@@ -2413,7 +2437,7 @@ static bool ilk_check_wm(int level,
 
 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
                                  int level,
-                                 struct hsw_pipe_wm_parameters *p,
+                                 const struct hsw_pipe_wm_parameters *p,
                                  struct intel_wm_level *result)
 {
         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
@@ -2435,8 +2459,8 @@ static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
 }
 
 static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
-                              int level, struct hsw_wm_maximums *max,
-                              struct hsw_pipe_wm_parameters *params,
+                              int level, const struct hsw_wm_maximums *max,
+                              const struct hsw_pipe_wm_parameters *params,
                               struct intel_wm_level *result)
 {
         enum pipe pipe;
@@ -2454,33 +2478,31 @@ static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
         return ilk_check_wm(level, max, result);
 }
 
-static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
-                                    enum pipe pipe,
-                                    struct hsw_pipe_wm_parameters *params)
+
+static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
+                                    const struct hsw_pipe_wm_parameters *params)
 {
-        uint32_t pri_val, cur_val, spr_val;
-        /* WM0 latency values stored in 0.1us units */
-        uint16_t pri_latency = dev_priv->wm.pri_latency[0];
-        uint16_t spr_latency = dev_priv->wm.spr_latency[0];
-        uint16_t cur_latency = dev_priv->wm.cur_latency[0];
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_wm_config config = {
+                .num_pipes_active = 1,
+                .sprites_enabled = params->spr.enabled,
+                .sprites_scaled = params->spr.scaled,
+        };
+        struct hsw_wm_maximums max;
+        struct intel_wm_level res;
+
+        if (!params->active)
+                return 0;
+
+        ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
 
-        pri_val = ilk_compute_pri_wm(params, pri_latency, false);
-        spr_val = ilk_compute_spr_wm(params, spr_latency);
-        cur_val = ilk_compute_cur_wm(params, cur_latency);
+        ilk_compute_wm_level(dev_priv, 0, params, &res);
 
-        WARN(pri_val > 127,
-             "Primary WM error, mode not supported for pipe %c\n",
-             pipe_name(pipe));
-        WARN(spr_val > 127,
-             "Sprite WM error, mode not supported for pipe %c\n",
-             pipe_name(pipe));
-        WARN(cur_val > 63,
-             "Cursor WM error, mode not supported for pipe %c\n",
-             pipe_name(pipe));
+        ilk_check_wm(0, &max, &res);
 
-        return (pri_val << WM0_PIPE_PLANE_SHIFT) |
-               (spr_val << WM0_PIPE_SPRITE_SHIFT) |
-               cur_val;
+        return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
+               (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
+               res.cur_val;
 }
 
 static uint32_t
@@ -2554,19 +2576,22 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
                 wm[3] *= 2;
 }
 
-static void intel_print_wm_latency(struct drm_device *dev,
-                                   const char *name,
-                                   const uint16_t wm[5])
+static int ilk_wm_max_level(const struct drm_device *dev)
 {
-        int level, max_level;
-
         /* how many WM levels are we expecting */
         if (IS_HASWELL(dev))
-                max_level = 4;
+                return 4;
         else if (INTEL_INFO(dev)->gen >= 6)
-                max_level = 3;
+                return 3;
         else
-                max_level = 2;
+                return 2;
+}
+
+static void intel_print_wm_latency(struct drm_device *dev,
+                                   const char *name,
+                                   const uint16_t wm[5])
+{
+        int level, max_level = ilk_wm_max_level(dev);
 
         for (level = 0; level <= max_level; level++) {
                 unsigned int latency = wm[level];
@@ -2633,8 +2658,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev,
                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
                 p->cur.bytes_per_pixel = 4;
-                p->pri.horiz_pixels =
-                        intel_crtc->config.requested_mode.hdisplay;
+                p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
                 p->cur.horiz_pixels = 64;
                 /* TODO: for now, assume primary and cursor planes are always enabled. */
                 p->pri.enabled = true;
@@ -2664,8 +2688,8 @@ static void hsw_compute_wm_parameters(struct drm_device *dev,
 }
 
 static void hsw_compute_wm_results(struct drm_device *dev,
-                                   struct hsw_pipe_wm_parameters *params,
-                                   struct hsw_wm_maximums *lp_maximums,
+                                   const struct hsw_pipe_wm_parameters *params,
+                                   const struct hsw_wm_maximums *lp_maximums,
                                    struct hsw_wm_values *results)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2709,7 +2733,7 @@ static void hsw_compute_wm_results(struct drm_device *dev,
         }
 
         for_each_pipe(pipe)
-                results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
+                results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
                                                              &params[pipe]);
 
         for_each_pipe(pipe) {
@@ -2841,8 +2865,9 @@ static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
 }
 
-static void haswell_update_wm(struct drm_device *dev)
+static void haswell_update_wm(struct drm_crtc *crtc)
 {
+        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
         struct hsw_pipe_wm_parameters params[3];
@@ -2879,7 +2904,7 @@ static void haswell_update_sprite_wm(struct drm_plane *plane,
         intel_plane->wm.horiz_pixels = sprite_width;
         intel_plane->wm.bytes_per_pixel = pixel_size;
 
-        haswell_update_wm(plane->dev);
+        haswell_update_wm(crtc);
 }
 
 static bool
@@ -2898,7 +2923,7 @@ sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
                 return false;
         }
 
-        clock = crtc->mode.clock;
+        clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
 
         /* Use the small buffer method to calculate the sprite watermark */
         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
@@ -2933,7 +2958,7 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
         }
 
         crtc = intel_get_crtc_for_plane(dev, plane);
-        clock = crtc->mode.clock;
+        clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
         if (!clock) {
                 *sprite_wm = 0;
                 return false;
@@ -3076,12 +3101,12 @@ static void sandybridge_update_sprite_wm(struct drm_plane *plane,
  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  * to set the non-SR watermarks to 8.
  */
-void intel_update_watermarks(struct drm_device *dev)
+void intel_update_watermarks(struct drm_crtc *crtc)
 {
-        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 
         if (dev_priv->display.update_wm)
-                dev_priv->display.update_wm(dev);
+                dev_priv->display.update_wm(crtc);
 }
 
 void intel_update_sprite_watermarks(struct drm_plane *plane,
@@ -3287,6 +3312,98 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
         return limits;
 }
 
+static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
+{
+        int new_power;
+
+        new_power = dev_priv->rps.power;
+        switch (dev_priv->rps.power) {
+        case LOW_POWER:
+                if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
+                        new_power = BETWEEN;
+                break;
+
+        case BETWEEN:
+                if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
+                        new_power = LOW_POWER;
+                else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
+                        new_power = HIGH_POWER;
+                break;
+
+        case HIGH_POWER:
+                if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
+                        new_power = BETWEEN;
+                break;
+        }
+        /* Max/min bins are special */
+        if (val == dev_priv->rps.min_delay)
+                new_power = LOW_POWER;
+        if (val == dev_priv->rps.max_delay)
+                new_power = HIGH_POWER;
+        if (new_power == dev_priv->rps.power)
+                return;
+
+        /* Note the units here are not exactly 1us, but 1280ns. */
+        switch (new_power) {
+        case LOW_POWER:
+                /* Upclock if more than 95% busy over 16ms */
+                I915_WRITE(GEN6_RP_UP_EI, 12500);
+                I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
+
+                /* Downclock if less than 85% busy over 32ms */
+                I915_WRITE(GEN6_RP_DOWN_EI, 25000);
+                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
+
+                I915_WRITE(GEN6_RP_CONTROL,
+                           GEN6_RP_MEDIA_TURBO |
+                           GEN6_RP_MEDIA_HW_NORMAL_MODE |
+                           GEN6_RP_MEDIA_IS_GFX |
+                           GEN6_RP_ENABLE |
+                           GEN6_RP_UP_BUSY_AVG |
+                           GEN6_RP_DOWN_IDLE_AVG);
+                break;
+
+        case BETWEEN:
+                /* Upclock if more than 90% busy over 13ms */
+                I915_WRITE(GEN6_RP_UP_EI, 10250);
+                I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
+
+                /* Downclock if less than 75% busy over 32ms */
+                I915_WRITE(GEN6_RP_DOWN_EI, 25000);
+                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
+
+                I915_WRITE(GEN6_RP_CONTROL,
+                           GEN6_RP_MEDIA_TURBO |
+                           GEN6_RP_MEDIA_HW_NORMAL_MODE |
+                           GEN6_RP_MEDIA_IS_GFX |
+                           GEN6_RP_ENABLE |
+                           GEN6_RP_UP_BUSY_AVG |
+                           GEN6_RP_DOWN_IDLE_AVG);
+                break;
+
+        case HIGH_POWER:
+                /* Upclock if more than 85% busy over 10ms */
+                I915_WRITE(GEN6_RP_UP_EI, 8000);
+                I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
+
+                /* Downclock if less than 60% busy over 32ms */
+                I915_WRITE(GEN6_RP_DOWN_EI, 25000);
+                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
+
+                I915_WRITE(GEN6_RP_CONTROL,
+                           GEN6_RP_MEDIA_TURBO |
+                           GEN6_RP_MEDIA_HW_NORMAL_MODE |
+                           GEN6_RP_MEDIA_IS_GFX |
+                           GEN6_RP_ENABLE |
+                           GEN6_RP_UP_BUSY_AVG |
+                           GEN6_RP_DOWN_IDLE_AVG);
+                break;
+        }
+
+        dev_priv->rps.power = new_power;
+        dev_priv->rps.last_adj = 0;
+}
+
 void gen6_set_rps(struct drm_device *dev, u8 val)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3299,6 +3416,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
         if (val == dev_priv->rps.cur_delay)
                 return;
 
+        gen6_set_rps_thresholds(dev_priv, val);
+
         if (IS_HASWELL(dev))
                 I915_WRITE(GEN6_RPNSWREQ,
                            HSW_FREQUENCY(val));
@@ -3320,6 +3439,28 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
         trace_intel_gpu_freq_change(val * 50);
 }
 
+void gen6_rps_idle(struct drm_i915_private *dev_priv)
+{
+        mutex_lock(&dev_priv->rps.hw_lock);
+        if (dev_priv->info->is_valleyview)
+                valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
+        else
+                gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
+        dev_priv->rps.last_adj = 0;
+        mutex_unlock(&dev_priv->rps.hw_lock);
+}
+
+void gen6_rps_boost(struct drm_i915_private *dev_priv)
+{
+        mutex_lock(&dev_priv->rps.hw_lock);
+        if (dev_priv->info->is_valleyview)
+                valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
+        else
+                gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
+        dev_priv->rps.last_adj = 0;
+        mutex_unlock(&dev_priv->rps.hw_lock);
+}
+
 /*
  * Wait until the previous freq change has completed,
  * or the timeout elapsed, and then update our notion
@@ -3501,7 +3642,10 @@ static void gen6_enable_rps(struct drm_device *dev)
 
         /* In units of 50MHz */
         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
-        dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
+        dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
+        dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
+        dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
+        dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
         dev_priv->rps.cur_delay = 0;
 
         /* disable the counters and set deterministic thresholds */
@@ -3549,38 +3693,9 @@ static void gen6_enable_rps(struct drm_device *dev)
                    GEN6_RC_CTL_EI_MODE(1) |
                    GEN6_RC_CTL_HW_ENABLE);
 
-        if (IS_HASWELL(dev)) {
-                I915_WRITE(GEN6_RPNSWREQ,
-                           HSW_FREQUENCY(10));
-                I915_WRITE(GEN6_RC_VIDEO_FREQ,
-                           HSW_FREQUENCY(12));
-        } else {
-                I915_WRITE(GEN6_RPNSWREQ,
-                           GEN6_FREQUENCY(10) |
-                           GEN6_OFFSET(0) |
-                           GEN6_AGGRESSIVE_TURBO);
-                I915_WRITE(GEN6_RC_VIDEO_FREQ,
-                           GEN6_FREQUENCY(12));
-        }
-
-        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
-        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
-                   dev_priv->rps.max_delay << 24 |
-                   dev_priv->rps.min_delay << 16);
-
-        I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
-        I915_WRITE(GEN6_RP_UP_EI, 66000);
-        I915_WRITE(GEN6_RP_DOWN_EI, 350000);
-
+        /* Power down if completely idle for over 50ms */
+        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
-        I915_WRITE(GEN6_RP_CONTROL,
-                   GEN6_RP_MEDIA_TURBO |
-                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-                   GEN6_RP_MEDIA_IS_GFX |
-                   GEN6_RP_ENABLE |
-                   GEN6_RP_UP_BUSY_AVG |
-                   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
 
         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
         if (!ret) {
@@ -3596,7 +3711,8 @@ static void gen6_enable_rps(struct drm_device *dev)
                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
         }
 
-        gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
+        dev_priv->rps.power = HIGH_POWER; /* force a reset */
+        gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
 
         gen6_enable_rps_interrupts(dev);
 
@@ -3638,9 +3754,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
         /* Convert from kHz to MHz */
         max_ia_freq /= 1000;
 
-        min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
-        /* convert DDR frequency from units of 133.3MHz to bandwidth */
-        min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
+        min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
+        /* convert DDR frequency from units of 266.6MHz to bandwidth */
+        min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
         /*
          * For each potential GPU frequency, load a ring frequency we'd like
@@ -3653,7 +3769,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
                 unsigned int ia_freq = 0, ring_freq = 0;
 
                 if (IS_HASWELL(dev)) {
-                        ring_freq = (gpu_freq * 5 + 3) / 4;
+                        ring_freq = mult_frac(gpu_freq, 5, 4);
                         ring_freq = max(min_ring_freq, ring_freq);
                         /* leave ia_freq as the default, chosen by cpufreq */
                 } else {
@@ -3709,24 +3825,6 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
 }
 
-static void vlv_rps_timer_work(struct work_struct *work)
-{
-        drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
-                                                    rps.vlv_work.work);
-
-        /*
-         * Timer fired, we must be idle.  Drop to min voltage state.
-         * Note: we use RPe here since it should match the
-         * Vmin we were shooting for.  That should give us better
-         * perf when we come back out of RC6 than if we used the
-         * min freq available.
-         */
-        mutex_lock(&dev_priv->rps.hw_lock);
-        if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
-                valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
-        mutex_unlock(&dev_priv->rps.hw_lock);
-}
-
 static void valleyview_setup_pctx(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3773,13 +3871,14 @@ static void valleyview_enable_rps(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_ring_buffer *ring;
-        u32 gtfifodbg, val;
+        u32 gtfifodbg, val, rc6_mode = 0;
         int i;
 
         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 
         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
-                DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
+                DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
+                                 gtfifodbg);
                 I915_WRITE(GTFIFODBG, gtfifodbg);
         }
 
@@ -3812,9 +3911,13 @@ static void valleyview_enable_rps(struct drm_device *dev)
         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
 
         /* allows RC6 residency counter to work */
-        I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
-        I915_WRITE(GEN6_RC_CONTROL,
-                   GEN7_RC_CTL_TO_MODE);
+        I915_WRITE(VLV_COUNTER_CONTROL,
+                   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+                                      VLV_MEDIA_RC6_COUNT_EN |
+                                      VLV_RENDER_RC6_COUNT_EN));
+        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
+                rc6_mode = GEN7_RC_CTL_TO_MODE;
+        I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
         switch ((val >> 6) & 3) {
@@ -3864,8 +3967,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
                                       dev_priv->rps.rpe_delay),
                          dev_priv->rps.rpe_delay);
 
-        INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
-
         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
 
         gen6_enable_rps_interrupts(dev);
@@ -4605,8 +4706,6 @@ void intel_disable_gt_powersave(struct drm_device *dev)
         } else if (INTEL_INFO(dev)->gen >= 6) {
                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
                 cancel_work_sync(&dev_priv->rps.work);
-                if (IS_VALLEYVIEW(dev))
-                        cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
                 mutex_lock(&dev_priv->rps.hw_lock);
                 if (IS_VALLEYVIEW(dev))
                         valleyview_disable_rps(dev);
@@ -5267,6 +5366,7 @@ bool intel_display_power_enabled(struct drm_device *dev,
         case POWER_DOMAIN_PIPE_A:
         case POWER_DOMAIN_TRANSCODER_EDP:
                 return true;
+        case POWER_DOMAIN_VGA:
         case POWER_DOMAIN_PIPE_B:
         case POWER_DOMAIN_PIPE_C:
         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
@@ -5323,12 +5423,87 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
                         spin_lock_irqsave(&dev->vbl_lock, irqflags);
                         for_each_pipe(p)
                                 if (p != PIPE_A)
-                                        dev->last_vblank[p] = 0;
+                                        dev->vblank[p].last = 0;
                         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
                 }
         }
 }
 
+static void __intel_power_well_get(struct i915_power_well *power_well)
+{
+        if (!power_well->count++)
+                __intel_set_power_well(power_well->device, true);
+}
+
+static void __intel_power_well_put(struct i915_power_well *power_well)
+{
+        WARN_ON(!power_well->count);
+        if (!--power_well->count)
+                __intel_set_power_well(power_well->device, false);
+}
+
+void intel_display_power_get(struct drm_device *dev,
+                             enum intel_display_power_domain domain)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct i915_power_well *power_well = &dev_priv->power_well;
+
+        if (!HAS_POWER_WELL(dev))
+                return;
+
+        switch (domain) {
+        case POWER_DOMAIN_PIPE_A:
+        case POWER_DOMAIN_TRANSCODER_EDP:
+                return;
+        case POWER_DOMAIN_VGA:
+        case POWER_DOMAIN_PIPE_B:
+        case POWER_DOMAIN_PIPE_C:
+        case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
+        case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
+        case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
+        case POWER_DOMAIN_TRANSCODER_A:
+        case POWER_DOMAIN_TRANSCODER_B:
+        case POWER_DOMAIN_TRANSCODER_C:
+                spin_lock_irq(&power_well->lock);
+                __intel_power_well_get(power_well);
+                spin_unlock_irq(&power_well->lock);
+                return;
+        default:
+                BUG();
+        }
+}
+
+void intel_display_power_put(struct drm_device *dev,
+                             enum intel_display_power_domain domain)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct i915_power_well *power_well = &dev_priv->power_well;
+
+        if (!HAS_POWER_WELL(dev))
+                return;
+
+        switch (domain) {
+        case POWER_DOMAIN_PIPE_A:
+        case POWER_DOMAIN_TRANSCODER_EDP:
+                return;
+        case POWER_DOMAIN_VGA:
+        case POWER_DOMAIN_PIPE_B:
+        case POWER_DOMAIN_PIPE_C:
+        case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
+        case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
+        case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
+        case POWER_DOMAIN_TRANSCODER_A:
+        case POWER_DOMAIN_TRANSCODER_B:
+        case POWER_DOMAIN_TRANSCODER_C:
+                spin_lock_irq(&power_well->lock);
+                __intel_power_well_put(power_well);
+                spin_unlock_irq(&power_well->lock);
+                return;
+        default:
+                BUG();
+        }
+}
+
 static struct i915_power_well *hsw_pwr;
 
 /* Display audio driver power well request */
@@ -5338,9 +5513,7 @@ void i915_request_power_well(void)
                 return;
 
         spin_lock_irq(&hsw_pwr->lock);
-        if (!hsw_pwr->count++ &&
-                        !hsw_pwr->i915_request)
-                __intel_set_power_well(hsw_pwr->device, true);
+        __intel_power_well_get(hsw_pwr);
         spin_unlock_irq(&hsw_pwr->lock);
 }
 EXPORT_SYMBOL_GPL(i915_request_power_well);
@@ -5352,10 +5525,7 @@ void i915_release_power_well(void)
                 return;
 
         spin_lock_irq(&hsw_pwr->lock);
-        WARN_ON(!hsw_pwr->count);
-        if (!--hsw_pwr->count &&
-                       !hsw_pwr->i915_request)
-                __intel_set_power_well(hsw_pwr->device, false);
+        __intel_power_well_put(hsw_pwr);
         spin_unlock_irq(&hsw_pwr->lock);
 }
 EXPORT_SYMBOL_GPL(i915_release_power_well);
@@ -5390,15 +5560,37 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
                 return;
 
         spin_lock_irq(&power_well->lock);
+
+        /*
+         * This function will only ever contribute one
+         * to the power well reference count. i915_request
+         * is what tracks whether we have or have not
+         * added the one to the reference count.
+         */
+        if (power_well->i915_request == enable)
+                goto out;
+
         power_well->i915_request = enable;
 
-        /* only reject "disable" power well request */
-        if (power_well->count && !enable) {
-                spin_unlock_irq(&power_well->lock);
+        if (enable)
+                __intel_power_well_get(power_well);
+        else
+                __intel_power_well_put(power_well);
+
+ out:
+        spin_unlock_irq(&power_well->lock);
+}
+
+static void intel_resume_power_well(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct i915_power_well *power_well = &dev_priv->power_well;
+
+        if (!HAS_POWER_WELL(dev))
                 return;
-        }
 
-        __intel_set_power_well(dev, enable);
+        spin_lock_irq(&power_well->lock);
+        __intel_set_power_well(dev, power_well->count > 0);
         spin_unlock_irq(&power_well->lock);
 }
 
@@ -5417,6 +5609,7 @@ void intel_init_power_well(struct drm_device *dev)
 
         /* For now, we need the power well to be always enabled. */
         intel_set_power_well(dev, true);
+        intel_resume_power_well(dev);
 
         /* We're taking over the BIOS, so clear any requests made by it since
          * the driver is in charge now. */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 460ee1026fca..b67104aaade5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -41,6 +41,16 @@ static inline int ring_space(struct intel_ring_buffer *ring)
         return space;
 }
 
+void __intel_ring_advance(struct intel_ring_buffer *ring)
+{
+        struct drm_i915_private *dev_priv = ring->dev->dev_private;
+
+        ring->tail &= ring->size - 1;
+        if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
+                return;
+        ring->write_tail(ring, ring->tail);
+}
+
 static int
 gen2_render_ring_flush(struct intel_ring_buffer *ring,
                        u32      invalidate_domains,
@@ -559,8 +569,8 @@ static int init_render_ring(struct intel_ring_buffer *ring)
         if (INTEL_INFO(dev)->gen >= 6)
                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-        if (HAS_L3_GPU_CACHE(dev))
-                I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+        if (HAS_L3_DPF(dev))
+                I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 
         return ret;
 }
@@ -593,7 +603,7 @@ update_mboxes(struct intel_ring_buffer *ring,
 #define MBOX_UPDATE_DWORDS 4
         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
         intel_ring_emit(ring, mmio_offset);
-        intel_ring_emit(ring, ring->outstanding_lazy_request);
+        intel_ring_emit(ring, ring->outstanding_lazy_seqno);
         intel_ring_emit(ring, MI_NOOP);
 }
 
@@ -629,9 +639,9 @@ gen6_add_request(struct intel_ring_buffer *ring)
 
         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
-        intel_ring_emit(ring, ring->outstanding_lazy_request);
+        intel_ring_emit(ring, ring->outstanding_lazy_seqno);
         intel_ring_emit(ring, MI_USER_INTERRUPT);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
 
         return 0;
 }
@@ -723,7 +733,7 @@ pc_render_add_request(struct intel_ring_buffer *ring)
                         PIPE_CONTROL_WRITE_FLUSH |
                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
-        intel_ring_emit(ring, ring->outstanding_lazy_request);
+        intel_ring_emit(ring, ring->outstanding_lazy_seqno);
         intel_ring_emit(ring, 0);
         PIPE_CONTROL_FLUSH(ring, scratch_addr);
         scratch_addr += 128; /* write to separate cachelines */
@@ -742,9 +752,9 @@ pc_render_add_request(struct intel_ring_buffer *ring)
                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
                         PIPE_CONTROL_NOTIFY);
         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
-        intel_ring_emit(ring, ring->outstanding_lazy_request);
+        intel_ring_emit(ring, ring->outstanding_lazy_seqno);
         intel_ring_emit(ring, 0);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
 
         return 0;
 }
@@ -963,9 +973,9 @@ i9xx_add_request(struct intel_ring_buffer *ring)
 
         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
-        intel_ring_emit(ring, ring->outstanding_lazy_request);
+        intel_ring_emit(ring, ring->outstanding_lazy_seqno);
         intel_ring_emit(ring, MI_USER_INTERRUPT);
-        intel_ring_advance(ring);
+        __intel_ring_advance(ring);
 
         return 0;
 }
@@ -987,10 +997,10 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (ring->irq_refcount++ == 0) {
-                if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
+                if (HAS_L3_DPF(dev) && ring->id == RCS)
                         I915_WRITE_IMR(ring,
                                        ~(ring->irq_enable_mask |
-                                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
+                                         GT_PARITY_ERROR(dev)));
                 else
                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
@@ -1009,9 +1019,8 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (--ring->irq_refcount == 0) {
-                if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
-                        I915_WRITE_IMR(ring,
-                                       ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+                if (HAS_L3_DPF(dev) && ring->id == RCS)
+                        I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
                 else
                         I915_WRITE_IMR(ring, ~0);
                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
@@ -1414,6 +1423,9 @@ static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
         if (ret != -ENOSPC)
                 return ret;
 
+        /* force the tail write in case we have been skipping them */
+        __intel_ring_advance(ring);
+
         trace_i915_ring_wait_begin(ring);
         /* With GEM the hangcheck timer should kick us out of the loop,
          * leaving it early runs the risk of corrupting GEM state (due
@@ -1475,7 +1487,7 @@ int intel_ring_idle(struct intel_ring_buffer *ring)
         int ret;
 
         /* We need to add any requests required to flush the objects and ring */
-        if (ring->outstanding_lazy_request) {
+        if (ring->outstanding_lazy_seqno) {
                 ret = i915_add_request(ring, NULL);
                 if (ret)
                         return ret;
@@ -1495,10 +1507,20 @@ int intel_ring_idle(struct intel_ring_buffer *ring)
 static int
 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
 {
-        if (ring->outstanding_lazy_request)
+        if (ring->outstanding_lazy_seqno)
                 return 0;
 
-        return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
+        if (ring->preallocated_lazy_request == NULL) {
+                struct drm_i915_gem_request *request;
+
+                request = kmalloc(sizeof(*request), GFP_KERNEL);
+                if (request == NULL)
+                        return -ENOMEM;
+
+                ring->preallocated_lazy_request = request;
+        }
+
+        return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
 }
 
 static int __intel_ring_begin(struct intel_ring_buffer *ring,
@@ -1545,7 +1567,7 @@ void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
 {
         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 
-        BUG_ON(ring->outstanding_lazy_request);
+        BUG_ON(ring->outstanding_lazy_seqno);
 
         if (INTEL_INFO(ring->dev)->gen >= 6) {
                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
@@ -1558,17 +1580,6 @@ void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
         ring->hangcheck.seqno = seqno;
 }
 
-void intel_ring_advance(struct intel_ring_buffer *ring)
-{
-        struct drm_i915_private *dev_priv = ring->dev->dev_private;
-
-        ring->tail &= ring->size - 1;
-        if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
-                return;
-        ring->write_tail(ring, ring->tail);
-}
-
-
 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
                                      u32 value)
 {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 68b1ca974d59..71a73f4fe252 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -34,6 +34,7 @@ struct  intel_hw_status_page {
 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 
 enum intel_ring_hangcheck_action {
+        HANGCHECK_IDLE = 0,
         HANGCHECK_WAIT,
         HANGCHECK_ACTIVE,
         HANGCHECK_KICK,
@@ -140,7 +141,8 @@ struct  intel_ring_buffer {
         /**
          * Do we have some not yet emitted requests outstanding?
          */
-        u32 outstanding_lazy_request;
+        struct drm_i915_gem_request *preallocated_lazy_request;
+        u32 outstanding_lazy_seqno;
         bool gpu_caches_dirty;
         bool fbc_dirty;
 
@@ -237,7 +239,12 @@ static inline void intel_ring_emit(struct intel_ring_buffer *ring,
         iowrite32(data, ring->virtual_start + ring->tail);
         ring->tail += 4;
 }
-void intel_ring_advance(struct intel_ring_buffer *ring);
+static inline void intel_ring_advance(struct intel_ring_buffer *ring)
+{
+        ring->tail &= ring->size - 1;
+}
+void __intel_ring_advance(struct intel_ring_buffer *ring);
+
 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
@@ -258,8 +265,8 @@ static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
 
 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
 {
-        BUG_ON(ring->outstanding_lazy_request == 0);
-        return ring->outstanding_lazy_request;
+        BUG_ON(ring->outstanding_lazy_seqno == 0);
+        return ring->outstanding_lazy_seqno;
 }
 
 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 49482fd5b76c..a583e8f718a7 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -539,7 +539,7 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
                 goto log_fail;
 
         while ((status == SDVO_CMD_STATUS_PENDING ||
-                        status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
+                status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
                 if (retry < 10)
                         msleep(15);
                 else
@@ -1068,7 +1068,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
 
 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
 {
-        unsigned dotclock = pipe_config->adjusted_mode.clock;
+        unsigned dotclock = pipe_config->port_clock;
         struct dpll *clock = &pipe_config->dpll;
 
         /* SDVO TV has fixed PLL values depend on its clock range,
@@ -1133,7 +1133,6 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
          */
         pipe_config->pixel_multiplier =
                 intel_sdvo_get_pixel_multiplier(adjusted_mode);
-        adjusted_mode->clock *= pipe_config->pixel_multiplier;
 
         if (intel_sdvo->color_range_auto) {
                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
@@ -1217,11 +1216,7 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
             !intel_sdvo_set_tv_format(intel_sdvo))
                 return;
 
-        /* We have tried to get input timing in mode_fixup, and filled into
-         * adjusted_mode.
-         */
         intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
-        input_dtd.part1.clock /= crtc->config.pixel_multiplier;
 
         if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
                 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
@@ -1330,6 +1325,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
         struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
         struct intel_sdvo_dtd dtd;
         int encoder_pixel_multiplier = 0;
+        int dotclock;
         u32 flags = 0, sdvox;
         u8 val;
         bool ret;
@@ -1368,6 +1364,13 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
                          >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
         }
 
+        dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
+
+        if (HAS_PCH_SPLIT(dev))
+                ironlake_check_encoder_dotclock(pipe_config, dotclock);
+
+        pipe_config->adjusted_mode.crtc_clock = dotclock;
+
         /* Cross check the port pixel multiplier with the sdvo encoder state. */
         if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
                                  &val, 1)) {
@@ -1770,6 +1773,9 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
 {
         struct edid *edid;
 
+        DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
+                      connector->base.id, drm_get_connector_name(connector));
+
         /* set the bus switch and get the modes */
         edid = intel_sdvo_get_edid(connector);
 
@@ -1865,6 +1871,9 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
         uint32_t reply = 0, format_map = 0;
         int i;
 
+        DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
+                      connector->base.id, drm_get_connector_name(connector));
+
         /* Read the list of supported input resolutions for the selected TV
          * format.
          */
@@ -1899,6 +1908,9 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
         struct drm_i915_private *dev_priv = connector->dev->dev_private;
         struct drm_display_mode *newmode;
 
+        DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
+                      connector->base.id, drm_get_connector_name(connector));
+
         /*
          * Fetch modes from VBT. For SDVO prefer the VBT mode since some
          * SDVO->LVDS transcoders can't cope with the EDID mode.
@@ -1930,7 +1942,6 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
                         break;
                 }
         }
-
 }
 
 static int intel_sdvo_get_modes(struct drm_connector *connector)
@@ -1998,7 +2009,6 @@ static void intel_sdvo_destroy(struct drm_connector *connector)
                                      intel_sdvo_connector->tv_format);
 
         intel_sdvo_destroy_enhance_property(connector);
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(intel_sdvo_connector);
 }
@@ -2394,7 +2404,9 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
         struct intel_connector *intel_connector;
         struct intel_sdvo_connector *intel_sdvo_connector;
 
-        intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
+        DRM_DEBUG_KMS("initialising DVI device %d\n", device);
+
+        intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
         if (!intel_sdvo_connector)
                 return false;
 
@@ -2442,7 +2454,9 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
         struct intel_connector *intel_connector;
         struct intel_sdvo_connector *intel_sdvo_connector;
 
-        intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
+        DRM_DEBUG_KMS("initialising TV type %d\n", type);
+
+        intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
         if (!intel_sdvo_connector)
                 return false;
 
@@ -2467,6 +2481,7 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
         return true;
 
 err:
+        drm_sysfs_connector_remove(connector);
         intel_sdvo_destroy(connector);
         return false;
 }
@@ -2479,7 +2494,9 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
         struct intel_connector *intel_connector;
         struct intel_sdvo_connector *intel_sdvo_connector;
 
-        intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
+        DRM_DEBUG_KMS("initialising analog device %d\n", device);
+
+        intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
         if (!intel_sdvo_connector)
                 return false;
 
@@ -2510,7 +2527,9 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
         struct intel_connector *intel_connector;
         struct intel_sdvo_connector *intel_sdvo_connector;
 
-        intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
+        DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
+
+        intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
         if (!intel_sdvo_connector)
                 return false;
 
@@ -2534,6 +2553,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
         return true;
 
 err:
+        drm_sysfs_connector_remove(connector);
         intel_sdvo_destroy(connector);
         return false;
 }
@@ -2605,8 +2625,10 @@ static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
 
         list_for_each_entry_safe(connector, tmp,
                                  &dev->mode_config.connector_list, head) {
-                if (intel_attached_encoder(connector) == &intel_sdvo->base)
+                if (intel_attached_encoder(connector) == &intel_sdvo->base) {
+                        drm_sysfs_connector_remove(connector);
                         intel_sdvo_destroy(connector);
+                }
         }
 }
 
@@ -2876,7 +2898,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
         struct intel_encoder *intel_encoder;
         struct intel_sdvo *intel_sdvo;
         int i;
-        intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
+        intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
         if (!intel_sdvo)
                 return false;
 
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 9a0e6c5ea540..acd1cfe8b7dd 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -101,19 +101,83 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
         return val;
 }
 
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
+u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
 {
         u32 val = 0;
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
+                        PUNIT_OPCODE_REG_READ, reg, &val);
+        return val;
+}
 
-        vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
-                        DPIO_OPCODE_REG_READ, reg, &val);
+void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
+                        PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
+u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+        u32 val = 0;
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
+                        PUNIT_OPCODE_REG_READ, reg, &val);
+        return val;
+}
+
+void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
+                        PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+        u32 val = 0;
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
+                        PUNIT_OPCODE_REG_READ, reg, &val);
+        return val;
+}
+
+void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
+                        PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
+u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+        u32 val = 0;
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
+                        PUNIT_OPCODE_REG_READ, reg, &val);
+        return val;
+}
+
+void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+        vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
+                        PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
 
+static u32 vlv_get_phy_port(enum pipe pipe)
+{
+        u32 port = IOSF_PORT_DPIO;
+
+        WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
+
+        return port;
+}
+
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
+{
+        u32 val = 0;
+
+        vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
+                        DPIO_OPCODE_REG_READ, reg, &val);
         return val;
 }
 
-void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
+void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
 {
-        vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
+        vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
                         DPIO_OPCODE_REG_WRITE, reg, &val);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index ad6ec4b39005..cae10bc746d0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -288,7 +288,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
                 dev_priv->sprite_scaling_enabled |= 1 << pipe;
 
                 if (!scaling_was_enabled) {
-                        intel_update_watermarks(dev);
+                        intel_update_watermarks(crtc);
                         intel_wait_for_vblank(dev, pipe);
                 }
                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
@@ -323,7 +323,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
         /* potentially re-enable LP watermarks */
         if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
-                intel_update_watermarks(dev);
+                intel_update_watermarks(crtc);
 }
 
 static void
@@ -349,7 +349,7 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 
         /* potentially re-enable LP watermarks */
         if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
-                intel_update_watermarks(dev);
+                intel_update_watermarks(crtc);
 }
 
 static int
@@ -652,8 +652,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
                 .y2 = crtc_y + crtc_h,
         };
         const struct drm_rect clip = {
-                .x2 = crtc->mode.hdisplay,
-                .y2 = crtc->mode.vdisplay,
+                .x2 = intel_crtc->config.pipe_src_w,
+                .y2 = intel_crtc->config.pipe_src_h,
         };
 
         intel_fb = to_intel_framebuffer(fb);
@@ -1034,7 +1034,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
         if (INTEL_INFO(dev)->gen < 5)
                 return -ENODEV;
 
-        intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
+        intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
         if (!intel_plane)
                 return -ENOMEM;
 
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index dd6f84bf6c22..d61aec23a523 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -912,7 +912,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
         if (!tv_mode)
                 return false;
 
-        pipe_config->adjusted_mode.clock = tv_mode->clock;
+        pipe_config->adjusted_mode.crtc_clock = tv_mode->clock;
         DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
         pipe_config->pipe_bpp = 8*3;
 
@@ -1044,7 +1044,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
                 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
 
         /* Enable two fixes for the chips that need them. */
-        if (dev->pci_device < 0x2772)
+        if (dev->pdev->device < 0x2772)
                 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
 
         I915_WRITE(TV_H_CTL_1, hctl1);
@@ -1433,7 +1433,6 @@ intel_tv_get_modes(struct drm_connector *connector)
 static void
 intel_tv_destroy(struct drm_connector *connector)
 {
-        drm_sysfs_connector_remove(connector);
         drm_connector_cleanup(connector);
         kfree(connector);
 }
@@ -1518,7 +1517,7 @@ static const struct drm_encoder_funcs intel_tv_enc_funcs = {
 static int tv_is_present_in_vbt(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct child_device_config *p_child;
+        union child_device_config *p_child;
         int i, ret;
 
         if (!dev_priv->vbt.child_dev_num)
@@ -1530,13 +1529,13 @@ static int tv_is_present_in_vbt(struct drm_device *dev)
                 /*
                  * If the device type is not TV, continue.
                  */
-                if (p_child->device_type != DEVICE_TYPE_INT_TV &&
-                        p_child->device_type != DEVICE_TYPE_TV)
+                if (p_child->old.device_type != DEVICE_TYPE_INT_TV &&
+                        p_child->old.device_type != DEVICE_TYPE_TV)
                         continue;
                 /* Only when the addin_offset is non-zero, it is regarded
                  * as present.
                  */
-                if (p_child->addin_offset) {
+                if (p_child->old.addin_offset) {
                         ret = 1;
                         break;
                 }
@@ -1590,12 +1589,12 @@ intel_tv_init(struct drm_device *dev)
             (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
                 return;
 
-        intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
+        intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
         if (!intel_tv) {
                 return;
         }
 
-        intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
+        intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
         if (!intel_connector) {
                 kfree(intel_tv);
                 return;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8649f1c36b00..288a3a654f06 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -204,6 +204,18 @@ static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
         gen6_gt_check_fifodbg(dev_priv);
 }
 
+static void gen6_force_wake_work(struct work_struct *work)
+{
+        struct drm_i915_private *dev_priv =
+                container_of(work, typeof(*dev_priv), uncore.force_wake_work.work);
+        unsigned long irqflags;
+
+        spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+        if (--dev_priv->uncore.forcewake_count == 0)
+                dev_priv->uncore.funcs.force_wake_put(dev_priv);
+        spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
 void intel_uncore_early_sanitize(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -216,6 +228,9 @@ void intel_uncore_init(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work,
+                          gen6_force_wake_work);
+
         if (IS_VALLEYVIEW(dev)) {
                 dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get;
                 dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put;
@@ -261,6 +276,16 @@ void intel_uncore_init(struct drm_device *dev)
         }
 }
 
+void intel_uncore_fini(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        flush_delayed_work(&dev_priv->uncore.force_wake_work);
+
+        /* Paranoia: make sure we have disabled everything before we exit. */
+        intel_uncore_sanitize(dev);
+}
+
 static void intel_uncore_forcewake_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -276,10 +301,26 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev)
 
 void intel_uncore_sanitize(struct drm_device *dev)
 {
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 reg_val;
+
         intel_uncore_forcewake_reset(dev);
 
         /* BIOS often leaves RC6 enabled, but disable it for hw init */
         intel_disable_gt_powersave(dev);
+
+        /* Turn off power gate, require especially for the BIOS less system */
+        if (IS_VALLEYVIEW(dev)) {
+
+                mutex_lock(&dev_priv->rps.hw_lock);
+                reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
+
+                if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
+                        vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
+
+                mutex_unlock(&dev_priv->rps.hw_lock);
+
+        }
 }
 
 /*
@@ -306,8 +347,12 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
         unsigned long irqflags;
 
         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-        if (--dev_priv->uncore.forcewake_count == 0)
-                dev_priv->uncore.funcs.force_wake_put(dev_priv);
+        if (--dev_priv->uncore.forcewake_count == 0) {
+                dev_priv->uncore.forcewake_count++;
+                mod_delayed_work(dev_priv->wq,
+                                 &dev_priv->uncore.force_wake_work,
+                                 1);
+        }
         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index cc3166dd445a..087db33f6cff 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -406,11 +406,6 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags)
         dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
         dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);
 
-        dev->counters += 3;
-        dev->types[6] = _DRM_STAT_IRQ;
-        dev->types[7] = _DRM_STAT_PRIMARY;
-        dev->types[8] = _DRM_STAT_SECONDARY;
-
         ret = drm_vblank_init(dev, 1);
 
         if (ret) {
diff --git a/drivers/gpu/drm/mga/mga_irq.c b/drivers/gpu/drm/mga/mga_irq.c
index 598c281def0a..2b0ceb8dc11b 100644
--- a/drivers/gpu/drm/mga/mga_irq.c
+++ b/drivers/gpu/drm/mga/mga_irq.c
@@ -169,5 +169,5 @@ void mga_driver_irq_uninstall(struct drm_device *dev)
         /* Disable *all* interrupts */
         MGA_WRITE(MGA_IEN, 0);
 
-        dev->irq_enabled = 0;
+        dev->irq_enabled = false;
 }
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c
index fcce7b2f8011..f15ea3c4a90a 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -99,7 +99,6 @@ static struct drm_driver driver = {
         .minor = DRIVER_MINOR,
         .patchlevel = DRIVER_PATCHLEVEL,
 
-        .gem_init_object = mgag200_gem_init_object,
         .gem_free_object = mgag200_gem_free_object,
         .dumb_create = mgag200_dumb_create,
         .dumb_map_offset = mgag200_dumb_mmap_offset,
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h
index baaae19332e2..cf11ee68a6d9 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.h
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.h
@@ -260,7 +260,6 @@ int mgag200_driver_unload(struct drm_device *dev);
 int mgag200_gem_create(struct drm_device *dev,
                    u32 size, bool iskernel,
                        struct drm_gem_object **obj);
-int mgag200_gem_init_object(struct drm_gem_object *obj);
 int mgag200_dumb_create(struct drm_file *file,
                         struct drm_device *dev,
                         struct drm_mode_create_dumb *args);
diff --git a/drivers/gpu/drm/mgag200/mgag200_main.c b/drivers/gpu/drm/mgag200/mgag200_main.c
index 0f8b861b10b3..b1120cb1db6d 100644
--- a/drivers/gpu/drm/mgag200/mgag200_main.c
+++ b/drivers/gpu/drm/mgag200/mgag200_main.c
@@ -310,12 +310,6 @@ int mgag200_dumb_create(struct drm_file *file,
         return 0;
 }
 
-int mgag200_gem_init_object(struct drm_gem_object *obj)
-{
-        BUG();
-        return 0;
-}
-
 void mgag200_bo_unref(struct mgag200_bo **bo)
 {
         struct ttm_buffer_object *tbo;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c
index 2e70462883e8..2a15b98b4d2b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/arb.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c
@@ -210,8 +210,8 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
         sim_data.nvclk_khz = NVClk;
         sim_data.bpp = bpp;
         sim_data.two_heads = nv_two_heads(dev);
-        if ((dev->pci_device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
-            (dev->pci_device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
+        if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
+            (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
                 uint32_t type;
 
                 pci_read_config_dword(pci_get_bus_and_slot(0, 1), 0x7c, &type);
@@ -256,8 +256,8 @@ nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm
 
         if (nv_device(drm->device)->card_type < NV_20)
                 nv04_update_arb(dev, vclk, bpp, burst, lwm);
-        else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
-                 (dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
+        else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
+                 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
                 *burst = 128;
                 *lwm = 0x0480;
         } else
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index d4fbf11360fe..0e3270c3ffd2 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -326,8 +326,6 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
                         regp->MiscOutReg = 0x23;        /* +hsync +vsync */
         }
 
-        regp->MiscOutReg |= (mode->clock_index & 0x03) << 2;
-
         /*
          * Time Sequencer
          */
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
index 93dd23ff0093..59d1c040b84f 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
@@ -490,8 +490,8 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
         /* BIOS scripts usually take care of the backlight, thanks
          * Apple for your consistency.
          */
-        if (dev->pci_device == 0x0174 || dev->pci_device == 0x0179 ||
-            dev->pci_device == 0x0189 || dev->pci_device == 0x0329) {
+        if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
+            dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
                 if (mode == DRM_MODE_DPMS_ON) {
                         nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
                         nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h
index 9928187f0a7d..2cf65e0b517e 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
@@ -127,7 +127,7 @@ static inline bool
 nv_two_heads(struct drm_device *dev)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        const int impl = dev->pci_device & 0x0ff0;
+        const int impl = dev->pdev->device & 0x0ff0;
 
         if (nv_device(drm->device)->card_type >= NV_10 && impl != 0x0100 &&
             impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
@@ -139,14 +139,14 @@ nv_two_heads(struct drm_device *dev)
 static inline bool
 nv_gf4_disp_arch(struct drm_device *dev)
 {
-        return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
+        return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
 }
 
 static inline bool
 nv_two_reg_pll(struct drm_device *dev)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        const int impl = dev->pci_device & 0x0ff0;
+        const int impl = dev->pdev->device & 0x0ff0;
 
         if (impl == 0x0310 || impl == 0x0340 || nv_device(drm->device)->card_type >= NV_40)
                 return true;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index 973056b86207..f8dee834527f 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -220,7 +220,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
         int ret;
 
         if (plltype == PLL_MEMORY &&
-            (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
+            (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
                 uint32_t mpllP;
 
                 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
@@ -230,7 +230,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
                 return 400000 / mpllP;
         } else
         if (plltype == PLL_MEMORY &&
-            (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
+            (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
                 uint32_t clock;
 
                 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 8f467e7bfd19..72055a35f845 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -130,7 +130,7 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16,
         if (chan->ntfy) {
                 nouveau_bo_vma_del(chan->ntfy, &chan->ntfy_vma);
                 nouveau_bo_unpin(chan->ntfy);
-                drm_gem_object_unreference_unlocked(chan->ntfy->gem);
+                drm_gem_object_unreference_unlocked(&chan->ntfy->gem);
         }
 
         if (chan->heap.block_size)
@@ -178,10 +178,10 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
                 getparam->value = device->chipset;
                 break;
         case NOUVEAU_GETPARAM_PCI_VENDOR:
-                getparam->value = dev->pci_vendor;
+                getparam->value = dev->pdev->vendor;
                 break;
         case NOUVEAU_GETPARAM_PCI_DEVICE:
-                getparam->value = dev->pci_device;
+                getparam->value = dev->pdev->device;
                 break;
         case NOUVEAU_GETPARAM_BUS_TYPE:
                 if (drm_pci_device_is_agp(dev))
@@ -320,7 +320,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
                         goto done;
         }
 
-        ret = drm_gem_handle_create(file_priv, chan->ntfy->gem,
+        ret = drm_gem_handle_create(file_priv, &chan->ntfy->gem,
                                     &init->notifier_handle);
         if (ret)
                 goto done;
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 2ffad2176b7f..630f6e84fc01 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -82,7 +82,7 @@ nv40_backlight_init(struct drm_connector *connector)
         memset(&props, 0, sizeof(struct backlight_properties));
         props.type = BACKLIGHT_RAW;
         props.max_brightness = 31;
-        bd = backlight_device_register("nv_backlight", &connector->kdev, drm,
+        bd = backlight_device_register("nv_backlight", connector->kdev, drm,
                                        &nv40_bl_ops, &props);
         if (IS_ERR(bd))
                 return PTR_ERR(bd);
@@ -204,7 +204,7 @@ nv50_backlight_init(struct drm_connector *connector)
         memset(&props, 0, sizeof(struct backlight_properties));
         props.type = BACKLIGHT_RAW;
         props.max_brightness = 100;
-        bd = backlight_device_register("nv_backlight", &connector->kdev,
+        bd = backlight_device_register("nv_backlight", connector->kdev,
                                        nv_encoder, ops, &props);
         if (IS_ERR(bd))
                 return PTR_ERR(bd);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 3e7287675ecf..4c3feaaa1037 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -127,8 +127,8 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_outp
 #ifdef __powerpc__
         /* Powerbook specific quirks */
         if (script == LVDS_RESET &&
-            (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
-             dev->pci_device == 0x0329))
+            (dev->pdev->device == 0x0179 || dev->pdev->device == 0x0189 ||
+             dev->pdev->device == 0x0329))
                 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
 #endif
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 755c38d06271..4172854d4365 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -146,7 +146,7 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
         struct drm_device *dev = drm->dev;
         struct nouveau_bo *nvbo = nouveau_bo(bo);
 
-        if (unlikely(nvbo->gem))
+        if (unlikely(nvbo->gem.filp))
                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
         WARN_ON(nvbo->pin_refcnt > 0);
         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
@@ -1267,7 +1267,7 @@ nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 {
         struct nouveau_bo *nvbo = nouveau_bo(bo);
 
-        return drm_vma_node_verify_access(&nvbo->gem->vma_node, filp);
+        return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
 }
 
 static int
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h
index 653dbbbd4fa1..ff17c1f432fc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -27,7 +27,10 @@ struct nouveau_bo {
         u32 tile_flags;
         struct nouveau_drm_tile *tile;
 
-        struct drm_gem_object *gem;
+        /* Only valid if allocated via nouveau_gem_new() and iff you hold a
+         * gem reference to it! For debugging, use gem.filp != NULL to test
+         * whether it is valid. */
+        struct drm_gem_object gem;
 
         /* protect by the ttm reservation lock */
         int pin_refcnt;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index c5b36f9e9a10..2136d0038252 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -215,8 +215,8 @@ nouveau_connector_set_encoder(struct drm_connector *connector,
                 connector->doublescan_allowed = true;
                 if (nv_device(drm->device)->card_type == NV_20 ||
                    (nv_device(drm->device)->card_type == NV_10 &&
-                    (dev->pci_device & 0x0ff0) != 0x0100 &&
-                    (dev->pci_device & 0x0ff0) != 0x0150))
+                    (dev->pdev->device & 0x0ff0) != 0x0100 &&
+                    (dev->pdev->device & 0x0ff0) != 0x0150))
                         /* HW is broken */
                         connector->interlace_allowed = false;
                 else
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 7848590f5568..bdd5cf71a24c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -50,7 +50,7 @@ nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb)
         struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
 
         if (fb->nvbo)
-                drm_gem_object_unreference_unlocked(fb->nvbo->gem);
+                drm_gem_object_unreference_unlocked(&fb->nvbo->gem);
 
         drm_framebuffer_cleanup(drm_fb);
         kfree(fb);
@@ -63,7 +63,7 @@ nouveau_user_framebuffer_create_handle(struct drm_framebuffer *drm_fb,
 {
         struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
 
-        return drm_gem_handle_create(file_priv, fb->nvbo->gem, handle);
+        return drm_gem_handle_create(file_priv, &fb->nvbo->gem, handle);
 }
 
 static const struct drm_framebuffer_funcs nouveau_framebuffer_funcs = {
@@ -674,8 +674,8 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
         if (ret)
                 return ret;
 
-        ret = drm_gem_handle_create(file_priv, bo->gem, &args->handle);
-        drm_gem_object_unreference_unlocked(bo->gem);
+        ret = drm_gem_handle_create(file_priv, &bo->gem, &args->handle);
+        drm_gem_object_unreference_unlocked(&bo->gem);
         return ret;
 }
 
@@ -688,7 +688,7 @@ nouveau_display_dumb_map_offset(struct drm_file *file_priv,
 
         gem = drm_gem_object_lookup(dev, file_priv, handle);
         if (gem) {
-                struct nouveau_bo *bo = gem->driver_private;
+                struct nouveau_bo *bo = nouveau_gem_object(gem);
                 *poffset = drm_vma_node_offset_addr(&bo->bo.vma_node);
                 drm_gem_object_unreference_unlocked(gem);
                 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index e893c5362402..428d818be775 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -834,7 +834,6 @@ driver = {
         .gem_prime_vmap = nouveau_gem_prime_vmap,
         .gem_prime_vunmap = nouveau_gem_prime_vunmap,
 
-        .gem_init_object = nouveau_gem_object_new,
         .gem_free_object = nouveau_gem_object_del,
         .gem_open_object = nouveau_gem_object_open,
         .gem_close_object = nouveau_gem_object_close,
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index a86ecf65c164..c80b519b513a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -420,7 +420,7 @@ nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *fbcon)
                 nouveau_bo_unmap(nouveau_fb->nvbo);
                 nouveau_bo_vma_del(nouveau_fb->nvbo, &nouveau_fb->vma);
                 nouveau_bo_unpin(nouveau_fb->nvbo);
-                drm_gem_object_unreference_unlocked(nouveau_fb->nvbo->gem);
+                drm_gem_object_unreference_unlocked(&nouveau_fb->nvbo->gem);
                 nouveau_fb->nvbo = NULL;
         }
         drm_fb_helper_fini(&fbcon->helper);
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index f32b71238c03..418a6177a653 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -34,29 +34,20 @@
 #include "nouveau_ttm.h"
 #include "nouveau_gem.h"
 
-int
-nouveau_gem_object_new(struct drm_gem_object *gem)
-{
-        return 0;
-}
-
 void
 nouveau_gem_object_del(struct drm_gem_object *gem)
 {
-        struct nouveau_bo *nvbo = gem->driver_private;
+        struct nouveau_bo *nvbo = nouveau_gem_object(gem);
         struct ttm_buffer_object *bo = &nvbo->bo;
 
-        if (!nvbo)
-                return;
-        nvbo->gem = NULL;
-
         if (gem->import_attach)
                 drm_prime_gem_destroy(gem, nvbo->bo.sg);
 
-        ttm_bo_unref(&bo);
-
         drm_gem_object_release(gem);
-        kfree(gem);
+
+        /* reset filp so nouveau_bo_del_ttm() can test for it */
+        gem->filp = NULL;
+        ttm_bo_unref(&bo);
 }
 
 int
@@ -186,14 +177,15 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain,
         if (nv_device(drm->device)->card_type >= NV_50)
                 nvbo->valid_domains &= domain;
 
-        nvbo->gem = drm_gem_object_alloc(dev, nvbo->bo.mem.size);
-        if (!nvbo->gem) {
+        /* Initialize the embedded gem-object. We return a single gem-reference
+         * to the caller, instead of a normal nouveau_bo ttm reference. */
+        ret = drm_gem_object_init(dev, &nvbo->gem, nvbo->bo.mem.size);
+        if (ret) {
                 nouveau_bo_ref(NULL, pnvbo);
                 return -ENOMEM;
         }
 
-        nvbo->bo.persistent_swap_storage = nvbo->gem->filp;
-        nvbo->gem->driver_private = nvbo;
+        nvbo->bo.persistent_swap_storage = nvbo->gem.filp;
         return 0;
 }
 
@@ -250,15 +242,15 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
         if (ret)
                 return ret;
 
-        ret = drm_gem_handle_create(file_priv, nvbo->gem, &req->info.handle);
+        ret = drm_gem_handle_create(file_priv, &nvbo->gem, &req->info.handle);
         if (ret == 0) {
-                ret = nouveau_gem_info(file_priv, nvbo->gem, &req->info);
+                ret = nouveau_gem_info(file_priv, &nvbo->gem, &req->info);
                 if (ret)
                         drm_gem_handle_delete(file_priv, req->info.handle);
         }
 
         /* drop reference from allocate - handle holds it now */
-        drm_gem_object_unreference_unlocked(nvbo->gem);
+        drm_gem_object_unreference_unlocked(&nvbo->gem);
         return ret;
 }
 
@@ -266,7 +258,7 @@ static int
 nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains,
                        uint32_t write_domains, uint32_t valid_domains)
 {
-        struct nouveau_bo *nvbo = gem->driver_private;
+        struct nouveau_bo *nvbo = nouveau_gem_object(gem);
         struct ttm_buffer_object *bo = &nvbo->bo;
         uint32_t domains = valid_domains & nvbo->valid_domains &
                 (write_domains ? write_domains : read_domains);
@@ -327,7 +319,7 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence,
                 list_del(&nvbo->entry);
                 nvbo->reserved_by = NULL;
                 ttm_bo_unreserve_ticket(&nvbo->bo, ticket);
-                drm_gem_object_unreference_unlocked(nvbo->gem);
+                drm_gem_object_unreference_unlocked(&nvbo->gem);
         }
 }
 
@@ -376,7 +368,7 @@ retry:
                         validate_fini(op, NULL);
                         return -ENOENT;
                 }
-                nvbo = gem->driver_private;
+                nvbo = nouveau_gem_object(gem);
                 if (nvbo == res_bo) {
                         res_bo = NULL;
                         drm_gem_object_unreference_unlocked(gem);
@@ -478,7 +470,7 @@ validate_list(struct nouveau_channel *chan, struct nouveau_cli *cli,
                         return ret;
                 }
 
-                ret = nouveau_gem_set_domain(nvbo->gem, b->read_domains,
+                ret = nouveau_gem_set_domain(&nvbo->gem, b->read_domains,
                                              b->write_domains,
                                              b->valid_domains);
                 if (unlikely(ret)) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h
index 502e4290aa8f..7caca057bc38 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.h
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.h
@@ -12,14 +12,13 @@
 static inline struct nouveau_bo *
 nouveau_gem_object(struct drm_gem_object *gem)
 {
-        return gem ? gem->driver_private : NULL;
+        return gem ? container_of(gem, struct nouveau_bo, gem) : NULL;
 }
 
 /* nouveau_gem.c */
 extern int nouveau_gem_new(struct drm_device *, int size, int align,
                            uint32_t domain, uint32_t tile_mode,
                            uint32_t tile_flags, struct nouveau_bo **);
-extern int nouveau_gem_object_new(struct drm_gem_object *);
 extern void nouveau_gem_object_del(struct drm_gem_object *);
 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
 extern void nouveau_gem_object_close(struct drm_gem_object *,
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index e90468d5e5c0..51a2cb102b44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -71,14 +71,16 @@ struct drm_gem_object *nouveau_gem_prime_import_sg_table(struct drm_device *dev,
                 return ERR_PTR(ret);
 
         nvbo->valid_domains = NOUVEAU_GEM_DOMAIN_GART;
-        nvbo->gem = drm_gem_object_alloc(dev, nvbo->bo.mem.size);
-        if (!nvbo->gem) {
+
+        /* Initialize the embedded gem-object. We return a single gem-reference
+         * to the caller, instead of a normal nouveau_bo ttm reference. */
+        ret = drm_gem_object_init(dev, &nvbo->gem, nvbo->bo.mem.size);
+        if (ret) {
                 nouveau_bo_ref(NULL, &nvbo);
                 return ERR_PTR(-ENOMEM);
         }
 
-        nvbo->gem->driver_private = nvbo;
-        return nvbo->gem;
+        return &nvbo->gem;
 }
 
 int nouveau_gem_prime_pin(struct drm_gem_object *obj)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 2603d909f49c..e7fa3cd96743 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -620,7 +620,6 @@ static struct drm_driver omap_drm_driver = {
                 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
                 .gem_prime_export = omap_gem_prime_export,
                 .gem_prime_import = omap_gem_prime_import,
-                .gem_init_object = omap_gem_init_object,
                 .gem_free_object = omap_gem_free_object,
                 .gem_vm_ops = &omap_gem_vm_ops,
                 .dumb_create = omap_gem_dumb_create,
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index 30b95b736658..07847693cf49 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -220,7 +220,6 @@ struct drm_gem_object *omap_gem_new(struct drm_device *dev,
 int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file,
                 union omap_gem_size gsize, uint32_t flags, uint32_t *handle);
 void omap_gem_free_object(struct drm_gem_object *obj);
-int omap_gem_init_object(struct drm_gem_object *obj);
 void *omap_gem_vaddr(struct drm_gem_object *obj);
 int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
                 uint32_t handle, uint64_t *offset);
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c
index 533f6ebec531..5aec3e81fe24 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -1274,11 +1274,6 @@ unlock:
         return ret;
 }
 
-int omap_gem_init_object(struct drm_gem_object *obj)
-{
-        return -EINVAL;          /* unused */
-}
-
 /* don't call directly.. called from GEM core when it is time to actually
  * free the object..
  */
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c
index 9263db117ff8..cb858600185f 100644
--- a/drivers/gpu/drm/omapdrm/omap_irq.c
+++ b/drivers/gpu/drm/omapdrm/omap_irq.c
@@ -261,7 +261,7 @@ int omap_drm_irq_install(struct drm_device *dev)
                 mutex_unlock(&dev->struct_mutex);
                 return -EBUSY;
         }
-        dev->irq_enabled = 1;
+        dev->irq_enabled = true;
         mutex_unlock(&dev->struct_mutex);
 
         /* Before installing handler */
@@ -272,7 +272,7 @@ int omap_drm_irq_install(struct drm_device *dev)
 
         if (ret < 0) {
                 mutex_lock(&dev->struct_mutex);
-                dev->irq_enabled = 0;
+                dev->irq_enabled = false;
                 mutex_unlock(&dev->struct_mutex);
                 return ret;
         }
@@ -283,7 +283,7 @@ int omap_drm_irq_install(struct drm_device *dev)
 
         if (ret < 0) {
                 mutex_lock(&dev->struct_mutex);
-                dev->irq_enabled = 0;
+                dev->irq_enabled = false;
                 mutex_unlock(&dev->struct_mutex);
                 dispc_free_irq(dev);
         }
@@ -294,11 +294,12 @@ int omap_drm_irq_install(struct drm_device *dev)
 int omap_drm_irq_uninstall(struct drm_device *dev)
 {
         unsigned long irqflags;
-        int irq_enabled, i;
+        bool irq_enabled;
+        int i;
 
         mutex_lock(&dev->struct_mutex);
         irq_enabled = dev->irq_enabled;
-        dev->irq_enabled = 0;
+        dev->irq_enabled = false;
         mutex_unlock(&dev->struct_mutex);
 
         /*
@@ -307,9 +308,9 @@ int omap_drm_irq_uninstall(struct drm_device *dev)
         if (dev->num_crtcs) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
                 for (i = 0; i < dev->num_crtcs; i++) {
-                        DRM_WAKEUP(&dev->vbl_queue[i]);
-                        dev->vblank_enabled[i] = 0;
-                        dev->last_vblank[i] =
+                        DRM_WAKEUP(&dev->vblank[i].queue);
+                        dev->vblank[i].enabled = false;
+                        dev->vblank[i].last =
                                 dev->driver->get_vblank_counter(dev, i);
                 }
                 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c
index 514118ae72d4..fee8748bdca5 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.c
+++ b/drivers/gpu/drm/qxl/qxl_drv.c
@@ -225,7 +225,6 @@ static struct drm_driver qxl_driver = {
         .debugfs_init = qxl_debugfs_init,
         .debugfs_cleanup = qxl_debugfs_takedown,
 #endif
-        .gem_init_object = qxl_gem_object_init,
         .gem_free_object = qxl_gem_object_free,
         .gem_open_object = qxl_gem_object_open,
         .gem_close_object = qxl_gem_object_close,
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index f7c9adde46a0..41d22ed26060 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -412,7 +412,6 @@ int qxl_gem_object_create_with_handle(struct qxl_device *qdev,
                                       struct qxl_surface *surf,
                                       struct qxl_bo **qobj,
                                       uint32_t *handle);
-int qxl_gem_object_init(struct drm_gem_object *obj);
 void qxl_gem_object_free(struct drm_gem_object *gobj);
 int qxl_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv);
 void qxl_gem_object_close(struct drm_gem_object *obj,
diff --git a/drivers/gpu/drm/qxl/qxl_gem.c b/drivers/gpu/drm/qxl/qxl_gem.c
index 1648e4125af7..b96f0c9d89b2 100644
--- a/drivers/gpu/drm/qxl/qxl_gem.c
+++ b/drivers/gpu/drm/qxl/qxl_gem.c
@@ -28,12 +28,6 @@
 #include "qxl_drv.h"
 #include "qxl_object.h"
 
-int qxl_gem_object_init(struct drm_gem_object *obj)
-{
-        /* we do nothings here */
-        return 0;
-}
-
 void qxl_gem_object_free(struct drm_gem_object *gobj)
 {
         struct qxl_bo *qobj = gem_to_qxl_bo(gobj);
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 00885417ffff..fb3ae07a1469 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -690,8 +690,7 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 
         /* set the lane count on the sink */
         tmp = dp_info->dp_lane_count;
-        if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
-            dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
+        if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 32923d2f6002..28e2dc48e015 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -213,7 +213,7 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
         props.type = BACKLIGHT_RAW;
         snprintf(bl_name, sizeof(bl_name),
                  "radeon_bl%d", dev->primary->index);
-        bd = backlight_device_register(bl_name, &drm_connector->kdev,
+        bd = backlight_device_register(bl_name, drm_connector->kdev,
                                        pdata, &radeon_atom_backlight_ops, &props);
         if (IS_ERR(bd)) {
                 DRM_ERROR("Backlight registration failed\n");
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 061b227dae0c..c155d6f3fa68 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -499,7 +499,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
         fp2_gen_cntl = 0;
 
-        if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
+        if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
         }
 
@@ -536,7 +536,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
                 (RADEON_CRTC_SYNC_TRISTAT |
                  RADEON_CRTC_DISPLAY_DIS)));
 
-        if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
+        if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
         }
 
@@ -554,7 +554,7 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
         }
         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
-        if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
+        if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
         }
         return r;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index cdd12dcd988b..22f685827b7e 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -100,7 +100,6 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
 irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS);
-int radeon_gem_object_init(struct drm_gem_object *obj);
 void radeon_gem_object_free(struct drm_gem_object *obj);
 int radeon_gem_object_open(struct drm_gem_object *obj,
                                 struct drm_file *file_priv);
@@ -408,7 +407,6 @@ static struct drm_driver kms_driver = {
         .irq_uninstall = radeon_driver_irq_uninstall_kms,
         .irq_handler = radeon_driver_irq_handler_kms,
         .ioctls = radeon_ioctls_kms,
-        .gem_init_object = radeon_gem_object_init,
         .gem_free_object = radeon_gem_object_free,
         .gem_open_object = radeon_gem_object_open,
         .gem_close_object = radeon_gem_object_close,
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index dce99c8a5835..805c5e566b9a 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -29,13 +29,6 @@
 #include <drm/radeon_drm.h>
 #include "radeon.h"
 
-int radeon_gem_object_init(struct drm_gem_object *obj)
-{
-        BUG();
-
-        return 0;
-}
-
 void radeon_gem_object_free(struct drm_gem_object *gobj)
 {
         struct radeon_bo *robj = gem_to_radeon_bo(gobj);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 61580ddc4eb2..d6b36766e8c9 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -191,7 +191,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 
         switch (info->request) {
         case RADEON_INFO_DEVICE_ID:
-                *value = dev->pci_device;
+                *value = dev->pdev->device;
                 break;
         case RADEON_INFO_NUM_GB_PIPES:
                 *value = rdev->num_gb_pipes;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 62cd512f5c8d..c89971d904c3 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -392,7 +392,7 @@ void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
         props.type = BACKLIGHT_RAW;
         snprintf(bl_name, sizeof(bl_name),
                  "radeon_bl%d", dev->primary->index);
-        bd = backlight_device_register(bl_name, &drm_connector->kdev,
+        bd = backlight_device_register(bl_name, drm_connector->kdev,
                                        pdata, &radeon_backlight_ops, &props);
         if (IS_ERR(bd)) {
                 DRM_ERROR("Backlight registration failed\n");
diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c
index 7650dc0d78ce..3ddd6cd98ac1 100644
--- a/drivers/gpu/drm/udl/udl_drv.c
+++ b/drivers/gpu/drm/udl/udl_drv.c
@@ -77,7 +77,6 @@ static struct drm_driver driver = {
         .unload = udl_driver_unload,
 
         /* gem hooks */
-        .gem_init_object = udl_gem_init_object,
         .gem_free_object = udl_gem_free_object,
         .gem_vm_ops = &udl_gem_vm_ops,
 
diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h
index 56aec9409fa3..1fbf7b357f16 100644
--- a/drivers/gpu/drm/udl/udl_drv.h
+++ b/drivers/gpu/drm/udl/udl_drv.h
@@ -115,7 +115,6 @@ int udl_dumb_create(struct drm_file *file_priv,
 int udl_gem_mmap(struct drm_file *file_priv, struct drm_device *dev,
                  uint32_t handle, uint64_t *offset);
 
-int udl_gem_init_object(struct drm_gem_object *obj);
 void udl_gem_free_object(struct drm_gem_object *gem_obj);
 struct udl_gem_object *udl_gem_alloc_object(struct drm_device *dev,
                                             size_t size);
diff --git a/drivers/gpu/drm/udl/udl_gem.c b/drivers/gpu/drm/udl/udl_gem.c
index 8bf646183bac..24ffbe990736 100644
--- a/drivers/gpu/drm/udl/udl_gem.c
+++ b/drivers/gpu/drm/udl/udl_gem.c
@@ -107,13 +107,6 @@ int udl_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
         }
 }
 
-int udl_gem_init_object(struct drm_gem_object *obj)
-{
-        BUG();
-
-        return 0;
-}
-
 static int udl_gem_get_pages(struct udl_gem_object *obj, gfp_t gfpmask)
 {
         struct page **pages;
diff --git a/drivers/gpu/drm/via/via_mm.c b/drivers/gpu/drm/via/via_mm.c
index 7e3ad87c366c..927889105483 100644
--- a/drivers/gpu/drm/via/via_mm.c
+++ b/drivers/gpu/drm/via/via_mm.c
@@ -79,7 +79,7 @@ int via_final_context(struct drm_device *dev, int context)
 
         /* Linux specific until context tracking code gets ported to BSD */
         /* Last context, perform cleanup */
-        if (dev->ctx_count == 1 && dev->dev_private) {
+        if (list_is_singular(&dev->ctxlist) && dev->dev_private) {
                 DRM_DEBUG("Last Context\n");
                 drm_irq_uninstall(dev);
                 via_cleanup_futex(dev_priv);
diff --git a/drivers/gpu/host1x/drm/drm.c b/drivers/gpu/host1x/drm/drm.c
index 8c61ceeaa12d..df7d90a3a4fa 100644
--- a/drivers/gpu/host1x/drm/drm.c
+++ b/drivers/gpu/host1x/drm/drm.c
@@ -264,7 +264,7 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
          * core, so we need to set this manually in order to allow the
          * DRM_IOCTL_WAIT_VBLANK to operate correctly.
          */
-        drm->irq_enabled = 1;
+        drm->irq_enabled = true;
 
         err = drm_vblank_init(drm, drm->mode_config.num_crtc);
         if (err < 0)