diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 11 |
4 files changed, 35 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 14098ace1569..e585a3b947eb 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -3421,7 +3421,8 @@ void evergreen_fini(struct radeon_device *rdev) | |||
3421 | 3421 | ||
3422 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev) | 3422 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev) |
3423 | { | 3423 | { |
3424 | u32 link_width_cntl, speed_cntl; | 3424 | u32 link_width_cntl, speed_cntl, mask; |
3425 | int ret; | ||
3425 | 3426 | ||
3426 | if (radeon_pcie_gen2 == 0) | 3427 | if (radeon_pcie_gen2 == 0) |
3427 | return; | 3428 | return; |
@@ -3436,6 +3437,15 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) | |||
3436 | if (ASIC_IS_X2(rdev)) | 3437 | if (ASIC_IS_X2(rdev)) |
3437 | return; | 3438 | return; |
3438 | 3439 | ||
3440 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); | ||
3441 | if (ret != 0) | ||
3442 | return; | ||
3443 | |||
3444 | if (!(mask & DRM_PCIE_SPEED_50)) | ||
3445 | return; | ||
3446 | |||
3447 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); | ||
3448 | |||
3439 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | 3449 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
3440 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || | 3450 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || |
3441 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | 3451 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index e2dee80e27dc..637280f541a3 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -3681,6 +3681,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) | |||
3681 | { | 3681 | { |
3682 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; | 3682 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; |
3683 | u16 link_cntl2; | 3683 | u16 link_cntl2; |
3684 | u32 mask; | ||
3685 | int ret; | ||
3684 | 3686 | ||
3685 | if (radeon_pcie_gen2 == 0) | 3687 | if (radeon_pcie_gen2 == 0) |
3686 | return; | 3688 | return; |
@@ -3699,6 +3701,15 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) | |||
3699 | if (rdev->family <= CHIP_R600) | 3701 | if (rdev->family <= CHIP_R600) |
3700 | return; | 3702 | return; |
3701 | 3703 | ||
3704 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); | ||
3705 | if (ret != 0) | ||
3706 | return; | ||
3707 | |||
3708 | if (!(mask & DRM_PCIE_SPEED_50)) | ||
3709 | return; | ||
3710 | |||
3711 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); | ||
3712 | |||
3702 | /* 55 nm r6xx asics */ | 3713 | /* 55 nm r6xx asics */ |
3703 | if ((rdev->family == CHIP_RV670) || | 3714 | if ((rdev->family == CHIP_RV670) || |
3704 | (rdev->family == CHIP_RV620) || | 3715 | (rdev->family == CHIP_RV620) || |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 2c4d53fd20c5..042fcfff3bc4 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -133,7 +133,7 @@ int radeon_tv = 1; | |||
133 | int radeon_audio = 0; | 133 | int radeon_audio = 0; |
134 | int radeon_disp_priority = 0; | 134 | int radeon_disp_priority = 0; |
135 | int radeon_hw_i2c = 0; | 135 | int radeon_hw_i2c = 0; |
136 | int radeon_pcie_gen2 = 0; | 136 | int radeon_pcie_gen2 = -1; |
137 | int radeon_msi = -1; | 137 | int radeon_msi = -1; |
138 | int radeon_lockup_timeout = 10000; | 138 | int radeon_lockup_timeout = 10000; |
139 | 139 | ||
@@ -179,7 +179,7 @@ module_param_named(disp_priority, radeon_disp_priority, int, 0444); | |||
179 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); | 179 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
180 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); | 180 | module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); |
181 | 181 | ||
182 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (1 = enable)"); | 182 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
183 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); | 183 | module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); |
184 | 184 | ||
185 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); | 185 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index eb4704e72bdb..ca8ffec10ff6 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -1112,6 +1112,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) | |||
1112 | { | 1112 | { |
1113 | u32 link_width_cntl, lanes, speed_cntl, tmp; | 1113 | u32 link_width_cntl, lanes, speed_cntl, tmp; |
1114 | u16 link_cntl2; | 1114 | u16 link_cntl2; |
1115 | u32 mask; | ||
1116 | int ret; | ||
1115 | 1117 | ||
1116 | if (radeon_pcie_gen2 == 0) | 1118 | if (radeon_pcie_gen2 == 0) |
1117 | return; | 1119 | return; |
@@ -1126,6 +1128,15 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev) | |||
1126 | if (ASIC_IS_X2(rdev)) | 1128 | if (ASIC_IS_X2(rdev)) |
1127 | return; | 1129 | return; |
1128 | 1130 | ||
1131 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); | ||
1132 | if (ret != 0) | ||
1133 | return; | ||
1134 | |||
1135 | if (!(mask & DRM_PCIE_SPEED_50)) | ||
1136 | return; | ||
1137 | |||
1138 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); | ||
1139 | |||
1129 | /* advertise upconfig capability */ | 1140 | /* advertise upconfig capability */ |
1130 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | 1141 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
1131 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | 1142 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |