diff options
Diffstat (limited to 'drivers/gpu/drm')
20 files changed, 107 insertions, 31 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index b726b478a4f5..6345878ae1e7 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
@@ -143,7 +143,7 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode) | |||
143 | int old_dpms; | 143 | int old_dpms; |
144 | 144 | ||
145 | /* PCH platforms and VLV only support on/off. */ | 145 | /* PCH platforms and VLV only support on/off. */ |
146 | if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON) | 146 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
147 | mode = DRM_MODE_DPMS_OFF; | 147 | mode = DRM_MODE_DPMS_OFF; |
148 | 148 | ||
149 | if (mode == connector->dpms) | 149 | if (mode == connector->dpms) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 461a637f1ef7..4154bcd7a070 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3841,6 +3841,17 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |||
3841 | } | 3841 | } |
3842 | } | 3842 | } |
3843 | 3843 | ||
3844 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | ||
3845 | /* Use VBT settings if we have an eDP panel */ | ||
3846 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | ||
3847 | |||
3848 | if (edp_bpc < display_bpc) { | ||
3849 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); | ||
3850 | display_bpc = edp_bpc; | ||
3851 | } | ||
3852 | continue; | ||
3853 | } | ||
3854 | |||
3844 | /* | 3855 | /* |
3845 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | 3856 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
3846 | * through, clamp it down. (Note: >12bpc will be caught below.) | 3857 | * through, clamp it down. (Note: >12bpc will be caught below.) |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 79d308da29ff..c600fb06e25e 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -2382,6 +2382,18 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) | |||
2382 | return true; | 2382 | return true; |
2383 | } | 2383 | } |
2384 | 2384 | ||
2385 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) | ||
2386 | { | ||
2387 | struct drm_device *dev = intel_sdvo->base.base.dev; | ||
2388 | struct drm_connector *connector, *tmp; | ||
2389 | |||
2390 | list_for_each_entry_safe(connector, tmp, | ||
2391 | &dev->mode_config.connector_list, head) { | ||
2392 | if (intel_attached_encoder(connector) == &intel_sdvo->base) | ||
2393 | intel_sdvo_destroy(connector); | ||
2394 | } | ||
2395 | } | ||
2396 | |||
2385 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | 2397 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2386 | struct intel_sdvo_connector *intel_sdvo_connector, | 2398 | struct intel_sdvo_connector *intel_sdvo_connector, |
2387 | int type) | 2399 | int type) |
@@ -2705,7 +2717,8 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) | |||
2705 | intel_sdvo->caps.output_flags) != true) { | 2717 | intel_sdvo->caps.output_flags) != true) { |
2706 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", | 2718 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
2707 | SDVO_NAME(intel_sdvo)); | 2719 | SDVO_NAME(intel_sdvo)); |
2708 | goto err; | 2720 | /* Output_setup can leave behind connectors! */ |
2721 | goto err_output; | ||
2709 | } | 2722 | } |
2710 | 2723 | ||
2711 | /* Only enable the hotplug irq if we need it, to work around noisy | 2724 | /* Only enable the hotplug irq if we need it, to work around noisy |
@@ -2718,12 +2731,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) | |||
2718 | 2731 | ||
2719 | /* Set the input timing to the screen. Assume always input 0. */ | 2732 | /* Set the input timing to the screen. Assume always input 0. */ |
2720 | if (!intel_sdvo_set_target_input(intel_sdvo)) | 2733 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
2721 | goto err; | 2734 | goto err_output; |
2722 | 2735 | ||
2723 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, | 2736 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
2724 | &intel_sdvo->pixel_clock_min, | 2737 | &intel_sdvo->pixel_clock_min, |
2725 | &intel_sdvo->pixel_clock_max)) | 2738 | &intel_sdvo->pixel_clock_max)) |
2726 | goto err; | 2739 | goto err_output; |
2727 | 2740 | ||
2728 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " | 2741 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
2729 | "clock range %dMHz - %dMHz, " | 2742 | "clock range %dMHz - %dMHz, " |
@@ -2743,6 +2756,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) | |||
2743 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); | 2756 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
2744 | return true; | 2757 | return true; |
2745 | 2758 | ||
2759 | err_output: | ||
2760 | intel_sdvo_output_cleanup(intel_sdvo); | ||
2761 | |||
2746 | err: | 2762 | err: |
2747 | drm_encoder_cleanup(&intel_encoder->base); | 2763 | drm_encoder_cleanup(&intel_encoder->base); |
2748 | i2c_del_adapter(&intel_sdvo->ddc); | 2764 | i2c_del_adapter(&intel_sdvo->ddc); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 05a909a17cee..15b182c84ce8 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | |||
@@ -49,13 +49,7 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) | |||
49 | if (chan->vblank.crtc != crtc) | 49 | if (chan->vblank.crtc != crtc) |
50 | continue; | 50 | continue; |
51 | 51 | ||
52 | if (nv_device(priv)->chipset == 0x50) { | 52 | if (nv_device(priv)->chipset >= 0xc0) { |
53 | nv_wr32(priv, 0x001704, chan->vblank.channel); | ||
54 | nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); | ||
55 | bar->flush(bar); | ||
56 | nv_wr32(priv, 0x001570, chan->vblank.offset); | ||
57 | nv_wr32(priv, 0x001574, chan->vblank.value); | ||
58 | } else { | ||
59 | nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); | 53 | nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); |
60 | bar->flush(bar); | 54 | bar->flush(bar); |
61 | nv_wr32(priv, 0x06000c, | 55 | nv_wr32(priv, 0x06000c, |
@@ -63,6 +57,17 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) | |||
63 | nv_wr32(priv, 0x060010, | 57 | nv_wr32(priv, 0x060010, |
64 | lower_32_bits(chan->vblank.offset)); | 58 | lower_32_bits(chan->vblank.offset)); |
65 | nv_wr32(priv, 0x060014, chan->vblank.value); | 59 | nv_wr32(priv, 0x060014, chan->vblank.value); |
60 | } else { | ||
61 | nv_wr32(priv, 0x001704, chan->vblank.channel); | ||
62 | nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); | ||
63 | bar->flush(bar); | ||
64 | if (nv_device(priv)->chipset == 0x50) { | ||
65 | nv_wr32(priv, 0x001570, chan->vblank.offset); | ||
66 | nv_wr32(priv, 0x001574, chan->vblank.value); | ||
67 | } else { | ||
68 | nv_wr32(priv, 0x060010, chan->vblank.offset); | ||
69 | nv_wr32(priv, 0x060014, chan->vblank.value); | ||
70 | } | ||
66 | } | 71 | } |
67 | 72 | ||
68 | list_del(&chan->vblank.head); | 73 | list_del(&chan->vblank.head); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c index e45035efb8ca..7bbb1e1b7a8d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c | |||
@@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) | |||
669 | }); | 669 | }); |
670 | } | 670 | } |
671 | 671 | ||
672 | void | 672 | int |
673 | nv40_grctx_init(struct nouveau_device *device, u32 *size) | 673 | nv40_grctx_init(struct nouveau_device *device, u32 *size) |
674 | { | 674 | { |
675 | u32 ctxprog[256], i; | 675 | u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; |
676 | struct nouveau_grctx ctx = { | 676 | struct nouveau_grctx ctx = { |
677 | .device = device, | 677 | .device = device, |
678 | .mode = NOUVEAU_GRCTX_PROG, | 678 | .mode = NOUVEAU_GRCTX_PROG, |
679 | .data = ctxprog, | 679 | .data = ctxprog, |
680 | .ctxprog_max = ARRAY_SIZE(ctxprog) | 680 | .ctxprog_max = 256, |
681 | }; | 681 | }; |
682 | 682 | ||
683 | if (!ctxprog) | ||
684 | return -ENOMEM; | ||
685 | |||
683 | nv40_grctx_generate(&ctx); | 686 | nv40_grctx_generate(&ctx); |
684 | 687 | ||
685 | nv_wr32(device, 0x400324, 0); | 688 | nv_wr32(device, 0x400324, 0); |
686 | for (i = 0; i < ctx.ctxprog_len; i++) | 689 | for (i = 0; i < ctx.ctxprog_len; i++) |
687 | nv_wr32(device, 0x400328, ctxprog[i]); | 690 | nv_wr32(device, 0x400328, ctxprog[i]); |
688 | *size = ctx.ctxvals_pos * 4; | 691 | *size = ctx.ctxvals_pos * 4; |
692 | |||
693 | kfree(ctxprog); | ||
694 | return 0; | ||
689 | } | 695 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c index 425001204a89..cc6574eeb80e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c | |||
@@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object) | |||
346 | return ret; | 346 | return ret; |
347 | 347 | ||
348 | /* generate and upload context program */ | 348 | /* generate and upload context program */ |
349 | nv40_grctx_init(nv_device(priv), &priv->size); | 349 | ret = nv40_grctx_init(nv_device(priv), &priv->size); |
350 | if (ret) | ||
351 | return ret; | ||
350 | 352 | ||
351 | /* No context present currently */ | 353 | /* No context present currently */ |
352 | nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); | 354 | nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h index d2ac975afc2e..7da35a4e7970 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h | |||
@@ -15,7 +15,7 @@ nv44_graph_class(void *priv) | |||
15 | return !(0x0baf & (1 << (device->chipset & 0x0f))); | 15 | return !(0x0baf & (1 << (device->chipset & 0x0f))); |
16 | } | 16 | } |
17 | 17 | ||
18 | void nv40_grctx_init(struct nouveau_device *, u32 *size); | 18 | int nv40_grctx_init(struct nouveau_device *, u32 *size); |
19 | void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); | 19 | void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); |
20 | 20 | ||
21 | #endif | 21 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/core/include/core/object.h index 818feabbf4a0..486f1a9217fd 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/object.h +++ b/drivers/gpu/drm/nouveau/core/include/core/object.h | |||
@@ -175,14 +175,18 @@ nv_mo32(void *obj, u32 addr, u32 mask, u32 data) | |||
175 | return temp; | 175 | return temp; |
176 | } | 176 | } |
177 | 177 | ||
178 | static inline bool | 178 | static inline int |
179 | nv_strncmp(void *obj, u32 addr, u32 len, const char *str) | 179 | nv_memcmp(void *obj, u32 addr, const char *str, u32 len) |
180 | { | 180 | { |
181 | unsigned char c1, c2; | ||
182 | |||
181 | while (len--) { | 183 | while (len--) { |
182 | if (nv_ro08(obj, addr++) != *(str++)) | 184 | c1 = nv_ro08(obj, addr++); |
183 | return false; | 185 | c2 = *(str++); |
186 | if (c1 != c2) | ||
187 | return c1 - c2; | ||
184 | } | 188 | } |
185 | return true; | 189 | return 0; |
186 | } | 190 | } |
187 | 191 | ||
188 | #endif | 192 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h index 39e73b91d360..41b7a6a76f19 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h | |||
@@ -54,6 +54,7 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, | |||
54 | int clk, struct nouveau_pll_vals *); | 54 | int clk, struct nouveau_pll_vals *); |
55 | int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, | 55 | int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, |
56 | struct nouveau_pll_vals *); | 56 | struct nouveau_pll_vals *); |
57 | 57 | int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, | |
58 | int clk, struct nouveau_pll_vals *); | ||
58 | 59 | ||
59 | #endif | 60 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c index 7d750382a833..c51197157749 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c | |||
@@ -64,7 +64,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | |||
64 | } | 64 | } |
65 | } else | 65 | } else |
66 | if (*ver >= 0x15) { | 66 | if (*ver >= 0x15) { |
67 | if (!nv_strncmp(bios, dcb - 7, 7, "DEV_REC")) { | 67 | if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) { |
68 | u16 i2c = nv_ro16(bios, dcb + 2); | 68 | u16 i2c = nv_ro16(bios, dcb + 2); |
69 | *hdr = 4; | 69 | *hdr = 4; |
70 | *cnt = (i2c - dcb) / 10; | 70 | *cnt = (i2c - dcb) / 10; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c index cc8d7d162d7c..9068c98b96f6 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | |||
@@ -66,6 +66,24 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq) | |||
66 | return ret; | 66 | return ret; |
67 | } | 67 | } |
68 | 68 | ||
69 | int | ||
70 | nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, | ||
71 | int clk, struct nouveau_pll_vals *pv) | ||
72 | { | ||
73 | int ret, N, M, P; | ||
74 | |||
75 | ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P); | ||
76 | |||
77 | if (ret > 0) { | ||
78 | pv->refclk = info->refclk; | ||
79 | pv->N1 = N; | ||
80 | pv->M1 = M; | ||
81 | pv->log2P = P; | ||
82 | } | ||
83 | return ret; | ||
84 | } | ||
85 | |||
86 | |||
69 | static int | 87 | static int |
70 | nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 88 | nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
71 | struct nouveau_oclass *oclass, void *data, u32 size, | 89 | struct nouveau_oclass *oclass, void *data, u32 size, |
@@ -80,6 +98,7 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
80 | return ret; | 98 | return ret; |
81 | 99 | ||
82 | priv->base.pll_set = nva3_clock_pll_set; | 100 | priv->base.pll_set = nva3_clock_pll_set; |
101 | priv->base.pll_calc = nva3_clock_pll_calc; | ||
83 | return 0; | 102 | return 0; |
84 | } | 103 | } |
85 | 104 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c index 5ccce0b17bf3..f6962c9b6c36 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c | |||
@@ -79,6 +79,7 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
79 | return ret; | 79 | return ret; |
80 | 80 | ||
81 | priv->base.pll_set = nvc0_clock_pll_set; | 81 | priv->base.pll_set = nvc0_clock_pll_set; |
82 | priv->base.pll_calc = nva3_clock_pll_calc; | ||
82 | return 0; | 83 | return 0; |
83 | } | 84 | } |
84 | 85 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index cc79c796afee..cbf1fc60a386 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c | |||
@@ -241,6 +241,10 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) | |||
241 | 241 | ||
242 | if (unlikely(!abi16)) | 242 | if (unlikely(!abi16)) |
243 | return -ENOMEM; | 243 | return -ENOMEM; |
244 | |||
245 | if (!drm->channel) | ||
246 | return nouveau_abi16_put(abi16, -ENODEV); | ||
247 | |||
244 | client = nv_client(abi16->client); | 248 | client = nv_client(abi16->client); |
245 | 249 | ||
246 | if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) | 250 | if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 0910125cbbc3..8503b2ea570a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c | |||
@@ -129,7 +129,8 @@ nouveau_accel_init(struct nouveau_drm *drm) | |||
129 | 129 | ||
130 | /* initialise synchronisation routines */ | 130 | /* initialise synchronisation routines */ |
131 | if (device->card_type < NV_10) ret = nv04_fence_create(drm); | 131 | if (device->card_type < NV_10) ret = nv04_fence_create(drm); |
132 | else if (device->chipset < 0x84) ret = nv10_fence_create(drm); | 132 | else if (device->card_type < NV_50) ret = nv10_fence_create(drm); |
133 | else if (device->chipset < 0x84) ret = nv50_fence_create(drm); | ||
133 | else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); | 134 | else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); |
134 | else ret = nvc0_fence_create(drm); | 135 | else ret = nvc0_fence_create(drm); |
135 | if (ret) { | 136 | if (ret) { |
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index ba498f8e47a2..010bae19554a 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c | |||
@@ -1625,7 +1625,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) | |||
1625 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | 1625 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
1626 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | 1626 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
1627 | /* some early dce3.2 boards have a bug in their transmitter control table */ | 1627 | /* some early dce3.2 boards have a bug in their transmitter control table */ |
1628 | if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730)) | 1628 | if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730)) |
1629 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | 1629 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
1630 | } | 1630 | } |
1631 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { | 1631 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index af31f829f4a8..219942c660d7 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1330,6 +1330,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav | |||
1330 | break; | 1330 | break; |
1331 | udelay(1); | 1331 | udelay(1); |
1332 | } | 1332 | } |
1333 | } else { | ||
1334 | save->crtc_enabled[i] = false; | ||
1333 | } | 1335 | } |
1334 | } | 1336 | } |
1335 | 1337 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c index 10ea17a6b2a6..42433344cb1b 100644 --- a/drivers/gpu/drm/radeon/radeon_agp.c +++ b/drivers/gpu/drm/radeon/radeon_agp.c | |||
@@ -69,9 +69,12 @@ static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { | |||
69 | /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ | 69 | /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ |
70 | { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59, | 70 | { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59, |
71 | PCI_VENDOR_ID_DELL, 0x00e3, 2}, | 71 | PCI_VENDOR_ID_DELL, 0x00e3, 2}, |
72 | /* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */ | 72 | /* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */ |
73 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66, | 73 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66, |
74 | PCI_VENDOR_ID_DELL, 0x0149, 1}, | 74 | PCI_VENDOR_ID_DELL, 0x0149, 1}, |
75 | /* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */ | ||
76 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, | ||
77 | PCI_VENDOR_ID_IBM, 0x0531, 1}, | ||
75 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ | 78 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ |
76 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, | 79 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
77 | 0x1025, 0x0061, 1}, | 80 | 0x1025, 0x0061, 1}, |
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 860dc4813e99..bd2a3b40cd12 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c | |||
@@ -749,7 +749,10 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, | |||
749 | /* clear the pages coming from the pool if requested */ | 749 | /* clear the pages coming from the pool if requested */ |
750 | if (flags & TTM_PAGE_FLAG_ZERO_ALLOC) { | 750 | if (flags & TTM_PAGE_FLAG_ZERO_ALLOC) { |
751 | list_for_each_entry(p, &plist, lru) { | 751 | list_for_each_entry(p, &plist, lru) { |
752 | clear_page(page_address(p)); | 752 | if (PageHighMem(p)) |
753 | clear_highpage(p); | ||
754 | else | ||
755 | clear_page(page_address(p)); | ||
753 | } | 756 | } |
754 | } | 757 | } |
755 | 758 | ||
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index bf8260133ea9..7d759a430294 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c | |||
@@ -308,9 +308,7 @@ int ttm_tt_swapin(struct ttm_tt *ttm) | |||
308 | if (unlikely(to_page == NULL)) | 308 | if (unlikely(to_page == NULL)) |
309 | goto out_err; | 309 | goto out_err; |
310 | 310 | ||
311 | preempt_disable(); | ||
312 | copy_highpage(to_page, from_page); | 311 | copy_highpage(to_page, from_page); |
313 | preempt_enable(); | ||
314 | page_cache_release(from_page); | 312 | page_cache_release(from_page); |
315 | } | 313 | } |
316 | 314 | ||
@@ -358,9 +356,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage) | |||
358 | ret = PTR_ERR(to_page); | 356 | ret = PTR_ERR(to_page); |
359 | goto out_err; | 357 | goto out_err; |
360 | } | 358 | } |
361 | preempt_disable(); | ||
362 | copy_highpage(to_page, from_page); | 359 | copy_highpage(to_page, from_page); |
363 | preempt_enable(); | ||
364 | set_page_dirty(to_page); | 360 | set_page_dirty(to_page); |
365 | mark_page_accessed(to_page); | 361 | mark_page_accessed(to_page); |
366 | page_cache_release(to_page); | 362 | page_cache_release(to_page); |
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c index b07ca2e4d04b..7290811f89be 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | |||
@@ -110,6 +110,8 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data, | |||
110 | memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size); | 110 | memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size); |
111 | 111 | ||
112 | ret = copy_to_user(buffer, bounce, size); | 112 | ret = copy_to_user(buffer, bounce, size); |
113 | if (ret) | ||
114 | ret = -EFAULT; | ||
113 | vfree(bounce); | 115 | vfree(bounce); |
114 | 116 | ||
115 | if (unlikely(ret != 0)) | 117 | if (unlikely(ret != 0)) |