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-rw-r--r--drivers/gpu/drm/drm_drv.c13
-rw-r--r--drivers/gpu/drm/drm_edid.c2
-rw-r--r--drivers/gpu/drm/drm_ioc32.c89
-rw-r--r--drivers/gpu/drm/drm_mm.c4
-rw-r--r--drivers/gpu/drm/i2c/ch7006_drv.c5
-rw-r--r--drivers/gpu/drm/i2c/ch7006_mode.c5
-rw-r--r--drivers/gpu/drm/i810/i810_dma.c2
-rw-r--r--drivers/gpu/drm/i810/i810_drv.c2
-rw-r--r--drivers/gpu/drm/i830/i830_dma.c2
-rw-r--r--drivers/gpu/drm/i830/i830_drv.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c2
-rw-r--r--drivers/gpu/drm/i915/i915_ioc32.c23
-rw-r--r--drivers/gpu/drm/mga/mga_drv.c2
-rw-r--r--drivers/gpu/drm/mga/mga_ioc32.c13
-rw-r--r--drivers/gpu/drm/nouveau/Makefile5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c621
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c19
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c28
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h27
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c22
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.c161
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.h133
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ioc32.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c147
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dac.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv04_display.c11
-rw-r--r--drivers/gpu/drm/nouveau/nv04_graph.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv10_graph.c197
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c4
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c212
-rw-r--r--drivers/gpu/drm/nouveau/nv40_grctx.c678
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c22
-rw-r--r--drivers/gpu/drm/nouveau/nv50_cursor.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv50_dac.c20
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c20
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c16
-rw-r--r--drivers/gpu/drm/r128/r128_drv.c2
-rw-r--r--drivers/gpu/drm/r128/r128_ioc32.c16
-rw-r--r--drivers/gpu/drm/radeon/atom.c12
-rw-r--r--drivers/gpu/drm/radeon/atom.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios.h199
-rw-r--r--drivers/gpu/drm/radeon/r100.c4
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h4
-rw-r--r--drivers/gpu/drm/radeon/r300.c30
-rw-r--r--drivers/gpu/drm/radeon/r300_cmdbuf.c6
-rw-r--r--drivers/gpu/drm/radeon/r300_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h7
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c105
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c80
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_ioc32.c38
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c4
-rw-r--r--drivers/gpu/drm/savage/savage_drv.c2
-rw-r--r--drivers/gpu/drm/sis/sis_drv.c2
-rw-r--r--drivers/gpu/drm/tdfx/tdfx_drv.c2
-rw-r--r--drivers/gpu/drm/via/via_drv.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c47
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h10
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c157
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c6
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_irq.c6
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c149
82 files changed, 2499 insertions, 1064 deletions
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index ff2f1042cb44..766c46875a20 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -434,11 +434,11 @@ static int drm_version(struct drm_device *dev, void *data,
434 * Looks up the ioctl function in the ::ioctls table, checking for root 434 * Looks up the ioctl function in the ::ioctls table, checking for root
435 * previleges if so required, and dispatches to the respective function. 435 * previleges if so required, and dispatches to the respective function.
436 */ 436 */
437int drm_ioctl(struct inode *inode, struct file *filp, 437long drm_ioctl(struct file *filp,
438 unsigned int cmd, unsigned long arg) 438 unsigned int cmd, unsigned long arg)
439{ 439{
440 struct drm_file *file_priv = filp->private_data; 440 struct drm_file *file_priv = filp->private_data;
441 struct drm_device *dev = file_priv->minor->dev; 441 struct drm_device *dev;
442 struct drm_ioctl_desc *ioctl; 442 struct drm_ioctl_desc *ioctl;
443 drm_ioctl_t *func; 443 drm_ioctl_t *func;
444 unsigned int nr = DRM_IOCTL_NR(cmd); 444 unsigned int nr = DRM_IOCTL_NR(cmd);
@@ -446,6 +446,7 @@ int drm_ioctl(struct inode *inode, struct file *filp,
446 char stack_kdata[128]; 446 char stack_kdata[128];
447 char *kdata = NULL; 447 char *kdata = NULL;
448 448
449 dev = file_priv->minor->dev;
449 atomic_inc(&dev->ioctl_count); 450 atomic_inc(&dev->ioctl_count);
450 atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]); 451 atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
451 ++file_priv->ioctl_count; 452 ++file_priv->ioctl_count;
@@ -501,7 +502,13 @@ int drm_ioctl(struct inode *inode, struct file *filp,
501 goto err_i1; 502 goto err_i1;
502 } 503 }
503 } 504 }
504 retcode = func(dev, kdata, file_priv); 505 if (ioctl->flags & DRM_UNLOCKED)
506 retcode = func(dev, kdata, file_priv);
507 else {
508 lock_kernel();
509 retcode = func(dev, kdata, file_priv);
510 unlock_kernel();
511 }
505 512
506 if (cmd & IOC_OUT) { 513 if (cmd & IOC_OUT) {
507 if (copy_to_user((void __user *)arg, kdata, 514 if (copy_to_user((void __user *)arg, kdata,
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c39b26f1abed..5c9f79877cbf 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -913,7 +913,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
913 const int rates[] = { 60, 85, 75, 60, 50 }; 913 const int rates[] = { 60, 85, 75, 60, 50 };
914 914
915 for (i = 0; i < 4; i++) { 915 for (i = 0; i < 4; i++) {
916 int width, height; 916 int uninitialized_var(width), height;
917 cvt = &(timing->data.other_data.data.cvt[i]); 917 cvt = &(timing->data.other_data.data.cvt[i]);
918 918
919 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 8) + 1) * 2; 919 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 8) + 1) * 2;
diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c
index 282d9fdf9f4e..d61d185cf040 100644
--- a/drivers/gpu/drm/drm_ioc32.c
+++ b/drivers/gpu/drm/drm_ioc32.c
@@ -104,7 +104,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd,
104 &version->desc)) 104 &version->desc))
105 return -EFAULT; 105 return -EFAULT;
106 106
107 err = drm_ioctl(file->f_path.dentry->d_inode, file, 107 err = drm_ioctl(file,
108 DRM_IOCTL_VERSION, (unsigned long)version); 108 DRM_IOCTL_VERSION, (unsigned long)version);
109 if (err) 109 if (err)
110 return err; 110 return err;
@@ -145,8 +145,7 @@ static int compat_drm_getunique(struct file *file, unsigned int cmd,
145 &u->unique)) 145 &u->unique))
146 return -EFAULT; 146 return -EFAULT;
147 147
148 err = drm_ioctl(file->f_path.dentry->d_inode, file, 148 err = drm_ioctl(file, DRM_IOCTL_GET_UNIQUE, (unsigned long)u);
149 DRM_IOCTL_GET_UNIQUE, (unsigned long)u);
150 if (err) 149 if (err)
151 return err; 150 return err;
152 151
@@ -174,8 +173,7 @@ static int compat_drm_setunique(struct file *file, unsigned int cmd,
174 &u->unique)) 173 &u->unique))
175 return -EFAULT; 174 return -EFAULT;
176 175
177 return drm_ioctl(file->f_path.dentry->d_inode, file, 176 return drm_ioctl(file, DRM_IOCTL_SET_UNIQUE, (unsigned long)u);
178 DRM_IOCTL_SET_UNIQUE, (unsigned long)u);
179} 177}
180 178
181typedef struct drm_map32 { 179typedef struct drm_map32 {
@@ -205,8 +203,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd,
205 if (__put_user(idx, &map->offset)) 203 if (__put_user(idx, &map->offset))
206 return -EFAULT; 204 return -EFAULT;
207 205
208 err = drm_ioctl(file->f_path.dentry->d_inode, file, 206 err = drm_ioctl(file, DRM_IOCTL_GET_MAP, (unsigned long)map);
209 DRM_IOCTL_GET_MAP, (unsigned long)map);
210 if (err) 207 if (err)
211 return err; 208 return err;
212 209
@@ -246,8 +243,7 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd,
246 || __put_user(m32.flags, &map->flags)) 243 || __put_user(m32.flags, &map->flags))
247 return -EFAULT; 244 return -EFAULT;
248 245
249 err = drm_ioctl(file->f_path.dentry->d_inode, file, 246 err = drm_ioctl(file, DRM_IOCTL_ADD_MAP, (unsigned long)map);
250 DRM_IOCTL_ADD_MAP, (unsigned long)map);
251 if (err) 247 if (err)
252 return err; 248 return err;
253 249
@@ -284,8 +280,7 @@ static int compat_drm_rmmap(struct file *file, unsigned int cmd,
284 if (__put_user((void *)(unsigned long)handle, &map->handle)) 280 if (__put_user((void *)(unsigned long)handle, &map->handle))
285 return -EFAULT; 281 return -EFAULT;
286 282
287 return drm_ioctl(file->f_path.dentry->d_inode, file, 283 return drm_ioctl(file, DRM_IOCTL_RM_MAP, (unsigned long)map);
288 DRM_IOCTL_RM_MAP, (unsigned long)map);
289} 284}
290 285
291typedef struct drm_client32 { 286typedef struct drm_client32 {
@@ -314,8 +309,7 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd,
314 if (__put_user(idx, &client->idx)) 309 if (__put_user(idx, &client->idx))
315 return -EFAULT; 310 return -EFAULT;
316 311
317 err = drm_ioctl(file->f_path.dentry->d_inode, file, 312 err = drm_ioctl(file, DRM_IOCTL_GET_CLIENT, (unsigned long)client);
318 DRM_IOCTL_GET_CLIENT, (unsigned long)client);
319 if (err) 313 if (err)
320 return err; 314 return err;
321 315
@@ -351,8 +345,7 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd,
351 if (!access_ok(VERIFY_WRITE, stats, sizeof(*stats))) 345 if (!access_ok(VERIFY_WRITE, stats, sizeof(*stats)))
352 return -EFAULT; 346 return -EFAULT;
353 347
354 err = drm_ioctl(file->f_path.dentry->d_inode, file, 348 err = drm_ioctl(file, DRM_IOCTL_GET_STATS, (unsigned long)stats);
355 DRM_IOCTL_GET_STATS, (unsigned long)stats);
356 if (err) 349 if (err)
357 return err; 350 return err;
358 351
@@ -395,8 +388,7 @@ static int compat_drm_addbufs(struct file *file, unsigned int cmd,
395 || __put_user(agp_start, &buf->agp_start)) 388 || __put_user(agp_start, &buf->agp_start))
396 return -EFAULT; 389 return -EFAULT;
397 390
398 err = drm_ioctl(file->f_path.dentry->d_inode, file, 391 err = drm_ioctl(file, DRM_IOCTL_ADD_BUFS, (unsigned long)buf);
399 DRM_IOCTL_ADD_BUFS, (unsigned long)buf);
400 if (err) 392 if (err)
401 return err; 393 return err;
402 394
@@ -427,8 +419,7 @@ static int compat_drm_markbufs(struct file *file, unsigned int cmd,
427 || __put_user(b32.high_mark, &buf->high_mark)) 419 || __put_user(b32.high_mark, &buf->high_mark))
428 return -EFAULT; 420 return -EFAULT;
429 421
430 return drm_ioctl(file->f_path.dentry->d_inode, file, 422 return drm_ioctl(file, DRM_IOCTL_MARK_BUFS, (unsigned long)buf);
431 DRM_IOCTL_MARK_BUFS, (unsigned long)buf);
432} 423}
433 424
434typedef struct drm_buf_info32 { 425typedef struct drm_buf_info32 {
@@ -469,8 +460,7 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd,
469 || __put_user(list, &request->list)) 460 || __put_user(list, &request->list))
470 return -EFAULT; 461 return -EFAULT;
471 462
472 err = drm_ioctl(file->f_path.dentry->d_inode, file, 463 err = drm_ioctl(file, DRM_IOCTL_INFO_BUFS, (unsigned long)request);
473 DRM_IOCTL_INFO_BUFS, (unsigned long)request);
474 if (err) 464 if (err)
475 return err; 465 return err;
476 466
@@ -531,8 +521,7 @@ static int compat_drm_mapbufs(struct file *file, unsigned int cmd,
531 || __put_user(list, &request->list)) 521 || __put_user(list, &request->list))
532 return -EFAULT; 522 return -EFAULT;
533 523
534 err = drm_ioctl(file->f_path.dentry->d_inode, file, 524 err = drm_ioctl(file, DRM_IOCTL_MAP_BUFS, (unsigned long)request);
535 DRM_IOCTL_MAP_BUFS, (unsigned long)request);
536 if (err) 525 if (err)
537 return err; 526 return err;
538 527
@@ -578,8 +567,7 @@ static int compat_drm_freebufs(struct file *file, unsigned int cmd,
578 &request->list)) 567 &request->list))
579 return -EFAULT; 568 return -EFAULT;
580 569
581 return drm_ioctl(file->f_path.dentry->d_inode, file, 570 return drm_ioctl(file, DRM_IOCTL_FREE_BUFS, (unsigned long)request);
582 DRM_IOCTL_FREE_BUFS, (unsigned long)request);
583} 571}
584 572
585typedef struct drm_ctx_priv_map32 { 573typedef struct drm_ctx_priv_map32 {
@@ -605,8 +593,7 @@ static int compat_drm_setsareactx(struct file *file, unsigned int cmd,
605 &request->handle)) 593 &request->handle))
606 return -EFAULT; 594 return -EFAULT;
607 595
608 return drm_ioctl(file->f_path.dentry->d_inode, file, 596 return drm_ioctl(file, DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request);
609 DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request);
610} 597}
611 598
612static int compat_drm_getsareactx(struct file *file, unsigned int cmd, 599static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
@@ -628,8 +615,7 @@ static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
628 if (__put_user(ctx_id, &request->ctx_id)) 615 if (__put_user(ctx_id, &request->ctx_id))
629 return -EFAULT; 616 return -EFAULT;
630 617
631 err = drm_ioctl(file->f_path.dentry->d_inode, file, 618 err = drm_ioctl(file, DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request);
632 DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request);
633 if (err) 619 if (err)
634 return err; 620 return err;
635 621
@@ -664,8 +650,7 @@ static int compat_drm_resctx(struct file *file, unsigned int cmd,
664 &res->contexts)) 650 &res->contexts))
665 return -EFAULT; 651 return -EFAULT;
666 652
667 err = drm_ioctl(file->f_path.dentry->d_inode, file, 653 err = drm_ioctl(file, DRM_IOCTL_RES_CTX, (unsigned long)res);
668 DRM_IOCTL_RES_CTX, (unsigned long)res);
669 if (err) 654 if (err)
670 return err; 655 return err;
671 656
@@ -718,8 +703,7 @@ static int compat_drm_dma(struct file *file, unsigned int cmd,
718 &d->request_sizes)) 703 &d->request_sizes))
719 return -EFAULT; 704 return -EFAULT;
720 705
721 err = drm_ioctl(file->f_path.dentry->d_inode, file, 706 err = drm_ioctl(file, DRM_IOCTL_DMA, (unsigned long)d);
722 DRM_IOCTL_DMA, (unsigned long)d);
723 if (err) 707 if (err)
724 return err; 708 return err;
725 709
@@ -751,8 +735,7 @@ static int compat_drm_agp_enable(struct file *file, unsigned int cmd,
751 if (put_user(m32.mode, &mode->mode)) 735 if (put_user(m32.mode, &mode->mode))
752 return -EFAULT; 736 return -EFAULT;
753 737
754 return drm_ioctl(file->f_path.dentry->d_inode, file, 738 return drm_ioctl(file, DRM_IOCTL_AGP_ENABLE, (unsigned long)mode);
755 DRM_IOCTL_AGP_ENABLE, (unsigned long)mode);
756} 739}
757 740
758typedef struct drm_agp_info32 { 741typedef struct drm_agp_info32 {
@@ -781,8 +764,7 @@ static int compat_drm_agp_info(struct file *file, unsigned int cmd,
781 if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) 764 if (!access_ok(VERIFY_WRITE, info, sizeof(*info)))
782 return -EFAULT; 765 return -EFAULT;
783 766
784 err = drm_ioctl(file->f_path.dentry->d_inode, file, 767 err = drm_ioctl(file, DRM_IOCTL_AGP_INFO, (unsigned long)info);
785 DRM_IOCTL_AGP_INFO, (unsigned long)info);
786 if (err) 768 if (err)
787 return err; 769 return err;
788 770
@@ -827,16 +809,14 @@ static int compat_drm_agp_alloc(struct file *file, unsigned int cmd,
827 || __put_user(req32.type, &request->type)) 809 || __put_user(req32.type, &request->type))
828 return -EFAULT; 810 return -EFAULT;
829 811
830 err = drm_ioctl(file->f_path.dentry->d_inode, file, 812 err = drm_ioctl(file, DRM_IOCTL_AGP_ALLOC, (unsigned long)request);
831 DRM_IOCTL_AGP_ALLOC, (unsigned long)request);
832 if (err) 813 if (err)
833 return err; 814 return err;
834 815
835 if (__get_user(req32.handle, &request->handle) 816 if (__get_user(req32.handle, &request->handle)
836 || __get_user(req32.physical, &request->physical) 817 || __get_user(req32.physical, &request->physical)
837 || copy_to_user(argp, &req32, sizeof(req32))) { 818 || copy_to_user(argp, &req32, sizeof(req32))) {
838 drm_ioctl(file->f_path.dentry->d_inode, file, 819 drm_ioctl(file, DRM_IOCTL_AGP_FREE, (unsigned long)request);
839 DRM_IOCTL_AGP_FREE, (unsigned long)request);
840 return -EFAULT; 820 return -EFAULT;
841 } 821 }
842 822
@@ -856,8 +836,7 @@ static int compat_drm_agp_free(struct file *file, unsigned int cmd,
856 || __put_user(handle, &request->handle)) 836 || __put_user(handle, &request->handle))
857 return -EFAULT; 837 return -EFAULT;
858 838
859 return drm_ioctl(file->f_path.dentry->d_inode, file, 839 return drm_ioctl(file, DRM_IOCTL_AGP_FREE, (unsigned long)request);
860 DRM_IOCTL_AGP_FREE, (unsigned long)request);
861} 840}
862 841
863typedef struct drm_agp_binding32 { 842typedef struct drm_agp_binding32 {
@@ -881,8 +860,7 @@ static int compat_drm_agp_bind(struct file *file, unsigned int cmd,
881 || __put_user(req32.offset, &request->offset)) 860 || __put_user(req32.offset, &request->offset))
882 return -EFAULT; 861 return -EFAULT;
883 862
884 return drm_ioctl(file->f_path.dentry->d_inode, file, 863 return drm_ioctl(file, DRM_IOCTL_AGP_BIND, (unsigned long)request);
885 DRM_IOCTL_AGP_BIND, (unsigned long)request);
886} 864}
887 865
888static int compat_drm_agp_unbind(struct file *file, unsigned int cmd, 866static int compat_drm_agp_unbind(struct file *file, unsigned int cmd,
@@ -898,8 +876,7 @@ static int compat_drm_agp_unbind(struct file *file, unsigned int cmd,
898 || __put_user(handle, &request->handle)) 876 || __put_user(handle, &request->handle))
899 return -EFAULT; 877 return -EFAULT;
900 878
901 return drm_ioctl(file->f_path.dentry->d_inode, file, 879 return drm_ioctl(file, DRM_IOCTL_AGP_UNBIND, (unsigned long)request);
902 DRM_IOCTL_AGP_UNBIND, (unsigned long)request);
903} 880}
904#endif /* __OS_HAS_AGP */ 881#endif /* __OS_HAS_AGP */
905 882
@@ -923,8 +900,7 @@ static int compat_drm_sg_alloc(struct file *file, unsigned int cmd,
923 || __put_user(x, &request->size)) 900 || __put_user(x, &request->size))
924 return -EFAULT; 901 return -EFAULT;
925 902
926 err = drm_ioctl(file->f_path.dentry->d_inode, file, 903 err = drm_ioctl(file, DRM_IOCTL_SG_ALLOC, (unsigned long)request);
927 DRM_IOCTL_SG_ALLOC, (unsigned long)request);
928 if (err) 904 if (err)
929 return err; 905 return err;
930 906
@@ -950,8 +926,7 @@ static int compat_drm_sg_free(struct file *file, unsigned int cmd,
950 || __put_user(x << PAGE_SHIFT, &request->handle)) 926 || __put_user(x << PAGE_SHIFT, &request->handle))
951 return -EFAULT; 927 return -EFAULT;
952 928
953 return drm_ioctl(file->f_path.dentry->d_inode, file, 929 return drm_ioctl(file, DRM_IOCTL_SG_FREE, (unsigned long)request);
954 DRM_IOCTL_SG_FREE, (unsigned long)request);
955} 930}
956 931
957#if defined(CONFIG_X86) || defined(CONFIG_IA64) 932#if defined(CONFIG_X86) || defined(CONFIG_IA64)
@@ -981,8 +956,7 @@ static int compat_drm_update_draw(struct file *file, unsigned int cmd,
981 __put_user(update32.data, &request->data)) 956 __put_user(update32.data, &request->data))
982 return -EFAULT; 957 return -EFAULT;
983 958
984 err = drm_ioctl(file->f_path.dentry->d_inode, file, 959 err = drm_ioctl(file, DRM_IOCTL_UPDATE_DRAW, (unsigned long)request);
985 DRM_IOCTL_UPDATE_DRAW, (unsigned long)request);
986 return err; 960 return err;
987} 961}
988#endif 962#endif
@@ -1023,8 +997,7 @@ static int compat_drm_wait_vblank(struct file *file, unsigned int cmd,
1023 || __put_user(req32.request.signal, &request->request.signal)) 997 || __put_user(req32.request.signal, &request->request.signal))
1024 return -EFAULT; 998 return -EFAULT;
1025 999
1026 err = drm_ioctl(file->f_path.dentry->d_inode, file, 1000 err = drm_ioctl(file, DRM_IOCTL_WAIT_VBLANK, (unsigned long)request);
1027 DRM_IOCTL_WAIT_VBLANK, (unsigned long)request);
1028 if (err) 1001 if (err)
1029 return err; 1002 return err;
1030 1003
@@ -1094,16 +1067,14 @@ long drm_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1094 * than always failing. 1067 * than always failing.
1095 */ 1068 */
1096 if (nr >= ARRAY_SIZE(drm_compat_ioctls)) 1069 if (nr >= ARRAY_SIZE(drm_compat_ioctls))
1097 return drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 1070 return drm_ioctl(filp, cmd, arg);
1098 1071
1099 fn = drm_compat_ioctls[nr]; 1072 fn = drm_compat_ioctls[nr];
1100 1073
1101 lock_kernel(); /* XXX for now */
1102 if (fn != NULL) 1074 if (fn != NULL)
1103 ret = (*fn) (filp, cmd, arg); 1075 ret = (*fn) (filp, cmd, arg);
1104 else 1076 else
1105 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 1077 ret = drm_ioctl(filp, cmd, arg);
1106 unlock_kernel();
1107 1078
1108 return ret; 1079 return ret;
1109} 1080}
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index d7d7eac3ddd2..cdec32977129 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -358,7 +358,7 @@ struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm,
358 if (entry->size >= size + wasted) { 358 if (entry->size >= size + wasted) {
359 if (!best_match) 359 if (!best_match)
360 return entry; 360 return entry;
361 if (size < best_size) { 361 if (entry->size < best_size) {
362 best = entry; 362 best = entry;
363 best_size = entry->size; 363 best_size = entry->size;
364 } 364 }
@@ -408,7 +408,7 @@ struct drm_mm_node *drm_mm_search_free_in_range(const struct drm_mm *mm,
408 if (entry->size >= size + wasted) { 408 if (entry->size >= size + wasted) {
409 if (!best_match) 409 if (!best_match)
410 return entry; 410 return entry;
411 if (size < best_size) { 411 if (entry->size < best_size) {
412 best = entry; 412 best = entry;
413 best_size = entry->size; 413 best_size = entry->size;
414 } 414 }
diff --git a/drivers/gpu/drm/i2c/ch7006_drv.c b/drivers/gpu/drm/i2c/ch7006_drv.c
index 9422a74c8b54..81681a07a806 100644
--- a/drivers/gpu/drm/i2c/ch7006_drv.c
+++ b/drivers/gpu/drm/i2c/ch7006_drv.c
@@ -408,6 +408,11 @@ static int ch7006_probe(struct i2c_client *client, const struct i2c_device_id *i
408 408
409 ch7006_info(client, "Detected version ID: %x\n", val); 409 ch7006_info(client, "Detected version ID: %x\n", val);
410 410
411 /* I don't know what this is for, but otherwise I get no
412 * signal.
413 */
414 ch7006_write(client, 0x3d, 0x0);
415
411 return 0; 416 return 0;
412 417
413fail: 418fail:
diff --git a/drivers/gpu/drm/i2c/ch7006_mode.c b/drivers/gpu/drm/i2c/ch7006_mode.c
index 87f5445092e8..e447dfb63890 100644
--- a/drivers/gpu/drm/i2c/ch7006_mode.c
+++ b/drivers/gpu/drm/i2c/ch7006_mode.c
@@ -427,11 +427,6 @@ void ch7006_state_load(struct i2c_client *client,
427 ch7006_load_reg(client, state, CH7006_SUBC_INC7); 427 ch7006_load_reg(client, state, CH7006_SUBC_INC7);
428 ch7006_load_reg(client, state, CH7006_PLL_CONTROL); 428 ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
429 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0); 429 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
430
431 /* I don't know what this is for, but otherwise I get no
432 * signal.
433 */
434 ch7006_write(client, 0x3d, 0x0);
435} 430}
436 431
437void ch7006_state_save(struct i2c_client *client, 432void ch7006_state_save(struct i2c_client *client,
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index 7d1d88cdf2dc..de32d22a8c39 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -115,7 +115,7 @@ static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
115static const struct file_operations i810_buffer_fops = { 115static const struct file_operations i810_buffer_fops = {
116 .open = drm_open, 116 .open = drm_open,
117 .release = drm_release, 117 .release = drm_release,
118 .ioctl = drm_ioctl, 118 .unlocked_ioctl = drm_ioctl,
119 .mmap = i810_mmap_buffers, 119 .mmap = i810_mmap_buffers,
120 .fasync = drm_fasync, 120 .fasync = drm_fasync,
121}; 121};
diff --git a/drivers/gpu/drm/i810/i810_drv.c b/drivers/gpu/drm/i810/i810_drv.c
index fabb9a817966..c1e02752e023 100644
--- a/drivers/gpu/drm/i810/i810_drv.c
+++ b/drivers/gpu/drm/i810/i810_drv.c
@@ -59,7 +59,7 @@ static struct drm_driver driver = {
59 .owner = THIS_MODULE, 59 .owner = THIS_MODULE,
60 .open = drm_open, 60 .open = drm_open,
61 .release = drm_release, 61 .release = drm_release,
62 .ioctl = drm_ioctl, 62 .unlocked_ioctl = drm_ioctl,
63 .mmap = drm_mmap, 63 .mmap = drm_mmap,
64 .poll = drm_poll, 64 .poll = drm_poll,
65 .fasync = drm_fasync, 65 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/i830/i830_dma.c b/drivers/gpu/drm/i830/i830_dma.c
index 877bf6cb14a4..06bd732e6463 100644
--- a/drivers/gpu/drm/i830/i830_dma.c
+++ b/drivers/gpu/drm/i830/i830_dma.c
@@ -117,7 +117,7 @@ static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
117static const struct file_operations i830_buffer_fops = { 117static const struct file_operations i830_buffer_fops = {
118 .open = drm_open, 118 .open = drm_open,
119 .release = drm_release, 119 .release = drm_release,
120 .ioctl = drm_ioctl, 120 .unlocked_ioctl = drm_ioctl,
121 .mmap = i830_mmap_buffers, 121 .mmap = i830_mmap_buffers,
122 .fasync = drm_fasync, 122 .fasync = drm_fasync,
123}; 123};
diff --git a/drivers/gpu/drm/i830/i830_drv.c b/drivers/gpu/drm/i830/i830_drv.c
index 389597e4a623..44f990bed8f4 100644
--- a/drivers/gpu/drm/i830/i830_drv.c
+++ b/drivers/gpu/drm/i830/i830_drv.c
@@ -70,7 +70,7 @@ static struct drm_driver driver = {
70 .owner = THIS_MODULE, 70 .owner = THIS_MODULE,
71 .open = drm_open, 71 .open = drm_open,
72 .release = drm_release, 72 .release = drm_release,
73 .ioctl = drm_ioctl, 73 .unlocked_ioctl = drm_ioctl,
74 .mmap = drm_mmap, 74 .mmap = drm_mmap,
75 .poll = drm_poll, 75 .poll = drm_poll,
76 .fasync = drm_fasync, 76 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2fa217862058..24286ca168fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -329,7 +329,7 @@ static struct drm_driver driver = {
329 .owner = THIS_MODULE, 329 .owner = THIS_MODULE,
330 .open = drm_open, 330 .open = drm_open,
331 .release = drm_release, 331 .release = drm_release,
332 .ioctl = drm_ioctl, 332 .unlocked_ioctl = drm_ioctl,
333 .mmap = drm_gem_mmap, 333 .mmap = drm_gem_mmap,
334 .poll = drm_poll, 334 .poll = drm_poll,
335 .fasync = drm_fasync, 335 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/i915/i915_ioc32.c b/drivers/gpu/drm/i915/i915_ioc32.c
index 1fe68a251b75..13b028994b2b 100644
--- a/drivers/gpu/drm/i915/i915_ioc32.c
+++ b/drivers/gpu/drm/i915/i915_ioc32.c
@@ -66,8 +66,7 @@ static int compat_i915_batchbuffer(struct file *file, unsigned int cmd,
66 &batchbuffer->cliprects)) 66 &batchbuffer->cliprects))
67 return -EFAULT; 67 return -EFAULT;
68 68
69 return drm_ioctl(file->f_path.dentry->d_inode, file, 69 return drm_ioctl(file, DRM_IOCTL_I915_BATCHBUFFER,
70 DRM_IOCTL_I915_BATCHBUFFER,
71 (unsigned long)batchbuffer); 70 (unsigned long)batchbuffer);
72} 71}
73 72
@@ -102,8 +101,8 @@ static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd,
102 &cmdbuffer->cliprects)) 101 &cmdbuffer->cliprects))
103 return -EFAULT; 102 return -EFAULT;
104 103
105 return drm_ioctl(file->f_path.dentry->d_inode, file, 104 return drm_ioctl(file, DRM_IOCTL_I915_CMDBUFFER,
106 DRM_IOCTL_I915_CMDBUFFER, (unsigned long)cmdbuffer); 105 (unsigned long)cmdbuffer);
107} 106}
108 107
109typedef struct drm_i915_irq_emit32 { 108typedef struct drm_i915_irq_emit32 {
@@ -125,8 +124,8 @@ static int compat_i915_irq_emit(struct file *file, unsigned int cmd,
125 &request->irq_seq)) 124 &request->irq_seq))
126 return -EFAULT; 125 return -EFAULT;
127 126
128 return drm_ioctl(file->f_path.dentry->d_inode, file, 127 return drm_ioctl(file, DRM_IOCTL_I915_IRQ_EMIT,
129 DRM_IOCTL_I915_IRQ_EMIT, (unsigned long)request); 128 (unsigned long)request);
130} 129}
131typedef struct drm_i915_getparam32 { 130typedef struct drm_i915_getparam32 {
132 int param; 131 int param;
@@ -149,8 +148,8 @@ static int compat_i915_getparam(struct file *file, unsigned int cmd,
149 &request->value)) 148 &request->value))
150 return -EFAULT; 149 return -EFAULT;
151 150
152 return drm_ioctl(file->f_path.dentry->d_inode, file, 151 return drm_ioctl(file, DRM_IOCTL_I915_GETPARAM,
153 DRM_IOCTL_I915_GETPARAM, (unsigned long)request); 152 (unsigned long)request);
154} 153}
155 154
156typedef struct drm_i915_mem_alloc32 { 155typedef struct drm_i915_mem_alloc32 {
@@ -178,8 +177,8 @@ static int compat_i915_alloc(struct file *file, unsigned int cmd,
178 &request->region_offset)) 177 &request->region_offset))
179 return -EFAULT; 178 return -EFAULT;
180 179
181 return drm_ioctl(file->f_path.dentry->d_inode, file, 180 return drm_ioctl(file, DRM_IOCTL_I915_ALLOC,
182 DRM_IOCTL_I915_ALLOC, (unsigned long)request); 181 (unsigned long)request);
183} 182}
184 183
185drm_ioctl_compat_t *i915_compat_ioctls[] = { 184drm_ioctl_compat_t *i915_compat_ioctls[] = {
@@ -211,12 +210,10 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
211 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls)) 210 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls))
212 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE]; 211 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE];
213 212
214 lock_kernel(); /* XXX for now */
215 if (fn != NULL) 213 if (fn != NULL)
216 ret = (*fn) (filp, cmd, arg); 214 ret = (*fn) (filp, cmd, arg);
217 else 215 else
218 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 216 ret = drm_ioctl(filp, cmd, arg);
219 unlock_kernel();
220 217
221 return ret; 218 return ret;
222} 219}
diff --git a/drivers/gpu/drm/mga/mga_drv.c b/drivers/gpu/drm/mga/mga_drv.c
index 97ee566ef749..ddfe16197b59 100644
--- a/drivers/gpu/drm/mga/mga_drv.c
+++ b/drivers/gpu/drm/mga/mga_drv.c
@@ -68,7 +68,7 @@ static struct drm_driver driver = {
68 .owner = THIS_MODULE, 68 .owner = THIS_MODULE,
69 .open = drm_open, 69 .open = drm_open,
70 .release = drm_release, 70 .release = drm_release,
71 .ioctl = drm_ioctl, 71 .unlocked_ioctl = drm_ioctl,
72 .mmap = drm_mmap, 72 .mmap = drm_mmap,
73 .poll = drm_poll, 73 .poll = drm_poll,
74 .fasync = drm_fasync, 74 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/mga/mga_ioc32.c b/drivers/gpu/drm/mga/mga_ioc32.c
index 30d00478ddee..c1f877b7bac1 100644
--- a/drivers/gpu/drm/mga/mga_ioc32.c
+++ b/drivers/gpu/drm/mga/mga_ioc32.c
@@ -100,8 +100,7 @@ static int compat_mga_init(struct file *file, unsigned int cmd,
100 if (err) 100 if (err)
101 return -EFAULT; 101 return -EFAULT;
102 102
103 return drm_ioctl(file->f_path.dentry->d_inode, file, 103 return drm_ioctl(file, DRM_IOCTL_MGA_INIT, (unsigned long)init);
104 DRM_IOCTL_MGA_INIT, (unsigned long)init);
105} 104}
106 105
107typedef struct drm_mga_getparam32 { 106typedef struct drm_mga_getparam32 {
@@ -125,8 +124,7 @@ static int compat_mga_getparam(struct file *file, unsigned int cmd,
125 &getparam->value)) 124 &getparam->value))
126 return -EFAULT; 125 return -EFAULT;
127 126
128 return drm_ioctl(file->f_path.dentry->d_inode, file, 127 return drm_ioctl(file, DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
129 DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
130} 128}
131 129
132typedef struct drm_mga_drm_bootstrap32 { 130typedef struct drm_mga_drm_bootstrap32 {
@@ -166,8 +164,7 @@ static int compat_mga_dma_bootstrap(struct file *file, unsigned int cmd,
166 || __put_user(dma_bootstrap32.agp_size, &dma_bootstrap->agp_size)) 164 || __put_user(dma_bootstrap32.agp_size, &dma_bootstrap->agp_size))
167 return -EFAULT; 165 return -EFAULT;
168 166
169 err = drm_ioctl(file->f_path.dentry->d_inode, file, 167 err = drm_ioctl(file, DRM_IOCTL_MGA_DMA_BOOTSTRAP,
170 DRM_IOCTL_MGA_DMA_BOOTSTRAP,
171 (unsigned long)dma_bootstrap); 168 (unsigned long)dma_bootstrap);
172 if (err) 169 if (err)
173 return err; 170 return err;
@@ -220,12 +217,10 @@ long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
220 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) 217 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
221 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE]; 218 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE];
222 219
223 lock_kernel(); /* XXX for now */
224 if (fn != NULL) 220 if (fn != NULL)
225 ret = (*fn) (filp, cmd, arg); 221 ret = (*fn) (filp, cmd, arg);
226 else 222 else
227 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 223 ret = drm_ioctl(filp, cmd, arg);
228 unlock_kernel();
229 224
230 return ret; 225 return ret;
231} 226}
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 1d90d4d0144f..48c290b5da8c 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -8,14 +8,15 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
8 nouveau_sgdma.o nouveau_dma.o \ 8 nouveau_sgdma.o nouveau_dma.o \
9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ 9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ 10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ 11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
12 nouveau_dp.o \ 12 nouveau_dp.o nouveau_grctx.o \
13 nv04_timer.o \ 13 nv04_timer.o \
14 nv04_mc.o nv40_mc.o nv50_mc.o \ 14 nv04_mc.o nv40_mc.o nv50_mc.o \
15 nv04_fb.o nv10_fb.o nv40_fb.o \ 15 nv04_fb.o nv10_fb.o nv40_fb.o \
16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \ 16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \
17 nv04_graph.o nv10_graph.o nv20_graph.o \ 17 nv04_graph.o nv10_graph.o nv20_graph.o \
18 nv40_graph.o nv50_graph.o \ 18 nv40_graph.o nv50_graph.o \
19 nv40_grctx.o \
19 nv04_instmem.o nv50_instmem.o \ 20 nv04_instmem.o nv50_instmem.o \
20 nv50_crtc.o nv50_dac.o nv50_sor.o \ 21 nv50_crtc.o nv50_dac.o nv50_sor.o \
21 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 22 nv50_cursor.o nv50_display.o nv50_fbcon.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 5eec5ed69489..ba143972769f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -181,43 +181,42 @@ struct methods {
181 const char desc[8]; 181 const char desc[8];
182 void (*loadbios)(struct drm_device *, uint8_t *); 182 void (*loadbios)(struct drm_device *, uint8_t *);
183 const bool rw; 183 const bool rw;
184 int score;
185}; 184};
186 185
187static struct methods nv04_methods[] = { 186static struct methods nv04_methods[] = {
188 { "PROM", load_vbios_prom, false }, 187 { "PROM", load_vbios_prom, false },
189 { "PRAMIN", load_vbios_pramin, true }, 188 { "PRAMIN", load_vbios_pramin, true },
190 { "PCIROM", load_vbios_pci, true }, 189 { "PCIROM", load_vbios_pci, true },
191 { }
192}; 190};
193 191
194static struct methods nv50_methods[] = { 192static struct methods nv50_methods[] = {
195 { "PRAMIN", load_vbios_pramin, true }, 193 { "PRAMIN", load_vbios_pramin, true },
196 { "PROM", load_vbios_prom, false }, 194 { "PROM", load_vbios_prom, false },
197 { "PCIROM", load_vbios_pci, true }, 195 { "PCIROM", load_vbios_pci, true },
198 { }
199}; 196};
200 197
198#define METHODCNT 3
199
201static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 200static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
202{ 201{
203 struct drm_nouveau_private *dev_priv = dev->dev_private; 202 struct drm_nouveau_private *dev_priv = dev->dev_private;
204 struct methods *methods, *method; 203 struct methods *methods;
204 int i;
205 int testscore = 3; 205 int testscore = 3;
206 int scores[METHODCNT];
206 207
207 if (nouveau_vbios) { 208 if (nouveau_vbios) {
208 method = nv04_methods; 209 methods = nv04_methods;
209 while (method->loadbios) { 210 for (i = 0; i < METHODCNT; i++)
210 if (!strcasecmp(nouveau_vbios, method->desc)) 211 if (!strcasecmp(nouveau_vbios, methods[i].desc))
211 break; 212 break;
212 method++;
213 }
214 213
215 if (method->loadbios) { 214 if (i < METHODCNT) {
216 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 215 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
217 method->desc); 216 methods[i].desc);
218 217
219 method->loadbios(dev, data); 218 methods[i].loadbios(dev, data);
220 if (score_vbios(dev, data, method->rw)) 219 if (score_vbios(dev, data, methods[i].rw))
221 return true; 220 return true;
222 } 221 }
223 222
@@ -229,28 +228,24 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
229 else 228 else
230 methods = nv50_methods; 229 methods = nv50_methods;
231 230
232 method = methods; 231 for (i = 0; i < METHODCNT; i++) {
233 while (method->loadbios) {
234 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
235 method->desc); 233 methods[i].desc);
236 data[0] = data[1] = 0; /* avoid reuse of previous image */ 234 data[0] = data[1] = 0; /* avoid reuse of previous image */
237 method->loadbios(dev, data); 235 methods[i].loadbios(dev, data);
238 method->score = score_vbios(dev, data, method->rw); 236 scores[i] = score_vbios(dev, data, methods[i].rw);
239 if (method->score == testscore) 237 if (scores[i] == testscore)
240 return true; 238 return true;
241 method++;
242 } 239 }
243 240
244 while (--testscore > 0) { 241 while (--testscore > 0) {
245 method = methods; 242 for (i = 0; i < METHODCNT; i++) {
246 while (method->loadbios) { 243 if (scores[i] == testscore) {
247 if (method->score == testscore) {
248 NV_TRACE(dev, "Using BIOS image from %s\n", 244 NV_TRACE(dev, "Using BIOS image from %s\n",
249 method->desc); 245 methods[i].desc);
250 method->loadbios(dev, data); 246 methods[i].loadbios(dev, data);
251 return true; 247 return true;
252 } 248 }
253 method++;
254 } 249 }
255 } 250 }
256 251
@@ -261,10 +256,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
261struct init_tbl_entry { 256struct init_tbl_entry {
262 char *name; 257 char *name;
263 uint8_t id; 258 uint8_t id;
264 int length; 259 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
265 int length_offset;
266 int length_multiplier;
267 bool (*handler)(struct nvbios *, uint16_t, struct init_exec *);
268}; 260};
269 261
270struct bit_entry { 262struct bit_entry {
@@ -820,7 +812,7 @@ static uint32_t get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
820 } 812 }
821} 813}
822 814
823static bool 815static int
824init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 816init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
825 struct init_exec *iexec) 817 struct init_exec *iexec)
826{ 818{
@@ -852,9 +844,10 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
852 uint32_t reg = ROM32(bios->data[offset + 7]); 844 uint32_t reg = ROM32(bios->data[offset + 7]);
853 uint8_t config; 845 uint8_t config;
854 uint32_t configval; 846 uint32_t configval;
847 int len = 11 + count * 4;
855 848
856 if (!iexec->execute) 849 if (!iexec->execute)
857 return true; 850 return len;
858 851
859 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 852 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
860 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 853 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
@@ -865,7 +858,7 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
865 NV_ERROR(bios->dev, 858 NV_ERROR(bios->dev,
866 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 859 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
867 offset, config, count); 860 offset, config, count);
868 return false; 861 return 0;
869 } 862 }
870 863
871 configval = ROM32(bios->data[offset + 11 + config * 4]); 864 configval = ROM32(bios->data[offset + 11 + config * 4]);
@@ -874,10 +867,10 @@ init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
874 867
875 bios_wr32(bios, reg, configval); 868 bios_wr32(bios, reg, configval);
876 869
877 return true; 870 return len;
878} 871}
879 872
880static bool 873static int
881init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 874init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
882{ 875{
883 /* 876 /*
@@ -912,10 +905,10 @@ init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
912 905
913 iexec->repeat = false; 906 iexec->repeat = false;
914 907
915 return true; 908 return 2;
916} 909}
917 910
918static bool 911static int
919init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 912init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
920 struct init_exec *iexec) 913 struct init_exec *iexec)
921{ 914{
@@ -951,9 +944,10 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
951 uint32_t reg = ROM32(bios->data[offset + 8]); 944 uint32_t reg = ROM32(bios->data[offset + 8]);
952 uint8_t config; 945 uint8_t config;
953 uint16_t freq; 946 uint16_t freq;
947 int len = 12 + count * 2;
954 948
955 if (!iexec->execute) 949 if (!iexec->execute)
956 return true; 950 return len;
957 951
958 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 952 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
959 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 953 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
@@ -966,7 +960,7 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
966 NV_ERROR(bios->dev, 960 NV_ERROR(bios->dev,
967 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 961 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
968 offset, config, count); 962 offset, config, count);
969 return false; 963 return 0;
970 } 964 }
971 965
972 freq = ROM16(bios->data[offset + 12 + config * 2]); 966 freq = ROM16(bios->data[offset + 12 + config * 2]);
@@ -986,10 +980,10 @@ init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
986 980
987 setPLL(bios, reg, freq * 10); 981 setPLL(bios, reg, freq * 10);
988 982
989 return true; 983 return len;
990} 984}
991 985
992static bool 986static int
993init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 987init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
994{ 988{
995 /* 989 /*
@@ -1007,12 +1001,12 @@ init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1007 * we're not in repeat mode 1001 * we're not in repeat mode
1008 */ 1002 */
1009 if (iexec->repeat) 1003 if (iexec->repeat)
1010 return false; 1004 return 0;
1011 1005
1012 return true; 1006 return 1;
1013} 1007}
1014 1008
1015static bool 1009static int
1016init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1010init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1017{ 1011{
1018 /* 1012 /*
@@ -1041,7 +1035,7 @@ init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1041 uint8_t crtcdata; 1035 uint8_t crtcdata;
1042 1036
1043 if (!iexec->execute) 1037 if (!iexec->execute)
1044 return true; 1038 return 11;
1045 1039
1046 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1040 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1047 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1041 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
@@ -1060,10 +1054,10 @@ init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1060 crtcdata |= (uint8_t)data; 1054 crtcdata |= (uint8_t)data;
1061 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1055 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1062 1056
1063 return true; 1057 return 11;
1064} 1058}
1065 1059
1066static bool 1060static int
1067init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1061init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1068{ 1062{
1069 /* 1063 /*
@@ -1079,10 +1073,10 @@ init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1079 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1073 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1080 1074
1081 iexec->execute = !iexec->execute; 1075 iexec->execute = !iexec->execute;
1082 return true; 1076 return 1;
1083} 1077}
1084 1078
1085static bool 1079static int
1086init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1080init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1087 struct init_exec *iexec) 1081 struct init_exec *iexec)
1088{ 1082{
@@ -1100,7 +1094,7 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1100 uint8_t cond = bios->data[offset + 1]; 1094 uint8_t cond = bios->data[offset + 1];
1101 1095
1102 if (!iexec->execute) 1096 if (!iexec->execute)
1103 return true; 1097 return 2;
1104 1098
1105 if (io_flag_condition_met(bios, offset, cond)) 1099 if (io_flag_condition_met(bios, offset, cond))
1106 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1100 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
@@ -1109,10 +1103,10 @@ init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1109 iexec->execute = false; 1103 iexec->execute = false;
1110 } 1104 }
1111 1105
1112 return true; 1106 return 2;
1113} 1107}
1114 1108
1115static bool 1109static int
1116init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1110init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1117 struct init_exec *iexec) 1111 struct init_exec *iexec)
1118{ 1112{
@@ -1140,11 +1134,12 @@ init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1140 uint32_t mask = ROM32(bios->data[offset + 9]); 1134 uint32_t mask = ROM32(bios->data[offset + 9]);
1141 uint32_t data = ROM32(bios->data[offset + 13]); 1135 uint32_t data = ROM32(bios->data[offset + 13]);
1142 uint8_t count = bios->data[offset + 17]; 1136 uint8_t count = bios->data[offset + 17];
1137 int len = 18 + count * 2;
1143 uint32_t value; 1138 uint32_t value;
1144 int i; 1139 int i;
1145 1140
1146 if (!iexec->execute) 1141 if (!iexec->execute)
1147 return true; 1142 return len;
1148 1143
1149 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1144 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1150 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1145 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
@@ -1164,10 +1159,10 @@ init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1164 bios_wr32(bios, controlreg, value); 1159 bios_wr32(bios, controlreg, value);
1165 } 1160 }
1166 1161
1167 return true; 1162 return len;
1168} 1163}
1169 1164
1170static bool 1165static int
1171init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1166init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1172 struct init_exec *iexec) 1167 struct init_exec *iexec)
1173{ 1168{
@@ -1196,25 +1191,26 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1196 uint8_t shift = bios->data[offset + 5]; 1191 uint8_t shift = bios->data[offset + 5];
1197 uint8_t count = bios->data[offset + 6]; 1192 uint8_t count = bios->data[offset + 6];
1198 uint32_t reg = ROM32(bios->data[offset + 7]); 1193 uint32_t reg = ROM32(bios->data[offset + 7]);
1194 int len = 11 + count * 4;
1199 uint8_t config; 1195 uint8_t config;
1200 uint32_t freq; 1196 uint32_t freq;
1201 1197
1202 if (!iexec->execute) 1198 if (!iexec->execute)
1203 return true; 1199 return len;
1204 1200
1205 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1201 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1206 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1202 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1207 offset, crtcport, crtcindex, mask, shift, count, reg); 1203 offset, crtcport, crtcindex, mask, shift, count, reg);
1208 1204
1209 if (!reg) 1205 if (!reg)
1210 return true; 1206 return len;
1211 1207
1212 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1208 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1213 if (config > count) { 1209 if (config > count) {
1214 NV_ERROR(bios->dev, 1210 NV_ERROR(bios->dev,
1215 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1211 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1216 offset, config, count); 1212 offset, config, count);
1217 return false; 1213 return 0;
1218 } 1214 }
1219 1215
1220 freq = ROM32(bios->data[offset + 11 + config * 4]); 1216 freq = ROM32(bios->data[offset + 11 + config * 4]);
@@ -1224,10 +1220,10 @@ init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1224 1220
1225 setPLL(bios, reg, freq); 1221 setPLL(bios, reg, freq);
1226 1222
1227 return true; 1223 return len;
1228} 1224}
1229 1225
1230static bool 1226static int
1231init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1227init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1232{ 1228{
1233 /* 1229 /*
@@ -1244,16 +1240,16 @@ init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1244 uint32_t freq = ROM32(bios->data[offset + 5]); 1240 uint32_t freq = ROM32(bios->data[offset + 5]);
1245 1241
1246 if (!iexec->execute) 1242 if (!iexec->execute)
1247 return true; 1243 return 9;
1248 1244
1249 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1245 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1250 offset, reg, freq); 1246 offset, reg, freq);
1251 1247
1252 setPLL(bios, reg, freq); 1248 setPLL(bios, reg, freq);
1253 return true; 1249 return 9;
1254} 1250}
1255 1251
1256static bool 1252static int
1257init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1253init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1258{ 1254{
1259 /* 1255 /*
@@ -1277,12 +1273,13 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1277 uint8_t i2c_index = bios->data[offset + 1]; 1273 uint8_t i2c_index = bios->data[offset + 1];
1278 uint8_t i2c_address = bios->data[offset + 2]; 1274 uint8_t i2c_address = bios->data[offset + 2];
1279 uint8_t count = bios->data[offset + 3]; 1275 uint8_t count = bios->data[offset + 3];
1276 int len = 4 + count * 3;
1280 struct nouveau_i2c_chan *chan; 1277 struct nouveau_i2c_chan *chan;
1281 struct i2c_msg msg; 1278 struct i2c_msg msg;
1282 int i; 1279 int i;
1283 1280
1284 if (!iexec->execute) 1281 if (!iexec->execute)
1285 return true; 1282 return len;
1286 1283
1287 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1284 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1288 "Count: 0x%02X\n", 1285 "Count: 0x%02X\n",
@@ -1290,7 +1287,7 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1290 1287
1291 chan = init_i2c_device_find(bios->dev, i2c_index); 1288 chan = init_i2c_device_find(bios->dev, i2c_index);
1292 if (!chan) 1289 if (!chan)
1293 return false; 1290 return 0;
1294 1291
1295 for (i = 0; i < count; i++) { 1292 for (i = 0; i < count; i++) {
1296 uint8_t i2c_reg = bios->data[offset + 4 + i * 3]; 1293 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
@@ -1303,7 +1300,7 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1303 msg.len = 1; 1300 msg.len = 1;
1304 msg.buf = &value; 1301 msg.buf = &value;
1305 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1302 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1306 return false; 1303 return 0;
1307 1304
1308 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1305 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1309 "Mask: 0x%02X, Data: 0x%02X\n", 1306 "Mask: 0x%02X, Data: 0x%02X\n",
@@ -1317,14 +1314,14 @@ init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1317 msg.len = 1; 1314 msg.len = 1;
1318 msg.buf = &value; 1315 msg.buf = &value;
1319 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1316 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1320 return false; 1317 return 0;
1321 } 1318 }
1322 } 1319 }
1323 1320
1324 return true; 1321 return len;
1325} 1322}
1326 1323
1327static bool 1324static int
1328init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1325init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1329{ 1326{
1330 /* 1327 /*
@@ -1346,12 +1343,13 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1346 uint8_t i2c_index = bios->data[offset + 1]; 1343 uint8_t i2c_index = bios->data[offset + 1];
1347 uint8_t i2c_address = bios->data[offset + 2]; 1344 uint8_t i2c_address = bios->data[offset + 2];
1348 uint8_t count = bios->data[offset + 3]; 1345 uint8_t count = bios->data[offset + 3];
1346 int len = 4 + count * 2;
1349 struct nouveau_i2c_chan *chan; 1347 struct nouveau_i2c_chan *chan;
1350 struct i2c_msg msg; 1348 struct i2c_msg msg;
1351 int i; 1349 int i;
1352 1350
1353 if (!iexec->execute) 1351 if (!iexec->execute)
1354 return true; 1352 return len;
1355 1353
1356 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1354 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1357 "Count: 0x%02X\n", 1355 "Count: 0x%02X\n",
@@ -1359,7 +1357,7 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1359 1357
1360 chan = init_i2c_device_find(bios->dev, i2c_index); 1358 chan = init_i2c_device_find(bios->dev, i2c_index);
1361 if (!chan) 1359 if (!chan)
1362 return false; 1360 return 0;
1363 1361
1364 for (i = 0; i < count; i++) { 1362 for (i = 0; i < count; i++) {
1365 uint8_t i2c_reg = bios->data[offset + 4 + i * 2]; 1363 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
@@ -1374,14 +1372,14 @@ init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1374 msg.len = 1; 1372 msg.len = 1;
1375 msg.buf = &data; 1373 msg.buf = &data;
1376 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1374 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1377 return false; 1375 return 0;
1378 } 1376 }
1379 } 1377 }
1380 1378
1381 return true; 1379 return len;
1382} 1380}
1383 1381
1384static bool 1382static int
1385init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1383init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1386{ 1384{
1387 /* 1385 /*
@@ -1401,13 +1399,14 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1401 uint8_t i2c_index = bios->data[offset + 1]; 1399 uint8_t i2c_index = bios->data[offset + 1];
1402 uint8_t i2c_address = bios->data[offset + 2]; 1400 uint8_t i2c_address = bios->data[offset + 2];
1403 uint8_t count = bios->data[offset + 3]; 1401 uint8_t count = bios->data[offset + 3];
1402 int len = 4 + count;
1404 struct nouveau_i2c_chan *chan; 1403 struct nouveau_i2c_chan *chan;
1405 struct i2c_msg msg; 1404 struct i2c_msg msg;
1406 uint8_t data[256]; 1405 uint8_t data[256];
1407 int i; 1406 int i;
1408 1407
1409 if (!iexec->execute) 1408 if (!iexec->execute)
1410 return true; 1409 return len;
1411 1410
1412 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1411 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1413 "Count: 0x%02X\n", 1412 "Count: 0x%02X\n",
@@ -1415,7 +1414,7 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1415 1414
1416 chan = init_i2c_device_find(bios->dev, i2c_index); 1415 chan = init_i2c_device_find(bios->dev, i2c_index);
1417 if (!chan) 1416 if (!chan)
1418 return false; 1417 return 0;
1419 1418
1420 for (i = 0; i < count; i++) { 1419 for (i = 0; i < count; i++) {
1421 data[i] = bios->data[offset + 4 + i]; 1420 data[i] = bios->data[offset + 4 + i];
@@ -1429,13 +1428,13 @@ init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1429 msg.len = count; 1428 msg.len = count;
1430 msg.buf = data; 1429 msg.buf = data;
1431 if (i2c_transfer(&chan->adapter, &msg, 1) != 1) 1430 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
1432 return false; 1431 return 0;
1433 } 1432 }
1434 1433
1435 return true; 1434 return len;
1436} 1435}
1437 1436
1438static bool 1437static int
1439init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1438init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1440{ 1439{
1441 /* 1440 /*
@@ -1460,7 +1459,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1460 uint32_t reg, value; 1459 uint32_t reg, value;
1461 1460
1462 if (!iexec->execute) 1461 if (!iexec->execute)
1463 return true; 1462 return 5;
1464 1463
1465 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1464 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1466 "Mask: 0x%02X, Data: 0x%02X\n", 1465 "Mask: 0x%02X, Data: 0x%02X\n",
@@ -1468,7 +1467,7 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1468 1467
1469 reg = get_tmds_index_reg(bios->dev, mlv); 1468 reg = get_tmds_index_reg(bios->dev, mlv);
1470 if (!reg) 1469 if (!reg)
1471 return false; 1470 return 0;
1472 1471
1473 bios_wr32(bios, reg, 1472 bios_wr32(bios, reg,
1474 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1473 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
@@ -1476,10 +1475,10 @@ init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1476 bios_wr32(bios, reg + 4, value); 1475 bios_wr32(bios, reg + 4, value);
1477 bios_wr32(bios, reg, tmdsaddr); 1476 bios_wr32(bios, reg, tmdsaddr);
1478 1477
1479 return true; 1478 return 5;
1480} 1479}
1481 1480
1482static bool 1481static int
1483init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1482init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1484 struct init_exec *iexec) 1483 struct init_exec *iexec)
1485{ 1484{
@@ -1500,18 +1499,19 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1500 1499
1501 uint8_t mlv = bios->data[offset + 1]; 1500 uint8_t mlv = bios->data[offset + 1];
1502 uint8_t count = bios->data[offset + 2]; 1501 uint8_t count = bios->data[offset + 2];
1502 int len = 3 + count * 2;
1503 uint32_t reg; 1503 uint32_t reg;
1504 int i; 1504 int i;
1505 1505
1506 if (!iexec->execute) 1506 if (!iexec->execute)
1507 return true; 1507 return len;
1508 1508
1509 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1509 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1510 offset, mlv, count); 1510 offset, mlv, count);
1511 1511
1512 reg = get_tmds_index_reg(bios->dev, mlv); 1512 reg = get_tmds_index_reg(bios->dev, mlv);
1513 if (!reg) 1513 if (!reg)
1514 return false; 1514 return 0;
1515 1515
1516 for (i = 0; i < count; i++) { 1516 for (i = 0; i < count; i++) {
1517 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1517 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
@@ -1521,10 +1521,10 @@ init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1521 bios_wr32(bios, reg, tmdsaddr); 1521 bios_wr32(bios, reg, tmdsaddr);
1522 } 1522 }
1523 1523
1524 return true; 1524 return len;
1525} 1525}
1526 1526
1527static bool 1527static int
1528init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1528init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1529 struct init_exec *iexec) 1529 struct init_exec *iexec)
1530{ 1530{
@@ -1547,11 +1547,12 @@ init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1547 uint8_t crtcindex2 = bios->data[offset + 2]; 1547 uint8_t crtcindex2 = bios->data[offset + 2];
1548 uint8_t baseaddr = bios->data[offset + 3]; 1548 uint8_t baseaddr = bios->data[offset + 3];
1549 uint8_t count = bios->data[offset + 4]; 1549 uint8_t count = bios->data[offset + 4];
1550 int len = 5 + count;
1550 uint8_t oldaddr, data; 1551 uint8_t oldaddr, data;
1551 int i; 1552 int i;
1552 1553
1553 if (!iexec->execute) 1554 if (!iexec->execute)
1554 return true; 1555 return len;
1555 1556
1556 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1557 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1557 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1558 "BaseAddr: 0x%02X, Count: 0x%02X\n",
@@ -1568,10 +1569,10 @@ init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1568 1569
1569 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1570 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1570 1571
1571 return true; 1572 return len;
1572} 1573}
1573 1574
1574static bool 1575static int
1575init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1576init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1576{ 1577{
1577 /* 1578 /*
@@ -1592,7 +1593,7 @@ init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1592 uint8_t value; 1593 uint8_t value;
1593 1594
1594 if (!iexec->execute) 1595 if (!iexec->execute)
1595 return true; 1596 return 4;
1596 1597
1597 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1598 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1598 offset, crtcindex, mask, data); 1599 offset, crtcindex, mask, data);
@@ -1601,10 +1602,10 @@ init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1601 value |= data; 1602 value |= data;
1602 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1603 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1603 1604
1604 return true; 1605 return 4;
1605} 1606}
1606 1607
1607static bool 1608static int
1608init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1609init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1609{ 1610{
1610 /* 1611 /*
@@ -1621,14 +1622,14 @@ init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1621 uint8_t data = bios->data[offset + 2]; 1622 uint8_t data = bios->data[offset + 2];
1622 1623
1623 if (!iexec->execute) 1624 if (!iexec->execute)
1624 return true; 1625 return 3;
1625 1626
1626 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1627 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1627 1628
1628 return true; 1629 return 3;
1629} 1630}
1630 1631
1631static bool 1632static int
1632init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1633init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1633{ 1634{
1634 /* 1635 /*
@@ -1645,18 +1646,19 @@ init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1645 */ 1646 */
1646 1647
1647 uint8_t count = bios->data[offset + 1]; 1648 uint8_t count = bios->data[offset + 1];
1649 int len = 2 + count * 2;
1648 int i; 1650 int i;
1649 1651
1650 if (!iexec->execute) 1652 if (!iexec->execute)
1651 return true; 1653 return len;
1652 1654
1653 for (i = 0; i < count; i++) 1655 for (i = 0; i < count; i++)
1654 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1656 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1655 1657
1656 return true; 1658 return len;
1657} 1659}
1658 1660
1659static bool 1661static int
1660init_condition_time(struct nvbios *bios, uint16_t offset, 1662init_condition_time(struct nvbios *bios, uint16_t offset,
1661 struct init_exec *iexec) 1663 struct init_exec *iexec)
1662{ 1664{
@@ -1680,7 +1682,7 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
1680 unsigned cnt; 1682 unsigned cnt;
1681 1683
1682 if (!iexec->execute) 1684 if (!iexec->execute)
1683 return true; 1685 return 3;
1684 1686
1685 if (retries > 100) 1687 if (retries > 100)
1686 retries = 100; 1688 retries = 100;
@@ -1711,10 +1713,10 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
1711 iexec->execute = false; 1713 iexec->execute = false;
1712 } 1714 }
1713 1715
1714 return true; 1716 return 3;
1715} 1717}
1716 1718
1717static bool 1719static int
1718init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1720init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1719 struct init_exec *iexec) 1721 struct init_exec *iexec)
1720{ 1722{
@@ -1734,10 +1736,11 @@ init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1734 1736
1735 uint32_t basereg = ROM32(bios->data[offset + 1]); 1737 uint32_t basereg = ROM32(bios->data[offset + 1]);
1736 uint32_t count = bios->data[offset + 5]; 1738 uint32_t count = bios->data[offset + 5];
1739 int len = 6 + count * 4;
1737 int i; 1740 int i;
1738 1741
1739 if (!iexec->execute) 1742 if (!iexec->execute)
1740 return true; 1743 return len;
1741 1744
1742 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1745 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1743 offset, basereg, count); 1746 offset, basereg, count);
@@ -1749,10 +1752,10 @@ init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1749 bios_wr32(bios, reg, data); 1752 bios_wr32(bios, reg, data);
1750 } 1753 }
1751 1754
1752 return true; 1755 return len;
1753} 1756}
1754 1757
1755static bool 1758static int
1756init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1759init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1757{ 1760{
1758 /* 1761 /*
@@ -1768,7 +1771,7 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1768 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 1771 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1769 1772
1770 if (!iexec->execute) 1773 if (!iexec->execute)
1771 return true; 1774 return 3;
1772 1775
1773 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 1776 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1774 offset, sub_offset); 1777 offset, sub_offset);
@@ -1777,10 +1780,10 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1777 1780
1778 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 1781 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1779 1782
1780 return true; 1783 return 3;
1781} 1784}
1782 1785
1783static bool 1786static int
1784init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1787init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1785{ 1788{
1786 /* 1789 /*
@@ -1808,7 +1811,7 @@ init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1808 uint32_t srcvalue, dstvalue; 1811 uint32_t srcvalue, dstvalue;
1809 1812
1810 if (!iexec->execute) 1813 if (!iexec->execute)
1811 return true; 1814 return 22;
1812 1815
1813 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 1816 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1814 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 1817 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
@@ -1827,10 +1830,10 @@ init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1827 1830
1828 bios_wr32(bios, dstreg, dstvalue | srcvalue); 1831 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1829 1832
1830 return true; 1833 return 22;
1831} 1834}
1832 1835
1833static bool 1836static int
1834init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1837init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1835{ 1838{
1836 /* 1839 /*
@@ -1848,14 +1851,14 @@ init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1848 uint8_t data = bios->data[offset + 4]; 1851 uint8_t data = bios->data[offset + 4];
1849 1852
1850 if (!iexec->execute) 1853 if (!iexec->execute)
1851 return true; 1854 return 5;
1852 1855
1853 bios_idxprt_wr(bios, crtcport, crtcindex, data); 1856 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1854 1857
1855 return true; 1858 return 5;
1856} 1859}
1857 1860
1858static bool 1861static int
1859init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1862init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1860{ 1863{
1861 /* 1864 /*
@@ -1904,7 +1907,7 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1904 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 1907 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1905 1908
1906 if (dev_priv->card_type >= NV_50) 1909 if (dev_priv->card_type >= NV_50)
1907 return true; 1910 return 1;
1908 1911
1909 /* 1912 /*
1910 * On every card I've seen, this step gets done for us earlier in 1913 * On every card I've seen, this step gets done for us earlier in
@@ -1922,10 +1925,10 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1922 /* write back the saved configuration value */ 1925 /* write back the saved configuration value */
1923 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 1926 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
1924 1927
1925 return true; 1928 return 1;
1926} 1929}
1927 1930
1928static bool 1931static int
1929init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1932init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1930{ 1933{
1931 /* 1934 /*
@@ -1959,10 +1962,10 @@ init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1959 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 1962 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1960 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 1963 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
1961 1964
1962 return true; 1965 return 13;
1963} 1966}
1964 1967
1965static bool 1968static int
1966init_configure_mem(struct nvbios *bios, uint16_t offset, 1969init_configure_mem(struct nvbios *bios, uint16_t offset,
1967 struct init_exec *iexec) 1970 struct init_exec *iexec)
1968{ 1971{
@@ -1983,7 +1986,7 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
1983 uint32_t reg, data; 1986 uint32_t reg, data;
1984 1987
1985 if (bios->major_version > 2) 1988 if (bios->major_version > 2)
1986 return false; 1989 return 0;
1987 1990
1988 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 1991 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
1989 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 1992 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
@@ -2015,10 +2018,10 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
2015 bios_wr32(bios, reg, data); 2018 bios_wr32(bios, reg, data);
2016 } 2019 }
2017 2020
2018 return true; 2021 return 1;
2019} 2022}
2020 2023
2021static bool 2024static int
2022init_configure_clk(struct nvbios *bios, uint16_t offset, 2025init_configure_clk(struct nvbios *bios, uint16_t offset,
2023 struct init_exec *iexec) 2026 struct init_exec *iexec)
2024{ 2027{
@@ -2038,7 +2041,7 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
2038 int clock; 2041 int clock;
2039 2042
2040 if (bios->major_version > 2) 2043 if (bios->major_version > 2)
2041 return false; 2044 return 0;
2042 2045
2043 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2046 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2044 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2047 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
@@ -2048,10 +2051,10 @@ init_configure_clk(struct nvbios *bios, uint16_t offset,
2048 clock *= 2; 2051 clock *= 2;
2049 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2052 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2050 2053
2051 return true; 2054 return 1;
2052} 2055}
2053 2056
2054static bool 2057static int
2055init_configure_preinit(struct nvbios *bios, uint16_t offset, 2058init_configure_preinit(struct nvbios *bios, uint16_t offset,
2056 struct init_exec *iexec) 2059 struct init_exec *iexec)
2057{ 2060{
@@ -2071,15 +2074,15 @@ init_configure_preinit(struct nvbios *bios, uint16_t offset,
2071 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2074 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2072 2075
2073 if (bios->major_version > 2) 2076 if (bios->major_version > 2)
2074 return false; 2077 return 0;
2075 2078
2076 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2079 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2077 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2080 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2078 2081
2079 return true; 2082 return 1;
2080} 2083}
2081 2084
2082static bool 2085static int
2083init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2086init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2084{ 2087{
2085 /* 2088 /*
@@ -2099,7 +2102,7 @@ init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2099 uint8_t data = bios->data[offset + 4]; 2102 uint8_t data = bios->data[offset + 4];
2100 2103
2101 if (!iexec->execute) 2104 if (!iexec->execute)
2102 return true; 2105 return 5;
2103 2106
2104 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2107 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2105 offset, crtcport, mask, data); 2108 offset, crtcport, mask, data);
@@ -2158,15 +2161,15 @@ init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2158 for (i = 0; i < 2; i++) 2161 for (i = 0; i < 2; i++)
2159 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2162 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2160 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2163 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2161 return true; 2164 return 5;
2162 } 2165 }
2163 2166
2164 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2167 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2165 data); 2168 data);
2166 return true; 2169 return 5;
2167} 2170}
2168 2171
2169static bool 2172static int
2170init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2173init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2171{ 2174{
2172 /* 2175 /*
@@ -2181,7 +2184,7 @@ init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2181 uint8_t sub = bios->data[offset + 1]; 2184 uint8_t sub = bios->data[offset + 1];
2182 2185
2183 if (!iexec->execute) 2186 if (!iexec->execute)
2184 return true; 2187 return 2;
2185 2188
2186 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2189 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2187 2190
@@ -2191,10 +2194,10 @@ init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2191 2194
2192 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2195 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2193 2196
2194 return true; 2197 return 2;
2195} 2198}
2196 2199
2197static bool 2200static int
2198init_ram_condition(struct nvbios *bios, uint16_t offset, 2201init_ram_condition(struct nvbios *bios, uint16_t offset,
2199 struct init_exec *iexec) 2202 struct init_exec *iexec)
2200{ 2203{
@@ -2215,7 +2218,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
2215 uint8_t data; 2218 uint8_t data;
2216 2219
2217 if (!iexec->execute) 2220 if (!iexec->execute)
2218 return true; 2221 return 3;
2219 2222
2220 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2223 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2221 2224
@@ -2229,10 +2232,10 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
2229 iexec->execute = false; 2232 iexec->execute = false;
2230 } 2233 }
2231 2234
2232 return true; 2235 return 3;
2233} 2236}
2234 2237
2235static bool 2238static int
2236init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2239init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2237{ 2240{
2238 /* 2241 /*
@@ -2251,17 +2254,17 @@ init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2251 uint32_t data = ROM32(bios->data[offset + 9]); 2254 uint32_t data = ROM32(bios->data[offset + 9]);
2252 2255
2253 if (!iexec->execute) 2256 if (!iexec->execute)
2254 return true; 2257 return 13;
2255 2258
2256 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2259 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2257 offset, reg, mask, data); 2260 offset, reg, mask, data);
2258 2261
2259 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2262 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2260 2263
2261 return true; 2264 return 13;
2262} 2265}
2263 2266
2264static bool 2267static int
2265init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2268init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2266{ 2269{
2267 /* 2270 /*
@@ -2285,7 +2288,7 @@ init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2285 int i; 2288 int i;
2286 2289
2287 if (!iexec->execute) 2290 if (!iexec->execute)
2288 return true; 2291 return 2;
2289 2292
2290 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2293 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2291 "Count: 0x%02X\n", 2294 "Count: 0x%02X\n",
@@ -2300,10 +2303,10 @@ init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2300 bios_wr32(bios, reg, data); 2303 bios_wr32(bios, reg, data);
2301 } 2304 }
2302 2305
2303 return true; 2306 return 2;
2304} 2307}
2305 2308
2306static bool 2309static int
2307init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2310init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2308{ 2311{
2309 /* 2312 /*
@@ -2315,10 +2318,10 @@ init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2315 */ 2318 */
2316 2319
2317 /* mild retval abuse to stop parsing this table */ 2320 /* mild retval abuse to stop parsing this table */
2318 return false; 2321 return 0;
2319} 2322}
2320 2323
2321static bool 2324static int
2322init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2325init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2323{ 2326{
2324 /* 2327 /*
@@ -2330,15 +2333,15 @@ init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2330 */ 2333 */
2331 2334
2332 if (iexec->execute) 2335 if (iexec->execute)
2333 return true; 2336 return 1;
2334 2337
2335 iexec->execute = true; 2338 iexec->execute = true;
2336 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2339 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2337 2340
2338 return true; 2341 return 1;
2339} 2342}
2340 2343
2341static bool 2344static int
2342init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2345init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2343{ 2346{
2344 /* 2347 /*
@@ -2353,7 +2356,7 @@ init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2353 unsigned time = ROM16(bios->data[offset + 1]); 2356 unsigned time = ROM16(bios->data[offset + 1]);
2354 2357
2355 if (!iexec->execute) 2358 if (!iexec->execute)
2356 return true; 2359 return 3;
2357 2360
2358 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2361 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2359 offset, time); 2362 offset, time);
@@ -2363,10 +2366,10 @@ init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2363 else 2366 else
2364 msleep((time + 900) / 1000); 2367 msleep((time + 900) / 1000);
2365 2368
2366 return true; 2369 return 3;
2367} 2370}
2368 2371
2369static bool 2372static int
2370init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2373init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2371{ 2374{
2372 /* 2375 /*
@@ -2383,7 +2386,7 @@ init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2383 uint8_t cond = bios->data[offset + 1]; 2386 uint8_t cond = bios->data[offset + 1];
2384 2387
2385 if (!iexec->execute) 2388 if (!iexec->execute)
2386 return true; 2389 return 2;
2387 2390
2388 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2391 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2389 2392
@@ -2394,10 +2397,10 @@ init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2394 iexec->execute = false; 2397 iexec->execute = false;
2395 } 2398 }
2396 2399
2397 return true; 2400 return 2;
2398} 2401}
2399 2402
2400static bool 2403static int
2401init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2404init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2402{ 2405{
2403 /* 2406 /*
@@ -2414,7 +2417,7 @@ init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2414 uint8_t cond = bios->data[offset + 1]; 2417 uint8_t cond = bios->data[offset + 1];
2415 2418
2416 if (!iexec->execute) 2419 if (!iexec->execute)
2417 return true; 2420 return 2;
2418 2421
2419 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 2422 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2420 2423
@@ -2425,10 +2428,10 @@ init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2425 iexec->execute = false; 2428 iexec->execute = false;
2426 } 2429 }
2427 2430
2428 return true; 2431 return 2;
2429} 2432}
2430 2433
2431static bool 2434static int
2432init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2435init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2433{ 2436{
2434 /* 2437 /*
@@ -2451,7 +2454,7 @@ init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2451 uint8_t value; 2454 uint8_t value;
2452 2455
2453 if (!iexec->execute) 2456 if (!iexec->execute)
2454 return true; 2457 return 6;
2455 2458
2456 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 2459 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2457 "Data: 0x%02X\n", 2460 "Data: 0x%02X\n",
@@ -2460,10 +2463,10 @@ init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2460 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 2463 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2461 bios_idxprt_wr(bios, crtcport, crtcindex, value); 2464 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2462 2465
2463 return true; 2466 return 6;
2464} 2467}
2465 2468
2466static bool 2469static int
2467init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2470init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2468{ 2471{
2469 /* 2472 /*
@@ -2481,16 +2484,16 @@ init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2481 uint16_t freq = ROM16(bios->data[offset + 5]); 2484 uint16_t freq = ROM16(bios->data[offset + 5]);
2482 2485
2483 if (!iexec->execute) 2486 if (!iexec->execute)
2484 return true; 2487 return 7;
2485 2488
2486 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 2489 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2487 2490
2488 setPLL(bios, reg, freq * 10); 2491 setPLL(bios, reg, freq * 10);
2489 2492
2490 return true; 2493 return 7;
2491} 2494}
2492 2495
2493static bool 2496static int
2494init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2497init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2495{ 2498{
2496 /* 2499 /*
@@ -2507,17 +2510,17 @@ init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2507 uint32_t value = ROM32(bios->data[offset + 5]); 2510 uint32_t value = ROM32(bios->data[offset + 5]);
2508 2511
2509 if (!iexec->execute) 2512 if (!iexec->execute)
2510 return true; 2513 return 9;
2511 2514
2512 if (reg == 0x000200) 2515 if (reg == 0x000200)
2513 value |= 1; 2516 value |= 1;
2514 2517
2515 bios_wr32(bios, reg, value); 2518 bios_wr32(bios, reg, value);
2516 2519
2517 return true; 2520 return 9;
2518} 2521}
2519 2522
2520static bool 2523static int
2521init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 2524init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2522 struct init_exec *iexec) 2525 struct init_exec *iexec)
2523{ 2526{
@@ -2543,14 +2546,15 @@ init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2543 uint8_t type = bios->data[offset + 1]; 2546 uint8_t type = bios->data[offset + 1];
2544 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 2547 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2545 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 2548 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
2549 int len = 2 + bios->ram_restrict_group_count * 4;
2546 int i; 2550 int i;
2547 2551
2548 if (!iexec->execute) 2552 if (!iexec->execute)
2549 return true; 2553 return len;
2550 2554
2551 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 2555 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2552 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 2556 NV_ERROR(dev, "PLL limits table not version 3.x\n");
2553 return true; /* deliberate, allow default clocks to remain */ 2557 return len; /* deliberate, allow default clocks to remain */
2554 } 2558 }
2555 2559
2556 entry = pll_limits + pll_limits[1]; 2560 entry = pll_limits + pll_limits[1];
@@ -2563,15 +2567,15 @@ init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2563 offset, type, reg, freq); 2567 offset, type, reg, freq);
2564 2568
2565 setPLL(bios, reg, freq); 2569 setPLL(bios, reg, freq);
2566 return true; 2570 return len;
2567 } 2571 }
2568 } 2572 }
2569 2573
2570 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 2574 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
2571 return true; 2575 return len;
2572} 2576}
2573 2577
2574static bool 2578static int
2575init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2579init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2576{ 2580{
2577 /* 2581 /*
@@ -2581,10 +2585,10 @@ init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2581 * 2585 *
2582 */ 2586 */
2583 2587
2584 return true; 2588 return 1;
2585} 2589}
2586 2590
2587static bool 2591static int
2588init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2592init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2589{ 2593{
2590 /* 2594 /*
@@ -2594,10 +2598,10 @@ init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2594 * 2598 *
2595 */ 2599 */
2596 2600
2597 return true; 2601 return 1;
2598} 2602}
2599 2603
2600static bool 2604static int
2601init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2605init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2602{ 2606{
2603 /* 2607 /*
@@ -2615,14 +2619,17 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2615 const uint8_t *gpio_entry; 2619 const uint8_t *gpio_entry;
2616 int i; 2620 int i;
2617 2621
2622 if (!iexec->execute)
2623 return 1;
2624
2618 if (bios->bdcb.version != 0x40) { 2625 if (bios->bdcb.version != 0x40) {
2619 NV_ERROR(bios->dev, "DCB table not version 4.0\n"); 2626 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
2620 return false; 2627 return 0;
2621 } 2628 }
2622 2629
2623 if (!bios->bdcb.gpio_table_ptr) { 2630 if (!bios->bdcb.gpio_table_ptr) {
2624 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); 2631 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
2625 return false; 2632 return 0;
2626 } 2633 }
2627 2634
2628 gpio_entry = gpio_table + gpio_table[1]; 2635 gpio_entry = gpio_table + gpio_table[1];
@@ -2660,13 +2667,10 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2660 bios_wr32(bios, r, v); 2667 bios_wr32(bios, r, v);
2661 } 2668 }
2662 2669
2663 return true; 2670 return 1;
2664} 2671}
2665 2672
2666/* hack to avoid moving the itbl_entry array before this function */ 2673static int
2667int init_ram_restrict_zm_reg_group_blocklen;
2668
2669static bool
2670init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 2674init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2671 struct init_exec *iexec) 2675 struct init_exec *iexec)
2672{ 2676{
@@ -2692,21 +2696,21 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2692 uint8_t regincrement = bios->data[offset + 5]; 2696 uint8_t regincrement = bios->data[offset + 5];
2693 uint8_t count = bios->data[offset + 6]; 2697 uint8_t count = bios->data[offset + 6];
2694 uint32_t strap_ramcfg, data; 2698 uint32_t strap_ramcfg, data;
2695 uint16_t blocklen; 2699 /* previously set by 'M' BIT table */
2700 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2701 int len = 7 + count * blocklen;
2696 uint8_t index; 2702 uint8_t index;
2697 int i; 2703 int i;
2698 2704
2699 /* previously set by 'M' BIT table */
2700 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2701 2705
2702 if (!iexec->execute) 2706 if (!iexec->execute)
2703 return true; 2707 return len;
2704 2708
2705 if (!blocklen) { 2709 if (!blocklen) {
2706 NV_ERROR(bios->dev, 2710 NV_ERROR(bios->dev,
2707 "0x%04X: Zero block length - has the M table " 2711 "0x%04X: Zero block length - has the M table "
2708 "been parsed?\n", offset); 2712 "been parsed?\n", offset);
2709 return false; 2713 return 0;
2710 } 2714 }
2711 2715
2712 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 2716 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
@@ -2724,10 +2728,10 @@ init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2724 reg += regincrement; 2728 reg += regincrement;
2725 } 2729 }
2726 2730
2727 return true; 2731 return len;
2728} 2732}
2729 2733
2730static bool 2734static int
2731init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2735init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2732{ 2736{
2733 /* 2737 /*
@@ -2744,14 +2748,14 @@ init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2744 uint32_t dstreg = ROM32(bios->data[offset + 5]); 2748 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2745 2749
2746 if (!iexec->execute) 2750 if (!iexec->execute)
2747 return true; 2751 return 9;
2748 2752
2749 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 2753 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2750 2754
2751 return true; 2755 return 9;
2752} 2756}
2753 2757
2754static bool 2758static int
2755init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 2759init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2756 struct init_exec *iexec) 2760 struct init_exec *iexec)
2757{ 2761{
@@ -2769,20 +2773,21 @@ init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2769 2773
2770 uint32_t reg = ROM32(bios->data[offset + 1]); 2774 uint32_t reg = ROM32(bios->data[offset + 1]);
2771 uint8_t count = bios->data[offset + 5]; 2775 uint8_t count = bios->data[offset + 5];
2776 int len = 6 + count * 4;
2772 int i; 2777 int i;
2773 2778
2774 if (!iexec->execute) 2779 if (!iexec->execute)
2775 return true; 2780 return len;
2776 2781
2777 for (i = 0; i < count; i++) { 2782 for (i = 0; i < count; i++) {
2778 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 2783 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2779 bios_wr32(bios, reg, data); 2784 bios_wr32(bios, reg, data);
2780 } 2785 }
2781 2786
2782 return true; 2787 return len;
2783} 2788}
2784 2789
2785static bool 2790static int
2786init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2791init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2787{ 2792{
2788 /* 2793 /*
@@ -2793,10 +2798,10 @@ init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2793 * Seemingly does nothing 2798 * Seemingly does nothing
2794 */ 2799 */
2795 2800
2796 return true; 2801 return 1;
2797} 2802}
2798 2803
2799static bool 2804static int
2800init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2805init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2801{ 2806{
2802 /* 2807 /*
@@ -2829,13 +2834,13 @@ init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2829 val <<= bios->data[offset + 16]; 2834 val <<= bios->data[offset + 16];
2830 2835
2831 if (!iexec->execute) 2836 if (!iexec->execute)
2832 return true; 2837 return 17;
2833 2838
2834 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 2839 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
2835 return true; 2840 return 17;
2836} 2841}
2837 2842
2838static bool 2843static int
2839init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2844init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2840{ 2845{
2841 /* 2846 /*
@@ -2859,13 +2864,13 @@ init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2859 val = (val & mask) | ((val + add) & ~mask); 2864 val = (val & mask) | ((val + add) & ~mask);
2860 2865
2861 if (!iexec->execute) 2866 if (!iexec->execute)
2862 return true; 2867 return 13;
2863 2868
2864 bios_wr32(bios, reg, val); 2869 bios_wr32(bios, reg, val);
2865 return true; 2870 return 13;
2866} 2871}
2867 2872
2868static bool 2873static int
2869init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2874init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2870{ 2875{
2871 /* 2876 /*
@@ -2883,32 +2888,33 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2883 struct drm_device *dev = bios->dev; 2888 struct drm_device *dev = bios->dev;
2884 struct nouveau_i2c_chan *auxch; 2889 struct nouveau_i2c_chan *auxch;
2885 uint32_t addr = ROM32(bios->data[offset + 1]); 2890 uint32_t addr = ROM32(bios->data[offset + 1]);
2886 uint8_t len = bios->data[offset + 5]; 2891 uint8_t count = bios->data[offset + 5];
2892 int len = 6 + count * 2;
2887 int ret, i; 2893 int ret, i;
2888 2894
2889 if (!bios->display.output) { 2895 if (!bios->display.output) {
2890 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 2896 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
2891 return false; 2897 return 0;
2892 } 2898 }
2893 2899
2894 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2900 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2895 if (!auxch) { 2901 if (!auxch) {
2896 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 2902 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2897 bios->display.output->i2c_index); 2903 bios->display.output->i2c_index);
2898 return false; 2904 return 0;
2899 } 2905 }
2900 2906
2901 if (!iexec->execute) 2907 if (!iexec->execute)
2902 return true; 2908 return len;
2903 2909
2904 offset += 6; 2910 offset += 6;
2905 for (i = 0; i < len; i++, offset += 2) { 2911 for (i = 0; i < count; i++, offset += 2) {
2906 uint8_t data; 2912 uint8_t data;
2907 2913
2908 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 2914 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2909 if (ret) { 2915 if (ret) {
2910 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 2916 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
2911 return false; 2917 return 0;
2912 } 2918 }
2913 2919
2914 data &= bios->data[offset + 0]; 2920 data &= bios->data[offset + 0];
@@ -2917,14 +2923,14 @@ init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2917 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 2923 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2918 if (ret) { 2924 if (ret) {
2919 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 2925 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
2920 return false; 2926 return 0;
2921 } 2927 }
2922 } 2928 }
2923 2929
2924 return true; 2930 return len;
2925} 2931}
2926 2932
2927static bool 2933static int
2928init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2934init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2929{ 2935{
2930 /* 2936 /*
@@ -2941,106 +2947,99 @@ init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2941 struct drm_device *dev = bios->dev; 2947 struct drm_device *dev = bios->dev;
2942 struct nouveau_i2c_chan *auxch; 2948 struct nouveau_i2c_chan *auxch;
2943 uint32_t addr = ROM32(bios->data[offset + 1]); 2949 uint32_t addr = ROM32(bios->data[offset + 1]);
2944 uint8_t len = bios->data[offset + 5]; 2950 uint8_t count = bios->data[offset + 5];
2951 int len = 6 + count;
2945 int ret, i; 2952 int ret, i;
2946 2953
2947 if (!bios->display.output) { 2954 if (!bios->display.output) {
2948 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 2955 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
2949 return false; 2956 return 0;
2950 } 2957 }
2951 2958
2952 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 2959 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2953 if (!auxch) { 2960 if (!auxch) {
2954 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 2961 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2955 bios->display.output->i2c_index); 2962 bios->display.output->i2c_index);
2956 return false; 2963 return 0;
2957 } 2964 }
2958 2965
2959 if (!iexec->execute) 2966 if (!iexec->execute)
2960 return true; 2967 return len;
2961 2968
2962 offset += 6; 2969 offset += 6;
2963 for (i = 0; i < len; i++, offset++) { 2970 for (i = 0; i < count; i++, offset++) {
2964 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 2971 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
2965 if (ret) { 2972 if (ret) {
2966 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 2973 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
2967 return false; 2974 return 0;
2968 } 2975 }
2969 } 2976 }
2970 2977
2971 return true; 2978 return len;
2972} 2979}
2973 2980
2974static struct init_tbl_entry itbl_entry[] = { 2981static struct init_tbl_entry itbl_entry[] = {
2975 /* command name , id , length , offset , mult , command handler */ 2982 /* command name , id , length , offset , mult , command handler */
2976 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 2983 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
2977 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog }, 2984 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
2978 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat }, 2985 { "INIT_REPEAT" , 0x33, init_repeat },
2979 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll }, 2986 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
2980 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat }, 2987 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
2981 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy }, 2988 { "INIT_COPY" , 0x37, init_copy },
2982 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not }, 2989 { "INIT_NOT" , 0x38, init_not },
2983 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition }, 2990 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
2984 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched }, 2991 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
2985 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 }, 2992 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
2986 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 }, 2993 { "INIT_PLL2" , 0x4B, init_pll2 },
2987 { "INIT_I2C_BYTE" , 0x4C, 4 , 3 , 3 , init_i2c_byte }, 2994 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
2988 { "INIT_ZM_I2C_BYTE" , 0x4D, 4 , 3 , 2 , init_zm_i2c_byte }, 2995 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
2989 { "INIT_ZM_I2C" , 0x4E, 4 , 3 , 1 , init_zm_i2c }, 2996 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
2990 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds }, 2997 { "INIT_TMDS" , 0x4F, init_tmds },
2991 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group }, 2998 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
2992 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch }, 2999 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
2993 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr }, 3000 { "INIT_CR" , 0x52, init_cr },
2994 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr }, 3001 { "INIT_ZM_CR" , 0x53, init_zm_cr },
2995 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group }, 3002 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
2996 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time }, 3003 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
2997 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence }, 3004 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
2998 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3005 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
2999 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct }, 3006 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3000 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg }, 3007 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3001 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io }, 3008 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3002 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem }, 3009 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3003 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset }, 3010 { "INIT_RESET" , 0x65, init_reset },
3004 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem }, 3011 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3005 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk }, 3012 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3006 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit }, 3013 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3007 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io }, 3014 { "INIT_IO" , 0x69, init_io },
3008 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub }, 3015 { "INIT_SUB" , 0x6B, init_sub },
3009 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition }, 3016 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3010 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg }, 3017 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3011 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro }, 3018 { "INIT_MACRO" , 0x6F, init_macro },
3012 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done }, 3019 { "INIT_DONE" , 0x71, init_done },
3013 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume }, 3020 { "INIT_RESUME" , 0x72, init_resume },
3014 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3021 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3015 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time }, 3022 { "INIT_TIME" , 0x74, init_time },
3016 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition }, 3023 { "INIT_CONDITION" , 0x75, init_condition },
3017 { "INIT_IO_CONDITION" , 0x76, 2 , 0 , 0 , init_io_condition }, 3024 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3018 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io }, 3025 { "INIT_INDEX_IO" , 0x78, init_index_io },
3019 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll }, 3026 { "INIT_PLL" , 0x79, init_pll },
3020 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg }, 3027 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3021 /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */ 3028 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3022 { "INIT_RAM_RESTRICT_PLL" , 0x87, 2 , 0 , 0 , init_ram_restrict_pll }, 3029 { "INIT_8C" , 0x8C, init_8c },
3023 { "INIT_8C" , 0x8C, 1 , 0 , 0 , init_8c }, 3030 { "INIT_8D" , 0x8D, init_8d },
3024 { "INIT_8D" , 0x8D, 1 , 0 , 0 , init_8d }, 3031 { "INIT_GPIO" , 0x8E, init_gpio },
3025 { "INIT_GPIO" , 0x8E, 1 , 0 , 0 , init_gpio }, 3032 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3026 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */ 3033 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3027 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group }, 3034 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3028 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg }, 3035 { "INIT_RESERVED" , 0x92, init_reserved },
3029 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched }, 3036 { "INIT_96" , 0x96, init_96 },
3030 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved }, 3037 { "INIT_97" , 0x97, init_97 },
3031 { "INIT_96" , 0x96, 17 , 0 , 0 , init_96 }, 3038 { "INIT_AUXCH" , 0x98, init_auxch },
3032 { "INIT_97" , 0x97, 13 , 0 , 0 , init_97 }, 3039 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3033 { "INIT_AUXCH" , 0x98, 6 , 5 , 2 , init_auxch }, 3040 { NULL , 0 , NULL }
3034 { "INIT_ZM_AUXCH" , 0x99, 6 , 5 , 1 , init_zm_auxch },
3035 { NULL , 0 , 0 , 0 , 0 , NULL }
3036}; 3041};
3037 3042
3038static unsigned int get_init_table_entry_length(struct nvbios *bios, unsigned int offset, int i)
3039{
3040 /* Calculates the length of a given init table entry. */
3041 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
3042}
3043
3044#define MAX_TABLE_OPS 1000 3043#define MAX_TABLE_OPS 1000
3045 3044
3046static int 3045static int
@@ -3056,7 +3055,7 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
3056 * is changed back to EXECUTE. 3055 * is changed back to EXECUTE.
3057 */ 3056 */
3058 3057
3059 int count = 0, i; 3058 int count = 0, i, res;
3060 uint8_t id; 3059 uint8_t id;
3061 3060
3062 /* 3061 /*
@@ -3076,22 +3075,21 @@ parse_init_table(struct nvbios *bios, unsigned int offset,
3076 offset, itbl_entry[i].id, itbl_entry[i].name); 3075 offset, itbl_entry[i].id, itbl_entry[i].name);
3077 3076
3078 /* execute eventual command handler */ 3077 /* execute eventual command handler */
3079 if (itbl_entry[i].handler) 3078 res = (*itbl_entry[i].handler)(bios, offset, iexec);
3080 if (!(*itbl_entry[i].handler)(bios, offset, iexec)) 3079 if (!res)
3081 break; 3080 break;
3081 /*
3082 * Add the offset of the current command including all data
3083 * of that command. The offset will then be pointing on the
3084 * next op code.
3085 */
3086 offset += res;
3082 } else { 3087 } else {
3083 NV_ERROR(bios->dev, 3088 NV_ERROR(bios->dev,
3084 "0x%04X: Init table command not found: " 3089 "0x%04X: Init table command not found: "
3085 "0x%02X\n", offset, id); 3090 "0x%02X\n", offset, id);
3086 return -ENOENT; 3091 return -ENOENT;
3087 } 3092 }
3088
3089 /*
3090 * Add the offset of the current command including all data
3091 * of that command. The offset will then be pointing on the
3092 * next op code.
3093 */
3094 offset += get_init_table_entry_length(bios, offset, i);
3095 } 3093 }
3096 3094
3097 if (offset >= bios->length) 3095 if (offset >= bios->length)
@@ -3854,7 +3852,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3854 * script tables is a pointer to the script to execute. 3852 * script tables is a pointer to the script to execute.
3855 */ 3853 */
3856 3854
3857 NV_DEBUG(dev, "Searching for output entry for %d %d %d\n", 3855 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
3858 dcbent->type, dcbent->location, dcbent->or); 3856 dcbent->type, dcbent->location, dcbent->or);
3859 otable = bios_output_config_match(dev, dcbent, table[1] + 3857 otable = bios_output_config_match(dev, dcbent, table[1] +
3860 bios->display.script_table_ptr, 3858 bios->display.script_table_ptr,
@@ -3884,7 +3882,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3884 if (pxclk == 0) { 3882 if (pxclk == 0) {
3885 script = ROM16(otable[6]); 3883 script = ROM16(otable[6]);
3886 if (!script) { 3884 if (!script) {
3887 NV_DEBUG(dev, "output script 0 not found\n"); 3885 NV_DEBUG_KMS(dev, "output script 0 not found\n");
3888 return 1; 3886 return 1;
3889 } 3887 }
3890 3888
@@ -3894,7 +3892,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3894 if (pxclk == -1) { 3892 if (pxclk == -1) {
3895 script = ROM16(otable[8]); 3893 script = ROM16(otable[8]);
3896 if (!script) { 3894 if (!script) {
3897 NV_DEBUG(dev, "output script 1 not found\n"); 3895 NV_DEBUG_KMS(dev, "output script 1 not found\n");
3898 return 1; 3896 return 1;
3899 } 3897 }
3900 3898
@@ -3907,7 +3905,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3907 else 3905 else
3908 script = 0; 3906 script = 0;
3909 if (!script) { 3907 if (!script) {
3910 NV_DEBUG(dev, "output script 2 not found\n"); 3908 NV_DEBUG_KMS(dev, "output script 2 not found\n");
3911 return 1; 3909 return 1;
3912 } 3910 }
3913 3911
@@ -3931,7 +3929,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3931 if (script) 3929 if (script)
3932 script = clkcmptable(bios, script, -pxclk); 3930 script = clkcmptable(bios, script, -pxclk);
3933 if (!script) { 3931 if (!script) {
3934 NV_DEBUG(dev, "clock script 1 not found\n"); 3932 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
3935 return 1; 3933 return 1;
3936 } 3934 }
3937 3935
@@ -4606,10 +4604,6 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4606 * stuff that we don't use - their use currently unknown 4604 * stuff that we don't use - their use currently unknown
4607 */ 4605 */
4608 4606
4609 uint16_t rr_strap_xlat;
4610 uint8_t rr_group_count;
4611 int i;
4612
4613 /* 4607 /*
4614 * Older bios versions don't have a sufficiently long table for 4608 * Older bios versions don't have a sufficiently long table for
4615 * what we want 4609 * what we want
@@ -4618,24 +4612,13 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4618 return 0; 4612 return 0;
4619 4613
4620 if (bitentry->id[1] < 2) { 4614 if (bitentry->id[1] < 2) {
4621 rr_group_count = bios->data[bitentry->offset + 2]; 4615 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4622 rr_strap_xlat = ROM16(bios->data[bitentry->offset + 3]); 4616 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
4623 } else { 4617 } else {
4624 rr_group_count = bios->data[bitentry->offset + 0]; 4618 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4625 rr_strap_xlat = ROM16(bios->data[bitentry->offset + 1]); 4619 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
4626 } 4620 }
4627 4621
4628 /* adjust length of INIT_87 */
4629 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x87); i++);
4630 itbl_entry[i].length += rr_group_count * 4;
4631
4632 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
4633 for (; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++);
4634 itbl_entry[i].length_multiplier = rr_group_count * 4;
4635
4636 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
4637 bios->ram_restrict_tbl_ptr = rr_strap_xlat;
4638
4639 return 0; 4622 return 0;
4640} 4623}
4641 4624
@@ -5234,7 +5217,7 @@ parse_dcb_connector_table(struct nvbios *bios)
5234 int i; 5217 int i;
5235 5218
5236 if (!bios->bdcb.connector_table_ptr) { 5219 if (!bios->bdcb.connector_table_ptr) {
5237 NV_DEBUG(dev, "No DCB connector table present\n"); 5220 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
5238 return; 5221 return;
5239 } 5222 }
5240 5223
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 1d5f10bd78ed..058e98c76d89 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -227,6 +227,7 @@ struct nvbios {
227 227
228 uint16_t pll_limit_tbl_ptr; 228 uint16_t pll_limit_tbl_ptr;
229 uint16_t ram_restrict_tbl_ptr; 229 uint16_t ram_restrict_tbl_ptr;
230 uint8_t ram_restrict_group_count;
230 231
231 uint16_t some_script_ptr; /* BIT I + 14 */ 232 uint16_t some_script_ptr; /* BIT I + 14 */
232 uint16_t init96_tbl_ptr; /* BIT I + 16 */ 233 uint16_t init96_tbl_ptr; /* BIT I + 16 */
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index aa2dfbc3e351..0cad6d834eb2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -154,6 +154,11 @@ nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype)
154 nvbo->placement.busy_placement = nvbo->placements; 154 nvbo->placement.busy_placement = nvbo->placements;
155 nvbo->placement.num_placement = n; 155 nvbo->placement.num_placement = n;
156 nvbo->placement.num_busy_placement = n; 156 nvbo->placement.num_busy_placement = n;
157
158 if (nvbo->pin_refcnt) {
159 while (n--)
160 nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
161 }
157} 162}
158 163
159int 164int
@@ -400,10 +405,16 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
400 struct nouveau_bo *nvbo = nouveau_bo(bo); 405 struct nouveau_bo *nvbo = nouveau_bo(bo);
401 406
402 switch (bo->mem.mem_type) { 407 switch (bo->mem.mem_type) {
408 case TTM_PL_VRAM:
409 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT |
410 TTM_PL_FLAG_SYSTEM);
411 break;
403 default: 412 default:
404 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); 413 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM);
405 break; 414 break;
406 } 415 }
416
417 *pl = nvbo->placement;
407} 418}
408 419
409 420
@@ -455,11 +466,8 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, int no_wait,
455 int ret; 466 int ret;
456 467
457 chan = nvbo->channel; 468 chan = nvbo->channel;
458 if (!chan || nvbo->tile_flags || nvbo->no_vm) { 469 if (!chan || nvbo->tile_flags || nvbo->no_vm)
459 chan = dev_priv->channel; 470 chan = dev_priv->channel;
460 if (!chan)
461 return -EINVAL;
462 }
463 471
464 src_offset = old_mem->mm_node->start << PAGE_SHIFT; 472 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
465 dst_offset = new_mem->mm_node->start << PAGE_SHIFT; 473 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
@@ -625,7 +633,8 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
625 return ret; 633 return ret;
626 } 634 }
627 635
628 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE) 636 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
637 !dev_priv->channel)
629 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 638 return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
630 639
631 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 640 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 032cf098fa1c..5a10deb8bdbd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -86,7 +86,7 @@ nouveau_connector_destroy(struct drm_connector *drm_connector)
86 struct nouveau_connector *connector = nouveau_connector(drm_connector); 86 struct nouveau_connector *connector = nouveau_connector(drm_connector);
87 struct drm_device *dev = connector->base.dev; 87 struct drm_device *dev = connector->base.dev;
88 88
89 NV_DEBUG(dev, "\n"); 89 NV_DEBUG_KMS(dev, "\n");
90 90
91 if (!connector) 91 if (!connector)
92 return; 92 return;
@@ -420,7 +420,7 @@ nouveau_connector_native_mode(struct nouveau_connector *connector)
420 /* Use preferred mode if there is one.. */ 420 /* Use preferred mode if there is one.. */
421 list_for_each_entry(mode, &connector->base.probed_modes, head) { 421 list_for_each_entry(mode, &connector->base.probed_modes, head) {
422 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 422 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
423 NV_DEBUG(dev, "native mode from preferred\n"); 423 NV_DEBUG_KMS(dev, "native mode from preferred\n");
424 return drm_mode_duplicate(dev, mode); 424 return drm_mode_duplicate(dev, mode);
425 } 425 }
426 } 426 }
@@ -445,7 +445,7 @@ nouveau_connector_native_mode(struct nouveau_connector *connector)
445 largest = mode; 445 largest = mode;
446 } 446 }
447 447
448 NV_DEBUG(dev, "native mode from largest: %dx%d@%d\n", 448 NV_DEBUG_KMS(dev, "native mode from largest: %dx%d@%d\n",
449 high_w, high_h, high_v); 449 high_w, high_h, high_v);
450 return largest ? drm_mode_duplicate(dev, largest) : NULL; 450 return largest ? drm_mode_duplicate(dev, largest) : NULL;
451} 451}
@@ -725,7 +725,7 @@ nouveau_connector_create(struct drm_device *dev, int index, int type)
725 struct drm_encoder *encoder; 725 struct drm_encoder *encoder;
726 int ret; 726 int ret;
727 727
728 NV_DEBUG(dev, "\n"); 728 NV_DEBUG_KMS(dev, "\n");
729 729
730 nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL); 730 nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL);
731 if (!nv_connector) 731 if (!nv_connector)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index de61f4640e12..9e2926c48579 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -187,7 +187,7 @@ nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
187 if (ret) 187 if (ret)
188 return false; 188 return false;
189 189
190 NV_DEBUG(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]); 190 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
191 191
192 /* Keep all lanes at the same level.. */ 192 /* Keep all lanes at the same level.. */
193 for (i = 0; i < nv_encoder->dp.link_nr; i++) { 193 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
@@ -228,7 +228,7 @@ nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1); 228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
229 int dpe_headerlen, ret, i; 229 int dpe_headerlen, ret, i;
230 230
231 NV_DEBUG(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n", 231 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
232 config[0], config[1], config[2], config[3]); 232 config[0], config[1], config[2], config[3]);
233 233
234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen); 234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
@@ -276,12 +276,12 @@ nouveau_dp_link_train(struct drm_encoder *encoder)
276 bool cr_done, cr_max_vs, eq_done; 276 bool cr_done, cr_max_vs, eq_done;
277 int ret = 0, i, tries, voltage; 277 int ret = 0, i, tries, voltage;
278 278
279 NV_DEBUG(dev, "link training!!\n"); 279 NV_DEBUG_KMS(dev, "link training!!\n");
280train: 280train:
281 cr_done = eq_done = false; 281 cr_done = eq_done = false;
282 282
283 /* set link configuration */ 283 /* set link configuration */
284 NV_DEBUG(dev, "\tbegin train: bw %d, lanes %d\n", 284 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
285 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr); 285 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
286 286
287 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw); 287 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
@@ -297,7 +297,7 @@ train:
297 return false; 297 return false;
298 298
299 /* clock recovery */ 299 /* clock recovery */
300 NV_DEBUG(dev, "\tbegin cr\n"); 300 NV_DEBUG_KMS(dev, "\tbegin cr\n");
301 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1); 301 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
302 if (ret) 302 if (ret)
303 goto stop; 303 goto stop;
@@ -314,7 +314,7 @@ train:
314 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2); 314 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
315 if (ret) 315 if (ret)
316 break; 316 break;
317 NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n", 317 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
318 status[0], status[1]); 318 status[0], status[1]);
319 319
320 cr_done = true; 320 cr_done = true;
@@ -346,7 +346,7 @@ train:
346 goto stop; 346 goto stop;
347 347
348 /* channel equalisation */ 348 /* channel equalisation */
349 NV_DEBUG(dev, "\tbegin eq\n"); 349 NV_DEBUG_KMS(dev, "\tbegin eq\n");
350 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2); 350 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
351 if (ret) 351 if (ret)
352 goto stop; 352 goto stop;
@@ -357,7 +357,7 @@ train:
357 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3); 357 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
358 if (ret) 358 if (ret)
359 break; 359 break;
360 NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n", 360 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
361 status[0], status[1]); 361 status[0], status[1]);
362 362
363 eq_done = true; 363 eq_done = true;
@@ -395,9 +395,9 @@ stop:
395 395
396 /* retry at a lower setting, if possible */ 396 /* retry at a lower setting, if possible */
397 if (!ret && !(eq_done && cr_done)) { 397 if (!ret && !(eq_done && cr_done)) {
398 NV_DEBUG(dev, "\twe failed\n"); 398 NV_DEBUG_KMS(dev, "\twe failed\n");
399 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) { 399 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
400 NV_DEBUG(dev, "retry link training at low rate\n"); 400 NV_DEBUG_KMS(dev, "retry link training at low rate\n");
401 nv_encoder->dp.link_bw = DP_LINK_BW_1_62; 401 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
402 goto train; 402 goto train;
403 } 403 }
@@ -418,7 +418,7 @@ nouveau_dp_detect(struct drm_encoder *encoder)
418 if (ret) 418 if (ret)
419 return false; 419 return false;
420 420
421 NV_DEBUG(dev, "encoder: link_bw %d, link_nr %d\n" 421 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
422 "display: link_bw %d, link_nr %d version 0x%02x\n", 422 "display: link_bw %d, link_nr %d version 0x%02x\n",
423 nv_encoder->dcb->dpconf.link_bw, 423 nv_encoder->dcb->dpconf.link_bw,
424 nv_encoder->dcb->dpconf.link_nr, 424 nv_encoder->dcb->dpconf.link_nr,
@@ -446,7 +446,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
446 uint32_t tmp, ctrl, stat = 0, data32[4] = {}; 446 uint32_t tmp, ctrl, stat = 0, data32[4] = {};
447 int ret = 0, i, index = auxch->rd; 447 int ret = 0, i, index = auxch->rd;
448 448
449 NV_DEBUG(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr); 449 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
450 450
451 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd)); 451 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
452 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000); 452 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
@@ -472,7 +472,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
472 if (!(cmd & 1)) { 472 if (!(cmd & 1)) {
473 memcpy(data32, data, data_nr); 473 memcpy(data32, data, data_nr);
474 for (i = 0; i < 4; i++) { 474 for (i = 0; i < 4; i++) {
475 NV_DEBUG(dev, "wr %d: 0x%08x\n", i, data32[i]); 475 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
476 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]); 476 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
477 } 477 }
478 } 478 }
@@ -504,7 +504,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
504 if (cmd & 1) { 504 if (cmd & 1) {
505 for (i = 0; i < 4; i++) { 505 for (i = 0; i < 4; i++) {
506 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); 506 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
507 NV_DEBUG(dev, "rd %d: 0x%08x\n", i, data32[i]); 507 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
508 } 508 }
509 memcpy(data, data32, data_nr); 509 memcpy(data, data32, data_nr);
510 } 510 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 35249c35118f..06eb993e0883 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -35,6 +35,10 @@
35 35
36#include "drm_pciids.h" 36#include "drm_pciids.h"
37 37
38MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
39int nouveau_ctxfw = 0;
40module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
41
38MODULE_PARM_DESC(noagp, "Disable AGP"); 42MODULE_PARM_DESC(noagp, "Disable AGP");
39int nouveau_noagp; 43int nouveau_noagp;
40module_param_named(noagp, nouveau_noagp, int, 0400); 44module_param_named(noagp, nouveau_noagp, int, 0400);
@@ -273,7 +277,7 @@ nouveau_pci_resume(struct pci_dev *pdev)
273 277
274 for (i = 0; i < dev_priv->engine.fifo.channels; i++) { 278 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
275 chan = dev_priv->fifos[i]; 279 chan = dev_priv->fifos[i];
276 if (!chan) 280 if (!chan || !chan->pushbuf_bo)
277 continue; 281 continue;
278 282
279 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) 283 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
@@ -341,7 +345,7 @@ static struct drm_driver driver = {
341 .owner = THIS_MODULE, 345 .owner = THIS_MODULE,
342 .open = drm_open, 346 .open = drm_open,
343 .release = drm_release, 347 .release = drm_release,
344 .ioctl = drm_ioctl, 348 .unlocked_ioctl = drm_ioctl,
345 .mmap = nouveau_ttm_mmap, 349 .mmap = nouveau_ttm_mmap,
346 .poll = drm_poll, 350 .poll = drm_poll,
347 .fasync = drm_fasync, 351 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 88b4c7b77e7f..5f8cbb79c499 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -54,6 +54,7 @@ struct nouveau_fpriv {
54#include "nouveau_drm.h" 54#include "nouveau_drm.h"
55#include "nouveau_reg.h" 55#include "nouveau_reg.h"
56#include "nouveau_bios.h" 56#include "nouveau_bios.h"
57struct nouveau_grctx;
57 58
58#define MAX_NUM_DCB_ENTRIES 16 59#define MAX_NUM_DCB_ENTRIES 16
59 60
@@ -317,6 +318,7 @@ struct nouveau_pgraph_engine {
317 bool accel_blocked; 318 bool accel_blocked;
318 void *ctxprog; 319 void *ctxprog;
319 void *ctxvals; 320 void *ctxvals;
321 int grctx_size;
320 322
321 int (*init)(struct drm_device *); 323 int (*init)(struct drm_device *);
322 void (*takedown)(struct drm_device *); 324 void (*takedown)(struct drm_device *);
@@ -647,6 +649,7 @@ extern int nouveau_fbpercrtc;
647extern char *nouveau_tv_norm; 649extern char *nouveau_tv_norm;
648extern int nouveau_reg_debug; 650extern int nouveau_reg_debug;
649extern char *nouveau_vbios; 651extern char *nouveau_vbios;
652extern int nouveau_ctxfw;
650 653
651/* nouveau_state.c */ 654/* nouveau_state.c */
652extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 655extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
@@ -959,9 +962,7 @@ extern int nv40_graph_create_context(struct nouveau_channel *);
959extern void nv40_graph_destroy_context(struct nouveau_channel *); 962extern void nv40_graph_destroy_context(struct nouveau_channel *);
960extern int nv40_graph_load_context(struct nouveau_channel *); 963extern int nv40_graph_load_context(struct nouveau_channel *);
961extern int nv40_graph_unload_context(struct drm_device *); 964extern int nv40_graph_unload_context(struct drm_device *);
962extern int nv40_grctx_init(struct drm_device *); 965extern void nv40_grctx_init(struct nouveau_grctx *);
963extern void nv40_grctx_fini(struct drm_device *);
964extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *);
965 966
966/* nv50_graph.c */ 967/* nv50_graph.c */
967extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 968extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
@@ -975,6 +976,12 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
975extern int nv50_graph_unload_context(struct drm_device *); 976extern int nv50_graph_unload_context(struct drm_device *);
976extern void nv50_graph_context_switch(struct drm_device *); 977extern void nv50_graph_context_switch(struct drm_device *);
977 978
979/* nouveau_grctx.c */
980extern int nouveau_grctx_prog_load(struct drm_device *);
981extern void nouveau_grctx_vals_load(struct drm_device *,
982 struct nouveau_gpuobj *);
983extern void nouveau_grctx_fini(struct drm_device *);
984
978/* nv04_instmem.c */ 985/* nv04_instmem.c */
979extern int nv04_instmem_init(struct drm_device *); 986extern int nv04_instmem_init(struct drm_device *);
980extern void nv04_instmem_takedown(struct drm_device *); 987extern void nv04_instmem_takedown(struct drm_device *);
@@ -1207,14 +1214,24 @@ static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1207 pci_name(d->pdev), ##arg) 1214 pci_name(d->pdev), ##arg)
1208#ifndef NV_DEBUG_NOTRACE 1215#ifndef NV_DEBUG_NOTRACE
1209#define NV_DEBUG(d, fmt, arg...) do { \ 1216#define NV_DEBUG(d, fmt, arg...) do { \
1210 if (drm_debug) { \ 1217 if (drm_debug & DRM_UT_DRIVER) { \
1218 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1219 __LINE__, ##arg); \
1220 } \
1221} while (0)
1222#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1223 if (drm_debug & DRM_UT_KMS) { \
1211 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1224 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1212 __LINE__, ##arg); \ 1225 __LINE__, ##arg); \
1213 } \ 1226 } \
1214} while (0) 1227} while (0)
1215#else 1228#else
1216#define NV_DEBUG(d, fmt, arg...) do { \ 1229#define NV_DEBUG(d, fmt, arg...) do { \
1217 if (drm_debug) \ 1230 if (drm_debug & DRM_UT_DRIVER) \
1231 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1232} while (0)
1233#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1234 if (drm_debug & DRM_UT_KMS) \
1218 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1235 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1219} while (0) 1236} while (0)
1220#endif 1237#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 36e8c5e4503a..84af25c238b6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -58,7 +58,7 @@ nouveau_fbcon_sync(struct fb_info *info)
58 struct nouveau_channel *chan = dev_priv->channel; 58 struct nouveau_channel *chan = dev_priv->channel;
59 int ret, i; 59 int ret, i;
60 60
61 if (!chan->accel_done || 61 if (!chan || !chan->accel_done ||
62 info->state != FBINFO_STATE_RUNNING || 62 info->state != FBINFO_STATE_RUNNING ||
63 info->flags & FBINFO_HWACCEL_DISABLED) 63 info->flags & FBINFO_HWACCEL_DISABLED)
64 return 0; 64 return 0;
@@ -318,14 +318,16 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width,
318 par->nouveau_fb = nouveau_fb; 318 par->nouveau_fb = nouveau_fb;
319 par->dev = dev; 319 par->dev = dev;
320 320
321 switch (dev_priv->card_type) { 321 if (dev_priv->channel) {
322 case NV_50: 322 switch (dev_priv->card_type) {
323 nv50_fbcon_accel_init(info); 323 case NV_50:
324 break; 324 nv50_fbcon_accel_init(info);
325 default: 325 break;
326 nv04_fbcon_accel_init(info); 326 default:
327 break; 327 nv04_fbcon_accel_init(info);
328 }; 328 break;
329 };
330 }
329 331
330 nouveau_fbcon_zfill(dev); 332 nouveau_fbcon_zfill(dev);
331 333
@@ -347,7 +349,7 @@ out:
347int 349int
348nouveau_fbcon_probe(struct drm_device *dev) 350nouveau_fbcon_probe(struct drm_device *dev)
349{ 351{
350 NV_DEBUG(dev, "\n"); 352 NV_DEBUG_KMS(dev, "\n");
351 353
352 return drm_fb_helper_single_fb_probe(dev, 32, nouveau_fbcon_create); 354 return drm_fb_helper_single_fb_probe(dev, 32, nouveau_fbcon_create);
353} 355}
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
new file mode 100644
index 000000000000..419f4c2b3b89
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <linux/firmware.h>
26
27#include "drmP.h"
28#include "nouveau_drv.h"
29
30struct nouveau_ctxprog {
31 uint32_t signature;
32 uint8_t version;
33 uint16_t length;
34 uint32_t data[];
35} __attribute__ ((packed));
36
37struct nouveau_ctxvals {
38 uint32_t signature;
39 uint8_t version;
40 uint32_t length;
41 struct {
42 uint32_t offset;
43 uint32_t value;
44 } data[];
45} __attribute__ ((packed));
46
47int
48nouveau_grctx_prog_load(struct drm_device *dev)
49{
50 struct drm_nouveau_private *dev_priv = dev->dev_private;
51 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
52 const int chipset = dev_priv->chipset;
53 const struct firmware *fw;
54 const struct nouveau_ctxprog *cp;
55 const struct nouveau_ctxvals *cv;
56 char name[32];
57 int ret, i;
58
59 if (pgraph->accel_blocked)
60 return -ENODEV;
61
62 if (!pgraph->ctxprog) {
63 sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
64 ret = request_firmware(&fw, name, &dev->pdev->dev);
65 if (ret) {
66 NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
67 return ret;
68 }
69
70 pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);
71 if (!pgraph->ctxprog) {
72 NV_ERROR(dev, "OOM copying ctxprog\n");
73 release_firmware(fw);
74 return -ENOMEM;
75 }
76 memcpy(pgraph->ctxprog, fw->data, fw->size);
77
78 cp = pgraph->ctxprog;
79 if (le32_to_cpu(cp->signature) != 0x5043564e ||
80 cp->version != 0 ||
81 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
82 NV_ERROR(dev, "ctxprog invalid\n");
83 release_firmware(fw);
84 nouveau_grctx_fini(dev);
85 return -EINVAL;
86 }
87 release_firmware(fw);
88 }
89
90 if (!pgraph->ctxvals) {
91 sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
92 ret = request_firmware(&fw, name, &dev->pdev->dev);
93 if (ret) {
94 NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
95 nouveau_grctx_fini(dev);
96 return ret;
97 }
98
99 pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
100 if (!pgraph->ctxprog) {
101 NV_ERROR(dev, "OOM copying ctxprog\n");
102 release_firmware(fw);
103 nouveau_grctx_fini(dev);
104 return -ENOMEM;
105 }
106 memcpy(pgraph->ctxvals, fw->data, fw->size);
107
108 cv = (void *)pgraph->ctxvals;
109 if (le32_to_cpu(cv->signature) != 0x5643564e ||
110 cv->version != 0 ||
111 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
112 NV_ERROR(dev, "ctxvals invalid\n");
113 release_firmware(fw);
114 nouveau_grctx_fini(dev);
115 return -EINVAL;
116 }
117 release_firmware(fw);
118 }
119
120 cp = pgraph->ctxprog;
121
122 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
123 for (i = 0; i < le16_to_cpu(cp->length); i++)
124 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
125 le32_to_cpu(cp->data[i]));
126
127 return 0;
128}
129
130void
131nouveau_grctx_fini(struct drm_device *dev)
132{
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
135
136 if (pgraph->ctxprog) {
137 kfree(pgraph->ctxprog);
138 pgraph->ctxprog = NULL;
139 }
140
141 if (pgraph->ctxvals) {
142 kfree(pgraph->ctxprog);
143 pgraph->ctxvals = NULL;
144 }
145}
146
147void
148nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
149{
150 struct drm_nouveau_private *dev_priv = dev->dev_private;
151 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
152 struct nouveau_ctxvals *cv = pgraph->ctxvals;
153 int i;
154
155 if (!cv)
156 return;
157
158 for (i = 0; i < le32_to_cpu(cv->length); i++)
159 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
160 le32_to_cpu(cv->data[i].value));
161}
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.h b/drivers/gpu/drm/nouveau/nouveau_grctx.h
new file mode 100644
index 000000000000..5d39c4ce8006
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.h
@@ -0,0 +1,133 @@
1#ifndef __NOUVEAU_GRCTX_H__
2#define __NOUVEAU_GRCTX_H__
3
4struct nouveau_grctx {
5 struct drm_device *dev;
6
7 enum {
8 NOUVEAU_GRCTX_PROG,
9 NOUVEAU_GRCTX_VALS
10 } mode;
11 void *data;
12
13 uint32_t ctxprog_max;
14 uint32_t ctxprog_len;
15 uint32_t ctxprog_reg;
16 int ctxprog_label[32];
17 uint32_t ctxvals_pos;
18 uint32_t ctxvals_base;
19};
20
21#ifdef CP_CTX
22static inline void
23cp_out(struct nouveau_grctx *ctx, uint32_t inst)
24{
25 uint32_t *ctxprog = ctx->data;
26
27 if (ctx->mode != NOUVEAU_GRCTX_PROG)
28 return;
29
30 BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
31 ctxprog[ctx->ctxprog_len++] = inst;
32}
33
34static inline void
35cp_lsr(struct nouveau_grctx *ctx, uint32_t val)
36{
37 cp_out(ctx, CP_LOAD_SR | val);
38}
39
40static inline void
41cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length)
42{
43 ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
44
45 ctx->ctxvals_base = ctx->ctxvals_pos;
46 ctx->ctxvals_pos = ctx->ctxvals_base + length;
47
48 if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {
49 cp_lsr(ctx, length);
50 length = 0;
51 }
52
53 cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);
54}
55
56static inline void
57cp_name(struct nouveau_grctx *ctx, int name)
58{
59 uint32_t *ctxprog = ctx->data;
60 int i;
61
62 if (ctx->mode != NOUVEAU_GRCTX_PROG)
63 return;
64
65 ctx->ctxprog_label[name] = ctx->ctxprog_len;
66 for (i = 0; i < ctx->ctxprog_len; i++) {
67 if ((ctxprog[i] & 0xfff00000) != 0xff400000)
68 continue;
69 if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))
70 continue;
71 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |
72 (ctx->ctxprog_len << CP_BRA_IP_SHIFT);
73 }
74}
75
76static inline void
77_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
78{
79 int ip = 0;
80
81 if (mod != 2) {
82 ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;
83 if (ip == 0)
84 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);
85 }
86
87 cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
88 (state ? 0 : CP_BRA_IF_CLEAR));
89}
90#define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
91#ifdef CP_BRA_MOD
92#define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
93#define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
94#endif
95
96static inline void
97_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
98{
99 cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
100}
101#define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
102
103static inline void
104_cp_set(struct nouveau_grctx *ctx, int flag, int state)
105{
106 cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
107}
108#define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
109
110static inline void
111cp_pos(struct nouveau_grctx *ctx, int offset)
112{
113 ctx->ctxvals_pos = offset;
114 ctx->ctxvals_base = ctx->ctxvals_pos;
115
116 cp_lsr(ctx, ctx->ctxvals_pos);
117 cp_out(ctx, CP_SET_CONTEXT_POINTER);
118}
119
120static inline void
121gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)
122{
123 if (ctx->mode != NOUVEAU_GRCTX_VALS)
124 return;
125
126 reg = (reg - 0x00400000) / 4;
127 reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;
128
129 nv_wo32(ctx->dev, ctx->data, reg, val);
130}
131#endif
132
133#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_ioc32.c b/drivers/gpu/drm/nouveau/nouveau_ioc32.c
index a2c30f4611ba..475ba810bba3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ioc32.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ioc32.c
@@ -61,12 +61,10 @@ long nouveau_compat_ioctl(struct file *filp, unsigned int cmd,
61 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) 61 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
62 fn = nouveau_compat_ioctls[nr - DRM_COMMAND_BASE]; 62 fn = nouveau_compat_ioctls[nr - DRM_COMMAND_BASE];
63#endif 63#endif
64 lock_kernel(); /* XXX for now */
65 if (fn != NULL) 64 if (fn != NULL)
66 ret = (*fn)(filp, cmd, arg); 65 ret = (*fn)(filp, cmd, arg);
67 else 66 else
68 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 67 ret = drm_ioctl(filp, cmd, arg);
69 unlock_kernel();
70 68
71 return ret; 69 return ret;
72} 70}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 2ed41d339f6a..e76ec2d207a9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -299,12 +299,57 @@ nouveau_vga_set_decode(void *priv, bool state)
299 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 299 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
300} 300}
301 301
302static int
303nouveau_card_init_channel(struct drm_device *dev)
304{
305 struct drm_nouveau_private *dev_priv = dev->dev_private;
306 struct nouveau_gpuobj *gpuobj;
307 int ret;
308
309 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
310 (struct drm_file *)-2,
311 NvDmaFB, NvDmaTT);
312 if (ret)
313 return ret;
314
315 gpuobj = NULL;
316 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
317 0, nouveau_mem_fb_amount(dev),
318 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
319 &gpuobj);
320 if (ret)
321 goto out_err;
322
323 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
324 gpuobj, NULL);
325 if (ret)
326 goto out_err;
327
328 gpuobj = NULL;
329 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
330 dev_priv->gart_info.aper_size,
331 NV_DMA_ACCESS_RW, &gpuobj, NULL);
332 if (ret)
333 goto out_err;
334
335 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
336 gpuobj, NULL);
337 if (ret)
338 goto out_err;
339
340 return 0;
341out_err:
342 nouveau_gpuobj_del(dev, &gpuobj);
343 nouveau_channel_free(dev_priv->channel);
344 dev_priv->channel = NULL;
345 return ret;
346}
347
302int 348int
303nouveau_card_init(struct drm_device *dev) 349nouveau_card_init(struct drm_device *dev)
304{ 350{
305 struct drm_nouveau_private *dev_priv = dev->dev_private; 351 struct drm_nouveau_private *dev_priv = dev->dev_private;
306 struct nouveau_engine *engine; 352 struct nouveau_engine *engine;
307 struct nouveau_gpuobj *gpuobj;
308 int ret; 353 int ret;
309 354
310 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state); 355 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
@@ -317,7 +362,7 @@ nouveau_card_init(struct drm_device *dev)
317 /* Initialise internal driver API hooks */ 362 /* Initialise internal driver API hooks */
318 ret = nouveau_init_engine_ptrs(dev); 363 ret = nouveau_init_engine_ptrs(dev);
319 if (ret) 364 if (ret)
320 return ret; 365 goto out;
321 engine = &dev_priv->engine; 366 engine = &dev_priv->engine;
322 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED; 367 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
323 368
@@ -325,12 +370,12 @@ nouveau_card_init(struct drm_device *dev)
325 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 370 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
326 ret = nouveau_bios_init(dev); 371 ret = nouveau_bios_init(dev);
327 if (ret) 372 if (ret)
328 return ret; 373 goto out;
329 } 374 }
330 375
331 ret = nouveau_gpuobj_early_init(dev); 376 ret = nouveau_gpuobj_early_init(dev);
332 if (ret) 377 if (ret)
333 return ret; 378 goto out_bios;
334 379
335 /* Initialise instance memory, must happen before mem_init so we 380 /* Initialise instance memory, must happen before mem_init so we
336 * know exactly how much VRAM we're able to use for "normal" 381 * know exactly how much VRAM we're able to use for "normal"
@@ -338,100 +383,68 @@ nouveau_card_init(struct drm_device *dev)
338 */ 383 */
339 ret = engine->instmem.init(dev); 384 ret = engine->instmem.init(dev);
340 if (ret) 385 if (ret)
341 return ret; 386 goto out_gpuobj_early;
342 387
343 /* Setup the memory manager */ 388 /* Setup the memory manager */
344 ret = nouveau_mem_init(dev); 389 ret = nouveau_mem_init(dev);
345 if (ret) 390 if (ret)
346 return ret; 391 goto out_instmem;
347 392
348 ret = nouveau_gpuobj_init(dev); 393 ret = nouveau_gpuobj_init(dev);
349 if (ret) 394 if (ret)
350 return ret; 395 goto out_mem;
351 396
352 /* PMC */ 397 /* PMC */
353 ret = engine->mc.init(dev); 398 ret = engine->mc.init(dev);
354 if (ret) 399 if (ret)
355 return ret; 400 goto out_gpuobj;
356 401
357 /* PTIMER */ 402 /* PTIMER */
358 ret = engine->timer.init(dev); 403 ret = engine->timer.init(dev);
359 if (ret) 404 if (ret)
360 return ret; 405 goto out_mc;
361 406
362 /* PFB */ 407 /* PFB */
363 ret = engine->fb.init(dev); 408 ret = engine->fb.init(dev);
364 if (ret) 409 if (ret)
365 return ret; 410 goto out_timer;
366 411
367 /* PGRAPH */ 412 /* PGRAPH */
368 ret = engine->graph.init(dev); 413 ret = engine->graph.init(dev);
369 if (ret) 414 if (ret)
370 return ret; 415 goto out_fb;
371 416
372 /* PFIFO */ 417 /* PFIFO */
373 ret = engine->fifo.init(dev); 418 ret = engine->fifo.init(dev);
374 if (ret) 419 if (ret)
375 return ret; 420 goto out_graph;
376 421
377 /* this call irq_preinstall, register irq handler and 422 /* this call irq_preinstall, register irq handler and
378 * call irq_postinstall 423 * call irq_postinstall
379 */ 424 */
380 ret = drm_irq_install(dev); 425 ret = drm_irq_install(dev);
381 if (ret) 426 if (ret)
382 return ret; 427 goto out_fifo;
383 428
384 ret = drm_vblank_init(dev, 0); 429 ret = drm_vblank_init(dev, 0);
385 if (ret) 430 if (ret)
386 return ret; 431 goto out_irq;
387 432
388 /* what about PVIDEO/PCRTC/PRAMDAC etc? */ 433 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
389 434
390 ret = nouveau_channel_alloc(dev, &dev_priv->channel, 435 if (!engine->graph.accel_blocked) {
391 (struct drm_file *)-2, 436 ret = nouveau_card_init_channel(dev);
392 NvDmaFB, NvDmaTT); 437 if (ret)
393 if (ret) 438 goto out_irq;
394 return ret;
395
396 gpuobj = NULL;
397 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
398 0, nouveau_mem_fb_amount(dev),
399 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
400 &gpuobj);
401 if (ret)
402 return ret;
403
404 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
405 gpuobj, NULL);
406 if (ret) {
407 nouveau_gpuobj_del(dev, &gpuobj);
408 return ret;
409 }
410
411 gpuobj = NULL;
412 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
413 dev_priv->gart_info.aper_size,
414 NV_DMA_ACCESS_RW, &gpuobj, NULL);
415 if (ret)
416 return ret;
417
418 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
419 gpuobj, NULL);
420 if (ret) {
421 nouveau_gpuobj_del(dev, &gpuobj);
422 return ret;
423 } 439 }
424 440
425 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 441 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
426 if (dev_priv->card_type >= NV_50) { 442 if (dev_priv->card_type >= NV_50)
427 ret = nv50_display_create(dev); 443 ret = nv50_display_create(dev);
428 if (ret) 444 else
429 return ret;
430 } else {
431 ret = nv04_display_create(dev); 445 ret = nv04_display_create(dev);
432 if (ret) 446 if (ret)
433 return ret; 447 goto out_irq;
434 }
435 } 448 }
436 449
437 ret = nouveau_backlight_init(dev); 450 ret = nouveau_backlight_init(dev);
@@ -444,6 +457,32 @@ nouveau_card_init(struct drm_device *dev)
444 drm_helper_initial_config(dev); 457 drm_helper_initial_config(dev);
445 458
446 return 0; 459 return 0;
460
461out_irq:
462 drm_irq_uninstall(dev);
463out_fifo:
464 engine->fifo.takedown(dev);
465out_graph:
466 engine->graph.takedown(dev);
467out_fb:
468 engine->fb.takedown(dev);
469out_timer:
470 engine->timer.takedown(dev);
471out_mc:
472 engine->mc.takedown(dev);
473out_gpuobj:
474 nouveau_gpuobj_takedown(dev);
475out_mem:
476 nouveau_mem_close(dev);
477out_instmem:
478 engine->instmem.takedown(dev);
479out_gpuobj_early:
480 nouveau_gpuobj_late_takedown(dev);
481out_bios:
482 nouveau_bios_takedown(dev);
483out:
484 vga_client_register(dev->pdev, NULL, NULL, NULL);
485 return ret;
447} 486}
448 487
449static void nouveau_card_takedown(struct drm_device *dev) 488static void nouveau_card_takedown(struct drm_device *dev)
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index b91363606055..d2f143ed97c1 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -143,10 +143,10 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
144 144
145 if (pv->NM2) 145 if (pv->NM2)
146 NV_TRACE(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 146 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
148 else 148 else
149 NV_TRACE(dev, "vpll: n %d m %d log2p %d\n", 149 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n",
150 pv->N1, pv->M1, pv->log2P); 150 pv->N1, pv->M1, pv->log2P);
151 151
152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
@@ -160,7 +160,7 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
160 unsigned char seq1 = 0, crtc17 = 0; 160 unsigned char seq1 = 0, crtc17 = 0;
161 unsigned char crtc1A; 161 unsigned char crtc1A;
162 162
163 NV_TRACE(dev, "Setting dpms mode %d on CRTC %d\n", mode, 163 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
164 nv_crtc->index); 164 nv_crtc->index);
165 165
166 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */ 166 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
@@ -603,7 +603,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
603 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 603 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
604 struct drm_nouveau_private *dev_priv = dev->dev_private; 604 struct drm_nouveau_private *dev_priv = dev->dev_private;
605 605
606 NV_DEBUG(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 606 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
607 drm_mode_debug_printmodeline(adjusted_mode); 607 drm_mode_debug_printmodeline(adjusted_mode);
608 608
609 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 609 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
@@ -703,7 +703,7 @@ static void nv_crtc_destroy(struct drm_crtc *crtc)
703{ 703{
704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
705 705
706 NV_DEBUG(crtc->dev, "\n"); 706 NV_DEBUG_KMS(crtc->dev, "\n");
707 707
708 if (!nv_crtc) 708 if (!nv_crtc)
709 return; 709 return;
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index a5fa51714e87..d9f32879ba38 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -205,7 +205,7 @@ out:
205 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1); 205 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
206 206
207 if (blue == 0x18) { 207 if (blue == 0x18) {
208 NV_TRACE(dev, "Load detected on head A\n"); 208 NV_INFO(dev, "Load detected on head A\n");
209 return connector_status_connected; 209 return connector_status_connected;
210 } 210 }
211 211
@@ -350,14 +350,10 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
350 struct drm_display_mode *mode, 350 struct drm_display_mode *mode,
351 struct drm_display_mode *adjusted_mode) 351 struct drm_display_mode *adjusted_mode)
352{ 352{
353 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
354 struct drm_device *dev = encoder->dev; 353 struct drm_device *dev = encoder->dev;
355 struct drm_nouveau_private *dev_priv = dev->dev_private; 354 struct drm_nouveau_private *dev_priv = dev->dev_private;
356 int head = nouveau_crtc(encoder->crtc)->index; 355 int head = nouveau_crtc(encoder->crtc)->index;
357 356
358 NV_TRACE(dev, "%s called for encoder %d\n", __func__,
359 nv_encoder->dcb->index);
360
361 if (nv_gf4_disp_arch(dev)) { 357 if (nv_gf4_disp_arch(dev)) {
362 struct drm_encoder *rebind; 358 struct drm_encoder *rebind;
363 uint32_t dac_offset = nv04_dac_output_offset(encoder); 359 uint32_t dac_offset = nv04_dac_output_offset(encoder);
@@ -466,7 +462,7 @@ static void nv04_dac_destroy(struct drm_encoder *encoder)
466{ 462{
467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
468 464
469 NV_DEBUG(encoder->dev, "\n"); 465 NV_DEBUG_KMS(encoder->dev, "\n");
470 466
471 drm_encoder_cleanup(encoder); 467 drm_encoder_cleanup(encoder);
472 kfree(nv_encoder); 468 kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index e5b33339d595..483f875bdb6a 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -261,7 +261,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
261 struct drm_display_mode *output_mode = &nv_encoder->mode; 261 struct drm_display_mode *output_mode = &nv_encoder->mode;
262 uint32_t mode_ratio, panel_ratio; 262 uint32_t mode_ratio, panel_ratio;
263 263
264 NV_DEBUG(dev, "Output mode on CRTC %d:\n", nv_crtc->index); 264 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
265 drm_mode_debug_printmodeline(output_mode); 265 drm_mode_debug_printmodeline(output_mode);
266 266
267 /* Initialize the FP registers in this CRTC. */ 267 /* Initialize the FP registers in this CRTC. */
@@ -413,7 +413,9 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
413 struct dcb_entry *dcbe = nv_encoder->dcb; 413 struct dcb_entry *dcbe = nv_encoder->dcb;
414 int head = nouveau_crtc(encoder->crtc)->index; 414 int head = nouveau_crtc(encoder->crtc)->index;
415 415
416 NV_TRACE(dev, "%s called for encoder %d\n", __func__, nv_encoder->dcb->index); 416 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
417 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
418 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
417 419
418 if (dcbe->type == OUTPUT_TMDS) 420 if (dcbe->type == OUTPUT_TMDS)
419 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); 421 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
@@ -550,7 +552,7 @@ static void nv04_dfp_destroy(struct drm_encoder *encoder)
550{ 552{
551 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 553 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
552 554
553 NV_DEBUG(encoder->dev, "\n"); 555 NV_DEBUG_KMS(encoder->dev, "\n");
554 556
555 drm_encoder_cleanup(encoder); 557 drm_encoder_cleanup(encoder);
556 kfree(nv_encoder); 558 kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c
index b47c757ff48b..ef77215fa5b9 100644
--- a/drivers/gpu/drm/nouveau/nv04_display.c
+++ b/drivers/gpu/drm/nouveau/nv04_display.c
@@ -99,10 +99,11 @@ nv04_display_create(struct drm_device *dev)
99 uint16_t connector[16] = { 0 }; 99 uint16_t connector[16] = { 0 };
100 int i, ret; 100 int i, ret;
101 101
102 NV_DEBUG(dev, "\n"); 102 NV_DEBUG_KMS(dev, "\n");
103 103
104 if (nv_two_heads(dev)) 104 if (nv_two_heads(dev))
105 nv04_display_store_initial_head_owner(dev); 105 nv04_display_store_initial_head_owner(dev);
106 nouveau_hw_save_vga_fonts(dev, 1);
106 107
107 drm_mode_config_init(dev); 108 drm_mode_config_init(dev);
108 drm_mode_create_scaling_mode_property(dev); 109 drm_mode_create_scaling_mode_property(dev);
@@ -203,8 +204,6 @@ nv04_display_create(struct drm_device *dev)
203 /* Save previous state */ 204 /* Save previous state */
204 NVLockVgaCrtcs(dev, false); 205 NVLockVgaCrtcs(dev, false);
205 206
206 nouveau_hw_save_vga_fonts(dev, 1);
207
208 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 207 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
209 crtc->funcs->save(crtc); 208 crtc->funcs->save(crtc);
210 209
@@ -223,7 +222,7 @@ nv04_display_destroy(struct drm_device *dev)
223 struct drm_encoder *encoder; 222 struct drm_encoder *encoder;
224 struct drm_crtc *crtc; 223 struct drm_crtc *crtc;
225 224
226 NV_DEBUG(dev, "\n"); 225 NV_DEBUG_KMS(dev, "\n");
227 226
228 /* Turn every CRTC off. */ 227 /* Turn every CRTC off. */
229 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 228 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -246,9 +245,9 @@ nv04_display_destroy(struct drm_device *dev)
246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
247 crtc->funcs->restore(crtc); 246 crtc->funcs->restore(crtc);
248 247
249 nouveau_hw_save_vga_fonts(dev, 0);
250
251 drm_mode_config_cleanup(dev); 248 drm_mode_config_cleanup(dev);
249
250 nouveau_hw_save_vga_fonts(dev, 0);
252} 251}
253 252
254void 253void
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index 396ee92118f6..d561d773c0f4 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -543,7 +543,7 @@ nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
543 543
544 nv_wi32(dev, instance, tmp); 544 nv_wi32(dev, instance, tmp);
545 nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp); 545 nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
546 nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + subc, tmp); 546 nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
547 return 0; 547 return 0;
548} 548}
549 549
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 6bf6804bb0ef..6870e0ee2e7e 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -389,49 +389,50 @@ struct graph_state {
389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)]; 389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)]; 390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
391 struct pipe_state pipe_state; 391 struct pipe_state pipe_state;
392 uint32_t lma_window[4];
392}; 393};
393 394
395#define PIPE_SAVE(dev, state, addr) \
396 do { \
397 int __i; \
398 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
399 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
400 state[__i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \
401 } while (0)
402
403#define PIPE_RESTORE(dev, state, addr) \
404 do { \
405 int __i; \
406 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
407 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
408 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, state[__i]); \
409 } while (0)
410
394static void nv10_graph_save_pipe(struct nouveau_channel *chan) 411static void nv10_graph_save_pipe(struct nouveau_channel *chan)
395{ 412{
396 struct drm_device *dev = chan->dev; 413 struct drm_device *dev = chan->dev;
397 struct graph_state *pgraph_ctx = chan->pgraph_ctx; 414 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
398 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; 415 struct pipe_state *pipe = &pgraph_ctx->pipe_state;
399 int i; 416
400#define PIPE_SAVE(addr) \ 417 PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
401 do { \ 418 PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
402 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \ 419 PIPE_SAVE(dev, pipe->pipe_0x6400, 0x6400);
403 for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \ 420 PIPE_SAVE(dev, pipe->pipe_0x6800, 0x6800);
404 fifo_pipe_state->pipe_##addr[i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \ 421 PIPE_SAVE(dev, pipe->pipe_0x6c00, 0x6c00);
405 } while (0) 422 PIPE_SAVE(dev, pipe->pipe_0x7000, 0x7000);
406 423 PIPE_SAVE(dev, pipe->pipe_0x7400, 0x7400);
407 PIPE_SAVE(0x4400); 424 PIPE_SAVE(dev, pipe->pipe_0x7800, 0x7800);
408 PIPE_SAVE(0x0200); 425 PIPE_SAVE(dev, pipe->pipe_0x0040, 0x0040);
409 PIPE_SAVE(0x6400); 426 PIPE_SAVE(dev, pipe->pipe_0x0000, 0x0000);
410 PIPE_SAVE(0x6800);
411 PIPE_SAVE(0x6c00);
412 PIPE_SAVE(0x7000);
413 PIPE_SAVE(0x7400);
414 PIPE_SAVE(0x7800);
415 PIPE_SAVE(0x0040);
416 PIPE_SAVE(0x0000);
417
418#undef PIPE_SAVE
419} 427}
420 428
421static void nv10_graph_load_pipe(struct nouveau_channel *chan) 429static void nv10_graph_load_pipe(struct nouveau_channel *chan)
422{ 430{
423 struct drm_device *dev = chan->dev; 431 struct drm_device *dev = chan->dev;
424 struct graph_state *pgraph_ctx = chan->pgraph_ctx; 432 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
425 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state; 433 struct pipe_state *pipe = &pgraph_ctx->pipe_state;
426 int i;
427 uint32_t xfmode0, xfmode1; 434 uint32_t xfmode0, xfmode1;
428#define PIPE_RESTORE(addr) \ 435 int i;
429 do { \
430 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
431 for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \
432 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
433 } while (0)
434
435 436
436 nouveau_wait_for_idle(dev); 437 nouveau_wait_for_idle(dev);
437 /* XXX check haiku comments */ 438 /* XXX check haiku comments */
@@ -457,24 +458,22 @@ static void nv10_graph_load_pipe(struct nouveau_channel *chan)
457 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008); 458 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
458 459
459 460
460 PIPE_RESTORE(0x0200); 461 PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
461 nouveau_wait_for_idle(dev); 462 nouveau_wait_for_idle(dev);
462 463
463 /* restore XFMODE */ 464 /* restore XFMODE */
464 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0); 465 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
465 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1); 466 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
466 PIPE_RESTORE(0x6400); 467 PIPE_RESTORE(dev, pipe->pipe_0x6400, 0x6400);
467 PIPE_RESTORE(0x6800); 468 PIPE_RESTORE(dev, pipe->pipe_0x6800, 0x6800);
468 PIPE_RESTORE(0x6c00); 469 PIPE_RESTORE(dev, pipe->pipe_0x6c00, 0x6c00);
469 PIPE_RESTORE(0x7000); 470 PIPE_RESTORE(dev, pipe->pipe_0x7000, 0x7000);
470 PIPE_RESTORE(0x7400); 471 PIPE_RESTORE(dev, pipe->pipe_0x7400, 0x7400);
471 PIPE_RESTORE(0x7800); 472 PIPE_RESTORE(dev, pipe->pipe_0x7800, 0x7800);
472 PIPE_RESTORE(0x4400); 473 PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
473 PIPE_RESTORE(0x0000); 474 PIPE_RESTORE(dev, pipe->pipe_0x0000, 0x0000);
474 PIPE_RESTORE(0x0040); 475 PIPE_RESTORE(dev, pipe->pipe_0x0040, 0x0040);
475 nouveau_wait_for_idle(dev); 476 nouveau_wait_for_idle(dev);
476
477#undef PIPE_RESTORE
478} 477}
479 478
480static void nv10_graph_create_pipe(struct nouveau_channel *chan) 479static void nv10_graph_create_pipe(struct nouveau_channel *chan)
@@ -832,6 +831,9 @@ int nv10_graph_init(struct drm_device *dev)
832 (1<<31)); 831 (1<<31));
833 if (dev_priv->chipset >= 0x17) { 832 if (dev_priv->chipset >= 0x17) {
834 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000); 833 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000);
834 nv_wr32(dev, 0x400a10, 0x3ff3fb6);
835 nv_wr32(dev, 0x400838, 0x2f8684);
836 nv_wr32(dev, 0x40083c, 0x115f3f);
835 nv_wr32(dev, 0x004006b0, 0x40000020); 837 nv_wr32(dev, 0x004006b0, 0x40000020);
836 } else 838 } else
837 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); 839 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
@@ -867,6 +869,115 @@ void nv10_graph_takedown(struct drm_device *dev)
867{ 869{
868} 870}
869 871
872static int
873nv17_graph_mthd_lma_window(struct nouveau_channel *chan, int grclass,
874 int mthd, uint32_t data)
875{
876 struct drm_device *dev = chan->dev;
877 struct graph_state *ctx = chan->pgraph_ctx;
878 struct pipe_state *pipe = &ctx->pipe_state;
879 struct drm_nouveau_private *dev_priv = dev->dev_private;
880 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
881 uint32_t pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
882 uint32_t xfmode0, xfmode1;
883 int i;
884
885 ctx->lma_window[(mthd - 0x1638) / 4] = data;
886
887 if (mthd != 0x1644)
888 return 0;
889
890 nouveau_wait_for_idle(dev);
891
892 PIPE_SAVE(dev, pipe_0x0040, 0x0040);
893 PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
894
895 PIPE_RESTORE(dev, ctx->lma_window, 0x6790);
896
897 nouveau_wait_for_idle(dev);
898
899 xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0);
900 xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1);
901
902 PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
903 PIPE_SAVE(dev, pipe_0x64c0, 0x64c0);
904 PIPE_SAVE(dev, pipe_0x6ab0, 0x6ab0);
905 PIPE_SAVE(dev, pipe_0x6a80, 0x6a80);
906
907 nouveau_wait_for_idle(dev);
908
909 nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000);
910 nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000);
911 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
912 for (i = 0; i < 4; i++)
913 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
914 for (i = 0; i < 4; i++)
915 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
916
917 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
918 for (i = 0; i < 3; i++)
919 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
920
921 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
922 for (i = 0; i < 3; i++)
923 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
924
925 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
926 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
927
928 PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
929
930 nouveau_wait_for_idle(dev);
931
932 PIPE_RESTORE(dev, pipe_0x0040, 0x0040);
933
934 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
935 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
936
937 PIPE_RESTORE(dev, pipe_0x64c0, 0x64c0);
938 PIPE_RESTORE(dev, pipe_0x6ab0, 0x6ab0);
939 PIPE_RESTORE(dev, pipe_0x6a80, 0x6a80);
940 PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
941
942 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
943 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
944
945 nouveau_wait_for_idle(dev);
946
947 pgraph->fifo_access(dev, true);
948
949 return 0;
950}
951
952static int
953nv17_graph_mthd_lma_enable(struct nouveau_channel *chan, int grclass,
954 int mthd, uint32_t data)
955{
956 struct drm_device *dev = chan->dev;
957 struct drm_nouveau_private *dev_priv = dev->dev_private;
958 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
959
960 nouveau_wait_for_idle(dev);
961
962 nv_wr32(dev, NV10_PGRAPH_DEBUG_4,
963 nv_rd32(dev, NV10_PGRAPH_DEBUG_4) | 0x1 << 8);
964 nv_wr32(dev, 0x004006b0,
965 nv_rd32(dev, 0x004006b0) | 0x8 << 24);
966
967 pgraph->fifo_access(dev, true);
968
969 return 0;
970}
971
972static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = {
973 { 0x1638, nv17_graph_mthd_lma_window },
974 { 0x163c, nv17_graph_mthd_lma_window },
975 { 0x1640, nv17_graph_mthd_lma_window },
976 { 0x1644, nv17_graph_mthd_lma_window },
977 { 0x1658, nv17_graph_mthd_lma_enable },
978 {}
979};
980
870struct nouveau_pgraph_object_class nv10_graph_grclass[] = { 981struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
871 { 0x0030, false, NULL }, /* null */ 982 { 0x0030, false, NULL }, /* null */
872 { 0x0039, false, NULL }, /* m2mf */ 983 { 0x0039, false, NULL }, /* m2mf */
@@ -887,6 +998,6 @@ struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
887 { 0x0095, false, NULL }, /* multitex_tri */ 998 { 0x0095, false, NULL }, /* multitex_tri */
888 { 0x0056, false, NULL }, /* celcius (nv10) */ 999 { 0x0056, false, NULL }, /* celcius (nv10) */
889 { 0x0096, false, NULL }, /* celcius (nv11) */ 1000 { 0x0096, false, NULL }, /* celcius (nv11) */
890 { 0x0099, false, NULL }, /* celcius (nv17) */ 1001 { 0x0099, false, nv17_graph_celsius_mthds }, /* celcius (nv17) */
891 {} 1002 {}
892}; 1003};
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 46cfd9c60478..81c01353a9f9 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -219,7 +219,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
219 return; 219 return;
220 nouveau_encoder(encoder)->last_dpms = mode; 220 nouveau_encoder(encoder)->last_dpms = mode;
221 221
222 NV_TRACE(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 222 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
223 mode, nouveau_encoder(encoder)->dcb->index); 223 mode, nouveau_encoder(encoder)->dcb->index);
224 224
225 regs->ptv_200 &= ~1; 225 regs->ptv_200 &= ~1;
@@ -619,7 +619,7 @@ static void nv17_tv_destroy(struct drm_encoder *encoder)
619{ 619{
620 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 620 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
621 621
622 NV_DEBUG(encoder->dev, "\n"); 622 NV_DEBUG_KMS(encoder->dev, "\n");
623 623
624 drm_encoder_cleanup(encoder); 624 drm_encoder_cleanup(encoder);
625 kfree(tv_enc); 625 kfree(tv_enc);
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 7e8547cb5833..2b332bb55acf 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -24,36 +24,10 @@
24 * 24 *
25 */ 25 */
26 26
27#include <linux/firmware.h>
28
29#include "drmP.h" 27#include "drmP.h"
30#include "drm.h" 28#include "drm.h"
31#include "nouveau_drv.h" 29#include "nouveau_drv.h"
32 30#include "nouveau_grctx.h"
33MODULE_FIRMWARE("nouveau/nv40.ctxprog");
34MODULE_FIRMWARE("nouveau/nv40.ctxvals");
35MODULE_FIRMWARE("nouveau/nv41.ctxprog");
36MODULE_FIRMWARE("nouveau/nv41.ctxvals");
37MODULE_FIRMWARE("nouveau/nv42.ctxprog");
38MODULE_FIRMWARE("nouveau/nv42.ctxvals");
39MODULE_FIRMWARE("nouveau/nv43.ctxprog");
40MODULE_FIRMWARE("nouveau/nv43.ctxvals");
41MODULE_FIRMWARE("nouveau/nv44.ctxprog");
42MODULE_FIRMWARE("nouveau/nv44.ctxvals");
43MODULE_FIRMWARE("nouveau/nv46.ctxprog");
44MODULE_FIRMWARE("nouveau/nv46.ctxvals");
45MODULE_FIRMWARE("nouveau/nv47.ctxprog");
46MODULE_FIRMWARE("nouveau/nv47.ctxvals");
47MODULE_FIRMWARE("nouveau/nv49.ctxprog");
48MODULE_FIRMWARE("nouveau/nv49.ctxvals");
49MODULE_FIRMWARE("nouveau/nv4a.ctxprog");
50MODULE_FIRMWARE("nouveau/nv4a.ctxvals");
51MODULE_FIRMWARE("nouveau/nv4b.ctxprog");
52MODULE_FIRMWARE("nouveau/nv4b.ctxvals");
53MODULE_FIRMWARE("nouveau/nv4c.ctxprog");
54MODULE_FIRMWARE("nouveau/nv4c.ctxvals");
55MODULE_FIRMWARE("nouveau/nv4e.ctxprog");
56MODULE_FIRMWARE("nouveau/nv4e.ctxvals");
57 31
58struct nouveau_channel * 32struct nouveau_channel *
59nv40_graph_channel(struct drm_device *dev) 33nv40_graph_channel(struct drm_device *dev)
@@ -83,27 +57,30 @@ nv40_graph_create_context(struct nouveau_channel *chan)
83{ 57{
84 struct drm_device *dev = chan->dev; 58 struct drm_device *dev = chan->dev;
85 struct drm_nouveau_private *dev_priv = dev->dev_private; 59 struct drm_nouveau_private *dev_priv = dev->dev_private;
86 struct nouveau_gpuobj *ctx; 60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
87 int ret; 61 int ret;
88 62
89 /* Allocate a 175KiB block of PRAMIN to store the context. This 63 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
90 * is massive overkill for a lot of chipsets, but it should be safe 64 16, NVOBJ_FLAG_ZERO_ALLOC,
91 * until we're able to implement this properly (will happen at more 65 &chan->ramin_grctx);
92 * or less the same time we're able to write our own context programs.
93 */
94 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 175*1024, 16,
95 NVOBJ_FLAG_ZERO_ALLOC,
96 &chan->ramin_grctx);
97 if (ret) 66 if (ret)
98 return ret; 67 return ret;
99 ctx = chan->ramin_grctx->gpuobj;
100 68
101 /* Initialise default context values */ 69 /* Initialise default context values */
102 dev_priv->engine.instmem.prepare_access(dev, true); 70 dev_priv->engine.instmem.prepare_access(dev, true);
103 nv40_grctx_vals_load(dev, ctx); 71 if (!pgraph->ctxprog) {
104 nv_wo32(dev, ctx, 0, ctx->im_pramin->start); 72 struct nouveau_grctx ctx = {};
105 dev_priv->engine.instmem.finish_access(dev);
106 73
74 ctx.dev = chan->dev;
75 ctx.mode = NOUVEAU_GRCTX_VALS;
76 ctx.data = chan->ramin_grctx->gpuobj;
77 nv40_grctx_init(&ctx);
78 } else {
79 nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
80 }
81 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
82 chan->ramin_grctx->gpuobj->im_pramin->start);
83 dev_priv->engine.instmem.finish_access(dev);
107 return 0; 84 return 0;
108} 85}
109 86
@@ -204,139 +181,6 @@ nv40_graph_unload_context(struct drm_device *dev)
204 return ret; 181 return ret;
205} 182}
206 183
207struct nouveau_ctxprog {
208 uint32_t signature;
209 uint8_t version;
210 uint16_t length;
211 uint32_t data[];
212} __attribute__ ((packed));
213
214struct nouveau_ctxvals {
215 uint32_t signature;
216 uint8_t version;
217 uint32_t length;
218 struct {
219 uint32_t offset;
220 uint32_t value;
221 } data[];
222} __attribute__ ((packed));
223
224int
225nv40_grctx_init(struct drm_device *dev)
226{
227 struct drm_nouveau_private *dev_priv = dev->dev_private;
228 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
229 const int chipset = dev_priv->chipset;
230 const struct firmware *fw;
231 const struct nouveau_ctxprog *cp;
232 const struct nouveau_ctxvals *cv;
233 char name[32];
234 int ret, i;
235
236 pgraph->accel_blocked = true;
237
238 if (!pgraph->ctxprog) {
239 sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
240 ret = request_firmware(&fw, name, &dev->pdev->dev);
241 if (ret) {
242 NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
243 return ret;
244 }
245
246 pgraph->ctxprog = kmalloc(fw->size, GFP_KERNEL);
247 if (!pgraph->ctxprog) {
248 NV_ERROR(dev, "OOM copying ctxprog\n");
249 release_firmware(fw);
250 return -ENOMEM;
251 }
252 memcpy(pgraph->ctxprog, fw->data, fw->size);
253
254 cp = pgraph->ctxprog;
255 if (le32_to_cpu(cp->signature) != 0x5043564e ||
256 cp->version != 0 ||
257 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
258 NV_ERROR(dev, "ctxprog invalid\n");
259 release_firmware(fw);
260 nv40_grctx_fini(dev);
261 return -EINVAL;
262 }
263 release_firmware(fw);
264 }
265
266 if (!pgraph->ctxvals) {
267 sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
268 ret = request_firmware(&fw, name, &dev->pdev->dev);
269 if (ret) {
270 NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
271 nv40_grctx_fini(dev);
272 return ret;
273 }
274
275 pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL);
276 if (!pgraph->ctxprog) {
277 NV_ERROR(dev, "OOM copying ctxprog\n");
278 release_firmware(fw);
279 nv40_grctx_fini(dev);
280 return -ENOMEM;
281 }
282 memcpy(pgraph->ctxvals, fw->data, fw->size);
283
284 cv = (void *)pgraph->ctxvals;
285 if (le32_to_cpu(cv->signature) != 0x5643564e ||
286 cv->version != 0 ||
287 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
288 NV_ERROR(dev, "ctxvals invalid\n");
289 release_firmware(fw);
290 nv40_grctx_fini(dev);
291 return -EINVAL;
292 }
293 release_firmware(fw);
294 }
295
296 cp = pgraph->ctxprog;
297
298 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
299 for (i = 0; i < le16_to_cpu(cp->length); i++)
300 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
301 le32_to_cpu(cp->data[i]));
302
303 pgraph->accel_blocked = false;
304 return 0;
305}
306
307void
308nv40_grctx_fini(struct drm_device *dev)
309{
310 struct drm_nouveau_private *dev_priv = dev->dev_private;
311 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
312
313 if (pgraph->ctxprog) {
314 kfree(pgraph->ctxprog);
315 pgraph->ctxprog = NULL;
316 }
317
318 if (pgraph->ctxvals) {
319 kfree(pgraph->ctxprog);
320 pgraph->ctxvals = NULL;
321 }
322}
323
324void
325nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
326{
327 struct drm_nouveau_private *dev_priv = dev->dev_private;
328 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
329 struct nouveau_ctxvals *cv = pgraph->ctxvals;
330 int i;
331
332 if (!cv)
333 return;
334
335 for (i = 0; i < le32_to_cpu(cv->length); i++)
336 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
337 le32_to_cpu(cv->data[i].value));
338}
339
340/* 184/*
341 * G70 0x47 185 * G70 0x47
342 * G71 0x49 186 * G71 0x49
@@ -359,7 +203,26 @@ nv40_graph_init(struct drm_device *dev)
359 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 203 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
360 NV_PMC_ENABLE_PGRAPH); 204 NV_PMC_ENABLE_PGRAPH);
361 205
362 nv40_grctx_init(dev); 206 if (nouveau_ctxfw) {
207 nouveau_grctx_prog_load(dev);
208 dev_priv->engine.graph.grctx_size = 175 * 1024;
209 }
210
211 if (!dev_priv->engine.graph.ctxprog) {
212 struct nouveau_grctx ctx = {};
213 uint32_t cp[256];
214
215 ctx.dev = dev;
216 ctx.mode = NOUVEAU_GRCTX_PROG;
217 ctx.data = cp;
218 ctx.ctxprog_max = 256;
219 nv40_grctx_init(&ctx);
220 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
221
222 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
223 for (i = 0; i < ctx.ctxprog_len; i++)
224 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
225 }
363 226
364 /* No context present currently */ 227 /* No context present currently */
365 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 228 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -539,6 +402,7 @@ nv40_graph_init(struct drm_device *dev)
539 402
540void nv40_graph_takedown(struct drm_device *dev) 403void nv40_graph_takedown(struct drm_device *dev)
541{ 404{
405 nouveau_grctx_fini(dev);
542} 406}
543 407
544struct nouveau_pgraph_object_class nv40_graph_grclass[] = { 408struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
diff --git a/drivers/gpu/drm/nouveau/nv40_grctx.c b/drivers/gpu/drm/nouveau/nv40_grctx.c
new file mode 100644
index 000000000000..11b11c31f543
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv40_grctx.c
@@ -0,0 +1,678 @@
1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25/* NVIDIA context programs handle a number of other conditions which are
26 * not implemented in our versions. It's not clear why NVIDIA context
27 * programs have this code, nor whether it's strictly necessary for
28 * correct operation. We'll implement additional handling if/when we
29 * discover it's necessary.
30 *
31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
32 * flag is set, this gets saved into the context.
33 * - On context save, the context program for all cards load nsource
34 * into a flag register and check for ILLEGAL_MTHD. If it's set,
35 * opcode 0x60000d is called before resuming normal operation.
36 * - Some context programs check more conditions than the above. NV44
37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
38 * and calls 0x60000d before resuming normal operation.
39 * - At the very beginning of NVIDIA's context programs, flag 9 is checked
40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared
41 * and then the ctxprog is aborted. It looks like a complicated NOP,
42 * its purpose is unknown.
43 * - In the section of code that loads the per-vs state, NVIDIA check
44 * flag 10. If it's set, they only transfer the small 0x300 byte block
45 * of state + the state for a single vs as opposed to the state for
46 * all vs units. It doesn't seem likely that it'll occur in normal
47 * operation, especially seeing as it appears NVIDIA may have screwed
48 * up the ctxprogs for some cards and have an invalid instruction
49 * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction.
50 * - There's a number of places where context offset 0 (where we place
51 * the PRAMIN offset of the context) is loaded into either 0x408000,
52 * 0x408004 or 0x408008. Not sure what's up there either.
53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup
54 * path for auto-loadctx.
55 */
56
57#define CP_FLAG_CLEAR 0
58#define CP_FLAG_SET 1
59#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
60#define CP_FLAG_SWAP_DIRECTION_LOAD 0
61#define CP_FLAG_SWAP_DIRECTION_SAVE 1
62#define CP_FLAG_USER_SAVE ((0 * 32) + 5)
63#define CP_FLAG_USER_SAVE_NOT_PENDING 0
64#define CP_FLAG_USER_SAVE_PENDING 1
65#define CP_FLAG_USER_LOAD ((0 * 32) + 6)
66#define CP_FLAG_USER_LOAD_NOT_PENDING 0
67#define CP_FLAG_USER_LOAD_PENDING 1
68#define CP_FLAG_STATUS ((3 * 32) + 0)
69#define CP_FLAG_STATUS_IDLE 0
70#define CP_FLAG_STATUS_BUSY 1
71#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4)
72#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
73#define CP_FLAG_AUTO_SAVE_PENDING 1
74#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5)
75#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
76#define CP_FLAG_AUTO_LOAD_PENDING 1
77#define CP_FLAG_UNK54 ((3 * 32) + 6)
78#define CP_FLAG_UNK54_CLEAR 0
79#define CP_FLAG_UNK54_SET 1
80#define CP_FLAG_ALWAYS ((3 * 32) + 8)
81#define CP_FLAG_ALWAYS_FALSE 0
82#define CP_FLAG_ALWAYS_TRUE 1
83#define CP_FLAG_UNK57 ((3 * 32) + 9)
84#define CP_FLAG_UNK57_CLEAR 0
85#define CP_FLAG_UNK57_SET 1
86
87#define CP_CTX 0x00100000
88#define CP_CTX_COUNT 0x000fc000
89#define CP_CTX_COUNT_SHIFT 14
90#define CP_CTX_REG 0x00003fff
91#define CP_LOAD_SR 0x00200000
92#define CP_LOAD_SR_VALUE 0x000fffff
93#define CP_BRA 0x00400000
94#define CP_BRA_IP 0x0000ff00
95#define CP_BRA_IP_SHIFT 8
96#define CP_BRA_IF_CLEAR 0x00000080
97#define CP_BRA_FLAG 0x0000007f
98#define CP_WAIT 0x00500000
99#define CP_WAIT_SET 0x00000080
100#define CP_WAIT_FLAG 0x0000007f
101#define CP_SET 0x00700000
102#define CP_SET_1 0x00000080
103#define CP_SET_FLAG 0x0000007f
104#define CP_NEXT_TO_SWAP 0x00600007
105#define CP_NEXT_TO_CURRENT 0x00600009
106#define CP_SET_CONTEXT_POINTER 0x0060000a
107#define CP_END 0x0060000e
108#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */
109#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
110#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
111
112#include "drmP.h"
113#include "nouveau_drv.h"
114#include "nouveau_grctx.h"
115
116/* TODO:
117 * - get vs count from 0x1540
118 * - document unimplemented bits compared to nvidia
119 * - nsource handling
120 * - R0 & 0x0200 handling
121 * - single-vs handling
122 * - 400314 bit 0
123 */
124
125static int
126nv40_graph_4097(struct drm_device *dev)
127{
128 struct drm_nouveau_private *dev_priv = dev->dev_private;
129
130 if ((dev_priv->chipset & 0xf0) == 0x60)
131 return 0;
132
133 return !!(0x0baf & (1 << dev_priv->chipset));
134}
135
136static int
137nv40_graph_vs_count(struct drm_device *dev)
138{
139 struct drm_nouveau_private *dev_priv = dev->dev_private;
140
141 switch (dev_priv->chipset) {
142 case 0x47:
143 case 0x49:
144 case 0x4b:
145 return 8;
146 case 0x40:
147 return 6;
148 case 0x41:
149 case 0x42:
150 return 5;
151 case 0x43:
152 case 0x44:
153 case 0x46:
154 case 0x4a:
155 return 3;
156 case 0x4c:
157 case 0x4e:
158 case 0x67:
159 default:
160 return 1;
161 }
162}
163
164
165enum cp_label {
166 cp_check_load = 1,
167 cp_setup_auto_load,
168 cp_setup_load,
169 cp_setup_save,
170 cp_swap_state,
171 cp_swap_state3d_3_is_save,
172 cp_prepare_exit,
173 cp_exit,
174};
175
176static void
177nv40_graph_construct_general(struct nouveau_grctx *ctx)
178{
179 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
180 int i;
181
182 cp_ctx(ctx, 0x4000a4, 1);
183 gr_def(ctx, 0x4000a4, 0x00000008);
184 cp_ctx(ctx, 0x400144, 58);
185 gr_def(ctx, 0x400144, 0x00000001);
186 cp_ctx(ctx, 0x400314, 1);
187 gr_def(ctx, 0x400314, 0x00000000);
188 cp_ctx(ctx, 0x400400, 10);
189 cp_ctx(ctx, 0x400480, 10);
190 cp_ctx(ctx, 0x400500, 19);
191 gr_def(ctx, 0x400514, 0x00040000);
192 gr_def(ctx, 0x400524, 0x55555555);
193 gr_def(ctx, 0x400528, 0x55555555);
194 gr_def(ctx, 0x40052c, 0x55555555);
195 gr_def(ctx, 0x400530, 0x55555555);
196 cp_ctx(ctx, 0x400560, 6);
197 gr_def(ctx, 0x400568, 0x0000ffff);
198 gr_def(ctx, 0x40056c, 0x0000ffff);
199 cp_ctx(ctx, 0x40057c, 5);
200 cp_ctx(ctx, 0x400710, 3);
201 gr_def(ctx, 0x400710, 0x20010001);
202 gr_def(ctx, 0x400714, 0x0f73ef00);
203 cp_ctx(ctx, 0x400724, 1);
204 gr_def(ctx, 0x400724, 0x02008821);
205 cp_ctx(ctx, 0x400770, 3);
206 if (dev_priv->chipset == 0x40) {
207 cp_ctx(ctx, 0x400814, 4);
208 cp_ctx(ctx, 0x400828, 5);
209 cp_ctx(ctx, 0x400840, 5);
210 gr_def(ctx, 0x400850, 0x00000040);
211 cp_ctx(ctx, 0x400858, 4);
212 gr_def(ctx, 0x400858, 0x00000040);
213 gr_def(ctx, 0x40085c, 0x00000040);
214 gr_def(ctx, 0x400864, 0x80000000);
215 cp_ctx(ctx, 0x40086c, 9);
216 gr_def(ctx, 0x40086c, 0x80000000);
217 gr_def(ctx, 0x400870, 0x80000000);
218 gr_def(ctx, 0x400874, 0x80000000);
219 gr_def(ctx, 0x400878, 0x80000000);
220 gr_def(ctx, 0x400888, 0x00000040);
221 gr_def(ctx, 0x40088c, 0x80000000);
222 cp_ctx(ctx, 0x4009c0, 8);
223 gr_def(ctx, 0x4009cc, 0x80000000);
224 gr_def(ctx, 0x4009dc, 0x80000000);
225 } else {
226 cp_ctx(ctx, 0x400840, 20);
227 if (!nv40_graph_4097(ctx->dev)) {
228 for (i = 0; i < 8; i++)
229 gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
230 }
231 gr_def(ctx, 0x400880, 0x00000040);
232 gr_def(ctx, 0x400884, 0x00000040);
233 gr_def(ctx, 0x400888, 0x00000040);
234 cp_ctx(ctx, 0x400894, 11);
235 gr_def(ctx, 0x400894, 0x00000040);
236 if (nv40_graph_4097(ctx->dev)) {
237 for (i = 0; i < 8; i++)
238 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
239 }
240 cp_ctx(ctx, 0x4008e0, 2);
241 cp_ctx(ctx, 0x4008f8, 2);
242 if (dev_priv->chipset == 0x4c ||
243 (dev_priv->chipset & 0xf0) == 0x60)
244 cp_ctx(ctx, 0x4009f8, 1);
245 }
246 cp_ctx(ctx, 0x400a00, 73);
247 gr_def(ctx, 0x400b0c, 0x0b0b0b0c);
248 cp_ctx(ctx, 0x401000, 4);
249 cp_ctx(ctx, 0x405004, 1);
250 switch (dev_priv->chipset) {
251 case 0x47:
252 case 0x49:
253 case 0x4b:
254 cp_ctx(ctx, 0x403448, 1);
255 gr_def(ctx, 0x403448, 0x00001010);
256 break;
257 default:
258 cp_ctx(ctx, 0x403440, 1);
259 switch (dev_priv->chipset) {
260 case 0x40:
261 gr_def(ctx, 0x403440, 0x00000010);
262 break;
263 case 0x44:
264 case 0x46:
265 case 0x4a:
266 gr_def(ctx, 0x403440, 0x00003010);
267 break;
268 case 0x41:
269 case 0x42:
270 case 0x43:
271 case 0x4c:
272 case 0x4e:
273 case 0x67:
274 default:
275 gr_def(ctx, 0x403440, 0x00001010);
276 break;
277 }
278 break;
279 }
280}
281
282static void
283nv40_graph_construct_state3d(struct nouveau_grctx *ctx)
284{
285 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
286 int i;
287
288 if (dev_priv->chipset == 0x40) {
289 cp_ctx(ctx, 0x401880, 51);
290 gr_def(ctx, 0x401940, 0x00000100);
291 } else
292 if (dev_priv->chipset == 0x46 || dev_priv->chipset == 0x47 ||
293 dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) {
294 cp_ctx(ctx, 0x401880, 32);
295 for (i = 0; i < 16; i++)
296 gr_def(ctx, 0x401880 + (i * 4), 0x00000111);
297 if (dev_priv->chipset == 0x46)
298 cp_ctx(ctx, 0x401900, 16);
299 cp_ctx(ctx, 0x401940, 3);
300 }
301 cp_ctx(ctx, 0x40194c, 18);
302 gr_def(ctx, 0x401954, 0x00000111);
303 gr_def(ctx, 0x401958, 0x00080060);
304 gr_def(ctx, 0x401974, 0x00000080);
305 gr_def(ctx, 0x401978, 0xffff0000);
306 gr_def(ctx, 0x40197c, 0x00000001);
307 gr_def(ctx, 0x401990, 0x46400000);
308 if (dev_priv->chipset == 0x40) {
309 cp_ctx(ctx, 0x4019a0, 2);
310 cp_ctx(ctx, 0x4019ac, 5);
311 } else {
312 cp_ctx(ctx, 0x4019a0, 1);
313 cp_ctx(ctx, 0x4019b4, 3);
314 }
315 gr_def(ctx, 0x4019bc, 0xffff0000);
316 switch (dev_priv->chipset) {
317 case 0x46:
318 case 0x47:
319 case 0x49:
320 case 0x4b:
321 cp_ctx(ctx, 0x4019c0, 18);
322 for (i = 0; i < 16; i++)
323 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888);
324 break;
325 }
326 cp_ctx(ctx, 0x401a08, 8);
327 gr_def(ctx, 0x401a10, 0x0fff0000);
328 gr_def(ctx, 0x401a14, 0x0fff0000);
329 gr_def(ctx, 0x401a1c, 0x00011100);
330 cp_ctx(ctx, 0x401a2c, 4);
331 cp_ctx(ctx, 0x401a44, 26);
332 for (i = 0; i < 16; i++)
333 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000);
334 gr_def(ctx, 0x401a8c, 0x4b7fffff);
335 if (dev_priv->chipset == 0x40) {
336 cp_ctx(ctx, 0x401ab8, 3);
337 } else {
338 cp_ctx(ctx, 0x401ab8, 1);
339 cp_ctx(ctx, 0x401ac0, 1);
340 }
341 cp_ctx(ctx, 0x401ad0, 8);
342 gr_def(ctx, 0x401ad0, 0x30201000);
343 gr_def(ctx, 0x401ad4, 0x70605040);
344 gr_def(ctx, 0x401ad8, 0xb8a89888);
345 gr_def(ctx, 0x401adc, 0xf8e8d8c8);
346 cp_ctx(ctx, 0x401b10, dev_priv->chipset == 0x40 ? 2 : 1);
347 gr_def(ctx, 0x401b10, 0x40100000);
348 cp_ctx(ctx, 0x401b18, dev_priv->chipset == 0x40 ? 6 : 5);
349 gr_def(ctx, 0x401b28, dev_priv->chipset == 0x40 ?
350 0x00000004 : 0x00000000);
351 cp_ctx(ctx, 0x401b30, 25);
352 gr_def(ctx, 0x401b34, 0x0000ffff);
353 gr_def(ctx, 0x401b68, 0x435185d6);
354 gr_def(ctx, 0x401b6c, 0x2155b699);
355 gr_def(ctx, 0x401b70, 0xfedcba98);
356 gr_def(ctx, 0x401b74, 0x00000098);
357 gr_def(ctx, 0x401b84, 0xffffffff);
358 gr_def(ctx, 0x401b88, 0x00ff7000);
359 gr_def(ctx, 0x401b8c, 0x0000ffff);
360 if (dev_priv->chipset != 0x44 && dev_priv->chipset != 0x4a &&
361 dev_priv->chipset != 0x4e)
362 cp_ctx(ctx, 0x401b94, 1);
363 cp_ctx(ctx, 0x401b98, 8);
364 gr_def(ctx, 0x401b9c, 0x00ff0000);
365 cp_ctx(ctx, 0x401bc0, 9);
366 gr_def(ctx, 0x401be0, 0x00ffff00);
367 cp_ctx(ctx, 0x401c00, 192);
368 for (i = 0; i < 16; i++) { /* fragment texture units */
369 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488);
370 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202);
371 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4);
372 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000);
373 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008);
374 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008);
375 }
376 for (i = 0; i < 4; i++) { /* vertex texture units */
377 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80);
378 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202);
379 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008);
380 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008);
381 }
382 cp_ctx(ctx, 0x400f5c, 3);
383 gr_def(ctx, 0x400f5c, 0x00000002);
384 cp_ctx(ctx, 0x400f84, 1);
385}
386
387static void
388nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
389{
390 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
391 int i;
392
393 cp_ctx(ctx, 0x402000, 1);
394 cp_ctx(ctx, 0x402404, dev_priv->chipset == 0x40 ? 1 : 2);
395 switch (dev_priv->chipset) {
396 case 0x40:
397 gr_def(ctx, 0x402404, 0x00000001);
398 break;
399 case 0x4c:
400 case 0x4e:
401 case 0x67:
402 gr_def(ctx, 0x402404, 0x00000020);
403 break;
404 case 0x46:
405 case 0x49:
406 case 0x4b:
407 gr_def(ctx, 0x402404, 0x00000421);
408 break;
409 default:
410 gr_def(ctx, 0x402404, 0x00000021);
411 }
412 if (dev_priv->chipset != 0x40)
413 gr_def(ctx, 0x402408, 0x030c30c3);
414 switch (dev_priv->chipset) {
415 case 0x44:
416 case 0x46:
417 case 0x4a:
418 case 0x4c:
419 case 0x4e:
420 case 0x67:
421 cp_ctx(ctx, 0x402440, 1);
422 gr_def(ctx, 0x402440, 0x00011001);
423 break;
424 default:
425 break;
426 }
427 cp_ctx(ctx, 0x402480, dev_priv->chipset == 0x40 ? 8 : 9);
428 gr_def(ctx, 0x402488, 0x3e020200);
429 gr_def(ctx, 0x40248c, 0x00ffffff);
430 switch (dev_priv->chipset) {
431 case 0x40:
432 gr_def(ctx, 0x402490, 0x60103f00);
433 break;
434 case 0x47:
435 gr_def(ctx, 0x402490, 0x40103f00);
436 break;
437 case 0x41:
438 case 0x42:
439 case 0x49:
440 case 0x4b:
441 gr_def(ctx, 0x402490, 0x20103f00);
442 break;
443 default:
444 gr_def(ctx, 0x402490, 0x0c103f00);
445 break;
446 }
447 gr_def(ctx, 0x40249c, dev_priv->chipset <= 0x43 ?
448 0x00020000 : 0x00040000);
449 cp_ctx(ctx, 0x402500, 31);
450 gr_def(ctx, 0x402530, 0x00008100);
451 if (dev_priv->chipset == 0x40)
452 cp_ctx(ctx, 0x40257c, 6);
453 cp_ctx(ctx, 0x402594, 16);
454 cp_ctx(ctx, 0x402800, 17);
455 gr_def(ctx, 0x402800, 0x00000001);
456 switch (dev_priv->chipset) {
457 case 0x47:
458 case 0x49:
459 case 0x4b:
460 cp_ctx(ctx, 0x402864, 1);
461 gr_def(ctx, 0x402864, 0x00001001);
462 cp_ctx(ctx, 0x402870, 3);
463 gr_def(ctx, 0x402878, 0x00000003);
464 if (dev_priv->chipset != 0x47) { /* belong at end!! */
465 cp_ctx(ctx, 0x402900, 1);
466 cp_ctx(ctx, 0x402940, 1);
467 cp_ctx(ctx, 0x402980, 1);
468 cp_ctx(ctx, 0x4029c0, 1);
469 cp_ctx(ctx, 0x402a00, 1);
470 cp_ctx(ctx, 0x402a40, 1);
471 cp_ctx(ctx, 0x402a80, 1);
472 cp_ctx(ctx, 0x402ac0, 1);
473 }
474 break;
475 case 0x40:
476 cp_ctx(ctx, 0x402844, 1);
477 gr_def(ctx, 0x402844, 0x00000001);
478 cp_ctx(ctx, 0x402850, 1);
479 break;
480 default:
481 cp_ctx(ctx, 0x402844, 1);
482 gr_def(ctx, 0x402844, 0x00001001);
483 cp_ctx(ctx, 0x402850, 2);
484 gr_def(ctx, 0x402854, 0x00000003);
485 break;
486 }
487
488 cp_ctx(ctx, 0x402c00, 4);
489 gr_def(ctx, 0x402c00, dev_priv->chipset == 0x40 ?
490 0x80800001 : 0x00888001);
491 switch (dev_priv->chipset) {
492 case 0x47:
493 case 0x49:
494 case 0x4b:
495 cp_ctx(ctx, 0x402c20, 40);
496 for (i = 0; i < 32; i++)
497 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff);
498 cp_ctx(ctx, 0x4030b8, 13);
499 gr_def(ctx, 0x4030dc, 0x00000005);
500 gr_def(ctx, 0x4030e8, 0x0000ffff);
501 break;
502 default:
503 cp_ctx(ctx, 0x402c10, 4);
504 if (dev_priv->chipset == 0x40)
505 cp_ctx(ctx, 0x402c20, 36);
506 else
507 if (dev_priv->chipset <= 0x42)
508 cp_ctx(ctx, 0x402c20, 24);
509 else
510 if (dev_priv->chipset <= 0x4a)
511 cp_ctx(ctx, 0x402c20, 16);
512 else
513 cp_ctx(ctx, 0x402c20, 8);
514 cp_ctx(ctx, 0x402cb0, dev_priv->chipset == 0x40 ? 12 : 13);
515 gr_def(ctx, 0x402cd4, 0x00000005);
516 if (dev_priv->chipset != 0x40)
517 gr_def(ctx, 0x402ce0, 0x0000ffff);
518 break;
519 }
520
521 cp_ctx(ctx, 0x403400, dev_priv->chipset == 0x40 ? 4 : 3);
522 cp_ctx(ctx, 0x403410, dev_priv->chipset == 0x40 ? 4 : 3);
523 cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->dev));
524 for (i = 0; i < nv40_graph_vs_count(ctx->dev); i++)
525 gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
526
527 if (dev_priv->chipset != 0x40) {
528 cp_ctx(ctx, 0x403600, 1);
529 gr_def(ctx, 0x403600, 0x00000001);
530 }
531 cp_ctx(ctx, 0x403800, 1);
532
533 cp_ctx(ctx, 0x403c18, 1);
534 gr_def(ctx, 0x403c18, 0x00000001);
535 switch (dev_priv->chipset) {
536 case 0x46:
537 case 0x47:
538 case 0x49:
539 case 0x4b:
540 cp_ctx(ctx, 0x405018, 1);
541 gr_def(ctx, 0x405018, 0x08e00001);
542 cp_ctx(ctx, 0x405c24, 1);
543 gr_def(ctx, 0x405c24, 0x000e3000);
544 break;
545 }
546 if (dev_priv->chipset != 0x4e)
547 cp_ctx(ctx, 0x405800, 11);
548 cp_ctx(ctx, 0x407000, 1);
549}
550
551static void
552nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
553{
554 int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084;
555
556 cp_out (ctx, 0x300000);
557 cp_lsr (ctx, len - 4);
558 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save);
559 cp_lsr (ctx, len);
560 cp_name(ctx, cp_swap_state3d_3_is_save);
561 cp_out (ctx, 0x800001);
562
563 ctx->ctxvals_pos += len;
564}
565
566static void
567nv40_graph_construct_shader(struct nouveau_grctx *ctx)
568{
569 struct drm_device *dev = ctx->dev;
570 struct drm_nouveau_private *dev_priv = dev->dev_private;
571 struct nouveau_gpuobj *obj = ctx->data;
572 int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
573 int offset, i;
574
575 vs_nr = nv40_graph_vs_count(ctx->dev);
576 vs_nr_b0 = 363;
577 vs_nr_b1 = dev_priv->chipset == 0x40 ? 128 : 64;
578 if (dev_priv->chipset == 0x40) {
579 b0_offset = 0x2200/4; /* 33a0 */
580 b1_offset = 0x55a0/4; /* 1500 */
581 vs_len = 0x6aa0/4;
582 } else
583 if (dev_priv->chipset == 0x41 || dev_priv->chipset == 0x42) {
584 b0_offset = 0x2200/4; /* 2200 */
585 b1_offset = 0x4400/4; /* 0b00 */
586 vs_len = 0x4f00/4;
587 } else {
588 b0_offset = 0x1d40/4; /* 2200 */
589 b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
590 vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4;
591 }
592
593 cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
594 cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029);
595
596 offset = ctx->ctxvals_pos;
597 ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
598
599 if (ctx->mode != NOUVEAU_GRCTX_VALS)
600 return;
601
602 offset += 0x0280/4;
603 for (i = 0; i < 16; i++, offset += 2)
604 nv_wo32(dev, obj, offset, 0x3f800000);
605
606 for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {
607 for (i = 0; i < vs_nr_b0 * 6; i += 6)
608 nv_wo32(dev, obj, offset + b0_offset + i, 0x00000001);
609 for (i = 0; i < vs_nr_b1 * 4; i += 4)
610 nv_wo32(dev, obj, offset + b1_offset + i, 0x3f800000);
611 }
612}
613
614void
615nv40_grctx_init(struct nouveau_grctx *ctx)
616{
617 /* decide whether we're loading/unloading the context */
618 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
619 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
620
621 cp_name(ctx, cp_check_load);
622 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
623 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
624 cp_bra (ctx, ALWAYS, TRUE, cp_exit);
625
626 /* setup for context load */
627 cp_name(ctx, cp_setup_auto_load);
628 cp_wait(ctx, STATUS, IDLE);
629 cp_out (ctx, CP_NEXT_TO_SWAP);
630 cp_name(ctx, cp_setup_load);
631 cp_wait(ctx, STATUS, IDLE);
632 cp_set (ctx, SWAP_DIRECTION, LOAD);
633 cp_out (ctx, 0x00910880); /* ?? */
634 cp_out (ctx, 0x00901ffe); /* ?? */
635 cp_out (ctx, 0x01940000); /* ?? */
636 cp_lsr (ctx, 0x20);
637 cp_out (ctx, 0x0060000b); /* ?? */
638 cp_wait(ctx, UNK57, CLEAR);
639 cp_out (ctx, 0x0060000c); /* ?? */
640 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
641
642 /* setup for context save */
643 cp_name(ctx, cp_setup_save);
644 cp_set (ctx, SWAP_DIRECTION, SAVE);
645
646 /* general PGRAPH state */
647 cp_name(ctx, cp_swap_state);
648 cp_pos (ctx, 0x00020/4);
649 nv40_graph_construct_general(ctx);
650 cp_wait(ctx, STATUS, IDLE);
651
652 /* 3D state, block 1 */
653 cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
654 nv40_graph_construct_state3d(ctx);
655 cp_wait(ctx, STATUS, IDLE);
656
657 /* 3D state, block 2 */
658 nv40_graph_construct_state3d_2(ctx);
659
660 /* Some other block of "random" state */
661 nv40_graph_construct_state3d_3(ctx);
662
663 /* Per-vertex shader state */
664 cp_pos (ctx, ctx->ctxvals_pos);
665 nv40_graph_construct_shader(ctx);
666
667 /* pre-exit state updates */
668 cp_name(ctx, cp_prepare_exit);
669 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
670 cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
671 cp_out (ctx, CP_NEXT_TO_CURRENT);
672
673 cp_name(ctx, cp_exit);
674 cp_set (ctx, USER_SAVE, NOT_PENDING);
675 cp_set (ctx, USER_LOAD, NOT_PENDING);
676 cp_out (ctx, CP_END);
677}
678
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index f8e28a1e44e7..118d3285fd8c 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -45,7 +45,7 @@ nv50_crtc_lut_load(struct drm_crtc *crtc)
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); 45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
46 int i; 46 int i;
47 47
48 NV_DEBUG(crtc->dev, "\n"); 48 NV_DEBUG_KMS(crtc->dev, "\n");
49 49
50 for (i = 0; i < 256; i++) { 50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); 51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
@@ -68,8 +68,8 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
68 struct nouveau_channel *evo = dev_priv->evo; 68 struct nouveau_channel *evo = dev_priv->evo;
69 int index = nv_crtc->index, ret; 69 int index = nv_crtc->index, ret;
70 70
71 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG(dev, "%s\n", blanked ? "blanked" : "unblanked"); 72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
73 73
74 if (blanked) { 74 if (blanked) {
75 nv_crtc->cursor.hide(nv_crtc, false); 75 nv_crtc->cursor.hide(nv_crtc, false);
@@ -139,7 +139,7 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
139 struct nouveau_channel *evo = dev_priv->evo; 139 struct nouveau_channel *evo = dev_priv->evo;
140 int ret; 140 int ret;
141 141
142 NV_DEBUG(dev, "\n"); 142 NV_DEBUG_KMS(dev, "\n");
143 143
144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); 144 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
145 if (ret) { 145 if (ret) {
@@ -193,7 +193,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
193 uint32_t outX, outY, horiz, vert; 193 uint32_t outX, outY, horiz, vert;
194 int ret; 194 int ret;
195 195
196 NV_DEBUG(dev, "\n"); 196 NV_DEBUG_KMS(dev, "\n");
197 197
198 switch (scaling_mode) { 198 switch (scaling_mode) {
199 case DRM_MODE_SCALE_NONE: 199 case DRM_MODE_SCALE_NONE:
@@ -301,7 +301,7 @@ nv50_crtc_destroy(struct drm_crtc *crtc)
301 struct drm_device *dev = crtc->dev; 301 struct drm_device *dev = crtc->dev;
302 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 302 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
303 303
304 NV_DEBUG(dev, "\n"); 304 NV_DEBUG_KMS(dev, "\n");
305 305
306 if (!crtc) 306 if (!crtc)
307 return; 307 return;
@@ -433,7 +433,7 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
433 struct drm_device *dev = crtc->dev; 433 struct drm_device *dev = crtc->dev;
434 struct drm_encoder *encoder; 434 struct drm_encoder *encoder;
435 435
436 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 436 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
437 437
438 /* Disconnect all unused encoders. */ 438 /* Disconnect all unused encoders. */
439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
@@ -458,7 +458,7 @@ nv50_crtc_commit(struct drm_crtc *crtc)
458 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 458 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
459 int ret; 459 int ret;
460 460
461 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 461 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
462 462
463 nv50_crtc_blank(nv_crtc, false); 463 nv50_crtc_blank(nv_crtc, false);
464 464
@@ -497,7 +497,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
497 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); 497 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
498 int ret, format; 498 int ret, format;
499 499
500 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 500 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
501 501
502 switch (drm_fb->depth) { 502 switch (drm_fb->depth) {
503 case 8: 503 case 8:
@@ -612,7 +612,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
612 612
613 *nv_crtc->mode = *adjusted_mode; 613 *nv_crtc->mode = *adjusted_mode;
614 614
615 NV_DEBUG(dev, "index %d\n", nv_crtc->index); 615 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
616 616
617 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 617 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
618 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 618 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
@@ -706,7 +706,7 @@ nv50_crtc_create(struct drm_device *dev, int index)
706 struct nouveau_crtc *nv_crtc = NULL; 706 struct nouveau_crtc *nv_crtc = NULL;
707 int ret, i; 707 int ret, i;
708 708
709 NV_DEBUG(dev, "\n"); 709 NV_DEBUG_KMS(dev, "\n");
710 710
711 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 711 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
712 if (!nv_crtc) 712 if (!nv_crtc)
diff --git a/drivers/gpu/drm/nouveau/nv50_cursor.c b/drivers/gpu/drm/nouveau/nv50_cursor.c
index e2e79a8f220d..753e723adb3a 100644
--- a/drivers/gpu/drm/nouveau/nv50_cursor.c
+++ b/drivers/gpu/drm/nouveau/nv50_cursor.c
@@ -41,7 +41,7 @@ nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
41 struct drm_device *dev = nv_crtc->base.dev; 41 struct drm_device *dev = nv_crtc->base.dev;
42 int ret; 42 int ret;
43 43
44 NV_DEBUG(dev, "\n"); 44 NV_DEBUG_KMS(dev, "\n");
45 45
46 if (update && nv_crtc->cursor.visible) 46 if (update && nv_crtc->cursor.visible)
47 return; 47 return;
@@ -76,7 +76,7 @@ nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
76 struct drm_device *dev = nv_crtc->base.dev; 76 struct drm_device *dev = nv_crtc->base.dev;
77 int ret; 77 int ret;
78 78
79 NV_DEBUG(dev, "\n"); 79 NV_DEBUG_KMS(dev, "\n");
80 80
81 if (update && !nv_crtc->cursor.visible) 81 if (update && !nv_crtc->cursor.visible)
82 return; 82 return;
@@ -116,7 +116,7 @@ nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
116static void 116static void
117nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 117nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
118{ 118{
119 NV_DEBUG(nv_crtc->base.dev, "\n"); 119 NV_DEBUG_KMS(nv_crtc->base.dev, "\n");
120 if (offset == nv_crtc->cursor.offset) 120 if (offset == nv_crtc->cursor.offset)
121 return; 121 return;
122 122
@@ -143,7 +143,7 @@ nv50_cursor_fini(struct nouveau_crtc *nv_crtc)
143 struct drm_device *dev = nv_crtc->base.dev; 143 struct drm_device *dev = nv_crtc->base.dev;
144 int idx = nv_crtc->index; 144 int idx = nv_crtc->index;
145 145
146 NV_DEBUG(dev, "\n"); 146 NV_DEBUG_KMS(dev, "\n");
147 147
148 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 0); 148 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 0);
149 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx), 149 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(idx),
diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c
index fb5838e3be24..f08f042a8e10 100644
--- a/drivers/gpu/drm/nouveau/nv50_dac.c
+++ b/drivers/gpu/drm/nouveau/nv50_dac.c
@@ -44,7 +44,7 @@ nv50_dac_disconnect(struct nouveau_encoder *nv_encoder)
44 struct nouveau_channel *evo = dev_priv->evo; 44 struct nouveau_channel *evo = dev_priv->evo;
45 int ret; 45 int ret;
46 46
47 NV_DEBUG(dev, "Disconnecting DAC %d\n", nv_encoder->or); 47 NV_DEBUG_KMS(dev, "Disconnecting DAC %d\n", nv_encoder->or);
48 48
49 ret = RING_SPACE(evo, 2); 49 ret = RING_SPACE(evo, 2);
50 if (ret) { 50 if (ret) {
@@ -81,11 +81,11 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
81 /* Use bios provided value if possible. */ 81 /* Use bios provided value if possible. */
82 if (dev_priv->vbios->dactestval) { 82 if (dev_priv->vbios->dactestval) {
83 load_pattern = dev_priv->vbios->dactestval; 83 load_pattern = dev_priv->vbios->dactestval;
84 NV_DEBUG(dev, "Using bios provided load_pattern of %d\n", 84 NV_DEBUG_KMS(dev, "Using bios provided load_pattern of %d\n",
85 load_pattern); 85 load_pattern);
86 } else { 86 } else {
87 load_pattern = 340; 87 load_pattern = 340;
88 NV_DEBUG(dev, "Using default load_pattern of %d\n", 88 NV_DEBUG_KMS(dev, "Using default load_pattern of %d\n",
89 load_pattern); 89 load_pattern);
90 } 90 }
91 91
@@ -103,9 +103,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
103 status = connector_status_connected; 103 status = connector_status_connected;
104 104
105 if (status == connector_status_connected) 105 if (status == connector_status_connected)
106 NV_DEBUG(dev, "Load was detected on output with or %d\n", or); 106 NV_DEBUG_KMS(dev, "Load was detected on output with or %d\n", or);
107 else 107 else
108 NV_DEBUG(dev, "Load was not detected on output with or %d\n", or); 108 NV_DEBUG_KMS(dev, "Load was not detected on output with or %d\n", or);
109 109
110 return status; 110 return status;
111} 111}
@@ -118,7 +118,7 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode)
118 uint32_t val; 118 uint32_t val;
119 int or = nv_encoder->or; 119 int or = nv_encoder->or;
120 120
121 NV_DEBUG(dev, "or %d mode %d\n", or, mode); 121 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
122 122
123 /* wait for it to be done */ 123 /* wait for it to be done */
124 if (!nv_wait(NV50_PDISPLAY_DAC_DPMS_CTRL(or), 124 if (!nv_wait(NV50_PDISPLAY_DAC_DPMS_CTRL(or),
@@ -173,7 +173,7 @@ nv50_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
173 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 173 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
174 struct nouveau_connector *connector; 174 struct nouveau_connector *connector;
175 175
176 NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or); 176 NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
177 177
178 connector = nouveau_encoder_connector_get(nv_encoder); 178 connector = nouveau_encoder_connector_get(nv_encoder);
179 if (!connector) { 179 if (!connector) {
@@ -213,7 +213,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
213 uint32_t mode_ctl = 0, mode_ctl2 = 0; 213 uint32_t mode_ctl = 0, mode_ctl2 = 0;
214 int ret; 214 int ret;
215 215
216 NV_DEBUG(dev, "or %d\n", nv_encoder->or); 216 NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or);
217 217
218 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); 218 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
219 219
@@ -264,7 +264,7 @@ nv50_dac_destroy(struct drm_encoder *encoder)
264 if (!encoder) 264 if (!encoder)
265 return; 265 return;
266 266
267 NV_DEBUG(encoder->dev, "\n"); 267 NV_DEBUG_KMS(encoder->dev, "\n");
268 268
269 drm_encoder_cleanup(encoder); 269 drm_encoder_cleanup(encoder);
270 kfree(nv_encoder); 270 kfree(nv_encoder);
@@ -280,7 +280,7 @@ nv50_dac_create(struct drm_device *dev, struct dcb_entry *entry)
280 struct nouveau_encoder *nv_encoder; 280 struct nouveau_encoder *nv_encoder;
281 struct drm_encoder *encoder; 281 struct drm_encoder *encoder;
282 282
283 NV_DEBUG(dev, "\n"); 283 NV_DEBUG_KMS(dev, "\n");
284 NV_INFO(dev, "Detected a DAC output\n"); 284 NV_INFO(dev, "Detected a DAC output\n");
285 285
286 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 286 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 12c5ee63495b..a9263d92a231 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -188,7 +188,7 @@ nv50_display_init(struct drm_device *dev)
188 uint64_t start; 188 uint64_t start;
189 int ret, i; 189 int ret, i;
190 190
191 NV_DEBUG(dev, "\n"); 191 NV_DEBUG_KMS(dev, "\n");
192 192
193 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 193 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
194 /* 194 /*
@@ -232,7 +232,7 @@ nv50_display_init(struct drm_device *dev)
232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); 232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233 /* RAM is clamped to 256 MiB. */ 233 /* RAM is clamped to 256 MiB. */
234 ram_amount = nouveau_mem_fb_amount(dev); 234 ram_amount = nouveau_mem_fb_amount(dev);
235 NV_DEBUG(dev, "ram_amount %d\n", ram_amount); 235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236 if (ram_amount > 256*1024*1024) 236 if (ram_amount > 256*1024*1024)
237 ram_amount = 256*1024*1024; 237 ram_amount = 256*1024*1024;
238 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); 238 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
@@ -398,7 +398,7 @@ static int nv50_display_disable(struct drm_device *dev)
398 struct drm_crtc *drm_crtc; 398 struct drm_crtc *drm_crtc;
399 int ret, i; 399 int ret, i;
400 400
401 NV_DEBUG(dev, "\n"); 401 NV_DEBUG_KMS(dev, "\n");
402 402
403 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 403 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
404 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 404 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
@@ -469,7 +469,7 @@ int nv50_display_create(struct drm_device *dev)
469 uint32_t connector[16] = {}; 469 uint32_t connector[16] = {};
470 int ret, i; 470 int ret, i;
471 471
472 NV_DEBUG(dev, "\n"); 472 NV_DEBUG_KMS(dev, "\n");
473 473
474 /* init basic kernel modesetting */ 474 /* init basic kernel modesetting */
475 drm_mode_config_init(dev); 475 drm_mode_config_init(dev);
@@ -573,7 +573,7 @@ int nv50_display_destroy(struct drm_device *dev)
573{ 573{
574 struct drm_nouveau_private *dev_priv = dev->dev_private; 574 struct drm_nouveau_private *dev_priv = dev->dev_private;
575 575
576 NV_DEBUG(dev, "\n"); 576 NV_DEBUG_KMS(dev, "\n");
577 577
578 drm_mode_config_cleanup(dev); 578 drm_mode_config_cleanup(dev);
579 579
@@ -617,7 +617,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead,
617 * CRTC separately, and submission will be blocked by the GPU 617 * CRTC separately, and submission will be blocked by the GPU
618 * until we handle each in turn. 618 * until we handle each in turn.
619 */ 619 */
620 NV_DEBUG(dev, "0x610030: 0x%08x\n", unk30); 620 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
621 head = ffs((unk30 >> 9) & 3) - 1; 621 head = ffs((unk30 >> 9) & 3) - 1;
622 if (head < 0) 622 if (head < 0)
623 return -EINVAL; 623 return -EINVAL;
@@ -661,7 +661,7 @@ nv50_display_irq_head(struct drm_device *dev, int *phead,
661 or = i; 661 or = i;
662 } 662 }
663 663
664 NV_DEBUG(dev, "type %d, or %d\n", type, or); 664 NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
665 if (type == OUTPUT_ANY) { 665 if (type == OUTPUT_ANY) {
666 NV_ERROR(dev, "unknown encoder!!\n"); 666 NV_ERROR(dev, "unknown encoder!!\n");
667 return -1; 667 return -1;
@@ -811,7 +811,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
811 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff; 811 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
812 script = nv50_display_script_select(dev, dcbent, pclk); 812 script = nv50_display_script_select(dev, dcbent, pclk);
813 813
814 NV_DEBUG(dev, "head %d pxclk: %dKHz\n", head, pclk); 814 NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
815 815
816 if (dcbent->type != OUTPUT_DP) 816 if (dcbent->type != OUTPUT_DP)
817 nouveau_bios_run_display_table(dev, dcbent, 0, -2); 817 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
@@ -870,7 +870,7 @@ nv50_display_irq_handler_bh(struct work_struct *work)
870 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 870 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
871 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 871 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
872 872
873 NV_DEBUG(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 873 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
874 874
875 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 875 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
876 nv50_display_unk10_handler(dev); 876 nv50_display_unk10_handler(dev);
@@ -974,7 +974,7 @@ nv50_display_irq_handler(struct drm_device *dev)
974 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 974 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
975 uint32_t clock; 975 uint32_t clock;
976 976
977 NV_DEBUG(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 977 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
978 978
979 if (!intr0 && !(intr1 & ~delayed)) 979 if (!intr0 && !(intr1 & ~delayed))
980 break; 980 break;
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 77ae1aaa0bce..b7282284f080 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -416,7 +416,7 @@ nv50_fifo_unload_context(struct drm_device *dev)
416 NV_DEBUG(dev, "\n"); 416 NV_DEBUG(dev, "\n");
417 417
418 chid = pfifo->channel_id(dev); 418 chid = pfifo->channel_id(dev);
419 if (chid < 0 || chid >= dev_priv->engine.fifo.channels) 419 if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
420 return 0; 420 return 0;
421 421
422 chan = dev_priv->fifos[chid]; 422 chan = dev_priv->fifos[chid];
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 177d8229336f..ca79f32be44c 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -107,9 +107,13 @@ nv50_graph_init_regs(struct drm_device *dev)
107static int 107static int
108nv50_graph_init_ctxctl(struct drm_device *dev) 108nv50_graph_init_ctxctl(struct drm_device *dev)
109{ 109{
110 struct drm_nouveau_private *dev_priv = dev->dev_private;
111
110 NV_DEBUG(dev, "\n"); 112 NV_DEBUG(dev, "\n");
111 113
112 nv40_grctx_init(dev); 114 nouveau_grctx_prog_load(dev);
115 if (!dev_priv->engine.graph.ctxprog)
116 dev_priv->engine.graph.accel_blocked = true;
113 117
114 nv_wr32(dev, 0x400320, 4); 118 nv_wr32(dev, 0x400320, 4);
115 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); 119 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
@@ -140,7 +144,7 @@ void
140nv50_graph_takedown(struct drm_device *dev) 144nv50_graph_takedown(struct drm_device *dev)
141{ 145{
142 NV_DEBUG(dev, "\n"); 146 NV_DEBUG(dev, "\n");
143 nv40_grctx_fini(dev); 147 nouveau_grctx_fini(dev);
144} 148}
145 149
146void 150void
@@ -207,7 +211,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
207 dev_priv->engine.instmem.finish_access(dev); 211 dev_priv->engine.instmem.finish_access(dev);
208 212
209 dev_priv->engine.instmem.prepare_access(dev, true); 213 dev_priv->engine.instmem.prepare_access(dev, true);
210 nv40_grctx_vals_load(dev, ctx); 214 nouveau_grctx_vals_load(dev, ctx);
211 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12); 215 nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
212 if ((dev_priv->chipset & 0xf0) == 0xa0) 216 if ((dev_priv->chipset & 0xf0) == 0xa0)
213 nv_wo32(dev, ctx, 0x00004/4, 0x00000000); 217 nv_wo32(dev, ctx, 0x00004/4, 0x00000000);
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index 8c280463a664..e395c16d30f5 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -44,7 +44,7 @@ nv50_sor_disconnect(struct nouveau_encoder *nv_encoder)
44 struct nouveau_channel *evo = dev_priv->evo; 44 struct nouveau_channel *evo = dev_priv->evo;
45 int ret; 45 int ret;
46 46
47 NV_DEBUG(dev, "Disconnecting SOR %d\n", nv_encoder->or); 47 NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or);
48 48
49 ret = RING_SPACE(evo, 2); 49 ret = RING_SPACE(evo, 2);
50 if (ret) { 50 if (ret) {
@@ -70,7 +70,7 @@ nv50_sor_dp_link_train(struct drm_encoder *encoder)
70 } 70 }
71 71
72 if (dpe->script0) { 72 if (dpe->script0) {
73 NV_DEBUG(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); 73 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
74 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0), 74 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
75 nv_encoder->dcb); 75 nv_encoder->dcb);
76 } 76 }
@@ -79,7 +79,7 @@ nv50_sor_dp_link_train(struct drm_encoder *encoder)
79 NV_ERROR(dev, "SOR-%d: link training failed\n", nv_encoder->or); 79 NV_ERROR(dev, "SOR-%d: link training failed\n", nv_encoder->or);
80 80
81 if (dpe->script1) { 81 if (dpe->script1) {
82 NV_DEBUG(dev, "SOR-%d: running DP script 1\n", nv_encoder->or); 82 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
83 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1), 83 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
84 nv_encoder->dcb); 84 nv_encoder->dcb);
85 } 85 }
@@ -93,7 +93,7 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
93 uint32_t val; 93 uint32_t val;
94 int or = nv_encoder->or; 94 int or = nv_encoder->or;
95 95
96 NV_DEBUG(dev, "or %d mode %d\n", or, mode); 96 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
97 97
98 /* wait for it to be done */ 98 /* wait for it to be done */
99 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or), 99 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or),
@@ -142,7 +142,7 @@ nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
142 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 142 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
143 struct nouveau_connector *connector; 143 struct nouveau_connector *connector;
144 144
145 NV_DEBUG(encoder->dev, "or %d\n", nv_encoder->or); 145 NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or);
146 146
147 connector = nouveau_encoder_connector_get(nv_encoder); 147 connector = nouveau_encoder_connector_get(nv_encoder);
148 if (!connector) { 148 if (!connector) {
@@ -182,7 +182,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
182 uint32_t mode_ctl = 0; 182 uint32_t mode_ctl = 0;
183 int ret; 183 int ret;
184 184
185 NV_DEBUG(dev, "or %d\n", nv_encoder->or); 185 NV_DEBUG_KMS(dev, "or %d\n", nv_encoder->or);
186 186
187 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); 187 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
188 188
@@ -246,7 +246,7 @@ nv50_sor_destroy(struct drm_encoder *encoder)
246 if (!encoder) 246 if (!encoder)
247 return; 247 return;
248 248
249 NV_DEBUG(encoder->dev, "\n"); 249 NV_DEBUG_KMS(encoder->dev, "\n");
250 250
251 drm_encoder_cleanup(encoder); 251 drm_encoder_cleanup(encoder);
252 252
@@ -265,7 +265,7 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
265 bool dum; 265 bool dum;
266 int type; 266 int type;
267 267
268 NV_DEBUG(dev, "\n"); 268 NV_DEBUG_KMS(dev, "\n");
269 269
270 switch (entry->type) { 270 switch (entry->type) {
271 case OUTPUT_TMDS: 271 case OUTPUT_TMDS:
diff --git a/drivers/gpu/drm/r128/r128_drv.c b/drivers/gpu/drm/r128/r128_drv.c
index 601f4c0e5da5..b806fdcc7170 100644
--- a/drivers/gpu/drm/r128/r128_drv.c
+++ b/drivers/gpu/drm/r128/r128_drv.c
@@ -64,7 +64,7 @@ static struct drm_driver driver = {
64 .owner = THIS_MODULE, 64 .owner = THIS_MODULE,
65 .open = drm_open, 65 .open = drm_open,
66 .release = drm_release, 66 .release = drm_release,
67 .ioctl = drm_ioctl, 67 .unlocked_ioctl = drm_ioctl,
68 .mmap = drm_mmap, 68 .mmap = drm_mmap,
69 .poll = drm_poll, 69 .poll = drm_poll,
70 .fasync = drm_fasync, 70 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/r128/r128_ioc32.c b/drivers/gpu/drm/r128/r128_ioc32.c
index d3cb676eee84..51c99fc4dd38 100644
--- a/drivers/gpu/drm/r128/r128_ioc32.c
+++ b/drivers/gpu/drm/r128/r128_ioc32.c
@@ -95,8 +95,7 @@ static int compat_r128_init(struct file *file, unsigned int cmd,
95 &init->agp_textures_offset)) 95 &init->agp_textures_offset))
96 return -EFAULT; 96 return -EFAULT;
97 97
98 return drm_ioctl(file->f_path.dentry->d_inode, file, 98 return drm_ioctl(file, DRM_IOCTL_R128_INIT, (unsigned long)init);
99 DRM_IOCTL_R128_INIT, (unsigned long)init);
100} 99}
101 100
102typedef struct drm_r128_depth32 { 101typedef struct drm_r128_depth32 {
@@ -129,8 +128,7 @@ static int compat_r128_depth(struct file *file, unsigned int cmd,
129 &depth->mask)) 128 &depth->mask))
130 return -EFAULT; 129 return -EFAULT;
131 130
132 return drm_ioctl(file->f_path.dentry->d_inode, file, 131 return drm_ioctl(file, DRM_IOCTL_R128_DEPTH, (unsigned long)depth);
133 DRM_IOCTL_R128_DEPTH, (unsigned long)depth);
134 132
135} 133}
136 134
@@ -153,8 +151,7 @@ static int compat_r128_stipple(struct file *file, unsigned int cmd,
153 &stipple->mask)) 151 &stipple->mask))
154 return -EFAULT; 152 return -EFAULT;
155 153
156 return drm_ioctl(file->f_path.dentry->d_inode, file, 154 return drm_ioctl(file, DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple);
157 DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple);
158} 155}
159 156
160typedef struct drm_r128_getparam32 { 157typedef struct drm_r128_getparam32 {
@@ -178,8 +175,7 @@ static int compat_r128_getparam(struct file *file, unsigned int cmd,
178 &getparam->value)) 175 &getparam->value))
179 return -EFAULT; 176 return -EFAULT;
180 177
181 return drm_ioctl(file->f_path.dentry->d_inode, file, 178 return drm_ioctl(file, DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam);
182 DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam);
183} 179}
184 180
185drm_ioctl_compat_t *r128_compat_ioctls[] = { 181drm_ioctl_compat_t *r128_compat_ioctls[] = {
@@ -210,12 +206,10 @@ long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
210 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(r128_compat_ioctls)) 206 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(r128_compat_ioctls))
211 fn = r128_compat_ioctls[nr - DRM_COMMAND_BASE]; 207 fn = r128_compat_ioctls[nr - DRM_COMMAND_BASE];
212 208
213 lock_kernel(); /* XXX for now */
214 if (fn != NULL) 209 if (fn != NULL)
215 ret = (*fn) (filp, cmd, arg); 210 ret = (*fn) (filp, cmd, arg);
216 else 211 else
217 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 212 ret = drm_ioctl(filp, cmd, arg);
218 unlock_kernel();
219 213
220 return ret; 214 return ret;
221} 215}
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 6578d19dff93..388140a7e651 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -58,6 +58,7 @@ typedef struct {
58} atom_exec_context; 58} atom_exec_context;
59 59
60int atom_debug = 0; 60int atom_debug = 0;
61static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
61void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 62void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
62 63
63static uint32_t atom_arg_mask[8] = 64static uint32_t atom_arg_mask[8] =
@@ -573,7 +574,7 @@ static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
573 else 574 else
574 SDEBUG(" table: %d\n", idx); 575 SDEBUG(" table: %d\n", idx);
575 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 576 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
576 atom_execute_table(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 577 atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
577} 578}
578 579
579static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 580static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
@@ -1040,7 +1041,7 @@ static struct {
1040 atom_op_shr, ATOM_ARG_MC}, { 1041 atom_op_shr, ATOM_ARG_MC}, {
1041atom_op_debug, 0},}; 1042atom_op_debug, 0},};
1042 1043
1043void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1044static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
1044{ 1045{
1045 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1046 int base = CU16(ctx->cmd_table + 4 + 2 * index);
1046 int len, ws, ps, ptr; 1047 int len, ws, ps, ptr;
@@ -1092,6 +1093,13 @@ void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1092 kfree(ectx.ws); 1093 kfree(ectx.ws);
1093} 1094}
1094 1095
1096void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1097{
1098 mutex_lock(&ctx->mutex);
1099 atom_execute_table_locked(ctx, index, params);
1100 mutex_unlock(&ctx->mutex);
1101}
1102
1095static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1103static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1096 1104
1097static void atom_index_iio(struct atom_context *ctx, int base) 1105static void atom_index_iio(struct atom_context *ctx, int base)
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 6671848e5ea1..47fd943f6d14 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -120,6 +120,7 @@ struct card_info {
120 120
121struct atom_context { 121struct atom_context {
122 struct card_info *card; 122 struct card_info *card;
123 struct mutex mutex;
123 void *bios; 124 void *bios;
124 uint32_t cmd_table, data_table; 125 uint32_t cmd_table, data_table;
125 uint16_t *iio; 126 uint16_t *iio;
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 5f48515c77a7..91ad0d1c1b17 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -4690,6 +4690,205 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 {
4690 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 4690 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
4691} ATOM_POWERPLAY_INFO_V3; 4691} ATOM_POWERPLAY_INFO_V3;
4692 4692
4693/* New PPlib */
4694/**************************************************************************/
4695typedef struct _ATOM_PPLIB_THERMALCONTROLLER
4696
4697{
4698 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
4699 UCHAR ucI2cLine; // as interpreted by DAL I2C
4700 UCHAR ucI2cAddress;
4701 UCHAR ucFanParameters; // Fan Control Parameters.
4702 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
4703 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
4704 UCHAR ucReserved; // ----
4705 UCHAR ucFlags; // to be defined
4706} ATOM_PPLIB_THERMALCONTROLLER;
4707
4708#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
4709#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
4710
4711#define ATOM_PP_THERMALCONTROLLER_NONE 0
4712#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
4713#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
4714#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
4715#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
4716#define ATOM_PP_THERMALCONTROLLER_LM64 5
4717#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
4718#define ATOM_PP_THERMALCONTROLLER_RV6xx 7
4719#define ATOM_PP_THERMALCONTROLLER_RV770 8
4720#define ATOM_PP_THERMALCONTROLLER_ADT7473 9
4721
4722typedef struct _ATOM_PPLIB_STATE
4723{
4724 UCHAR ucNonClockStateIndex;
4725 UCHAR ucClockStateIndices[1]; // variable-sized
4726} ATOM_PPLIB_STATE;
4727
4728//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
4729#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
4730#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
4731#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
4732#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
4733#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
4734#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
4735#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
4736#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
4737#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
4738#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
4739#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
4740#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
4741
4742typedef struct _ATOM_PPLIB_POWERPLAYTABLE
4743{
4744 ATOM_COMMON_TABLE_HEADER sHeader;
4745
4746 UCHAR ucDataRevision;
4747
4748 UCHAR ucNumStates;
4749 UCHAR ucStateEntrySize;
4750 UCHAR ucClockInfoSize;
4751 UCHAR ucNonClockSize;
4752
4753 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
4754 USHORT usStateArrayOffset;
4755
4756 // offset from start of this table to array of ASIC-specific structures,
4757 // currently ATOM_PPLIB_CLOCK_INFO.
4758 USHORT usClockInfoArrayOffset;
4759
4760 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
4761 USHORT usNonClockInfoArrayOffset;
4762
4763 USHORT usBackbiasTime; // in microseconds
4764 USHORT usVoltageTime; // in microseconds
4765 USHORT usTableSize; //the size of this structure, or the extended structure
4766
4767 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
4768
4769 ATOM_PPLIB_THERMALCONTROLLER sThermalController;
4770
4771 USHORT usBootClockInfoOffset;
4772 USHORT usBootNonClockInfoOffset;
4773
4774} ATOM_PPLIB_POWERPLAYTABLE;
4775
4776//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
4777#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
4778#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
4779#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
4780#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
4781#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
4782#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
4783// 2, 4, 6, 7 are reserved
4784
4785#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
4786#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
4787#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
4788#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
4789#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
4790#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
4791#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
4792#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
4793#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
4794#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
4795// remaining 3 bits are reserved
4796
4797//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
4798#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
4799#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
4800
4801// 0 is 2.5Gb/s, 1 is 5Gb/s
4802#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
4803#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
4804
4805// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
4806#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
4807#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
4808
4809// lookup into reduced refresh-rate table
4810#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
4811#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
4812
4813#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
4814#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
4815// 2-15 TBD as needed.
4816
4817#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
4818#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
4819#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
4820
4821#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
4822
4823// Contained in an array starting at the offset
4824// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
4825// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
4826typedef struct _ATOM_PPLIB_NONCLOCK_INFO
4827{
4828 USHORT usClassification;
4829 UCHAR ucMinTemperature;
4830 UCHAR ucMaxTemperature;
4831 ULONG ulCapsAndSettings;
4832 UCHAR ucRequiredPower;
4833 UCHAR ucUnused1[3];
4834} ATOM_PPLIB_NONCLOCK_INFO;
4835
4836// Contained in an array starting at the offset
4837// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
4838// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
4839typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
4840{
4841 USHORT usEngineClockLow;
4842 UCHAR ucEngineClockHigh;
4843
4844 USHORT usMemoryClockLow;
4845 UCHAR ucMemoryClockHigh;
4846
4847 USHORT usVDDC;
4848 USHORT usUnused1;
4849 USHORT usUnused2;
4850
4851 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
4852
4853} ATOM_PPLIB_R600_CLOCK_INFO;
4854
4855// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
4856#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
4857#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
4858#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
4859#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
4860#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
4861
4862typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
4863
4864{
4865 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
4866 UCHAR ucLowEngineClockHigh;
4867 USHORT usHighEngineClockLow; // High Engine clock in MHz.
4868 UCHAR ucHighEngineClockHigh;
4869 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
4870 UCHAR ucMemoryClockHigh; // Currentyl unused.
4871 UCHAR ucPadding; // For proper alignment and size.
4872 USHORT usVDDC; // For the 780, use: None, Low, High, Variable
4873 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
4874 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
4875 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
4876 ULONG ulFlags;
4877} ATOM_PPLIB_RS780_CLOCK_INFO;
4878
4879#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
4880#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
4881#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
4882#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
4883
4884#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
4885#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
4886#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
4887
4888#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
4889#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
4890#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
4891
4693/**************************************************************************/ 4892/**************************************************************************/
4694 4893
4695/* Following definitions are for compatiblity issue in different SW components. */ 4894/* Following definitions are for compatiblity issue in different SW components. */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 84e5df766d3f..71727460968f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2881,6 +2881,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2881 2881
2882 for (i = 0; i < track->num_cb; i++) { 2882 for (i = 0; i < track->num_cb; i++) {
2883 if (track->cb[i].robj == NULL) { 2883 if (track->cb[i].robj == NULL) {
2884 if (!(track->fastfill || track->color_channel_mask ||
2885 track->blend_read_enable)) {
2886 continue;
2887 }
2884 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2888 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2885 return -EINVAL; 2889 return -EINVAL;
2886 } 2890 }
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 7188c3778ee2..b27a6999d219 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -67,13 +67,15 @@ struct r100_cs_track {
67 unsigned immd_dwords; 67 unsigned immd_dwords;
68 unsigned num_arrays; 68 unsigned num_arrays;
69 unsigned max_indx; 69 unsigned max_indx;
70 unsigned color_channel_mask;
70 struct r100_cs_track_array arrays[11]; 71 struct r100_cs_track_array arrays[11];
71 struct r100_cs_track_cb cb[R300_MAX_CB]; 72 struct r100_cs_track_cb cb[R300_MAX_CB];
72 struct r100_cs_track_cb zb; 73 struct r100_cs_track_cb zb;
73 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 74 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
74 bool z_enabled; 75 bool z_enabled;
75 bool separate_cube; 76 bool separate_cube;
76 77 bool fastfill;
78 bool blend_read_enable;
77}; 79};
78 80
79int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 81int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2b5061..3f2cc9e2e8d9 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -887,6 +887,14 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
887 track->textures[i].cpp = 1; 887 track->textures[i].cpp = 1;
888 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 888 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
889 break; 889 break;
890 case R300_TX_FORMAT_ATI2N:
891 if (p->rdev->family < CHIP_R420) {
892 DRM_ERROR("Invalid texture format %u\n",
893 (idx_value & 0x1F));
894 return -EINVAL;
895 }
896 /* The same rules apply as for DXT3/5. */
897 /* Pass through. */
890 case R300_TX_FORMAT_DXT3: 898 case R300_TX_FORMAT_DXT3:
891 case R300_TX_FORMAT_DXT5: 899 case R300_TX_FORMAT_DXT5:
892 track->textures[i].cpp = 1; 900 track->textures[i].cpp = 1;
@@ -951,6 +959,16 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
951 track->textures[i].width_11 = tmp; 959 track->textures[i].width_11 = tmp;
952 tmp = ((idx_value >> 16) & 1) << 11; 960 tmp = ((idx_value >> 16) & 1) << 11;
953 track->textures[i].height_11 = tmp; 961 track->textures[i].height_11 = tmp;
962
963 /* ATI1N */
964 if (idx_value & (1 << 14)) {
965 /* The same rules apply as for DXT1. */
966 track->textures[i].compress_format =
967 R100_TRACK_COMP_DXT1;
968 }
969 } else if (idx_value & (1 << 14)) {
970 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
971 return -EINVAL;
954 } 972 }
955 break; 973 break;
956 case 0x4480: 974 case 0x4480:
@@ -992,6 +1010,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
992 } 1010 }
993 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1011 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
994 break; 1012 break;
1013 case 0x4e0c:
1014 /* RB3D_COLOR_CHANNEL_MASK */
1015 track->color_channel_mask = idx_value;
1016 break;
1017 case 0x4d1c:
1018 /* ZB_BW_CNTL */
1019 track->fastfill = !!(idx_value & (1 << 2));
1020 break;
1021 case 0x4e04:
1022 /* RB3D_BLENDCNTL */
1023 track->blend_read_enable = !!(idx_value & (1 << 2));
1024 break;
995 case 0x4be8: 1025 case 0x4be8:
996 /* valid register only on RV530 */ 1026 /* valid register only on RV530 */
997 if (p->rdev->family == CHIP_RV530) 1027 if (p->rdev->family == CHIP_RV530)
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
index cb2e470f97d4..34bffa0e4b73 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -990,7 +990,7 @@ static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
990 int sz; 990 int sz;
991 int addr; 991 int addr;
992 int type; 992 int type;
993 int clamp; 993 int isclamp;
994 int stride; 994 int stride;
995 RING_LOCALS; 995 RING_LOCALS;
996 996
@@ -999,10 +999,10 @@ static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
999 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo; 999 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
1000 1000
1001 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); 1001 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
1002 clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); 1002 isclamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
1003 1003
1004 addr |= (type << 16); 1004 addr |= (type << 16);
1005 addr |= (clamp << 17); 1005 addr |= (isclamp << 17);
1006 1006
1007 stride = type ? 4 : 6; 1007 stride = type ? 4 : 6;
1008 1008
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index 4b7afef35a65..1735a2b69580 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -900,6 +900,7 @@
900# define R300_TX_FORMAT_FL_I32 0x1B 900# define R300_TX_FORMAT_FL_I32 0x1B
901# define R300_TX_FORMAT_FL_I32A32 0x1C 901# define R300_TX_FORMAT_FL_I32A32 0x1C
902# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D 902# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
903# define R300_TX_FORMAT_ATI2N 0x1F
903 /* alpha modes, convenience mostly */ 904 /* alpha modes, convenience mostly */
904 /* if you have alpha, pick constant appropriate to the 905 /* if you have alpha, pick constant appropriate to the
905 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ 906 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0d820764f340..44060b92d9e6 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -170,7 +170,7 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
170 idx, relocs_chunk->length_dw); 170 idx, relocs_chunk->length_dw);
171 return -EINVAL; 171 return -EINVAL;
172 } 172 }
173 *cs_reloc = &p->relocs[0]; 173 *cs_reloc = p->relocs;
174 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; 174 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
175 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 175 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
176 return 0; 176 return 0;
@@ -717,7 +717,7 @@ static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
717 if (p->chunk_relocs_idx == -1) { 717 if (p->chunk_relocs_idx == -1) {
718 return 0; 718 return 0;
719 } 719 }
720 p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 720 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
721 if (p->relocs == NULL) { 721 if (p->relocs == NULL) {
722 return -ENOMEM; 722 return -ENOMEM;
723 } 723 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index cd650fd3964e..53b55608102b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -162,6 +162,7 @@ struct radeon_fence_driver {
162 struct list_head created; 162 struct list_head created;
163 struct list_head emited; 163 struct list_head emited;
164 struct list_head signaled; 164 struct list_head signaled;
165 bool initialized;
165}; 166};
166 167
167struct radeon_fence { 168struct radeon_fence {
@@ -202,8 +203,9 @@ struct radeon_surface_reg {
202struct radeon_mman { 203struct radeon_mman {
203 struct ttm_bo_global_ref bo_global_ref; 204 struct ttm_bo_global_ref bo_global_ref;
204 struct ttm_global_reference mem_global_ref; 205 struct ttm_global_reference mem_global_ref;
205 bool mem_global_referenced;
206 struct ttm_bo_device bdev; 206 struct ttm_bo_device bdev;
207 bool mem_global_referenced;
208 bool initialized;
207}; 209};
208 210
209struct radeon_bo { 211struct radeon_bo {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 636116bedcb4..eb29217bbf1d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -33,6 +33,7 @@
33 */ 33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
36void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
37 38
38uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
@@ -106,7 +107,7 @@ static struct radeon_asic r100_asic = {
106 .copy = &r100_copy_blit, 107 .copy = &r100_copy_blit,
107 .get_engine_clock = &radeon_legacy_get_engine_clock, 108 .get_engine_clock = &radeon_legacy_get_engine_clock,
108 .set_engine_clock = &radeon_legacy_set_engine_clock, 109 .set_engine_clock = &radeon_legacy_set_engine_clock,
109 .get_memory_clock = NULL, 110 .get_memory_clock = &radeon_legacy_get_memory_clock,
110 .set_memory_clock = NULL, 111 .set_memory_clock = NULL,
111 .set_pcie_lanes = NULL, 112 .set_pcie_lanes = NULL,
112 .set_clock_gating = &radeon_legacy_set_clock_gating, 113 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -166,7 +167,7 @@ static struct radeon_asic r300_asic = {
166 .copy = &r100_copy_blit, 167 .copy = &r100_copy_blit,
167 .get_engine_clock = &radeon_legacy_get_engine_clock, 168 .get_engine_clock = &radeon_legacy_get_engine_clock,
168 .set_engine_clock = &radeon_legacy_set_engine_clock, 169 .set_engine_clock = &radeon_legacy_set_engine_clock,
169 .get_memory_clock = NULL, 170 .get_memory_clock = &radeon_legacy_get_memory_clock,
170 .set_memory_clock = NULL, 171 .set_memory_clock = NULL,
171 .set_pcie_lanes = &rv370_set_pcie_lanes, 172 .set_pcie_lanes = &rv370_set_pcie_lanes,
172 .set_clock_gating = &radeon_legacy_set_clock_gating, 173 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -259,7 +260,7 @@ static struct radeon_asic rs400_asic = {
259 .copy = &r100_copy_blit, 260 .copy = &r100_copy_blit,
260 .get_engine_clock = &radeon_legacy_get_engine_clock, 261 .get_engine_clock = &radeon_legacy_get_engine_clock,
261 .set_engine_clock = &radeon_legacy_set_engine_clock, 262 .set_engine_clock = &radeon_legacy_set_engine_clock,
262 .get_memory_clock = NULL, 263 .get_memory_clock = &radeon_legacy_get_memory_clock,
263 .set_memory_clock = NULL, 264 .set_memory_clock = NULL,
264 .set_pcie_lanes = NULL, 265 .set_pcie_lanes = NULL,
265 .set_clock_gating = &radeon_legacy_set_clock_gating, 266 .set_clock_gating = &radeon_legacy_set_clock_gating,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 12a0c760e7ff..321044bef71c 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -745,8 +745,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
745 else 745 else
746 radeon_add_legacy_encoder(dev, 746 radeon_add_legacy_encoder(dev,
747 radeon_get_encoder_id(dev, 747 radeon_get_encoder_id(dev,
748 (1 << 748 (1 << i),
749 i),
750 dac), 749 dac),
751 (1 << i)); 750 (1 << i));
752 } 751 }
@@ -758,32 +757,30 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
758 if (bios_connectors[j].valid && (i != j)) { 757 if (bios_connectors[j].valid && (i != j)) {
759 if (bios_connectors[i].line_mux == 758 if (bios_connectors[i].line_mux ==
760 bios_connectors[j].line_mux) { 759 bios_connectors[j].line_mux) {
761 if (((bios_connectors[i]. 760 /* make sure not to combine LVDS */
762 devices & 761 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
763 (ATOM_DEVICE_DFP_SUPPORT)) 762 bios_connectors[i].line_mux = 53;
764 && (bios_connectors[j]. 763 bios_connectors[i].ddc_bus.valid = false;
765 devices & 764 continue;
766 (ATOM_DEVICE_CRT_SUPPORT))) 765 }
767 || 766 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
768 ((bios_connectors[j]. 767 bios_connectors[j].line_mux = 53;
769 devices & 768 bios_connectors[j].ddc_bus.valid = false;
770 (ATOM_DEVICE_DFP_SUPPORT)) 769 continue;
771 && (bios_connectors[i]. 770 }
772 devices & 771 /* combine analog and digital for DVI-I */
773 (ATOM_DEVICE_CRT_SUPPORT)))) { 772 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
774 bios_connectors[i]. 773 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
775 devices |= 774 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
776 bios_connectors[j]. 775 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
777 devices; 776 bios_connectors[i].devices |=
778 bios_connectors[i]. 777 bios_connectors[j].devices;
779 connector_type = 778 bios_connectors[i].connector_type =
780 DRM_MODE_CONNECTOR_DVII; 779 DRM_MODE_CONNECTOR_DVII;
781 if (bios_connectors[j].devices & 780 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
782 (ATOM_DEVICE_DFP_SUPPORT))
783 bios_connectors[i].hpd = 781 bios_connectors[i].hpd =
784 bios_connectors[j].hpd; 782 bios_connectors[j].hpd;
785 bios_connectors[j]. 783 bios_connectors[j].valid = false;
786 valid = false;
787 } 784 }
788 } 785 }
789 } 786 }
@@ -1234,6 +1231,61 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1234 return true; 1231 return true;
1235} 1232}
1236 1233
1234enum radeon_tv_std
1235radeon_atombios_get_tv_info(struct radeon_device *rdev)
1236{
1237 struct radeon_mode_info *mode_info = &rdev->mode_info;
1238 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1239 uint16_t data_offset;
1240 uint8_t frev, crev;
1241 struct _ATOM_ANALOG_TV_INFO *tv_info;
1242 enum radeon_tv_std tv_std = TV_STD_NTSC;
1243
1244 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1245
1246 tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1247
1248 switch (tv_info->ucTV_BootUpDefaultStandard) {
1249 case ATOM_TV_NTSC:
1250 tv_std = TV_STD_NTSC;
1251 DRM_INFO("Default TV standard: NTSC\n");
1252 break;
1253 case ATOM_TV_NTSCJ:
1254 tv_std = TV_STD_NTSC_J;
1255 DRM_INFO("Default TV standard: NTSC-J\n");
1256 break;
1257 case ATOM_TV_PAL:
1258 tv_std = TV_STD_PAL;
1259 DRM_INFO("Default TV standard: PAL\n");
1260 break;
1261 case ATOM_TV_PALM:
1262 tv_std = TV_STD_PAL_M;
1263 DRM_INFO("Default TV standard: PAL-M\n");
1264 break;
1265 case ATOM_TV_PALN:
1266 tv_std = TV_STD_PAL_N;
1267 DRM_INFO("Default TV standard: PAL-N\n");
1268 break;
1269 case ATOM_TV_PALCN:
1270 tv_std = TV_STD_PAL_CN;
1271 DRM_INFO("Default TV standard: PAL-CN\n");
1272 break;
1273 case ATOM_TV_PAL60:
1274 tv_std = TV_STD_PAL_60;
1275 DRM_INFO("Default TV standard: PAL-60\n");
1276 break;
1277 case ATOM_TV_SECAM:
1278 tv_std = TV_STD_SECAM;
1279 DRM_INFO("Default TV standard: SECAM\n");
1280 break;
1281 default:
1282 tv_std = TV_STD_NTSC;
1283 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1284 break;
1285 }
1286 return tv_std;
1287}
1288
1237struct radeon_encoder_tv_dac * 1289struct radeon_encoder_tv_dac *
1238radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1290radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1239{ 1291{
@@ -1269,6 +1321,7 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1269 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1321 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1270 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1322 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1271 1323
1324 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1272 } 1325 }
1273 return tv_dac; 1326 return tv_dac;
1274} 1327}
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index b062109efbee..812f24dbc2a8 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -62,7 +62,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
62} 62}
63 63
64/* 10 khz */ 64/* 10 khz */
65static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) 65uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
66{ 66{
67 struct radeon_pll *mpll = &rdev->clock.mpll; 67 struct radeon_pll *mpll = &rdev->clock.mpll;
68 uint32_t fb_div, ref_div, post_div, mclk; 68 uint32_t fb_div, ref_div, post_div, mclk;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index c5021a3445de..fd94dbca33ac 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -634,11 +634,10 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
634 return p_dac; 634 return p_dac;
635} 635}
636 636
637static enum radeon_tv_std 637enum radeon_tv_std
638radeon_combios_get_tv_info(struct radeon_encoder *encoder) 638radeon_combios_get_tv_info(struct radeon_device *rdev)
639{ 639{
640 struct drm_device *dev = encoder->base.dev; 640 struct drm_device *dev = rdev->ddev;
641 struct radeon_device *rdev = dev->dev_private;
642 uint16_t tv_info; 641 uint16_t tv_info;
643 enum radeon_tv_std tv_std = TV_STD_NTSC; 642 enum radeon_tv_std tv_std = TV_STD_NTSC;
644 643
@@ -779,7 +778,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
779 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 778 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
780 found = 1; 779 found = 1;
781 } 780 }
782 tv_dac->tv_std = radeon_combios_get_tv_info(encoder); 781 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
783 } 782 }
784 if (!found) { 783 if (!found) {
785 /* then check CRT table */ 784 /* then check CRT table */
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5eece186e03c..20161567dbff 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -208,6 +208,18 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
208 drm_mode_set_name(mode); 208 drm_mode_set_name(mode);
209 209
210 DRM_DEBUG("Adding native panel mode %s\n", mode->name); 210 DRM_DEBUG("Adding native panel mode %s\n", mode->name);
211 } else if (native_mode->hdisplay != 0 &&
212 native_mode->vdisplay != 0) {
213 /* mac laptops without an edid */
214 /* Note that this is not necessarily the exact panel mode,
215 * but an approximation based on the cvt formula. For these
216 * systems we should ideally read the mode info out of the
217 * registers or add a mode table, but this works and is much
218 * simpler.
219 */
220 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
221 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
222 DRM_DEBUG("Adding cvt approximation of native panel mode %s\n", mode->name);
211 } 223 }
212 return mode; 224 return mode;
213} 225}
@@ -1171,7 +1183,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1171 1); 1183 1);
1172 drm_connector_attach_property(&radeon_connector->base, 1184 drm_connector_attach_property(&radeon_connector->base,
1173 rdev->mode_info.tv_std_property, 1185 rdev->mode_info.tv_std_property,
1174 1); 1186 radeon_atombios_get_tv_info(rdev));
1175 } 1187 }
1176 break; 1188 break;
1177 case DRM_MODE_CONNECTOR_LVDS: 1189 case DRM_MODE_CONNECTOR_LVDS:
@@ -1315,7 +1327,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1315 1); 1327 1);
1316 drm_connector_attach_property(&radeon_connector->base, 1328 drm_connector_attach_property(&radeon_connector->base,
1317 rdev->mode_info.tv_std_property, 1329 rdev->mode_info.tv_std_property,
1318 1); 1330 radeon_combios_get_tv_info(rdev));
1319 } 1331 }
1320 break; 1332 break;
1321 case DRM_MODE_CONNECTOR_LVDS: 1333 case DRM_MODE_CONNECTOR_LVDS:
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 02bcdb1240c0..7c6848096bcd 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -391,6 +391,12 @@ int radeon_asic_init(struct radeon_device *rdev)
391 /* FIXME: not supported yet */ 391 /* FIXME: not supported yet */
392 return -EINVAL; 392 return -EINVAL;
393 } 393 }
394
395 if (rdev->flags & RADEON_IS_IGP) {
396 rdev->asic->get_memory_clock = NULL;
397 rdev->asic->set_memory_clock = NULL;
398 }
399
394 return 0; 400 return 0;
395} 401}
396 402
@@ -481,6 +487,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
481 atom_card_info->pll_write = cail_pll_write; 487 atom_card_info->pll_write = cail_pll_write;
482 488
483 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 489 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
490 mutex_init(&rdev->mode_info.atom_context->mutex);
484 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 491 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
485 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 492 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
486 return 0; 493 return 0;
@@ -539,9 +546,72 @@ void radeon_agp_disable(struct radeon_device *rdev)
539 } 546 }
540} 547}
541 548
542/* 549void radeon_check_arguments(struct radeon_device *rdev)
543 * Radeon device. 550{
544 */ 551 /* vramlimit must be a power of two */
552 switch (radeon_vram_limit) {
553 case 0:
554 case 4:
555 case 8:
556 case 16:
557 case 32:
558 case 64:
559 case 128:
560 case 256:
561 case 512:
562 case 1024:
563 case 2048:
564 case 4096:
565 break;
566 default:
567 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
568 radeon_vram_limit);
569 radeon_vram_limit = 0;
570 break;
571 }
572 radeon_vram_limit = radeon_vram_limit << 20;
573 /* gtt size must be power of two and greater or equal to 32M */
574 switch (radeon_gart_size) {
575 case 4:
576 case 8:
577 case 16:
578 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
579 radeon_gart_size);
580 radeon_gart_size = 512;
581 break;
582 case 32:
583 case 64:
584 case 128:
585 case 256:
586 case 512:
587 case 1024:
588 case 2048:
589 case 4096:
590 break;
591 default:
592 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
593 radeon_gart_size);
594 radeon_gart_size = 512;
595 break;
596 }
597 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
598 /* AGP mode can only be -1, 1, 2, 4, 8 */
599 switch (radeon_agpmode) {
600 case -1:
601 case 0:
602 case 1:
603 case 2:
604 case 4:
605 case 8:
606 break;
607 default:
608 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
609 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
610 radeon_agpmode = 0;
611 break;
612 }
613}
614
545int radeon_device_init(struct radeon_device *rdev, 615int radeon_device_init(struct radeon_device *rdev,
546 struct drm_device *ddev, 616 struct drm_device *ddev,
547 struct pci_dev *pdev, 617 struct pci_dev *pdev,
@@ -580,9 +650,9 @@ int radeon_device_init(struct radeon_device *rdev,
580 650
581 /* Set asic functions */ 651 /* Set asic functions */
582 r = radeon_asic_init(rdev); 652 r = radeon_asic_init(rdev);
583 if (r) { 653 if (r)
584 return r; 654 return r;
585 } 655 radeon_check_arguments(rdev);
586 656
587 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 657 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
588 radeon_agp_disable(rdev); 658 radeon_agp_disable(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a133b833e45d..91d72b70abc9 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -739,7 +739,7 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
739 { TV_STD_SECAM, "secam" }, 739 { TV_STD_SECAM, "secam" },
740}; 740};
741 741
742int radeon_modeset_create_props(struct radeon_device *rdev) 742static int radeon_modeset_create_props(struct radeon_device *rdev)
743{ 743{
744 int i, sz; 744 int i, sz;
745 745
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index dbd56ef82f9c..8ba3de7994d4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -196,7 +196,7 @@ static struct drm_driver driver_old = {
196 .owner = THIS_MODULE, 196 .owner = THIS_MODULE,
197 .open = drm_open, 197 .open = drm_open,
198 .release = drm_release, 198 .release = drm_release,
199 .ioctl = drm_ioctl, 199 .unlocked_ioctl = drm_ioctl,
200 .mmap = drm_mmap, 200 .mmap = drm_mmap,
201 .poll = drm_poll, 201 .poll = drm_poll,
202 .fasync = drm_fasync, 202 .fasync = drm_fasync,
@@ -284,7 +284,7 @@ static struct drm_driver kms_driver = {
284 .owner = THIS_MODULE, 284 .owner = THIS_MODULE,
285 .open = drm_open, 285 .open = drm_open,
286 .release = drm_release, 286 .release = drm_release,
287 .ioctl = drm_ioctl, 287 .unlocked_ioctl = drm_ioctl,
288 .mmap = radeon_mmap, 288 .mmap = radeon_mmap,
289 .poll = drm_poll, 289 .poll = drm_poll,
290 .fasync = drm_fasync, 290 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 0d1d908e5225..ccba95f83d11 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -233,6 +233,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
233 if (!ASIC_IS_AVIVO(rdev)) { 233 if (!ASIC_IS_AVIVO(rdev)) {
234 adjusted_mode->hdisplay = mode->hdisplay; 234 adjusted_mode->hdisplay = mode->hdisplay;
235 adjusted_mode->vdisplay = mode->vdisplay; 235 adjusted_mode->vdisplay = mode->vdisplay;
236 adjusted_mode->crtc_hdisplay = mode->hdisplay;
237 adjusted_mode->crtc_vdisplay = mode->vdisplay;
236 } 238 }
237 adjusted_mode->base.id = mode_id; 239 adjusted_mode->base.id = mode_id;
238 } 240 }
@@ -495,9 +497,9 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
495 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 497 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
496 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 498 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 499 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
498 if (dig->lvds_misc & (1 << 0)) 500 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
499 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 501 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
500 if (dig->lvds_misc & (1 << 1)) 502 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
501 args.v1.ucMisc |= (1 << 1); 503 args.v1.ucMisc |= (1 << 1);
502 } else { 504 } else {
503 if (dig_connector->linkb) 505 if (dig_connector->linkb)
@@ -524,18 +526,18 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
524 args.v2.ucTemporal = 0; 526 args.v2.ucTemporal = 0;
525 args.v2.ucFRC = 0; 527 args.v2.ucFRC = 0;
526 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
527 if (dig->lvds_misc & (1 << 0)) 529 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
528 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 530 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
529 if (dig->lvds_misc & (1 << 5)) { 531 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
530 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 532 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
531 if (dig->lvds_misc & (1 << 1)) 533 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
532 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 534 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
533 } 535 }
534 if (dig->lvds_misc & (1 << 6)) { 536 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
535 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 537 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
536 if (dig->lvds_misc & (1 << 1)) 538 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
537 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
538 if (((dig->lvds_misc >> 2) & 0x3) == 2) 540 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 541 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
540 } 542 }
541 } else { 543 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index cb4cd97ae39f..4cdd8b4f7549 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -324,7 +324,7 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
324 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 324 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
325 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); 325 r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
326 if (r) { 326 if (r) {
327 DRM_ERROR("Fence failed to get a scratch register."); 327 dev_err(rdev->dev, "fence failed to get scratch register\n");
328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 328 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
329 return r; 329 return r;
330 } 330 }
@@ -335,9 +335,10 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
335 INIT_LIST_HEAD(&rdev->fence_drv.signaled); 335 INIT_LIST_HEAD(&rdev->fence_drv.signaled);
336 rdev->fence_drv.count_timeout = 0; 336 rdev->fence_drv.count_timeout = 0;
337 init_waitqueue_head(&rdev->fence_drv.queue); 337 init_waitqueue_head(&rdev->fence_drv.queue);
338 rdev->fence_drv.initialized = true;
338 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 339 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
339 if (radeon_debugfs_fence_init(rdev)) { 340 if (radeon_debugfs_fence_init(rdev)) {
340 DRM_ERROR("Failed to register debugfs file for fence !\n"); 341 dev_err(rdev->dev, "fence debugfs file creation failed\n");
341 } 342 }
342 return 0; 343 return 0;
343} 344}
@@ -346,11 +347,13 @@ void radeon_fence_driver_fini(struct radeon_device *rdev)
346{ 347{
347 unsigned long irq_flags; 348 unsigned long irq_flags;
348 349
350 if (!rdev->fence_drv.initialized)
351 return;
349 wake_up_all(&rdev->fence_drv.queue); 352 wake_up_all(&rdev->fence_drv.queue);
350 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); 353 write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
351 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); 354 radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
352 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); 355 write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
353 DRM_INFO("radeon: fence finalized\n"); 356 rdev->fence_drv.initialized = false;
354} 357}
355 358
356 359
diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c
index a1bf11de308a..48b7cea31e08 100644
--- a/drivers/gpu/drm/radeon/radeon_ioc32.c
+++ b/drivers/gpu/drm/radeon/radeon_ioc32.c
@@ -92,8 +92,7 @@ static int compat_radeon_cp_init(struct file *file, unsigned int cmd,
92 &init->gart_textures_offset)) 92 &init->gart_textures_offset))
93 return -EFAULT; 93 return -EFAULT;
94 94
95 return drm_ioctl(file->f_path.dentry->d_inode, file, 95 return drm_ioctl(file, DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init);
96 DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init);
97} 96}
98 97
99typedef struct drm_radeon_clear32 { 98typedef struct drm_radeon_clear32 {
@@ -125,8 +124,7 @@ static int compat_radeon_cp_clear(struct file *file, unsigned int cmd,
125 &clr->depth_boxes)) 124 &clr->depth_boxes))
126 return -EFAULT; 125 return -EFAULT;
127 126
128 return drm_ioctl(file->f_path.dentry->d_inode, file, 127 return drm_ioctl(file, DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr);
129 DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr);
130} 128}
131 129
132typedef struct drm_radeon_stipple32 { 130typedef struct drm_radeon_stipple32 {
@@ -149,8 +147,7 @@ static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd,
149 &request->mask)) 147 &request->mask))
150 return -EFAULT; 148 return -EFAULT;
151 149
152 return drm_ioctl(file->f_path.dentry->d_inode, file, 150 return drm_ioctl(file, DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request);
153 DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request);
154} 151}
155 152
156typedef struct drm_radeon_tex_image32 { 153typedef struct drm_radeon_tex_image32 {
@@ -204,8 +201,7 @@ static int compat_radeon_cp_texture(struct file *file, unsigned int cmd,
204 &image->data)) 201 &image->data))
205 return -EFAULT; 202 return -EFAULT;
206 203
207 return drm_ioctl(file->f_path.dentry->d_inode, file, 204 return drm_ioctl(file, DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request);
208 DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request);
209} 205}
210 206
211typedef struct drm_radeon_vertex2_32 { 207typedef struct drm_radeon_vertex2_32 {
@@ -238,8 +234,7 @@ static int compat_radeon_cp_vertex2(struct file *file, unsigned int cmd,
238 &request->prim)) 234 &request->prim))
239 return -EFAULT; 235 return -EFAULT;
240 236
241 return drm_ioctl(file->f_path.dentry->d_inode, file, 237 return drm_ioctl(file, DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request);
242 DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request);
243} 238}
244 239
245typedef struct drm_radeon_cmd_buffer32 { 240typedef struct drm_radeon_cmd_buffer32 {
@@ -268,8 +263,7 @@ static int compat_radeon_cp_cmdbuf(struct file *file, unsigned int cmd,
268 &request->boxes)) 263 &request->boxes))
269 return -EFAULT; 264 return -EFAULT;
270 265
271 return drm_ioctl(file->f_path.dentry->d_inode, file, 266 return drm_ioctl(file, DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request);
272 DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request);
273} 267}
274 268
275typedef struct drm_radeon_getparam32 { 269typedef struct drm_radeon_getparam32 {
@@ -293,8 +287,7 @@ static int compat_radeon_cp_getparam(struct file *file, unsigned int cmd,
293 &request->value)) 287 &request->value))
294 return -EFAULT; 288 return -EFAULT;
295 289
296 return drm_ioctl(file->f_path.dentry->d_inode, file, 290 return drm_ioctl(file, DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request);
297 DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request);
298} 291}
299 292
300typedef struct drm_radeon_mem_alloc32 { 293typedef struct drm_radeon_mem_alloc32 {
@@ -322,8 +315,7 @@ static int compat_radeon_mem_alloc(struct file *file, unsigned int cmd,
322 &request->region_offset)) 315 &request->region_offset))
323 return -EFAULT; 316 return -EFAULT;
324 317
325 return drm_ioctl(file->f_path.dentry->d_inode, file, 318 return drm_ioctl(file, DRM_IOCTL_RADEON_ALLOC, (unsigned long)request);
326 DRM_IOCTL_RADEON_ALLOC, (unsigned long)request);
327} 319}
328 320
329typedef struct drm_radeon_irq_emit32 { 321typedef struct drm_radeon_irq_emit32 {
@@ -345,8 +337,7 @@ static int compat_radeon_irq_emit(struct file *file, unsigned int cmd,
345 &request->irq_seq)) 337 &request->irq_seq))
346 return -EFAULT; 338 return -EFAULT;
347 339
348 return drm_ioctl(file->f_path.dentry->d_inode, file, 340 return drm_ioctl(file, DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request);
349 DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request);
350} 341}
351 342
352/* The two 64-bit arches where alignof(u64)==4 in 32-bit code */ 343/* The two 64-bit arches where alignof(u64)==4 in 32-bit code */
@@ -372,8 +363,7 @@ static int compat_radeon_cp_setparam(struct file *file, unsigned int cmd,
372 &request->value)) 363 &request->value))
373 return -EFAULT; 364 return -EFAULT;
374 365
375 return drm_ioctl(file->f_dentry->d_inode, file, 366 return drm_ioctl(file, DRM_IOCTL_RADEON_SETPARAM, (unsigned long) request);
376 DRM_IOCTL_RADEON_SETPARAM, (unsigned long) request);
377} 367}
378#else 368#else
379#define compat_radeon_cp_setparam NULL 369#define compat_radeon_cp_setparam NULL
@@ -413,12 +403,10 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
413 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(radeon_compat_ioctls)) 403 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(radeon_compat_ioctls))
414 fn = radeon_compat_ioctls[nr - DRM_COMMAND_BASE]; 404 fn = radeon_compat_ioctls[nr - DRM_COMMAND_BASE];
415 405
416 lock_kernel(); /* XXX for now */
417 if (fn != NULL) 406 if (fn != NULL)
418 ret = (*fn) (filp, cmd, arg); 407 ret = (*fn) (filp, cmd, arg);
419 else 408 else
420 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg); 409 ret = drm_ioctl(filp, cmd, arg);
421 unlock_kernel();
422 410
423 return ret; 411 return ret;
424} 412}
@@ -431,9 +419,7 @@ long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long
431 if (nr < DRM_COMMAND_BASE) 419 if (nr < DRM_COMMAND_BASE)
432 return drm_compat_ioctl(filp, cmd, arg); 420 return drm_compat_ioctl(filp, cmd, arg);
433 421
434 lock_kernel(); /* XXX for now */ 422 ret = drm_ioctl(filp, cmd, arg);
435 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
436 unlock_kernel();
437 423
438 return ret; 424 return ret;
439} 425}
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index b82ede98e152..cc27485a07ad 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -43,8 +43,7 @@ static void radeon_overscan_setup(struct drm_crtc *crtc,
43} 43}
44 44
45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46 struct drm_display_mode *mode, 46 struct drm_display_mode *mode)
47 struct drm_display_mode *adjusted_mode)
48{ 47{
49 struct drm_device *dev = crtc->dev; 48 struct drm_device *dev = crtc->dev;
50 struct radeon_device *rdev = dev->dev_private; 49 struct radeon_device *rdev = dev->dev_private;
@@ -1059,7 +1058,7 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1059 radeon_set_pll(crtc, adjusted_mode); 1058 radeon_set_pll(crtc, adjusted_mode);
1060 radeon_overscan_setup(crtc, adjusted_mode); 1059 radeon_overscan_setup(crtc, adjusted_mode);
1061 if (radeon_crtc->crtc_id == 0) { 1060 if (radeon_crtc->crtc_id == 0) {
1062 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); 1061 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1063 } else { 1062 } else {
1064 if (radeon_crtc->rmx_type != RMX_OFF) { 1063 if (radeon_crtc->rmx_type != RMX_OFF) {
1065 /* FIXME: only first crtc has rmx what should we 1064 /* FIXME: only first crtc has rmx what should we
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index df00515e81fa..981508ff7037 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -207,6 +207,8 @@ static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
207 *adjusted_mode = *native_mode; 207 *adjusted_mode = *native_mode;
208 adjusted_mode->hdisplay = mode->hdisplay; 208 adjusted_mode->hdisplay = mode->hdisplay;
209 adjusted_mode->vdisplay = mode->vdisplay; 209 adjusted_mode->vdisplay = mode->vdisplay;
210 adjusted_mode->crtc_hdisplay = mode->hdisplay;
211 adjusted_mode->crtc_vdisplay = mode->vdisplay;
210 adjusted_mode->base.id = mode_id; 212 adjusted_mode->base.id = mode_id;
211 } 213 }
212 214
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3dcbe130c422..402369db5ba0 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -88,6 +88,7 @@ enum radeon_tv_std {
88 TV_STD_SCART_PAL, 88 TV_STD_SCART_PAL,
89 TV_STD_SECAM, 89 TV_STD_SECAM,
90 TV_STD_PAL_CN, 90 TV_STD_PAL_CN,
91 TV_STD_PAL_N,
91}; 92};
92 93
93/* radeon gpio-based i2c 94/* radeon gpio-based i2c
@@ -395,6 +396,11 @@ struct radeon_framebuffer {
395 struct drm_gem_object *obj; 396 struct drm_gem_object *obj;
396}; 397};
397 398
399extern enum radeon_tv_std
400radeon_combios_get_tv_info(struct radeon_device *rdev);
401extern enum radeon_tv_std
402radeon_atombios_get_tv_info(struct radeon_device *rdev);
403
398extern void radeon_connector_hotplug(struct drm_connector *connector); 404extern void radeon_connector_hotplug(struct drm_connector *connector);
399extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 405extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
400extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 406extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 391c973ec4db..9f5e2f929da9 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -42,8 +42,8 @@ void radeon_test_moves(struct radeon_device *rdev)
42 /* Number of tests = 42 /* Number of tests =
43 * (Total GTT - IB pool - writeback page - ring buffer) / test size 43 * (Total GTT - IB pool - writeback page - ring buffer) / test size
44 */ 44 */
45 n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE - 45 n = ((u32)(rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE -
46 rdev->cp.ring_size) / size; 46 rdev->cp.ring_size)) / size;
47 47
48 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); 48 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
49 if (!gtt_obj) { 49 if (!gtt_obj) {
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index d7fd160cc671..3b0c07b444a2 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -494,6 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
494 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 494 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
495 return r; 495 return r;
496 } 496 }
497 rdev->mman.initialized = true;
497 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 498 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
498 rdev->mc.real_vram_size >> PAGE_SHIFT); 499 rdev->mc.real_vram_size >> PAGE_SHIFT);
499 if (r) { 500 if (r) {
@@ -541,6 +542,8 @@ void radeon_ttm_fini(struct radeon_device *rdev)
541{ 542{
542 int r; 543 int r;
543 544
545 if (!rdev->mman.initialized)
546 return;
544 if (rdev->stollen_vga_memory) { 547 if (rdev->stollen_vga_memory) {
545 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 548 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
546 if (r == 0) { 549 if (r == 0) {
@@ -554,6 +557,7 @@ void radeon_ttm_fini(struct radeon_device *rdev)
554 ttm_bo_device_release(&rdev->mman.bdev); 557 ttm_bo_device_release(&rdev->mman.bdev);
555 radeon_gart_fini(rdev); 558 radeon_gart_fini(rdev);
556 radeon_ttm_global_fini(rdev); 559 radeon_ttm_global_fini(rdev);
560 rdev->mman.initialized = false;
557 DRM_INFO("radeon: ttm finalized\n"); 561 DRM_INFO("radeon: ttm finalized\n");
558} 562}
559 563
diff --git a/drivers/gpu/drm/savage/savage_drv.c b/drivers/gpu/drm/savage/savage_drv.c
index eee52aa92a7c..021de44c15ab 100644
--- a/drivers/gpu/drm/savage/savage_drv.c
+++ b/drivers/gpu/drm/savage/savage_drv.c
@@ -50,7 +50,7 @@ static struct drm_driver driver = {
50 .owner = THIS_MODULE, 50 .owner = THIS_MODULE,
51 .open = drm_open, 51 .open = drm_open,
52 .release = drm_release, 52 .release = drm_release,
53 .ioctl = drm_ioctl, 53 .unlocked_ioctl = drm_ioctl,
54 .mmap = drm_mmap, 54 .mmap = drm_mmap,
55 .poll = drm_poll, 55 .poll = drm_poll,
56 .fasync = drm_fasync, 56 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c
index e725cc0b1155..4fd1f067d380 100644
--- a/drivers/gpu/drm/sis/sis_drv.c
+++ b/drivers/gpu/drm/sis/sis_drv.c
@@ -80,7 +80,7 @@ static struct drm_driver driver = {
80 .owner = THIS_MODULE, 80 .owner = THIS_MODULE,
81 .open = drm_open, 81 .open = drm_open,
82 .release = drm_release, 82 .release = drm_release,
83 .ioctl = drm_ioctl, 83 .unlocked_ioctl = drm_ioctl,
84 .mmap = drm_mmap, 84 .mmap = drm_mmap,
85 .poll = drm_poll, 85 .poll = drm_poll,
86 .fasync = drm_fasync, 86 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/tdfx/tdfx_drv.c b/drivers/gpu/drm/tdfx/tdfx_drv.c
index 012ff2e356b2..ec5a43e65722 100644
--- a/drivers/gpu/drm/tdfx/tdfx_drv.c
+++ b/drivers/gpu/drm/tdfx/tdfx_drv.c
@@ -48,7 +48,7 @@ static struct drm_driver driver = {
48 .owner = THIS_MODULE, 48 .owner = THIS_MODULE,
49 .open = drm_open, 49 .open = drm_open,
50 .release = drm_release, 50 .release = drm_release,
51 .ioctl = drm_ioctl, 51 .unlocked_ioctl = drm_ioctl,
52 .mmap = drm_mmap, 52 .mmap = drm_mmap,
53 .poll = drm_poll, 53 .poll = drm_poll,
54 .fasync = drm_fasync, 54 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_drv.c
index bc2f51843005..7a1b210401e0 100644
--- a/drivers/gpu/drm/via/via_drv.c
+++ b/drivers/gpu/drm/via/via_drv.c
@@ -58,7 +58,7 @@ static struct drm_driver driver = {
58 .owner = THIS_MODULE, 58 .owner = THIS_MODULE,
59 .open = drm_open, 59 .open = drm_open,
60 .release = drm_release, 60 .release = drm_release,
61 .ioctl = drm_ioctl, 61 .unlocked_ioctl = drm_ioctl,
62 .mmap = drm_mmap, 62 .mmap = drm_mmap,
63 .poll = drm_poll, 63 .poll = drm_poll,
64 .fasync = drm_fasync, 64 .fasync = drm_fasync,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 7b48bb3b63b2..1db1ef30be2b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -103,37 +103,39 @@
103 */ 103 */
104 104
105static struct drm_ioctl_desc vmw_ioctls[] = { 105static struct drm_ioctl_desc vmw_ioctls[] = {
106 VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 0), 106 VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl,
107 DRM_AUTH | DRM_UNLOCKED),
107 VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 108 VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
108 0), 109 DRM_AUTH | DRM_UNLOCKED),
109 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 110 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
110 0), 111 DRM_AUTH | DRM_UNLOCKED),
111 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS, 112 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS,
112 vmw_kms_cursor_bypass_ioctl, 0), 113 vmw_kms_cursor_bypass_ioctl,
114 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
113 115
114 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl, 116 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl,
115 0), 117 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
116 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 118 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
117 0), 119 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
118 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 120 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
119 0), 121 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
120 122
121 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 123 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
122 0), 124 DRM_AUTH | DRM_UNLOCKED),
123 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 125 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
124 0), 126 DRM_AUTH | DRM_UNLOCKED),
125 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 127 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
126 0), 128 DRM_AUTH | DRM_UNLOCKED),
127 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 129 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
128 0), 130 DRM_AUTH | DRM_UNLOCKED),
129 VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl, 131 VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl,
130 0), 132 DRM_AUTH | DRM_UNLOCKED),
131 VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl, 133 VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl,
132 0), 134 DRM_AUTH | DRM_UNLOCKED),
133 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl, 135 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
134 0), 136 DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
135 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl, 137 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
136 0) 138 DRM_AUTH | DRM_UNLOCKED)
137}; 139};
138 140
139static struct pci_device_id vmw_pci_id_list[] = { 141static struct pci_device_id vmw_pci_id_list[] = {
@@ -460,11 +462,9 @@ static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
460 struct drm_file *file_priv = filp->private_data; 462 struct drm_file *file_priv = filp->private_data;
461 struct drm_device *dev = file_priv->minor->dev; 463 struct drm_device *dev = file_priv->minor->dev;
462 unsigned int nr = DRM_IOCTL_NR(cmd); 464 unsigned int nr = DRM_IOCTL_NR(cmd);
463 long ret;
464 465
465 /* 466 /*
466 * The driver private ioctls and TTM ioctls should be 467 * Do extra checking on driver private ioctls.
467 * thread-safe.
468 */ 468 */
469 469
470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
@@ -477,18 +477,9 @@ static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
477 nr - DRM_COMMAND_BASE); 477 nr - DRM_COMMAND_BASE);
478 return -EINVAL; 478 return -EINVAL;
479 } 479 }
480 return drm_ioctl(filp->f_path.dentry->d_inode,
481 filp, cmd, arg);
482 } 480 }
483 481
484 /* 482 return drm_ioctl(filp, cmd, arg);
485 * Not all old drm ioctls are thread-safe.
486 */
487
488 lock_kernel();
489 ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
490 unlock_kernel();
491 return ret;
492} 483}
493 484
494static int vmw_firstopen(struct drm_device *dev) 485static int vmw_firstopen(struct drm_device *dev)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 43546d09d1b0..e61bd85b6975 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -123,6 +123,7 @@ struct vmw_sw_context{
123 uint32_t last_cid; 123 uint32_t last_cid;
124 bool cid_valid; 124 bool cid_valid;
125 uint32_t last_sid; 125 uint32_t last_sid;
126 uint32_t sid_translation;
126 bool sid_valid; 127 bool sid_valid;
127 struct ttm_object_file *tfile; 128 struct ttm_object_file *tfile;
128 struct list_head validate_nodes; 129 struct list_head validate_nodes;
@@ -317,9 +318,10 @@ extern void vmw_surface_res_free(struct vmw_resource *res);
317extern int vmw_surface_init(struct vmw_private *dev_priv, 318extern int vmw_surface_init(struct vmw_private *dev_priv,
318 struct vmw_surface *srf, 319 struct vmw_surface *srf,
319 void (*res_free) (struct vmw_resource *res)); 320 void (*res_free) (struct vmw_resource *res));
320extern int vmw_user_surface_lookup(struct vmw_private *dev_priv, 321extern int vmw_user_surface_lookup_handle(struct vmw_private *dev_priv,
321 struct ttm_object_file *tfile, 322 struct ttm_object_file *tfile,
322 int sid, struct vmw_surface **out); 323 uint32_t handle,
324 struct vmw_surface **out);
323extern int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data, 325extern int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data,
324 struct drm_file *file_priv); 326 struct drm_file *file_priv);
325extern int vmw_surface_define_ioctl(struct drm_device *dev, void *data, 327extern int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
@@ -328,7 +330,7 @@ extern int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
328 struct drm_file *file_priv); 330 struct drm_file *file_priv);
329extern int vmw_surface_check(struct vmw_private *dev_priv, 331extern int vmw_surface_check(struct vmw_private *dev_priv,
330 struct ttm_object_file *tfile, 332 struct ttm_object_file *tfile,
331 int id); 333 uint32_t handle, int *id);
332extern void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo); 334extern void vmw_dmabuf_bo_free(struct ttm_buffer_object *bo);
333extern int vmw_dmabuf_init(struct vmw_private *dev_priv, 335extern int vmw_dmabuf_init(struct vmw_private *dev_priv,
334 struct vmw_dma_buffer *vmw_bo, 336 struct vmw_dma_buffer *vmw_bo,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 7a39f3e6dc2c..2e92da567403 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -73,21 +73,32 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
73 73
74static int vmw_cmd_sid_check(struct vmw_private *dev_priv, 74static int vmw_cmd_sid_check(struct vmw_private *dev_priv,
75 struct vmw_sw_context *sw_context, 75 struct vmw_sw_context *sw_context,
76 uint32_t sid) 76 uint32_t *sid)
77{ 77{
78 if (unlikely((!sw_context->sid_valid || sid != sw_context->last_sid) && 78 if (*sid == SVGA3D_INVALID_ID)
79 sid != SVGA3D_INVALID_ID)) { 79 return 0;
80 int ret = vmw_surface_check(dev_priv, sw_context->tfile, sid); 80
81 if (unlikely((!sw_context->sid_valid ||
82 *sid != sw_context->last_sid))) {
83 int real_id;
84 int ret = vmw_surface_check(dev_priv, sw_context->tfile,
85 *sid, &real_id);
81 86
82 if (unlikely(ret != 0)) { 87 if (unlikely(ret != 0)) {
83 DRM_ERROR("Could ot find or use surface %u\n", 88 DRM_ERROR("Could ot find or use surface 0x%08x "
84 (unsigned) sid); 89 "address 0x%08lx\n",
90 (unsigned int) *sid,
91 (unsigned long) sid);
85 return ret; 92 return ret;
86 } 93 }
87 94
88 sw_context->last_sid = sid; 95 sw_context->last_sid = *sid;
89 sw_context->sid_valid = true; 96 sw_context->sid_valid = true;
90 } 97 *sid = real_id;
98 sw_context->sid_translation = real_id;
99 } else
100 *sid = sw_context->sid_translation;
101
91 return 0; 102 return 0;
92} 103}
93 104
@@ -107,7 +118,8 @@ static int vmw_cmd_set_render_target_check(struct vmw_private *dev_priv,
107 return ret; 118 return ret;
108 119
109 cmd = container_of(header, struct vmw_sid_cmd, header); 120 cmd = container_of(header, struct vmw_sid_cmd, header);
110 return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.target.sid); 121 ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.target.sid);
122 return ret;
111} 123}
112 124
113static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv, 125static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
@@ -121,10 +133,10 @@ static int vmw_cmd_surface_copy_check(struct vmw_private *dev_priv,
121 int ret; 133 int ret;
122 134
123 cmd = container_of(header, struct vmw_sid_cmd, header); 135 cmd = container_of(header, struct vmw_sid_cmd, header);
124 ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.src.sid); 136 ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
125 if (unlikely(ret != 0)) 137 if (unlikely(ret != 0))
126 return ret; 138 return ret;
127 return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.dest.sid); 139 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
128} 140}
129 141
130static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv, 142static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
@@ -138,10 +150,10 @@ static int vmw_cmd_stretch_blt_check(struct vmw_private *dev_priv,
138 int ret; 150 int ret;
139 151
140 cmd = container_of(header, struct vmw_sid_cmd, header); 152 cmd = container_of(header, struct vmw_sid_cmd, header);
141 ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.src.sid); 153 ret = vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.src.sid);
142 if (unlikely(ret != 0)) 154 if (unlikely(ret != 0))
143 return ret; 155 return ret;
144 return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.dest.sid); 156 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.dest.sid);
145} 157}
146 158
147static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv, 159static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
@@ -154,7 +166,7 @@ static int vmw_cmd_blt_surf_screen_check(struct vmw_private *dev_priv,
154 } *cmd; 166 } *cmd;
155 167
156 cmd = container_of(header, struct vmw_sid_cmd, header); 168 cmd = container_of(header, struct vmw_sid_cmd, header);
157 return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.srcImage.sid); 169 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.srcImage.sid);
158} 170}
159 171
160static int vmw_cmd_present_check(struct vmw_private *dev_priv, 172static int vmw_cmd_present_check(struct vmw_private *dev_priv,
@@ -167,7 +179,7 @@ static int vmw_cmd_present_check(struct vmw_private *dev_priv,
167 } *cmd; 179 } *cmd;
168 180
169 cmd = container_of(header, struct vmw_sid_cmd, header); 181 cmd = container_of(header, struct vmw_sid_cmd, header);
170 return vmw_cmd_sid_check(dev_priv, sw_context, cmd->body.sid); 182 return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid);
171} 183}
172 184
173static int vmw_cmd_dma(struct vmw_private *dev_priv, 185static int vmw_cmd_dma(struct vmw_private *dev_priv,
@@ -187,12 +199,7 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
187 uint32_t cur_validate_node; 199 uint32_t cur_validate_node;
188 struct ttm_validate_buffer *val_buf; 200 struct ttm_validate_buffer *val_buf;
189 201
190
191 cmd = container_of(header, struct vmw_dma_cmd, header); 202 cmd = container_of(header, struct vmw_dma_cmd, header);
192 ret = vmw_cmd_sid_check(dev_priv, sw_context, cmd->dma.host.sid);
193 if (unlikely(ret != 0))
194 return ret;
195
196 handle = cmd->dma.guest.ptr.gmrId; 203 handle = cmd->dma.guest.ptr.gmrId;
197 ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo); 204 ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo);
198 if (unlikely(ret != 0)) { 205 if (unlikely(ret != 0)) {
@@ -228,14 +235,23 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
228 ++sw_context->cur_val_buf; 235 ++sw_context->cur_val_buf;
229 } 236 }
230 237
231 ret = vmw_user_surface_lookup(dev_priv, sw_context->tfile, 238 ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
232 cmd->dma.host.sid, &srf); 239 cmd->dma.host.sid, &srf);
233 if (ret) { 240 if (ret) {
234 DRM_ERROR("could not find surface\n"); 241 DRM_ERROR("could not find surface\n");
235 goto out_no_reloc; 242 goto out_no_reloc;
236 } 243 }
237 244
245 /**
246 * Patch command stream with device SID.
247 */
248
249 cmd->dma.host.sid = srf->res.id;
238 vmw_kms_cursor_snoop(srf, sw_context->tfile, bo, header); 250 vmw_kms_cursor_snoop(srf, sw_context->tfile, bo, header);
251 /**
252 * FIXME: May deadlock here when called from the
253 * command parsing code.
254 */
239 vmw_surface_unreference(&srf); 255 vmw_surface_unreference(&srf);
240 256
241out_no_reloc: 257out_no_reloc:
@@ -243,6 +259,90 @@ out_no_reloc:
243 return ret; 259 return ret;
244} 260}
245 261
262static int vmw_cmd_draw(struct vmw_private *dev_priv,
263 struct vmw_sw_context *sw_context,
264 SVGA3dCmdHeader *header)
265{
266 struct vmw_draw_cmd {
267 SVGA3dCmdHeader header;
268 SVGA3dCmdDrawPrimitives body;
269 } *cmd;
270 SVGA3dVertexDecl *decl = (SVGA3dVertexDecl *)(
271 (unsigned long)header + sizeof(*cmd));
272 SVGA3dPrimitiveRange *range;
273 uint32_t i;
274 uint32_t maxnum;
275 int ret;
276
277 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
278 if (unlikely(ret != 0))
279 return ret;
280
281 cmd = container_of(header, struct vmw_draw_cmd, header);
282 maxnum = (header->size - sizeof(cmd->body)) / sizeof(*decl);
283
284 if (unlikely(cmd->body.numVertexDecls > maxnum)) {
285 DRM_ERROR("Illegal number of vertex declarations.\n");
286 return -EINVAL;
287 }
288
289 for (i = 0; i < cmd->body.numVertexDecls; ++i, ++decl) {
290 ret = vmw_cmd_sid_check(dev_priv, sw_context,
291 &decl->array.surfaceId);
292 if (unlikely(ret != 0))
293 return ret;
294 }
295
296 maxnum = (header->size - sizeof(cmd->body) -
297 cmd->body.numVertexDecls * sizeof(*decl)) / sizeof(*range);
298 if (unlikely(cmd->body.numRanges > maxnum)) {
299 DRM_ERROR("Illegal number of index ranges.\n");
300 return -EINVAL;
301 }
302
303 range = (SVGA3dPrimitiveRange *) decl;
304 for (i = 0; i < cmd->body.numRanges; ++i, ++range) {
305 ret = vmw_cmd_sid_check(dev_priv, sw_context,
306 &range->indexArray.surfaceId);
307 if (unlikely(ret != 0))
308 return ret;
309 }
310 return 0;
311}
312
313
314static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
315 struct vmw_sw_context *sw_context,
316 SVGA3dCmdHeader *header)
317{
318 struct vmw_tex_state_cmd {
319 SVGA3dCmdHeader header;
320 SVGA3dCmdSetTextureState state;
321 };
322
323 SVGA3dTextureState *last_state = (SVGA3dTextureState *)
324 ((unsigned long) header + header->size + sizeof(header));
325 SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
326 ((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
327 int ret;
328
329 ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
330 if (unlikely(ret != 0))
331 return ret;
332
333 for (; cur_state < last_state; ++cur_state) {
334 if (likely(cur_state->name != SVGA3D_TS_BIND_TEXTURE))
335 continue;
336
337 ret = vmw_cmd_sid_check(dev_priv, sw_context,
338 &cur_state->value);
339 if (unlikely(ret != 0))
340 return ret;
341 }
342
343 return 0;
344}
345
246 346
247typedef int (*vmw_cmd_func) (struct vmw_private *, 347typedef int (*vmw_cmd_func) (struct vmw_private *,
248 struct vmw_sw_context *, 348 struct vmw_sw_context *,
@@ -264,7 +364,7 @@ static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
264 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check), 364 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERSTATE, &vmw_cmd_cid_check),
265 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET, 365 VMW_CMD_DEF(SVGA_3D_CMD_SETRENDERTARGET,
266 &vmw_cmd_set_render_target_check), 366 &vmw_cmd_set_render_target_check),
267 VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_cid_check), 367 VMW_CMD_DEF(SVGA_3D_CMD_SETTEXTURESTATE, &vmw_cmd_tex_state),
268 VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check), 368 VMW_CMD_DEF(SVGA_3D_CMD_SETMATERIAL, &vmw_cmd_cid_check),
269 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check), 369 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTDATA, &vmw_cmd_cid_check),
270 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check), 370 VMW_CMD_DEF(SVGA_3D_CMD_SETLIGHTENABLED, &vmw_cmd_cid_check),
@@ -276,7 +376,7 @@ static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
276 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_cid_check), 376 VMW_CMD_DEF(SVGA_3D_CMD_SHADER_DESTROY, &vmw_cmd_cid_check),
277 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_cid_check), 377 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER, &vmw_cmd_cid_check),
278 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_cid_check), 378 VMW_CMD_DEF(SVGA_3D_CMD_SET_SHADER_CONST, &vmw_cmd_cid_check),
279 VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_cid_check), 379 VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw),
280 VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check), 380 VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check),
281 VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check), 381 VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check),
282 VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_cid_check), 382 VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_cid_check),
@@ -291,6 +391,7 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
291 void *buf, uint32_t *size) 391 void *buf, uint32_t *size)
292{ 392{
293 uint32_t cmd_id; 393 uint32_t cmd_id;
394 uint32_t size_remaining = *size;
294 SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf; 395 SVGA3dCmdHeader *header = (SVGA3dCmdHeader *) buf;
295 int ret; 396 int ret;
296 397
@@ -304,6 +405,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
304 *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader); 405 *size = le32_to_cpu(header->size) + sizeof(SVGA3dCmdHeader);
305 406
306 cmd_id -= SVGA_3D_CMD_BASE; 407 cmd_id -= SVGA_3D_CMD_BASE;
408 if (unlikely(*size > size_remaining))
409 goto out_err;
410
307 if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)) 411 if (unlikely(cmd_id >= SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE))
308 goto out_err; 412 goto out_err;
309 413
@@ -326,6 +430,7 @@ static int vmw_cmd_check_all(struct vmw_private *dev_priv,
326 int ret; 430 int ret;
327 431
328 while (cur_size > 0) { 432 while (cur_size > 0) {
433 size = cur_size;
329 ret = vmw_cmd_check(dev_priv, sw_context, buf, &size); 434 ret = vmw_cmd_check(dev_priv, sw_context, buf, &size);
330 if (unlikely(ret != 0)) 435 if (unlikely(ret != 0))
331 return ret; 436 return ret;
@@ -386,7 +491,7 @@ static int vmw_validate_single_buffer(struct vmw_private *dev_priv,
386 return 0; 491 return 0;
387 492
388 ret = vmw_gmr_bind(dev_priv, bo); 493 ret = vmw_gmr_bind(dev_priv, bo);
389 if (likely(ret == 0 || ret == -ERESTART)) 494 if (likely(ret == 0 || ret == -ERESTARTSYS))
390 return ret; 495 return ret;
391 496
392 497
@@ -429,7 +534,7 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
429 534
430 ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex); 535 ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
431 if (unlikely(ret != 0)) { 536 if (unlikely(ret != 0)) {
432 ret = -ERESTART; 537 ret = -ERESTARTSYS;
433 goto out_no_cmd_mutex; 538 goto out_no_cmd_mutex;
434 } 539 }
435 540
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index 76b0693e2458..01feb48af333 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -191,7 +191,7 @@ static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
191 } 191 }
192 schedule_timeout(1); 192 schedule_timeout(1);
193 if (interruptible && signal_pending(current)) { 193 if (interruptible && signal_pending(current)) {
194 ret = -ERESTART; 194 ret = -ERESTARTSYS;
195 break; 195 break;
196 } 196 }
197 } 197 }
@@ -237,9 +237,7 @@ static int vmw_fifo_wait(struct vmw_private *dev_priv,
237 (dev_priv->fifo_queue, 237 (dev_priv->fifo_queue,
238 !vmw_fifo_is_full(dev_priv, bytes), timeout); 238 !vmw_fifo_is_full(dev_priv, bytes), timeout);
239 239
240 if (unlikely(ret == -ERESTARTSYS)) 240 if (unlikely(ret == 0))
241 ret = -ERESTART;
242 else if (unlikely(ret == 0))
243 ret = -EBUSY; 241 ret = -EBUSY;
244 else if (likely(ret > 0)) 242 else if (likely(ret > 0))
245 ret = 0; 243 ret = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
index 9e0f0306eedb..d40086fc8647 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c
@@ -155,7 +155,7 @@ int vmw_fallback_wait(struct vmw_private *dev_priv,
155 TASK_UNINTERRUPTIBLE); 155 TASK_UNINTERRUPTIBLE);
156 } 156 }
157 if (interruptible && signal_pending(current)) { 157 if (interruptible && signal_pending(current)) {
158 ret = -ERESTART; 158 ret = -ERESTARTSYS;
159 break; 159 break;
160 } 160 }
161 } 161 }
@@ -218,9 +218,7 @@ int vmw_wait_fence(struct vmw_private *dev_priv,
218 vmw_fence_signaled(dev_priv, sequence), 218 vmw_fence_signaled(dev_priv, sequence),
219 timeout); 219 timeout);
220 220
221 if (unlikely(ret == -ERESTARTSYS)) 221 if (unlikely(ret == 0))
222 ret = -ERESTART;
223 else if (unlikely(ret == 0))
224 ret = -EBUSY; 222 ret = -EBUSY;
225 else if (likely(ret > 0)) 223 else if (likely(ret > 0))
226 ret = 0; 224 ret = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index e9403be446fe..b1af76e371c3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -106,8 +106,8 @@ int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
106 int ret; 106 int ret;
107 107
108 if (handle) { 108 if (handle) {
109 ret = vmw_user_surface_lookup(dev_priv, tfile, 109 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110 handle, &surface); 110 handle, &surface);
111 if (!ret) { 111 if (!ret) {
112 if (!surface->snooper.image) { 112 if (!surface->snooper.image) {
113 DRM_ERROR("surface not suitable for cursor\n"); 113 DRM_ERROR("surface not suitable for cursor\n");
@@ -704,8 +704,8 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
704 struct vmw_dma_buffer *bo = NULL; 704 struct vmw_dma_buffer *bo = NULL;
705 int ret; 705 int ret;
706 706
707 ret = vmw_user_surface_lookup(dev_priv, tfile, 707 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
708 mode_cmd->handle, &surface); 708 mode_cmd->handle, &surface);
709 if (ret) 709 if (ret)
710 goto try_dmabuf; 710 goto try_dmabuf;
711 711
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index a1ceed0c8e07..c012d5927f65 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -488,28 +488,44 @@ static void vmw_user_surface_free(struct vmw_resource *res)
488 kfree(user_srf); 488 kfree(user_srf);
489} 489}
490 490
491int vmw_user_surface_lookup(struct vmw_private *dev_priv, 491int vmw_user_surface_lookup_handle(struct vmw_private *dev_priv,
492 struct ttm_object_file *tfile, 492 struct ttm_object_file *tfile,
493 int sid, struct vmw_surface **out) 493 uint32_t handle, struct vmw_surface **out)
494{ 494{
495 struct vmw_resource *res; 495 struct vmw_resource *res;
496 struct vmw_surface *srf; 496 struct vmw_surface *srf;
497 struct vmw_user_surface *user_srf; 497 struct vmw_user_surface *user_srf;
498 struct ttm_base_object *base;
499 int ret = -EINVAL;
498 500
499 res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, sid); 501 base = ttm_base_object_lookup(tfile, handle);
500 if (unlikely(res == NULL)) 502 if (unlikely(base == NULL))
501 return -EINVAL; 503 return -EINVAL;
502 504
503 if (res->res_free != &vmw_user_surface_free) 505 if (unlikely(base->object_type != VMW_RES_SURFACE))
504 return -EINVAL; 506 goto out_bad_resource;
505 507
506 srf = container_of(res, struct vmw_surface, res); 508 user_srf = container_of(base, struct vmw_user_surface, base);
507 user_srf = container_of(srf, struct vmw_user_surface, srf); 509 srf = &user_srf->srf;
508 if (user_srf->base.tfile != tfile && !user_srf->base.shareable) 510 res = &srf->res;
509 return -EPERM; 511
512 read_lock(&dev_priv->resource_lock);
513
514 if (!res->avail || res->res_free != &vmw_user_surface_free) {
515 read_unlock(&dev_priv->resource_lock);
516 goto out_bad_resource;
517 }
518
519 kref_get(&res->kref);
520 read_unlock(&dev_priv->resource_lock);
510 521
511 *out = srf; 522 *out = srf;
512 return 0; 523 ret = 0;
524
525out_bad_resource:
526 ttm_base_object_unref(&base);
527
528 return ret;
513} 529}
514 530
515static void vmw_user_surface_base_release(struct ttm_base_object **p_base) 531static void vmw_user_surface_base_release(struct ttm_base_object **p_base)
@@ -526,35 +542,10 @@ static void vmw_user_surface_base_release(struct ttm_base_object **p_base)
526int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data, 542int vmw_surface_destroy_ioctl(struct drm_device *dev, void *data,
527 struct drm_file *file_priv) 543 struct drm_file *file_priv)
528{ 544{
529 struct vmw_private *dev_priv = vmw_priv(dev);
530 struct vmw_resource *res;
531 struct vmw_surface *srf;
532 struct vmw_user_surface *user_srf;
533 struct drm_vmw_surface_arg *arg = (struct drm_vmw_surface_arg *)data; 545 struct drm_vmw_surface_arg *arg = (struct drm_vmw_surface_arg *)data;
534 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; 546 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
535 int ret = 0;
536
537 res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, arg->sid);
538 if (unlikely(res == NULL))
539 return -EINVAL;
540
541 if (res->res_free != &vmw_user_surface_free) {
542 ret = -EINVAL;
543 goto out;
544 }
545 547
546 srf = container_of(res, struct vmw_surface, res); 548 return ttm_ref_object_base_unref(tfile, arg->sid, TTM_REF_USAGE);
547 user_srf = container_of(srf, struct vmw_user_surface, srf);
548 if (user_srf->base.tfile != tfile && !user_srf->base.shareable) {
549 ret = -EPERM;
550 goto out;
551 }
552
553 ttm_ref_object_base_unref(tfile, user_srf->base.hash.key,
554 TTM_REF_USAGE);
555out:
556 vmw_resource_unreference(&res);
557 return ret;
558} 549}
559 550
560int vmw_surface_define_ioctl(struct drm_device *dev, void *data, 551int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
@@ -649,7 +640,10 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
649 } 640 }
650 srf->snooper.crtc = NULL; 641 srf->snooper.crtc = NULL;
651 642
652 rep->sid = res->id; 643 rep->sid = user_srf->base.hash.key;
644 if (rep->sid == SVGA3D_INVALID_ID)
645 DRM_ERROR("Created bad Surface ID.\n");
646
653 vmw_resource_unreference(&res); 647 vmw_resource_unreference(&res);
654 return 0; 648 return 0;
655out_err1: 649out_err1:
@@ -662,39 +656,33 @@ out_err0:
662int vmw_surface_reference_ioctl(struct drm_device *dev, void *data, 656int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
663 struct drm_file *file_priv) 657 struct drm_file *file_priv)
664{ 658{
665 struct vmw_private *dev_priv = vmw_priv(dev);
666 union drm_vmw_surface_reference_arg *arg = 659 union drm_vmw_surface_reference_arg *arg =
667 (union drm_vmw_surface_reference_arg *)data; 660 (union drm_vmw_surface_reference_arg *)data;
668 struct drm_vmw_surface_arg *req = &arg->req; 661 struct drm_vmw_surface_arg *req = &arg->req;
669 struct drm_vmw_surface_create_req *rep = &arg->rep; 662 struct drm_vmw_surface_create_req *rep = &arg->rep;
670 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; 663 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
671 struct vmw_resource *res;
672 struct vmw_surface *srf; 664 struct vmw_surface *srf;
673 struct vmw_user_surface *user_srf; 665 struct vmw_user_surface *user_srf;
674 struct drm_vmw_size __user *user_sizes; 666 struct drm_vmw_size __user *user_sizes;
675 int ret; 667 struct ttm_base_object *base;
668 int ret = -EINVAL;
676 669
677 res = vmw_resource_lookup(dev_priv, &dev_priv->surface_idr, req->sid); 670 base = ttm_base_object_lookup(tfile, req->sid);
678 if (unlikely(res == NULL)) 671 if (unlikely(base == NULL)) {
672 DRM_ERROR("Could not find surface to reference.\n");
679 return -EINVAL; 673 return -EINVAL;
680
681 if (res->res_free != &vmw_user_surface_free) {
682 ret = -EINVAL;
683 goto out;
684 } 674 }
685 675
686 srf = container_of(res, struct vmw_surface, res); 676 if (unlikely(base->object_type != VMW_RES_SURFACE))
687 user_srf = container_of(srf, struct vmw_user_surface, srf); 677 goto out_bad_resource;
688 if (user_srf->base.tfile != tfile && !user_srf->base.shareable) { 678
689 DRM_ERROR("Tried to reference none shareable surface\n"); 679 user_srf = container_of(base, struct vmw_user_surface, base);
690 ret = -EPERM; 680 srf = &user_srf->srf;
691 goto out;
692 }
693 681
694 ret = ttm_ref_object_add(tfile, &user_srf->base, TTM_REF_USAGE, NULL); 682 ret = ttm_ref_object_add(tfile, &user_srf->base, TTM_REF_USAGE, NULL);
695 if (unlikely(ret != 0)) { 683 if (unlikely(ret != 0)) {
696 DRM_ERROR("Could not add a reference to a surface.\n"); 684 DRM_ERROR("Could not add a reference to a surface.\n");
697 goto out; 685 goto out_no_reference;
698 } 686 }
699 687
700 rep->flags = srf->flags; 688 rep->flags = srf->flags;
@@ -706,40 +694,43 @@ int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
706 if (user_sizes) 694 if (user_sizes)
707 ret = copy_to_user(user_sizes, srf->sizes, 695 ret = copy_to_user(user_sizes, srf->sizes,
708 srf->num_sizes * sizeof(*srf->sizes)); 696 srf->num_sizes * sizeof(*srf->sizes));
709 if (unlikely(ret != 0)) { 697 if (unlikely(ret != 0))
710 DRM_ERROR("copy_to_user failed %p %u\n", 698 DRM_ERROR("copy_to_user failed %p %u\n",
711 user_sizes, srf->num_sizes); 699 user_sizes, srf->num_sizes);
712 /** 700out_bad_resource:
713 * FIXME: Unreference surface here? 701out_no_reference:
714 */ 702 ttm_base_object_unref(&base);
715 goto out; 703
716 }
717out:
718 vmw_resource_unreference(&res);
719 return ret; 704 return ret;
720} 705}
721 706
722int vmw_surface_check(struct vmw_private *dev_priv, 707int vmw_surface_check(struct vmw_private *dev_priv,
723 struct ttm_object_file *tfile, 708 struct ttm_object_file *tfile,
724 int id) 709 uint32_t handle, int *id)
725{ 710{
726 struct vmw_resource *res; 711 struct ttm_base_object *base;
727 int ret = 0; 712 struct vmw_user_surface *user_srf;
728 713
729 read_lock(&dev_priv->resource_lock); 714 int ret = -EPERM;
730 res = idr_find(&dev_priv->surface_idr, id);
731 if (res && res->avail) {
732 struct vmw_surface *srf =
733 container_of(res, struct vmw_surface, res);
734 struct vmw_user_surface *usrf =
735 container_of(srf, struct vmw_user_surface, srf);
736 715
737 if (usrf->base.tfile != tfile && !usrf->base.shareable) 716 base = ttm_base_object_lookup(tfile, handle);
738 ret = -EPERM; 717 if (unlikely(base == NULL))
739 } else 718 return -EINVAL;
740 ret = -EINVAL; 719
741 read_unlock(&dev_priv->resource_lock); 720 if (unlikely(base->object_type != VMW_RES_SURFACE))
721 goto out_bad_surface;
742 722
723 user_srf = container_of(base, struct vmw_user_surface, base);
724 *id = user_srf->srf.res.id;
725 ret = 0;
726
727out_bad_surface:
728 /**
729 * FIXME: May deadlock here when called from the
730 * command parsing code.
731 */
732
733 ttm_base_object_unref(&base);
743 return ret; 734 return ret;
744} 735}
745 736
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 21:10:34 -0500