30 files changed, 314 insertions, 65 deletions

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index eb92fe257a39..5873e481e5d2 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -610,7 +610,7 @@ static bool
 drm_monitor_supports_rb(struct edid *edid)
 {
         if (edid->revision >= 4) {
-                bool ret;
+                bool ret = false;
                 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
                 return ret;
         }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1fe0edda955..ed3224c37423 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -412,7 +412,6 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
          */
 
         spin_lock_irqsave(&dev_priv->rps_lock, flags);
-        WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
         dev_priv->pm_iir |= pm_iir;
         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
         POSTING_READ(GEN6_PMIMR);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0ede02a99d91..a748e5cabe14 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -740,8 +740,11 @@ static void i915_restore_display(struct drm_device *dev)
         if (HAS_PCH_SPLIT(dev)) {
                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
-                I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
+                /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
+                 * otherwise we get blank eDP screen after S3 on some machines
+                 */
                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
+                I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e0aa064def31..a8538ac0299d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6558,7 +6558,7 @@ static void intel_setup_outputs(struct drm_device *dev)
                 if (I915_READ(HDMIC) & PORT_DETECTED)
                         intel_hdmi_init(dev, HDMIC);
 
-                if (I915_READ(HDMID) & PORT_DETECTED)
+                if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
                         intel_hdmi_init(dev, HDMID);
 
                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
@@ -6921,19 +6921,6 @@ static void i915_disable_vga(struct drm_device *dev)
         POSTING_READ(vga_reg);
 }
 
-static void ivb_pch_pwm_override(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        /*
-         * IVB has CPU eDP backlight regs too, set things up to let the
-         * PCH regs control the backlight
-         */
-        I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
-        I915_WRITE(BLC_PWM_CPU_CTL, 0);
-        I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
-}
-
 void intel_modeset_init_hw(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6950,9 +6937,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
                 gen6_enable_rps(dev_priv);
                 gen6_update_ring_freq(dev_priv);
         }
-
-        if (IS_IVYBRIDGE(dev))
-                ivb_pch_pwm_override(dev);
 }
 
 void intel_modeset_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 296cfc201a81..c0449324143c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -32,6 +32,7 @@
 #include "drm.h"
 #include "drm_crtc.h"
 #include "drm_crtc_helper.h"
+#include "drm_edid.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
@@ -67,6 +68,8 @@ struct intel_dp {
         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
         struct delayed_work panel_vdd_work;
         bool want_panel_vdd;
+        struct edid *edid; /* cached EDID for eDP */
+        int edid_mode_count;
 };
 
 /**
@@ -371,7 +374,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         int recv_bytes;
         uint32_t status;
         uint32_t aux_clock_divider;
-        int try, precharge = 5;
+        int try, precharge;
 
         intel_dp_check_edp(intel_dp);
         /* The clock divider is based off the hrawclk,
@@ -391,6 +394,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         else
                 aux_clock_divider = intel_hrawclk(dev) / 2;
 
+        if (IS_GEN6(dev))
+                precharge = 3;
+        else
+                precharge = 5;
+
         /* Try to wait for any previous AUX channel activity */
         for (try = 0; try < 3; try++) {
                 status = I915_READ(ch_ctl);
@@ -1973,6 +1981,8 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
                 return;
 
+        ironlake_edp_panel_vdd_on(intel_dp);
+
         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
                               buf[0], buf[1], buf[2]);
@@ -1980,6 +1990,8 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
                               buf[0], buf[1], buf[2]);
+
+        ironlake_edp_panel_vdd_off(intel_dp, false);
 }
 
 static bool
@@ -2116,10 +2128,22 @@ intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
 {
         struct intel_dp *intel_dp = intel_attached_dp(connector);
         struct edid     *edid;
+        int size;
+
+        if (is_edp(intel_dp)) {
+                if (!intel_dp->edid)
+                        return NULL;
+
+                size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
+                edid = kmalloc(size, GFP_KERNEL);
+                if (!edid)
+                        return NULL;
+
+                memcpy(edid, intel_dp->edid, size);
+                return edid;
+        }
 
-        ironlake_edp_panel_vdd_on(intel_dp);
         edid = drm_get_edid(connector, adapter);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
         return edid;
 }
 
@@ -2129,9 +2153,17 @@ intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *ada
         struct intel_dp *intel_dp = intel_attached_dp(connector);
         int     ret;
 
-        ironlake_edp_panel_vdd_on(intel_dp);
+        if (is_edp(intel_dp)) {
+                drm_mode_connector_update_edid_property(connector,
+                                                        intel_dp->edid);
+                ret = drm_add_edid_modes(connector, intel_dp->edid);
+                drm_edid_to_eld(connector,
+                                intel_dp->edid);
+                connector->display_info.raw_edid = NULL;
+                return intel_dp->edid_mode_count;
+        }
+
         ret = intel_ddc_get_modes(connector, adapter);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
         return ret;
 }
 
@@ -2321,6 +2353,7 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
         i2c_del_adapter(&intel_dp->adapter);
         drm_encoder_cleanup(encoder);
         if (is_edp(intel_dp)) {
+                kfree(intel_dp->edid);
                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
                 ironlake_panel_vdd_off_sync(intel_dp);
         }
@@ -2504,11 +2537,14 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                         break;
         }
 
+        intel_dp_i2c_init(intel_dp, intel_connector, name);
+
         /* Cache some DPCD data in the eDP case */
         if (is_edp(intel_dp)) {
                 bool ret;
                 struct edp_power_seq    cur, vbt;
                 u32 pp_on, pp_off, pp_div;
+                struct edid *edid;
 
                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
@@ -2576,9 +2612,19 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                         intel_dp_destroy(&intel_connector->base);
                         return;
                 }
-        }
 
-        intel_dp_i2c_init(intel_dp, intel_connector, name);
+                ironlake_edp_panel_vdd_on(intel_dp);
+                edid = drm_get_edid(connector, &intel_dp->adapter);
+                if (edid) {
+                        drm_mode_connector_update_edid_property(connector,
+                                                                edid);
+                        intel_dp->edid_mode_count =
+                                drm_add_edid_modes(connector, edid);
+                        drm_edid_to_eld(connector, edid);
+                        intel_dp->edid = edid;
+                }
+                ironlake_edp_panel_vdd_off(intel_dp, false);
+        }
 
         intel_encoder->hot_plug = intel_dp_hot_plug;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 153b9a15469b..1074bc5dd418 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -467,7 +467,7 @@ int nouveau_fbcon_init(struct drm_device *dev)
         nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
 
         ret = drm_fb_helper_init(dev, &nfbdev->helper,
-                                 nv_two_heads(dev) ? 2 : 1, 4);
+                                 dev->mode_config.num_crtc, 4);
         if (ret) {
                 kfree(nfbdev);
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index a89240e5fb29..a25cf2cb931f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -1,3 +1,26 @@
+/*
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ */
 
 #include "drmP.h"
 #include "drm.h"
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 01d77d1554f4..3904d7964a4b 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         }
 
         if (tiling_flags & RADEON_TILING_MACRO) {
-                if (rdev->family >= CHIP_CAYMAN)
+                if (rdev->family >= CHIP_TAHITI)
+                        tmp = rdev->config.si.tile_config;
+                else if (rdev->family >= CHIP_CAYMAN)
                         tmp = rdev->config.cayman.tile_config;
                 else
                         tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         } else if (tiling_flags & RADEON_TILING_MICRO)
                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 
+        if ((rdev->family == CHIP_TAHITI) ||
+            (rdev->family == CHIP_PITCAIRN))
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
+        else if (rdev->family == CHIP_VERDE)
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
+
         switch (radeon_crtc->crtc_id) {
         case 0:
                 WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index e7b1ec5ae8c6..486ccdf4aacd 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1926,7 +1926,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 
         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
                 r600_hdmi_enable(encoder);
-                if (ASIC_IS_DCE4(rdev))
+                if (ASIC_IS_DCE6(rdev))
+                        ; /* TODO (use pointers instead of if-s?) */
+                else if (ASIC_IS_DCE4(rdev))
                         evergreen_hdmi_setmode(encoder, adjusted_mode);
                 else
                         r600_hdmi_setmode(encoder, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 01550d05e273..7fb3d2e0434c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 
+        if (rdev->family <= CHIP_SUMO2)
+                WREG32(SMX_SAR_CTL0, 0x00010000);
+
         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b4843d..c16554122ccd 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
         u32                     cb_color_view[12];
         u32                     cb_color_pitch[12];
         u32                     cb_color_slice[12];
+        u32                     cb_color_slice_idx[12];
         u32                     cb_color_attrib[12];
         u32                     cb_color_cmask_slice[8];/* unused */
         u32                     cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
                 track->cb_color_info[i] = 0;
                 track->cb_color_view[i] = 0xFFFFFFFF;
                 track->cb_color_pitch[i] = 0;
-                track->cb_color_slice[i] = 0;
+                track->cb_color_slice[i] = 0xfffffff;
+                track->cb_color_slice_idx[i] = 0;
         }
         track->cb_target_mask = 0xFFFFFFFF;
         track->cb_shader_mask = 0xFFFFFFFF;
         track->cb_dirty = true;
 
+        track->db_depth_slice = 0xffffffff;
         track->db_depth_view = 0xFFFFC000;
         track->db_depth_size = 0xFFFFFFFF;
         track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
 {
         struct evergreen_cs_track *track = p->track;
         unsigned palign, halign, tileb, slice_pt;
+        unsigned mtile_pr, mtile_ps, mtileb;
 
         tileb = 64 * surf->bpe * surf->nsamples;
-        palign = track->group_size / (8 * surf->bpe * surf->nsamples);
-        palign = MAX(8, palign);
         slice_pt = 1;
         if (tileb > surf->tsplit) {
                 slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
         /* macro tile width & height */
         palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
         halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
-        surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
+        mtileb = (palign / 8) * (halign / 8) * tileb;;
+        mtile_pr = surf->nbx / palign;
+        mtile_ps = (mtile_pr * surf->nby) / halign;
+        surf->layer_size = mtile_ps * mtileb * slice_pt;
         surf->base_align = (palign / 8) * (halign / 8) * tileb;
         surf->palign = palign;
         surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
 
         offset += surf.layer_size * mslice;
         if (offset > radeon_bo_size(track->cb_color_bo[id])) {
+                /* old ddx are broken they allocate bo with w*h*bpp but
+                 * program slice with ALIGN(h, 8), catch this and patch
+                 * command stream.
+                 */
+                if (!surf.mode) {
+                        volatile u32 *ib = p->ib.ptr;
+                        unsigned long tmp, nby, bsize, size, min = 0;
+
+                        /* find the height the ddx wants */
+                        if (surf.nby > 8) {
+                                min = surf.nby - 8;
+                        }
+                        bsize = radeon_bo_size(track->cb_color_bo[id]);
+                        tmp = track->cb_color_bo_offset[id] << 8;
+                        for (nby = surf.nby; nby > min; nby--) {
+                                size = nby * surf.nbx * surf.bpe * surf.nsamples;
+                                if ((tmp + size * mslice) <= bsize) {
+                                        break;
+                                }
+                        }
+                        if (nby > min) {
+                                surf.nby = nby;
+                                slice = ((nby * surf.nbx) / 64) - 1;
+                                if (!evergreen_surface_check(p, &surf, "cb")) {
+                                        /* check if this one works */
+                                        tmp += surf.layer_size * mslice;
+                                        if (tmp <= bsize) {
+                                                ib[track->cb_color_slice_idx[id]] = slice;
+                                                goto old_ddx_ok;
+                                        }
+                                }
+                        }
+                }
                 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
                          "offset %d, max layer %d, bo size %ld, slice %d)\n",
                          __func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
                         surf.tsplit, surf.mtilea);
                 return -EINVAL;
         }
+old_ddx_ok:
 
         return 0;
 }
@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR7_SLICE:
                 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+                track->cb_color_slice_idx[tmp] = idx;
                 track->cb_dirty = true;
                 break;
         case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR11_SLICE:
                 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+                track->cb_color_slice_idx[tmp] = idx;
                 track->cb_dirty = true;
                 break;
         case CB_COLOR0_ATTRIB:
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index a51f880985f8..65c54160028b 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -156,9 +156,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
-                return;
-
         /* Silent, r600_hdmi_enable will raise WARN for us */
         if (!dig->afmt->enabled)
                 return;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 2773039b4902..b50b15c70498 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -503,6 +503,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 
+#define SMX_SAR_CTL0                                    0xA008
 #define SMX_DC_CTL0                                     0xA020
 #define         USE_HASH_FUNCTION                               (1 << 0)
 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3186522a4458..b7bf18e40215 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1303,6 +1303,10 @@ static int cayman_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r)
+                return r;
+
         return 0;
 }
 
@@ -1329,6 +1333,7 @@ int cayman_resume(struct radeon_device *rdev)
 
 int cayman_suspend(struct radeon_device *rdev)
 {
+        r600_audio_fini(rdev);
         /* FIXME: we should wait for ring to be empty */
         radeon_ib_pool_suspend(rdev);
         radeon_vm_manager_suspend(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index f30dc95f83b1..bff627293812 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
                                NUM_CLIP_SEQ(3)));
         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+        WREG32(VC_ENHANCE, 0);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 7479a5c503e4..79b55916cf90 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -57,7 +57,7 @@ static bool radeon_dig_encoder(struct drm_encoder *encoder)
  */
 static int r600_audio_chipset_supported(struct radeon_device *rdev)
 {
-        return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE5(rdev))
+        return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev))
                 || rdev->family == CHIP_RS600
                 || rdev->family == CHIP_RS690
                 || rdev->family == CHIP_RS740;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0133f5f09bd6..ca87f7afaf23 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2079,6 +2079,48 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                         return -EINVAL;
                 }
                 break;
+        case PACKET3_STRMOUT_BASE_UPDATE:
+                if (p->family < CHIP_RV770) {
+                        DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
+                        return -EINVAL;
+                }
+                if (pkt->count != 1) {
+                        DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
+                        return -EINVAL;
+                }
+                if (idx_value > 3) {
+                        DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
+                        return -EINVAL;
+                }
+                {
+                        u64 offset;
+
+                        r = r600_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
+                                return -EINVAL;
+                        }
+
+                        if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
+                                return -EINVAL;
+                        }
+
+                        offset = radeon_get_ib_value(p, idx+1) << 8;
+                        if (offset != track->vgt_strmout_bo_offset[idx_value]) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
+                                          offset, track->vgt_strmout_bo_offset[idx_value]);
+                                return -EINVAL;
+                        }
+
+                        if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
+                                          offset + 4, radeon_bo_size(reloc->robj));
+                                return -EINVAL;
+                        }
+                        ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                }
+                break;
         case PACKET3_SURFACE_BASE_UPDATE:
                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 969c27529dfe..82a0a4c919c0 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -322,9 +322,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
-                return;
-
         /* Silent, r600_hdmi_enable will raise WARN for us */
         if (!dig->afmt->enabled)
                 return;
@@ -483,7 +480,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
         uint32_t offset;
         u32 hdmi;
 
-        if (ASIC_IS_DCE5(rdev))
+        if (ASIC_IS_DCE6(rdev))
                 return;
 
         /* Silent, r600_hdmi_enable will raise WARN for us */
@@ -543,7 +540,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
+        if (ASIC_IS_DCE6(rdev))
                 return;
 
         /* Called for ATOM_ENCODER_MODE_HDMI only */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a0dbf1fe6a40..025fd5b6c08c 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -485,6 +485,7 @@
 #define         TC_L2_SIZE(x)                                   ((x)<<5)
 #define         L2_DISABLE_LATE_HIT                             (1<<9)
 
+#define VC_ENHANCE                                      0x9714
 
 #define VGT_CACHE_INVALIDATION                          0x88C4
 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
@@ -1163,6 +1164,7 @@
 #define PACKET3_SET_CTL_CONST                           0x6F
 #define         PACKET3_SET_CTL_CONST_OFFSET                    0x0003cff0
 #define         PACKET3_SET_CTL_CONST_END                       0x0003e200
+#define PACKET3_STRMOUT_BASE_UPDATE                     0x72 /* r7xx */
 #define PACKET3_SURFACE_BASE_UPDATE                     0x73
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index f0bb2b543b13..2c4d53fd20c5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -57,9 +57,11 @@
  *   2.13.0 - virtual memory support, streamout
  *   2.14.0 - add evergreen tiling informations
  *   2.15.0 - add max_pipes query
+ *   2.16.0 - fix evergreen 2D tiled surface calculation
+ *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        15
+#define KMS_DRIVER_MINOR        17
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 08825548ee69..5b37e283ec38 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -801,9 +801,13 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work)
                 int i;
 
                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
-                        not_processed += radeon_fence_count_emitted(rdev, i);
-                        if (not_processed >= 3)
-                                break;
+                        struct radeon_ring *ring = &rdev->ring[i];
+
+                        if (ring->ready) {
+                                not_processed += radeon_fence_count_emitted(rdev, i);
+                                if (not_processed >= 3)
+                                        break;
+                        }
                 }
 
                 if (not_processed >= 3) { /* should upclock */
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index 8ddab4c76710..6bef46ace831 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -169,11 +169,17 @@ struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
         struct radeon_bo *bo = gem_to_radeon_bo(obj);
         int ret = 0;
 
+        ret = radeon_bo_reserve(bo, false);
+        if (unlikely(ret != 0))
+                return ERR_PTR(ret);
+
         /* pin buffer into GTT */
         ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
-        if (ret)
+        if (ret) {
+                radeon_bo_unreserve(bo);
                 return ERR_PTR(ret);
-
+        }
+        radeon_bo_unreserve(bo);
         return dma_buf_export(bo, &radeon_dmabuf_ops, obj->size, flags);
 }
 
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4ad0281fdc37..b4f51c569c36 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
                                        ACK_FLUSH_CTL(3) |
                                        SYNC_FLUSH_CTL));
 
+        if (rdev->family != CHIP_RV770)
+                WREG32(SMX_SAR_CTL0, 0x00003f3f);
+
         db_debug3 = RREG32(DB_DEBUG3);
         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
         switch (rdev->family) {
@@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
                                           NUM_CLIP_SEQ(3)));
-
+        WREG32(VC_ENHANCE, 0);
 }
 
 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index fdc089896011..b0adfc595d75 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -211,6 +211,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 
+#define SMX_SAR_CTL0                                    0xA008
 #define SMX_DC_CTL0                                     0xA020
 #define         USE_HASH_FUNCTION                               (1 << 0)
 #define         CACHE_DEPTH(x)                                  ((x) << 1)
@@ -310,6 +311,8 @@
 #define TCP_CNTL                                        0x9610
 #define TCP_CHAN_STEER                                  0x9614
 
+#define VC_ENHANCE                                      0x9714
+
 #define VGT_CACHE_INVALIDATION                          0x88C4
 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
 #define                 VC_ONLY                                         0
diff --git a/drivers/gpu/drm/radeon/si_reg.h b/drivers/gpu/drm/radeon/si_reg.h
index eda938a7cb6e..501f9d431d57 100644
--- a/drivers/gpu/drm/radeon/si_reg.h
+++ b/drivers/gpu/drm/radeon/si_reg.h
@@ -30,4 +30,76 @@
 #define SI_DC_GPIO_HPD_EN                        0x65b8
 #define SI_DC_GPIO_HPD_Y                         0x65bc
 
+#define SI_GRPH_CONTROL                          0x6804
+#       define SI_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
+#       define SI_GRPH_DEPTH_8BPP                0
+#       define SI_GRPH_DEPTH_16BPP               1
+#       define SI_GRPH_DEPTH_32BPP               2
+#       define SI_GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)
+#       define SI_ADDR_SURF_2_BANK               0
+#       define SI_ADDR_SURF_4_BANK               1
+#       define SI_ADDR_SURF_8_BANK               2
+#       define SI_ADDR_SURF_16_BANK              3
+#       define SI_GRPH_Z(x)                      (((x) & 0x3) << 4)
+#       define SI_GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)
+#       define SI_ADDR_SURF_BANK_WIDTH_1         0
+#       define SI_ADDR_SURF_BANK_WIDTH_2         1
+#       define SI_ADDR_SURF_BANK_WIDTH_4         2
+#       define SI_ADDR_SURF_BANK_WIDTH_8         3
+#       define SI_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
+/* 8 BPP */
+#       define SI_GRPH_FORMAT_INDEXED            0
+/* 16 BPP */
+#       define SI_GRPH_FORMAT_ARGB1555           0
+#       define SI_GRPH_FORMAT_ARGB565            1
+#       define SI_GRPH_FORMAT_ARGB4444           2
+#       define SI_GRPH_FORMAT_AI88               3
+#       define SI_GRPH_FORMAT_MONO16             4
+#       define SI_GRPH_FORMAT_BGRA5551           5
+/* 32 BPP */
+#       define SI_GRPH_FORMAT_ARGB8888           0
+#       define SI_GRPH_FORMAT_ARGB2101010        1
+#       define SI_GRPH_FORMAT_32BPP_DIG          2
+#       define SI_GRPH_FORMAT_8B_ARGB2101010     3
+#       define SI_GRPH_FORMAT_BGRA1010102        4
+#       define SI_GRPH_FORMAT_8B_BGRA1010102     5
+#       define SI_GRPH_FORMAT_RGB111110          6
+#       define SI_GRPH_FORMAT_BGR101111          7
+#       define SI_GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)
+#       define SI_ADDR_SURF_BANK_HEIGHT_1        0
+#       define SI_ADDR_SURF_BANK_HEIGHT_2        1
+#       define SI_ADDR_SURF_BANK_HEIGHT_4        2
+#       define SI_ADDR_SURF_BANK_HEIGHT_8        3
+#       define SI_GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)
+#       define SI_ADDR_SURF_TILE_SPLIT_64B       0
+#       define SI_ADDR_SURF_TILE_SPLIT_128B      1
+#       define SI_ADDR_SURF_TILE_SPLIT_256B      2
+#       define SI_ADDR_SURF_TILE_SPLIT_512B      3
+#       define SI_ADDR_SURF_TILE_SPLIT_1KB       4
+#       define SI_ADDR_SURF_TILE_SPLIT_2KB       5
+#       define SI_ADDR_SURF_TILE_SPLIT_4KB       6
+#       define SI_GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3
+#       define SI_GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
+#       define SI_GRPH_ARRAY_LINEAR_GENERAL      0
+#       define SI_GRPH_ARRAY_LINEAR_ALIGNED      1
+#       define SI_GRPH_ARRAY_1D_TILED_THIN1      2
+#       define SI_GRPH_ARRAY_2D_TILED_THIN1      4
+#       define SI_GRPH_PIPE_CONFIG(x)            (((x) & 0x1f) << 24)
+#       define SI_ADDR_SURF_P2                   0
+#       define SI_ADDR_SURF_P4_8x16              4
+#       define SI_ADDR_SURF_P4_16x16             5
+#       define SI_ADDR_SURF_P4_16x32             6
+#       define SI_ADDR_SURF_P4_32x32             7
+#       define SI_ADDR_SURF_P8_16x16_8x16        8
+#       define SI_ADDR_SURF_P8_16x32_8x16        9
+#       define SI_ADDR_SURF_P8_32x32_8x16        10
+#       define SI_ADDR_SURF_P8_16x32_16x16       11
+#       define SI_ADDR_SURF_P8_32x32_16x16       12
+#       define SI_ADDR_SURF_P8_32x32_16x32       13
+#       define SI_ADDR_SURF_P8_32x64_32x32       14
+
 #endif
diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c
index 30d98d14b5c5..dd14cd1a0033 100644
--- a/drivers/gpu/drm/sis/sis_drv.c
+++ b/drivers/gpu/drm/sis/sis_drv.c
@@ -47,9 +47,9 @@ static int sis_driver_load(struct drm_device *dev, unsigned long chipset)
         if (dev_priv == NULL)
                 return -ENOMEM;
 
+        idr_init(&dev_priv->object_idr);
         dev->dev_private = (void *)dev_priv;
         dev_priv->chipset = chipset;
-        idr_init(&dev->object_name_idr);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index b67cfcaa661f..36f4b28c1b90 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1204,6 +1204,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
                         (*destroy)(bo);
                 else
                         kfree(bo);
+                ttm_mem_global_free(mem_glob, acc_size);
                 return -EINVAL;
         }
         bo->destroy = destroy;
@@ -1307,22 +1308,14 @@ int ttm_bo_create(struct ttm_bo_device *bdev,
                         struct ttm_buffer_object **p_bo)
 {
         struct ttm_buffer_object *bo;
-        struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
         size_t acc_size;
         int ret;
 
-        acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
-        ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
-        if (unlikely(ret != 0))
-                return ret;
-
         bo = kzalloc(sizeof(*bo), GFP_KERNEL);
-
-        if (unlikely(bo == NULL)) {
-                ttm_mem_global_free(mem_glob, acc_size);
+        if (unlikely(bo == NULL))
                 return -ENOMEM;
-        }
 
+        acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
         ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
                                 buffer_start, interruptible,
                           persistent_swap_storage, acc_size, NULL, NULL);
diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c
index 4d02c46a9420..6e52069894b3 100644
--- a/drivers/gpu/drm/udl/udl_drv.c
+++ b/drivers/gpu/drm/udl/udl_drv.c
@@ -13,8 +13,21 @@
 
 static struct drm_driver driver;
 
+/*
+ * There are many DisplayLink-based graphics products, all with unique PIDs.
+ * So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
+ * We also require a match on SubClass (0x00) and Protocol (0x00),
+ * which is compatible with all known USB 2.0 era graphics chips and firmware,
+ * but allows DisplayLink to increment those for any future incompatible chips
+ */
 static struct usb_device_id id_table[] = {
-        {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,},
+        {.idVendor = 0x17e9, .bInterfaceClass = 0xff,
+         .bInterfaceSubClass = 0x00,
+         .bInterfaceProtocol = 0x00,
+         .match_flags = USB_DEVICE_ID_MATCH_VENDOR |
+                        USB_DEVICE_ID_MATCH_INT_CLASS |
+                        USB_DEVICE_ID_MATCH_INT_SUBCLASS |
+                        USB_DEVICE_ID_MATCH_INT_PROTOCOL,},
         {},
 };
 MODULE_DEVICE_TABLE(usb, id_table);
diff --git a/drivers/gpu/drm/udl/udl_main.c b/drivers/gpu/drm/udl/udl_main.c
index a8d5f09428c7..4c2d836a0893 100644
--- a/drivers/gpu/drm/udl/udl_main.c
+++ b/drivers/gpu/drm/udl/udl_main.c
@@ -61,7 +61,7 @@ static int udl_parse_vendor_descriptor(struct drm_device *dev,
                         u8 length;
                         u16 key;
 
-                        key = *((u16 *) desc);
+                        key = le16_to_cpu(*((u16 *) desc));
                         desc += sizeof(u16);
                         length = *desc;
                         desc++;
diff --git a/drivers/gpu/drm/via/via_map.c b/drivers/gpu/drm/via/via_map.c
index 1f182254e81e..c126182ac07e 100644
--- a/drivers/gpu/drm/via/via_map.c
+++ b/drivers/gpu/drm/via/via_map.c
@@ -100,12 +100,11 @@ int via_driver_load(struct drm_device *dev, unsigned long chipset)
         if (dev_priv == NULL)
                 return -ENOMEM;
 
+        idr_init(&dev_priv->object_idr);
         dev->dev_private = (void *)dev_priv;
 
         dev_priv->chipset = chipset;
 
-        idr_init(&dev->object_name_idr);
-
         pci_set_master(dev->pdev);
 
         ret = drm_vblank_init(dev, 1);