7 files changed, 169 insertions, 7 deletions

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index b1d8941e04d8..e89d89593af1 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -28,7 +28,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
              nv10_gpio.o nv50_gpio.o \
              nv50_calc.o \
              nv04_pm.o nv50_pm.o nva3_pm.o \
-             nv50_vram.o nv50_vm.o
+             nv50_vram.o nv50_vm.o nvc0_vm.o
 
 nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
 nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 42d1ad62b381..d17ffea3c617 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -909,8 +909,9 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
                         break;
                 }
 
-                ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size, 12,
-                                     NV_MEM_ACCESS_RW, &vram->bar_vma);
+                ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
+                                     vram->page_shift, NV_MEM_ACCESS_RW,
+                                     &vram->bar_vma);
                 if (ret)
                         return ret;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 8f13906185b2..57da219fb18b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -69,6 +69,7 @@ struct nouveau_vram {
         struct drm_device *dev;
 
         struct nouveau_vma bar_vma;
+        u8  page_shift;
 
         struct list_head regions;
         u32 memtype;
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 224181193a1f..07be1dd04530 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -731,6 +731,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
         if (ret)
                 return ret;
 
+        node->page_shift = 12;
+        if (nvbo->vma.node)
+                node->page_shift = nvbo->vma.node->type;
+
         mem->mm_node = node;
         mem->start   = node->offset >> PAGE_SHIFT;
         return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.c b/drivers/gpu/drm/nouveau/nouveau_vm.c
index b023a64c27d8..97d82aedf86b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.c
@@ -295,7 +295,34 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
                 vm->flush = nv50_vm_flush;
                 vm->spg_shift = 12;
                 vm->lpg_shift = 16;
+
                 pgt_bits = 29;
+                block = (1 << pgt_bits);
+                if (length < block)
+                        block = length;
+
+        } else
+        if (dev_priv->card_type == NV_C0) {
+                vm->map_pgt = nvc0_vm_map_pgt;
+                vm->map = nvc0_vm_map;
+                vm->map_sg = nvc0_vm_map_sg;
+                vm->unmap = nvc0_vm_unmap;
+                vm->flush = nvc0_vm_flush;
+                vm->spg_shift = 12;
+                vm->lpg_shift = 17;
+                pgt_bits = 27;
+
+                /* Should be 4096 everywhere, this is a hack that's
+                 * currently necessary to avoid an elusive bug that
+                 * causes corruption when mixing small/large pages
+                 */
+                if (length < (1ULL << 40))
+                        block = 4096;
+                else {
+                        block = (1 << pgt_bits);
+                        if (length < block)
+                                block = length;
+                }
         } else {
                 kfree(vm);
                 return -ENOSYS;
@@ -314,10 +341,6 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
         vm->refcount = 1;
         vm->pgt_bits = pgt_bits - 12;
 
-        block = (1 << pgt_bits);
-        if (length < block)
-                block = length;
-
         ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
                               block >> 12);
         if (ret) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h
index 105b6f65f19d..e1193515771b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.h
@@ -100,4 +100,14 @@ void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
 void nv50_vm_flush(struct nouveau_vm *);
 void nv50_vm_flush_engine(struct drm_device *, int engine);
 
+/* nvc0_vm.c */
+void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
+                     struct nouveau_gpuobj *pgt[2]);
+void nvc0_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
+                 struct nouveau_vram *, u32 pte, u32 cnt, u64 phys);
+void nvc0_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
+                    u32 pte, dma_addr_t *, u32 cnt);
+void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
+void nvc0_vm_flush(struct nouveau_vm *);
+
 #endif
diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c
new file mode 100644
index 000000000000..4b9251bb0ff4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_vm.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "drmP.h"
+
+#include "nouveau_drv.h"
+#include "nouveau_vm.h"
+
+void
+nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
+                struct nouveau_gpuobj *pgt[2])
+{
+        u32 pde[2] = { 0, 0 };
+
+        if (pgt[0])
+                pde[1] = 0x00000001 | (pgt[0]->vinst >> 8);
+        if (pgt[1])
+                pde[0] = 0x00000001 | (pgt[1]->vinst >> 8);
+
+        nv_wo32(pgd, (index * 8) + 0, pde[0]);
+        nv_wo32(pgd, (index * 8) + 4, pde[1]);
+}
+
+static inline u64
+nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
+{
+        phys >>= 8;
+
+        phys |= 0x00000001; /* present */
+//      if (vma->access & NV_MEM_ACCESS_SYS)
+//              phys |= 0x00000002;
+
+        phys |= ((u64)target  << 32);
+        phys |= ((u64)memtype << 36);
+
+        return phys;
+}
+
+void
+nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
+            struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
+{
+        u32 next = 1 << (vma->node->type - 8);
+
+        phys  = nvc0_vm_addr(vma, phys, mem->memtype, 0);
+        pte <<= 3;
+        while (cnt--) {
+                nv_wo32(pgt, pte + 0, lower_32_bits(phys));
+                nv_wo32(pgt, pte + 4, upper_32_bits(phys));
+                phys += next;
+                pte  += 8;
+        }
+}
+
+void
+nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
+               u32 pte, dma_addr_t *list, u32 cnt)
+{
+        pte <<= 3;
+        while (cnt--) {
+                u64 phys = nvc0_vm_addr(vma, *list++, 0, 5);
+                nv_wo32(pgt, pte + 0, lower_32_bits(phys));
+                nv_wo32(pgt, pte + 4, upper_32_bits(phys));
+                pte += 8;
+        }
+}
+
+void
+nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
+{
+        pte <<= 3;
+        while (cnt--) {
+                nv_wo32(pgt, pte + 0, 0x00000000);
+                nv_wo32(pgt, pte + 4, 0x00000000);
+                pte += 8;
+        }
+}
+
+void
+nvc0_vm_flush(struct nouveau_vm *vm)
+{
+        struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
+        struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
+        struct drm_device *dev = vm->dev;
+        struct nouveau_vm_pgd *vpgd;
+        u32 r100c80, engine;
+
+        pinstmem->flush(vm->dev);
+
+        if (vm == dev_priv->chan_vm)
+                engine = 1;
+        else
+                engine = 5;
+
+        list_for_each_entry(vpgd, &vm->pgd_list, head) {
+                r100c80 = nv_rd32(dev, 0x100c80);
+                nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
+                nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
+                if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80))
+                        NV_ERROR(dev, "vm flush timeout eng %d\n", engine);
+        }
+}