diff options
Diffstat (limited to 'drivers/gpu/drm')
51 files changed, 720 insertions, 335 deletions
diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c index 3cdbaf379bb5..be9a9c07d152 100644 --- a/drivers/gpu/drm/drm_info.c +++ b/drivers/gpu/drm/drm_info.c | |||
@@ -283,17 +283,18 @@ int drm_vma_info(struct seq_file *m, void *data) | |||
283 | #endif | 283 | #endif |
284 | 284 | ||
285 | mutex_lock(&dev->struct_mutex); | 285 | mutex_lock(&dev->struct_mutex); |
286 | seq_printf(m, "vma use count: %d, high_memory = %p, 0x%08llx\n", | 286 | seq_printf(m, "vma use count: %d, high_memory = %pK, 0x%pK\n", |
287 | atomic_read(&dev->vma_count), | 287 | atomic_read(&dev->vma_count), |
288 | high_memory, (u64)virt_to_phys(high_memory)); | 288 | high_memory, (void *)virt_to_phys(high_memory)); |
289 | 289 | ||
290 | list_for_each_entry(pt, &dev->vmalist, head) { | 290 | list_for_each_entry(pt, &dev->vmalist, head) { |
291 | vma = pt->vma; | 291 | vma = pt->vma; |
292 | if (!vma) | 292 | if (!vma) |
293 | continue; | 293 | continue; |
294 | seq_printf(m, | 294 | seq_printf(m, |
295 | "\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx000", | 295 | "\n%5d 0x%pK-0x%pK %c%c%c%c%c%c 0x%08lx000", |
296 | pt->pid, vma->vm_start, vma->vm_end, | 296 | pt->pid, |
297 | (void *)vma->vm_start, (void *)vma->vm_end, | ||
297 | vma->vm_flags & VM_READ ? 'r' : '-', | 298 | vma->vm_flags & VM_READ ? 'r' : '-', |
298 | vma->vm_flags & VM_WRITE ? 'w' : '-', | 299 | vma->vm_flags & VM_WRITE ? 'w' : '-', |
299 | vma->vm_flags & VM_EXEC ? 'x' : '-', | 300 | vma->vm_flags & VM_EXEC ? 'x' : '-', |
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cfb56d0ff367..0ad533f06af9 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); | |||
46 | unsigned int i915_powersave = 1; | 46 | unsigned int i915_powersave = 1; |
47 | module_param_named(powersave, i915_powersave, int, 0600); | 47 | module_param_named(powersave, i915_powersave, int, 0600); |
48 | 48 | ||
49 | unsigned int i915_enable_rc6 = 0; | ||
50 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); | ||
51 | |||
49 | unsigned int i915_lvds_downclock = 0; | 52 | unsigned int i915_lvds_downclock = 0; |
50 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); | 53 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
51 | 54 | ||
@@ -360,7 +363,7 @@ static int i915_drm_thaw(struct drm_device *dev) | |||
360 | /* Resume the modeset for every activated CRTC */ | 363 | /* Resume the modeset for every activated CRTC */ |
361 | drm_helper_resume_force_mode(dev); | 364 | drm_helper_resume_force_mode(dev); |
362 | 365 | ||
363 | if (dev_priv->renderctx && dev_priv->pwrctx) | 366 | if (IS_IRONLAKE_M(dev)) |
364 | ironlake_enable_rc6(dev); | 367 | ironlake_enable_rc6(dev); |
365 | } | 368 | } |
366 | 369 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a0149c619cdd..65dfe81d0035 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -958,6 +958,7 @@ extern unsigned int i915_fbpercrtc; | |||
958 | extern unsigned int i915_powersave; | 958 | extern unsigned int i915_powersave; |
959 | extern unsigned int i915_lvds_downclock; | 959 | extern unsigned int i915_lvds_downclock; |
960 | extern unsigned int i915_panel_use_ssc; | 960 | extern unsigned int i915_panel_use_ssc; |
961 | extern unsigned int i915_enable_rc6; | ||
961 | 962 | ||
962 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); | 963 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
963 | extern int i915_resume(struct drm_device *dev); | 964 | extern int i915_resume(struct drm_device *dev); |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5cfc68940f17..15d94c63918c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -174,7 +174,9 @@ | |||
174 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! | 174 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! |
175 | */ | 175 | */ |
176 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) | 176 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
177 | #define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */ | 177 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
178 | #define MI_INVALIDATE_TLB (1<<18) | ||
179 | #define MI_INVALIDATE_BSD (1<<7) | ||
178 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) | 180 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
179 | #define MI_BATCH_NON_SECURE (1) | 181 | #define MI_BATCH_NON_SECURE (1) |
180 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | 182 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7e42aa586504..3b006536b3d2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5558,9 +5558,7 @@ static void intel_crtc_reset(struct drm_crtc *crtc) | |||
5558 | /* Reset flags back to the 'unknown' status so that they | 5558 | /* Reset flags back to the 'unknown' status so that they |
5559 | * will be correctly set on the initial modeset. | 5559 | * will be correctly set on the initial modeset. |
5560 | */ | 5560 | */ |
5561 | intel_crtc->cursor_addr = 0; | ||
5562 | intel_crtc->dpms_mode = -1; | 5561 | intel_crtc->dpms_mode = -1; |
5563 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ | ||
5564 | } | 5562 | } |
5565 | 5563 | ||
5566 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | 5564 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
@@ -5666,6 +5664,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) | |||
5666 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | 5664 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
5667 | 5665 | ||
5668 | intel_crtc_reset(&intel_crtc->base); | 5666 | intel_crtc_reset(&intel_crtc->base); |
5667 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ | ||
5669 | 5668 | ||
5670 | if (HAS_PCH_SPLIT(dev)) { | 5669 | if (HAS_PCH_SPLIT(dev)) { |
5671 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | 5670 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
@@ -6463,52 +6462,60 @@ void intel_enable_clock_gating(struct drm_device *dev) | |||
6463 | } | 6462 | } |
6464 | } | 6463 | } |
6465 | 6464 | ||
6466 | void intel_disable_clock_gating(struct drm_device *dev) | 6465 | static void ironlake_teardown_rc6(struct drm_device *dev) |
6467 | { | 6466 | { |
6468 | struct drm_i915_private *dev_priv = dev->dev_private; | 6467 | struct drm_i915_private *dev_priv = dev->dev_private; |
6469 | 6468 | ||
6470 | if (dev_priv->renderctx) { | 6469 | if (dev_priv->renderctx) { |
6471 | struct drm_i915_gem_object *obj = dev_priv->renderctx; | 6470 | i915_gem_object_unpin(dev_priv->renderctx); |
6472 | 6471 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
6473 | I915_WRITE(CCID, 0); | ||
6474 | POSTING_READ(CCID); | ||
6475 | |||
6476 | i915_gem_object_unpin(obj); | ||
6477 | drm_gem_object_unreference(&obj->base); | ||
6478 | dev_priv->renderctx = NULL; | 6472 | dev_priv->renderctx = NULL; |
6479 | } | 6473 | } |
6480 | 6474 | ||
6481 | if (dev_priv->pwrctx) { | 6475 | if (dev_priv->pwrctx) { |
6482 | struct drm_i915_gem_object *obj = dev_priv->pwrctx; | 6476 | i915_gem_object_unpin(dev_priv->pwrctx); |
6477 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | ||
6478 | dev_priv->pwrctx = NULL; | ||
6479 | } | ||
6480 | } | ||
6481 | |||
6482 | static void ironlake_disable_rc6(struct drm_device *dev) | ||
6483 | { | ||
6484 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
6485 | |||
6486 | if (I915_READ(PWRCTXA)) { | ||
6487 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | ||
6488 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | ||
6489 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | ||
6490 | 50); | ||
6483 | 6491 | ||
6484 | I915_WRITE(PWRCTXA, 0); | 6492 | I915_WRITE(PWRCTXA, 0); |
6485 | POSTING_READ(PWRCTXA); | 6493 | POSTING_READ(PWRCTXA); |
6486 | 6494 | ||
6487 | i915_gem_object_unpin(obj); | 6495 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
6488 | drm_gem_object_unreference(&obj->base); | 6496 | POSTING_READ(RSTDBYCTL); |
6489 | dev_priv->pwrctx = NULL; | ||
6490 | } | 6497 | } |
6498 | |||
6499 | ironlake_disable_rc6(dev); | ||
6491 | } | 6500 | } |
6492 | 6501 | ||
6493 | static void ironlake_disable_rc6(struct drm_device *dev) | 6502 | static int ironlake_setup_rc6(struct drm_device *dev) |
6494 | { | 6503 | { |
6495 | struct drm_i915_private *dev_priv = dev->dev_private; | 6504 | struct drm_i915_private *dev_priv = dev->dev_private; |
6496 | 6505 | ||
6497 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | 6506 | if (dev_priv->renderctx == NULL) |
6498 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | 6507 | dev_priv->renderctx = intel_alloc_context_page(dev); |
6499 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | 6508 | if (!dev_priv->renderctx) |
6500 | 10); | 6509 | return -ENOMEM; |
6501 | POSTING_READ(CCID); | 6510 | |
6502 | I915_WRITE(PWRCTXA, 0); | 6511 | if (dev_priv->pwrctx == NULL) |
6503 | POSTING_READ(PWRCTXA); | 6512 | dev_priv->pwrctx = intel_alloc_context_page(dev); |
6504 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | 6513 | if (!dev_priv->pwrctx) { |
6505 | POSTING_READ(RSTDBYCTL); | 6514 | ironlake_teardown_rc6(dev); |
6506 | i915_gem_object_unpin(dev_priv->renderctx); | 6515 | return -ENOMEM; |
6507 | drm_gem_object_unreference(&dev_priv->renderctx->base); | 6516 | } |
6508 | dev_priv->renderctx = NULL; | 6517 | |
6509 | i915_gem_object_unpin(dev_priv->pwrctx); | 6518 | return 0; |
6510 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | ||
6511 | dev_priv->pwrctx = NULL; | ||
6512 | } | 6519 | } |
6513 | 6520 | ||
6514 | void ironlake_enable_rc6(struct drm_device *dev) | 6521 | void ironlake_enable_rc6(struct drm_device *dev) |
@@ -6516,15 +6523,26 @@ void ironlake_enable_rc6(struct drm_device *dev) | |||
6516 | struct drm_i915_private *dev_priv = dev->dev_private; | 6523 | struct drm_i915_private *dev_priv = dev->dev_private; |
6517 | int ret; | 6524 | int ret; |
6518 | 6525 | ||
6526 | /* rc6 disabled by default due to repeated reports of hanging during | ||
6527 | * boot and resume. | ||
6528 | */ | ||
6529 | if (!i915_enable_rc6) | ||
6530 | return; | ||
6531 | |||
6532 | ret = ironlake_setup_rc6(dev); | ||
6533 | if (ret) | ||
6534 | return; | ||
6535 | |||
6519 | /* | 6536 | /* |
6520 | * GPU can automatically power down the render unit if given a page | 6537 | * GPU can automatically power down the render unit if given a page |
6521 | * to save state. | 6538 | * to save state. |
6522 | */ | 6539 | */ |
6523 | ret = BEGIN_LP_RING(6); | 6540 | ret = BEGIN_LP_RING(6); |
6524 | if (ret) { | 6541 | if (ret) { |
6525 | ironlake_disable_rc6(dev); | 6542 | ironlake_teardown_rc6(dev); |
6526 | return; | 6543 | return; |
6527 | } | 6544 | } |
6545 | |||
6528 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); | 6546 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
6529 | OUT_RING(MI_SET_CONTEXT); | 6547 | OUT_RING(MI_SET_CONTEXT); |
6530 | OUT_RING(dev_priv->renderctx->gtt_offset | | 6548 | OUT_RING(dev_priv->renderctx->gtt_offset | |
@@ -6541,6 +6559,7 @@ void ironlake_enable_rc6(struct drm_device *dev) | |||
6541 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | 6559 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
6542 | } | 6560 | } |
6543 | 6561 | ||
6562 | |||
6544 | /* Set up chip specific display functions */ | 6563 | /* Set up chip specific display functions */ |
6545 | static void intel_init_display(struct drm_device *dev) | 6564 | static void intel_init_display(struct drm_device *dev) |
6546 | { | 6565 | { |
@@ -6783,21 +6802,9 @@ void intel_modeset_init(struct drm_device *dev) | |||
6783 | if (IS_GEN6(dev)) | 6802 | if (IS_GEN6(dev)) |
6784 | gen6_enable_rps(dev_priv); | 6803 | gen6_enable_rps(dev_priv); |
6785 | 6804 | ||
6786 | if (IS_IRONLAKE_M(dev)) { | 6805 | if (IS_IRONLAKE_M(dev)) |
6787 | dev_priv->renderctx = intel_alloc_context_page(dev); | ||
6788 | if (!dev_priv->renderctx) | ||
6789 | goto skip_rc6; | ||
6790 | dev_priv->pwrctx = intel_alloc_context_page(dev); | ||
6791 | if (!dev_priv->pwrctx) { | ||
6792 | i915_gem_object_unpin(dev_priv->renderctx); | ||
6793 | drm_gem_object_unreference(&dev_priv->renderctx->base); | ||
6794 | dev_priv->renderctx = NULL; | ||
6795 | goto skip_rc6; | ||
6796 | } | ||
6797 | ironlake_enable_rc6(dev); | 6806 | ironlake_enable_rc6(dev); |
6798 | } | ||
6799 | 6807 | ||
6800 | skip_rc6: | ||
6801 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); | 6808 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6802 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | 6809 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
6803 | (unsigned long)dev); | 6810 | (unsigned long)dev); |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1f4242b682c8..51cb4e36997f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -1639,6 +1639,24 @@ static int intel_dp_get_modes(struct drm_connector *connector) | |||
1639 | return 0; | 1639 | return 0; |
1640 | } | 1640 | } |
1641 | 1641 | ||
1642 | static bool | ||
1643 | intel_dp_detect_audio(struct drm_connector *connector) | ||
1644 | { | ||
1645 | struct intel_dp *intel_dp = intel_attached_dp(connector); | ||
1646 | struct edid *edid; | ||
1647 | bool has_audio = false; | ||
1648 | |||
1649 | edid = drm_get_edid(connector, &intel_dp->adapter); | ||
1650 | if (edid) { | ||
1651 | has_audio = drm_detect_monitor_audio(edid); | ||
1652 | |||
1653 | connector->display_info.raw_edid = NULL; | ||
1654 | kfree(edid); | ||
1655 | } | ||
1656 | |||
1657 | return has_audio; | ||
1658 | } | ||
1659 | |||
1642 | static int | 1660 | static int |
1643 | intel_dp_set_property(struct drm_connector *connector, | 1661 | intel_dp_set_property(struct drm_connector *connector, |
1644 | struct drm_property *property, | 1662 | struct drm_property *property, |
@@ -1652,17 +1670,23 @@ intel_dp_set_property(struct drm_connector *connector, | |||
1652 | return ret; | 1670 | return ret; |
1653 | 1671 | ||
1654 | if (property == intel_dp->force_audio_property) { | 1672 | if (property == intel_dp->force_audio_property) { |
1655 | if (val == intel_dp->force_audio) | 1673 | int i = val; |
1674 | bool has_audio; | ||
1675 | |||
1676 | if (i == intel_dp->force_audio) | ||
1656 | return 0; | 1677 | return 0; |
1657 | 1678 | ||
1658 | intel_dp->force_audio = val; | 1679 | intel_dp->force_audio = i; |
1659 | 1680 | ||
1660 | if (val > 0 && intel_dp->has_audio) | 1681 | if (i == 0) |
1661 | return 0; | 1682 | has_audio = intel_dp_detect_audio(connector); |
1662 | if (val < 0 && !intel_dp->has_audio) | 1683 | else |
1684 | has_audio = i > 0; | ||
1685 | |||
1686 | if (has_audio == intel_dp->has_audio) | ||
1663 | return 0; | 1687 | return 0; |
1664 | 1688 | ||
1665 | intel_dp->has_audio = val > 0; | 1689 | intel_dp->has_audio = has_audio; |
1666 | goto done; | 1690 | goto done; |
1667 | } | 1691 | } |
1668 | 1692 | ||
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 74db2557d644..2c431049963c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -298,7 +298,6 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |||
298 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | 298 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
299 | u16 *blue, int regno); | 299 | u16 *blue, int regno); |
300 | extern void intel_enable_clock_gating(struct drm_device *dev); | 300 | extern void intel_enable_clock_gating(struct drm_device *dev); |
301 | extern void intel_disable_clock_gating(struct drm_device *dev); | ||
302 | extern void ironlake_enable_drps(struct drm_device *dev); | 301 | extern void ironlake_enable_drps(struct drm_device *dev); |
303 | extern void ironlake_disable_drps(struct drm_device *dev); | 302 | extern void ironlake_disable_drps(struct drm_device *dev); |
304 | extern void gen6_enable_rps(struct drm_i915_private *dev_priv); | 303 | extern void gen6_enable_rps(struct drm_i915_private *dev_priv); |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 0d0273e7b029..c635c9e357b9 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -251,6 +251,27 @@ static int intel_hdmi_get_modes(struct drm_connector *connector) | |||
251 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | 251 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); |
252 | } | 252 | } |
253 | 253 | ||
254 | static bool | ||
255 | intel_hdmi_detect_audio(struct drm_connector *connector) | ||
256 | { | ||
257 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | ||
258 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | ||
259 | struct edid *edid; | ||
260 | bool has_audio = false; | ||
261 | |||
262 | edid = drm_get_edid(connector, | ||
263 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | ||
264 | if (edid) { | ||
265 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | ||
266 | has_audio = drm_detect_monitor_audio(edid); | ||
267 | |||
268 | connector->display_info.raw_edid = NULL; | ||
269 | kfree(edid); | ||
270 | } | ||
271 | |||
272 | return has_audio; | ||
273 | } | ||
274 | |||
254 | static int | 275 | static int |
255 | intel_hdmi_set_property(struct drm_connector *connector, | 276 | intel_hdmi_set_property(struct drm_connector *connector, |
256 | struct drm_property *property, | 277 | struct drm_property *property, |
@@ -264,17 +285,23 @@ intel_hdmi_set_property(struct drm_connector *connector, | |||
264 | return ret; | 285 | return ret; |
265 | 286 | ||
266 | if (property == intel_hdmi->force_audio_property) { | 287 | if (property == intel_hdmi->force_audio_property) { |
267 | if (val == intel_hdmi->force_audio) | 288 | int i = val; |
289 | bool has_audio; | ||
290 | |||
291 | if (i == intel_hdmi->force_audio) | ||
268 | return 0; | 292 | return 0; |
269 | 293 | ||
270 | intel_hdmi->force_audio = val; | 294 | intel_hdmi->force_audio = i; |
271 | 295 | ||
272 | if (val > 0 && intel_hdmi->has_audio) | 296 | if (i == 0) |
273 | return 0; | 297 | has_audio = intel_hdmi_detect_audio(connector); |
274 | if (val < 0 && !intel_hdmi->has_audio) | 298 | else |
299 | has_audio = i > 0; | ||
300 | |||
301 | if (has_audio == intel_hdmi->has_audio) | ||
275 | return 0; | 302 | return 0; |
276 | 303 | ||
277 | intel_hdmi->has_audio = val > 0; | 304 | intel_hdmi->has_audio = has_audio; |
278 | goto done; | 305 | goto done; |
279 | } | 306 | } |
280 | 307 | ||
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index ace8d5d30dd2..bcdba7bd5cfa 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
@@ -261,12 +261,6 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |||
261 | return true; | 261 | return true; |
262 | } | 262 | } |
263 | 263 | ||
264 | /* Make sure pre-965s set dither correctly */ | ||
265 | if (INTEL_INFO(dev)->gen < 4) { | ||
266 | if (dev_priv->lvds_dither) | ||
267 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | ||
268 | } | ||
269 | |||
270 | /* Native modes don't need fitting */ | 264 | /* Native modes don't need fitting */ |
271 | if (adjusted_mode->hdisplay == mode->hdisplay && | 265 | if (adjusted_mode->hdisplay == mode->hdisplay && |
272 | adjusted_mode->vdisplay == mode->vdisplay) | 266 | adjusted_mode->vdisplay == mode->vdisplay) |
@@ -374,10 +368,16 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |||
374 | } | 368 | } |
375 | 369 | ||
376 | out: | 370 | out: |
371 | /* If not enabling scaling, be consistent and always use 0. */ | ||
377 | if ((pfit_control & PFIT_ENABLE) == 0) { | 372 | if ((pfit_control & PFIT_ENABLE) == 0) { |
378 | pfit_control = 0; | 373 | pfit_control = 0; |
379 | pfit_pgm_ratios = 0; | 374 | pfit_pgm_ratios = 0; |
380 | } | 375 | } |
376 | |||
377 | /* Make sure pre-965 set dither correctly */ | ||
378 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | ||
379 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | ||
380 | |||
381 | if (pfit_control != intel_lvds->pfit_control || | 381 | if (pfit_control != intel_lvds->pfit_control || |
382 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { | 382 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { |
383 | intel_lvds->pfit_control = pfit_control; | 383 | intel_lvds->pfit_control = pfit_control; |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6218fa97aa1e..445f27efe677 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -1059,22 +1059,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, | |||
1059 | } | 1059 | } |
1060 | 1060 | ||
1061 | static int gen6_ring_flush(struct intel_ring_buffer *ring, | 1061 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1062 | u32 invalidate_domains, | 1062 | u32 invalidate, u32 flush) |
1063 | u32 flush_domains) | ||
1064 | { | 1063 | { |
1064 | uint32_t cmd; | ||
1065 | int ret; | 1065 | int ret; |
1066 | 1066 | ||
1067 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) | 1067 | if (((invalidate | flush) & I915_GEM_GPU_DOMAINS) == 0) |
1068 | return 0; | 1068 | return 0; |
1069 | 1069 | ||
1070 | ret = intel_ring_begin(ring, 4); | 1070 | ret = intel_ring_begin(ring, 4); |
1071 | if (ret) | 1071 | if (ret) |
1072 | return ret; | 1072 | return ret; |
1073 | 1073 | ||
1074 | intel_ring_emit(ring, MI_FLUSH_DW); | 1074 | cmd = MI_FLUSH_DW; |
1075 | intel_ring_emit(ring, 0); | 1075 | if (invalidate & I915_GEM_GPU_DOMAINS) |
1076 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | ||
1077 | intel_ring_emit(ring, cmd); | ||
1076 | intel_ring_emit(ring, 0); | 1078 | intel_ring_emit(ring, 0); |
1077 | intel_ring_emit(ring, 0); | 1079 | intel_ring_emit(ring, 0); |
1080 | intel_ring_emit(ring, MI_NOOP); | ||
1078 | intel_ring_advance(ring); | 1081 | intel_ring_advance(ring); |
1079 | return 0; | 1082 | return 0; |
1080 | } | 1083 | } |
@@ -1230,22 +1233,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring, | |||
1230 | } | 1233 | } |
1231 | 1234 | ||
1232 | static int blt_ring_flush(struct intel_ring_buffer *ring, | 1235 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
1233 | u32 invalidate_domains, | 1236 | u32 invalidate, u32 flush) |
1234 | u32 flush_domains) | ||
1235 | { | 1237 | { |
1238 | uint32_t cmd; | ||
1236 | int ret; | 1239 | int ret; |
1237 | 1240 | ||
1238 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) | 1241 | if (((invalidate | flush) & I915_GEM_DOMAIN_RENDER) == 0) |
1239 | return 0; | 1242 | return 0; |
1240 | 1243 | ||
1241 | ret = blt_ring_begin(ring, 4); | 1244 | ret = blt_ring_begin(ring, 4); |
1242 | if (ret) | 1245 | if (ret) |
1243 | return ret; | 1246 | return ret; |
1244 | 1247 | ||
1245 | intel_ring_emit(ring, MI_FLUSH_DW); | 1248 | cmd = MI_FLUSH_DW; |
1246 | intel_ring_emit(ring, 0); | 1249 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
1250 | cmd |= MI_INVALIDATE_TLB; | ||
1251 | intel_ring_emit(ring, cmd); | ||
1247 | intel_ring_emit(ring, 0); | 1252 | intel_ring_emit(ring, 0); |
1248 | intel_ring_emit(ring, 0); | 1253 | intel_ring_emit(ring, 0); |
1254 | intel_ring_emit(ring, MI_NOOP); | ||
1249 | intel_ring_advance(ring); | 1255 | intel_ring_advance(ring); |
1250 | return 0; | 1256 | return 0; |
1251 | } | 1257 | } |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 6a09c1413d60..7c50cdce84f0 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -46,6 +46,7 @@ | |||
46 | SDVO_TV_MASK) | 46 | SDVO_TV_MASK) |
47 | 47 | ||
48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | 48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
49 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) | ||
49 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) | 50 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
50 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) | 51 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
51 | 52 | ||
@@ -1359,7 +1360,8 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) | |||
1359 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | 1360 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
1360 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | 1361 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
1361 | } | 1362 | } |
1362 | } | 1363 | } else |
1364 | status = connector_status_disconnected; | ||
1363 | connector->display_info.raw_edid = NULL; | 1365 | connector->display_info.raw_edid = NULL; |
1364 | kfree(edid); | 1366 | kfree(edid); |
1365 | } | 1367 | } |
@@ -1407,10 +1409,25 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) | |||
1407 | 1409 | ||
1408 | if ((intel_sdvo_connector->output_flag & response) == 0) | 1410 | if ((intel_sdvo_connector->output_flag & response) == 0) |
1409 | ret = connector_status_disconnected; | 1411 | ret = connector_status_disconnected; |
1410 | else if (response & SDVO_TMDS_MASK) | 1412 | else if (IS_TMDS(intel_sdvo_connector)) |
1411 | ret = intel_sdvo_hdmi_sink_detect(connector); | 1413 | ret = intel_sdvo_hdmi_sink_detect(connector); |
1412 | else | 1414 | else { |
1413 | ret = connector_status_connected; | 1415 | struct edid *edid; |
1416 | |||
1417 | /* if we have an edid check it matches the connection */ | ||
1418 | edid = intel_sdvo_get_edid(connector); | ||
1419 | if (edid == NULL) | ||
1420 | edid = intel_sdvo_get_analog_edid(connector); | ||
1421 | if (edid != NULL) { | ||
1422 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | ||
1423 | ret = connector_status_disconnected; | ||
1424 | else | ||
1425 | ret = connector_status_connected; | ||
1426 | connector->display_info.raw_edid = NULL; | ||
1427 | kfree(edid); | ||
1428 | } else | ||
1429 | ret = connector_status_connected; | ||
1430 | } | ||
1414 | 1431 | ||
1415 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | 1432 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
1416 | if (ret == connector_status_connected) { | 1433 | if (ret == connector_status_connected) { |
@@ -1446,10 +1463,15 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) | |||
1446 | edid = intel_sdvo_get_analog_edid(connector); | 1463 | edid = intel_sdvo_get_analog_edid(connector); |
1447 | 1464 | ||
1448 | if (edid != NULL) { | 1465 | if (edid != NULL) { |
1449 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { | 1466 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
1467 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | ||
1468 | bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector); | ||
1469 | |||
1470 | if (connector_is_digital == monitor_is_digital) { | ||
1450 | drm_mode_connector_update_edid_property(connector, edid); | 1471 | drm_mode_connector_update_edid_property(connector, edid); |
1451 | drm_add_edid_modes(connector, edid); | 1472 | drm_add_edid_modes(connector, edid); |
1452 | } | 1473 | } |
1474 | |||
1453 | connector->display_info.raw_edid = NULL; | 1475 | connector->display_info.raw_edid = NULL; |
1454 | kfree(edid); | 1476 | kfree(edid); |
1455 | } | 1477 | } |
@@ -1668,6 +1690,22 @@ static void intel_sdvo_destroy(struct drm_connector *connector) | |||
1668 | kfree(connector); | 1690 | kfree(connector); |
1669 | } | 1691 | } |
1670 | 1692 | ||
1693 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) | ||
1694 | { | ||
1695 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | ||
1696 | struct edid *edid; | ||
1697 | bool has_audio = false; | ||
1698 | |||
1699 | if (!intel_sdvo->is_hdmi) | ||
1700 | return false; | ||
1701 | |||
1702 | edid = intel_sdvo_get_edid(connector); | ||
1703 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | ||
1704 | has_audio = drm_detect_monitor_audio(edid); | ||
1705 | |||
1706 | return has_audio; | ||
1707 | } | ||
1708 | |||
1671 | static int | 1709 | static int |
1672 | intel_sdvo_set_property(struct drm_connector *connector, | 1710 | intel_sdvo_set_property(struct drm_connector *connector, |
1673 | struct drm_property *property, | 1711 | struct drm_property *property, |
@@ -1684,17 +1722,23 @@ intel_sdvo_set_property(struct drm_connector *connector, | |||
1684 | return ret; | 1722 | return ret; |
1685 | 1723 | ||
1686 | if (property == intel_sdvo_connector->force_audio_property) { | 1724 | if (property == intel_sdvo_connector->force_audio_property) { |
1687 | if (val == intel_sdvo_connector->force_audio) | 1725 | int i = val; |
1726 | bool has_audio; | ||
1727 | |||
1728 | if (i == intel_sdvo_connector->force_audio) | ||
1688 | return 0; | 1729 | return 0; |
1689 | 1730 | ||
1690 | intel_sdvo_connector->force_audio = val; | 1731 | intel_sdvo_connector->force_audio = i; |
1691 | 1732 | ||
1692 | if (val > 0 && intel_sdvo->has_hdmi_audio) | 1733 | if (i == 0) |
1693 | return 0; | 1734 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
1694 | if (val < 0 && !intel_sdvo->has_hdmi_audio) | 1735 | else |
1736 | has_audio = i > 0; | ||
1737 | |||
1738 | if (has_audio == intel_sdvo->has_hdmi_audio) | ||
1695 | return 0; | 1739 | return 0; |
1696 | 1740 | ||
1697 | intel_sdvo->has_hdmi_audio = val > 0; | 1741 | intel_sdvo->has_hdmi_audio = has_audio; |
1698 | goto done; | 1742 | goto done; |
1699 | } | 1743 | } |
1700 | 1744 | ||
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 93206e4eaa6f..fe4a53a50b83 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c | |||
@@ -1234,7 +1234,8 @@ static const struct drm_display_mode reported_modes[] = { | |||
1234 | * \return false if TV is disconnected. | 1234 | * \return false if TV is disconnected. |
1235 | */ | 1235 | */ |
1236 | static int | 1236 | static int |
1237 | intel_tv_detect_type (struct intel_tv *intel_tv) | 1237 | intel_tv_detect_type (struct intel_tv *intel_tv, |
1238 | struct drm_connector *connector) | ||
1238 | { | 1239 | { |
1239 | struct drm_encoder *encoder = &intel_tv->base.base; | 1240 | struct drm_encoder *encoder = &intel_tv->base.base; |
1240 | struct drm_device *dev = encoder->dev; | 1241 | struct drm_device *dev = encoder->dev; |
@@ -1245,11 +1246,13 @@ intel_tv_detect_type (struct intel_tv *intel_tv) | |||
1245 | int type; | 1246 | int type; |
1246 | 1247 | ||
1247 | /* Disable TV interrupts around load detect or we'll recurse */ | 1248 | /* Disable TV interrupts around load detect or we'll recurse */ |
1248 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 1249 | if (connector->polled & DRM_CONNECTOR_POLL_HPD) { |
1249 | i915_disable_pipestat(dev_priv, 0, | 1250 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
1250 | PIPE_HOTPLUG_INTERRUPT_ENABLE | | 1251 | i915_disable_pipestat(dev_priv, 0, |
1251 | PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); | 1252 | PIPE_HOTPLUG_INTERRUPT_ENABLE | |
1252 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 1253 | PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); |
1254 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | ||
1255 | } | ||
1253 | 1256 | ||
1254 | save_tv_dac = tv_dac = I915_READ(TV_DAC); | 1257 | save_tv_dac = tv_dac = I915_READ(TV_DAC); |
1255 | save_tv_ctl = tv_ctl = I915_READ(TV_CTL); | 1258 | save_tv_ctl = tv_ctl = I915_READ(TV_CTL); |
@@ -1302,11 +1305,13 @@ intel_tv_detect_type (struct intel_tv *intel_tv) | |||
1302 | I915_WRITE(TV_CTL, save_tv_ctl); | 1305 | I915_WRITE(TV_CTL, save_tv_ctl); |
1303 | 1306 | ||
1304 | /* Restore interrupt config */ | 1307 | /* Restore interrupt config */ |
1305 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 1308 | if (connector->polled & DRM_CONNECTOR_POLL_HPD) { |
1306 | i915_enable_pipestat(dev_priv, 0, | 1309 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
1307 | PIPE_HOTPLUG_INTERRUPT_ENABLE | | 1310 | i915_enable_pipestat(dev_priv, 0, |
1308 | PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); | 1311 | PIPE_HOTPLUG_INTERRUPT_ENABLE | |
1309 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 1312 | PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); |
1313 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | ||
1314 | } | ||
1310 | 1315 | ||
1311 | return type; | 1316 | return type; |
1312 | } | 1317 | } |
@@ -1356,7 +1361,7 @@ intel_tv_detect(struct drm_connector *connector, bool force) | |||
1356 | drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V); | 1361 | drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V); |
1357 | 1362 | ||
1358 | if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) { | 1363 | if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) { |
1359 | type = intel_tv_detect_type(intel_tv); | 1364 | type = intel_tv_detect_type(intel_tv, connector); |
1360 | } else if (force) { | 1365 | } else if (force) { |
1361 | struct drm_crtc *crtc; | 1366 | struct drm_crtc *crtc; |
1362 | int dpms_mode; | 1367 | int dpms_mode; |
@@ -1364,7 +1369,7 @@ intel_tv_detect(struct drm_connector *connector, bool force) | |||
1364 | crtc = intel_get_load_detect_pipe(&intel_tv->base, connector, | 1369 | crtc = intel_get_load_detect_pipe(&intel_tv->base, connector, |
1365 | &mode, &dpms_mode); | 1370 | &mode, &dpms_mode); |
1366 | if (crtc) { | 1371 | if (crtc) { |
1367 | type = intel_tv_detect_type(intel_tv); | 1372 | type = intel_tv_detect_type(intel_tv, connector); |
1368 | intel_release_load_detect_pipe(&intel_tv->base, connector, | 1373 | intel_release_load_detect_pipe(&intel_tv->base, connector, |
1369 | dpms_mode); | 1374 | dpms_mode); |
1370 | } else | 1375 | } else |
@@ -1658,6 +1663,18 @@ intel_tv_init(struct drm_device *dev) | |||
1658 | intel_encoder = &intel_tv->base; | 1663 | intel_encoder = &intel_tv->base; |
1659 | connector = &intel_connector->base; | 1664 | connector = &intel_connector->base; |
1660 | 1665 | ||
1666 | /* The documentation, for the older chipsets at least, recommend | ||
1667 | * using a polling method rather than hotplug detection for TVs. | ||
1668 | * This is because in order to perform the hotplug detection, the PLLs | ||
1669 | * for the TV must be kept alive increasing power drain and starving | ||
1670 | * bandwidth from other encoders. Notably for instance, it causes | ||
1671 | * pipe underruns on Crestline when this encoder is supposedly idle. | ||
1672 | * | ||
1673 | * More recent chipsets favour HDMI rather than integrated S-Video. | ||
1674 | */ | ||
1675 | connector->polled = | ||
1676 | DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; | ||
1677 | |||
1661 | drm_connector_init(dev, connector, &intel_tv_connector_funcs, | 1678 | drm_connector_init(dev, connector, &intel_tv_connector_funcs, |
1662 | DRM_MODE_CONNECTOR_SVIDEO); | 1679 | DRM_MODE_CONNECTOR_SVIDEO); |
1663 | 1680 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 49e5e99917e2..6bdab891c64e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c | |||
@@ -6228,7 +6228,7 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, | |||
6228 | entry->tvconf.has_component_output = false; | 6228 | entry->tvconf.has_component_output = false; |
6229 | break; | 6229 | break; |
6230 | case OUTPUT_LVDS: | 6230 | case OUTPUT_LVDS: |
6231 | if ((conn & 0x00003f00) != 0x10) | 6231 | if ((conn & 0x00003f00) >> 8 != 0x10) |
6232 | entry->lvdsconf.use_straps_for_mode = true; | 6232 | entry->lvdsconf.use_straps_for_mode = true; |
6233 | entry->lvdsconf.use_power_scripts = true; | 6233 | entry->lvdsconf.use_power_scripts = true; |
6234 | break; | 6234 | break; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index a7fae26f4654..d38a4d9f9b0b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c | |||
@@ -128,6 +128,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |||
128 | } | 128 | } |
129 | } | 129 | } |
130 | 130 | ||
131 | nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; | ||
131 | nouveau_bo_placement_set(nvbo, flags, 0); | 132 | nouveau_bo_placement_set(nvbo, flags, 0); |
132 | 133 | ||
133 | nvbo->channel = chan; | 134 | nvbo->channel = chan; |
@@ -166,17 +167,17 @@ static void | |||
166 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | 167 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) |
167 | { | 168 | { |
168 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | 169 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); |
170 | int vram_pages = dev_priv->vram_size >> PAGE_SHIFT; | ||
169 | 171 | ||
170 | if (dev_priv->card_type == NV_10 && | 172 | if (dev_priv->card_type == NV_10 && |
171 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) { | 173 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) && |
174 | nvbo->bo.mem.num_pages < vram_pages / 2) { | ||
172 | /* | 175 | /* |
173 | * Make sure that the color and depth buffers are handled | 176 | * Make sure that the color and depth buffers are handled |
174 | * by independent memory controller units. Up to a 9x | 177 | * by independent memory controller units. Up to a 9x |
175 | * speed up when alpha-blending and depth-test are enabled | 178 | * speed up when alpha-blending and depth-test are enabled |
176 | * at the same time. | 179 | * at the same time. |
177 | */ | 180 | */ |
178 | int vram_pages = dev_priv->vram_size >> PAGE_SHIFT; | ||
179 | |||
180 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { | 181 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { |
181 | nvbo->placement.fpfn = vram_pages / 2; | 182 | nvbo->placement.fpfn = vram_pages / 2; |
182 | nvbo->placement.lpfn = ~0; | 183 | nvbo->placement.lpfn = ~0; |
@@ -785,7 +786,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |||
785 | if (ret) | 786 | if (ret) |
786 | goto out; | 787 | goto out; |
787 | 788 | ||
788 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); | 789 | ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem); |
789 | out: | 790 | out: |
790 | ttm_bo_mem_put(bo, &tmp_mem); | 791 | ttm_bo_mem_put(bo, &tmp_mem); |
791 | return ret; | 792 | return ret; |
@@ -811,11 +812,11 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |||
811 | if (ret) | 812 | if (ret) |
812 | return ret; | 813 | return ret; |
813 | 814 | ||
814 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem); | 815 | ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem); |
815 | if (ret) | 816 | if (ret) |
816 | goto out; | 817 | goto out; |
817 | 818 | ||
818 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); | 819 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem); |
819 | if (ret) | 820 | if (ret) |
820 | goto out; | 821 | goto out; |
821 | 822 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index a21e00076839..390d82c3c4b0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c | |||
@@ -507,6 +507,7 @@ nouveau_connector_native_mode(struct drm_connector *connector) | |||
507 | int high_w = 0, high_h = 0, high_v = 0; | 507 | int high_w = 0, high_h = 0, high_v = 0; |
508 | 508 | ||
509 | list_for_each_entry(mode, &nv_connector->base.probed_modes, head) { | 509 | list_for_each_entry(mode, &nv_connector->base.probed_modes, head) { |
510 | mode->vrefresh = drm_mode_vrefresh(mode); | ||
510 | if (helper->mode_valid(connector, mode) != MODE_OK || | 511 | if (helper->mode_valid(connector, mode) != MODE_OK || |
511 | (mode->flags & DRM_MODE_FLAG_INTERLACE)) | 512 | (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
512 | continue; | 513 | continue; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c index f05c0cddfeca..4399e2f34db4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/drivers/gpu/drm/nouveau/nouveau_pm.c | |||
@@ -543,7 +543,7 @@ nouveau_pm_resume(struct drm_device *dev) | |||
543 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; | 543 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; |
544 | struct nouveau_pm_level *perflvl; | 544 | struct nouveau_pm_level *perflvl; |
545 | 545 | ||
546 | if (pm->cur == &pm->boot) | 546 | if (!pm->cur || pm->cur == &pm->boot) |
547 | return; | 547 | return; |
548 | 548 | ||
549 | perflvl = pm->cur; | 549 | perflvl = pm->cur; |
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c index ef23550407b5..c82db37d9f41 100644 --- a/drivers/gpu/drm/nouveau/nv04_dfp.c +++ b/drivers/gpu/drm/nouveau/nv04_dfp.c | |||
@@ -342,8 +342,8 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, | |||
342 | if (nv_encoder->dcb->type == OUTPUT_LVDS) { | 342 | if (nv_encoder->dcb->type == OUTPUT_LVDS) { |
343 | bool duallink, dummy; | 343 | bool duallink, dummy; |
344 | 344 | ||
345 | nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode-> | 345 | nouveau_bios_parse_lvds_table(dev, output_mode->clock, |
346 | clock, &duallink, &dummy); | 346 | &duallink, &dummy); |
347 | if (duallink) | 347 | if (duallink) |
348 | regp->fp_control |= (8 << 28); | 348 | regp->fp_control |= (8 << 28); |
349 | } else | 349 | } else |
@@ -518,8 +518,6 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode) | |||
518 | return; | 518 | return; |
519 | 519 | ||
520 | if (nv_encoder->dcb->lvdsconf.use_power_scripts) { | 520 | if (nv_encoder->dcb->lvdsconf.use_power_scripts) { |
521 | struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder); | ||
522 | |||
523 | /* when removing an output, crtc may not be set, but PANEL_OFF | 521 | /* when removing an output, crtc may not be set, but PANEL_OFF |
524 | * must still be run | 522 | * must still be run |
525 | */ | 523 | */ |
@@ -527,12 +525,8 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode) | |||
527 | nv04_dfp_get_bound_head(dev, nv_encoder->dcb); | 525 | nv04_dfp_get_bound_head(dev, nv_encoder->dcb); |
528 | 526 | ||
529 | if (mode == DRM_MODE_DPMS_ON) { | 527 | if (mode == DRM_MODE_DPMS_ON) { |
530 | if (!nv_connector->native_mode) { | ||
531 | NV_ERROR(dev, "Not turning on LVDS without native mode\n"); | ||
532 | return; | ||
533 | } | ||
534 | call_lvds_script(dev, nv_encoder->dcb, head, | 528 | call_lvds_script(dev, nv_encoder->dcb, head, |
535 | LVDS_PANEL_ON, nv_connector->native_mode->clock); | 529 | LVDS_PANEL_ON, nv_encoder->mode.clock); |
536 | } else | 530 | } else |
537 | /* pxclk of 0 is fine for PANEL_OFF, and for a | 531 | /* pxclk of 0 is fine for PANEL_OFF, and for a |
538 | * disconnected LVDS encoder there is no native_mode | 532 | * disconnected LVDS encoder there is no native_mode |
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c index 8870d72388c8..18d30c2c1aa6 100644 --- a/drivers/gpu/drm/nouveau/nv40_graph.c +++ b/drivers/gpu/drm/nouveau/nv40_graph.c | |||
@@ -211,18 +211,32 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i) | |||
211 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; | 211 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; |
212 | 212 | ||
213 | switch (dev_priv->chipset) { | 213 | switch (dev_priv->chipset) { |
214 | case 0x40: | ||
215 | case 0x41: /* guess */ | ||
216 | case 0x42: | ||
217 | case 0x43: | ||
218 | case 0x45: /* guess */ | ||
219 | case 0x4e: | ||
220 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); | ||
221 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); | ||
222 | nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); | ||
223 | nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch); | ||
224 | nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); | ||
225 | nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); | ||
226 | break; | ||
214 | case 0x44: | 227 | case 0x44: |
215 | case 0x4a: | 228 | case 0x4a: |
216 | case 0x4e: | ||
217 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); | 229 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); |
218 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); | 230 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); |
219 | nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); | 231 | nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); |
220 | break; | 232 | break; |
221 | |||
222 | case 0x46: | 233 | case 0x46: |
223 | case 0x47: | 234 | case 0x47: |
224 | case 0x49: | 235 | case 0x49: |
225 | case 0x4b: | 236 | case 0x4b: |
237 | case 0x4c: | ||
238 | case 0x67: | ||
239 | default: | ||
226 | nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch); | 240 | nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch); |
227 | nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit); | 241 | nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit); |
228 | nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr); | 242 | nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr); |
@@ -230,15 +244,6 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i) | |||
230 | nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); | 244 | nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); |
231 | nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); | 245 | nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); |
232 | break; | 246 | break; |
233 | |||
234 | default: | ||
235 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); | ||
236 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); | ||
237 | nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); | ||
238 | nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch); | ||
239 | nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); | ||
240 | nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); | ||
241 | break; | ||
242 | } | 247 | } |
243 | } | 248 | } |
244 | 249 | ||
@@ -396,17 +401,20 @@ nv40_graph_init(struct drm_device *dev) | |||
396 | break; | 401 | break; |
397 | default: | 402 | default: |
398 | switch (dev_priv->chipset) { | 403 | switch (dev_priv->chipset) { |
399 | case 0x46: | 404 | case 0x41: |
400 | case 0x47: | 405 | case 0x42: |
401 | case 0x49: | 406 | case 0x43: |
402 | case 0x4b: | 407 | case 0x45: |
403 | nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0)); | 408 | case 0x4e: |
404 | nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1)); | 409 | case 0x44: |
405 | break; | 410 | case 0x4a: |
406 | default: | ||
407 | nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0)); | 411 | nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0)); |
408 | nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1)); | 412 | nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1)); |
409 | break; | 413 | break; |
414 | default: | ||
415 | nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0)); | ||
416 | nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1)); | ||
417 | break; | ||
410 | } | 418 | } |
411 | nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0)); | 419 | nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0)); |
412 | nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1)); | 420 | nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1)); |
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index b1537000a104..a4e5e53e0a62 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -48,29 +48,29 @@ static void atombios_overscan_setup(struct drm_crtc *crtc, | |||
48 | 48 | ||
49 | switch (radeon_crtc->rmx_type) { | 49 | switch (radeon_crtc->rmx_type) { |
50 | case RMX_CENTER: | 50 | case RMX_CENTER: |
51 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; | 51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
52 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; | 52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
53 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; | 53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
54 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; | 54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
55 | break; | 55 | break; |
56 | case RMX_ASPECT: | 56 | case RMX_ASPECT: |
57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; | 57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; | 58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
59 | 59 | ||
60 | if (a1 > a2) { | 60 | if (a1 > a2) { |
61 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; | 61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
62 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; | 62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
63 | } else if (a2 > a1) { | 63 | } else if (a2 > a1) { |
64 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; | 64 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
65 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; | 65 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
66 | } | 66 | } |
67 | break; | 67 | break; |
68 | case RMX_FULL: | 68 | case RMX_FULL: |
69 | default: | 69 | default: |
70 | args.usOverscanRight = radeon_crtc->h_border; | 70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
71 | args.usOverscanLeft = radeon_crtc->h_border; | 71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
72 | args.usOverscanBottom = radeon_crtc->v_border; | 72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
73 | args.usOverscanTop = radeon_crtc->v_border; | 73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
74 | break; | 74 | break; |
75 | } | 75 | } |
76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
@@ -419,23 +419,23 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, | |||
419 | memset(&args, 0, sizeof(args)); | 419 | memset(&args, 0, sizeof(args)); |
420 | 420 | ||
421 | if (ASIC_IS_DCE5(rdev)) { | 421 | if (ASIC_IS_DCE5(rdev)) { |
422 | args.v3.usSpreadSpectrumAmountFrac = 0; | 422 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
423 | args.v3.ucSpreadSpectrumType = ss->type; | 423 | args.v3.ucSpreadSpectrumType = ss->type; |
424 | switch (pll_id) { | 424 | switch (pll_id) { |
425 | case ATOM_PPLL1: | 425 | case ATOM_PPLL1: |
426 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; | 426 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
427 | args.v3.usSpreadSpectrumAmount = ss->amount; | 427 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
428 | args.v3.usSpreadSpectrumStep = ss->step; | 428 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
429 | break; | 429 | break; |
430 | case ATOM_PPLL2: | 430 | case ATOM_PPLL2: |
431 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; | 431 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
432 | args.v3.usSpreadSpectrumAmount = ss->amount; | 432 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
433 | args.v3.usSpreadSpectrumStep = ss->step; | 433 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
434 | break; | 434 | break; |
435 | case ATOM_DCPLL: | 435 | case ATOM_DCPLL: |
436 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; | 436 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
437 | args.v3.usSpreadSpectrumAmount = 0; | 437 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); |
438 | args.v3.usSpreadSpectrumStep = 0; | 438 | args.v3.usSpreadSpectrumStep = cpu_to_le16(0); |
439 | break; | 439 | break; |
440 | case ATOM_PPLL_INVALID: | 440 | case ATOM_PPLL_INVALID: |
441 | return; | 441 | return; |
@@ -447,18 +447,18 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, | |||
447 | switch (pll_id) { | 447 | switch (pll_id) { |
448 | case ATOM_PPLL1: | 448 | case ATOM_PPLL1: |
449 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; | 449 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
450 | args.v2.usSpreadSpectrumAmount = ss->amount; | 450 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
451 | args.v2.usSpreadSpectrumStep = ss->step; | 451 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
452 | break; | 452 | break; |
453 | case ATOM_PPLL2: | 453 | case ATOM_PPLL2: |
454 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; | 454 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
455 | args.v2.usSpreadSpectrumAmount = ss->amount; | 455 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
456 | args.v2.usSpreadSpectrumStep = ss->step; | 456 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
457 | break; | 457 | break; |
458 | case ATOM_DCPLL: | 458 | case ATOM_DCPLL: |
459 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; | 459 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
460 | args.v2.usSpreadSpectrumAmount = 0; | 460 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); |
461 | args.v2.usSpreadSpectrumStep = 0; | 461 | args.v2.usSpreadSpectrumStep = cpu_to_le16(0); |
462 | break; | 462 | break; |
463 | case ATOM_PPLL_INVALID: | 463 | case ATOM_PPLL_INVALID: |
464 | return; | 464 | return; |
@@ -538,7 +538,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
538 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; | 538 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
539 | else | 539 | else |
540 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; | 540 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
541 | |||
542 | } | 541 | } |
543 | 542 | ||
544 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 543 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
@@ -555,29 +554,28 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
555 | dp_clock = dig_connector->dp_clock; | 554 | dp_clock = dig_connector->dp_clock; |
556 | } | 555 | } |
557 | } | 556 | } |
558 | /* this might work properly with the new pll algo */ | 557 | |
559 | #if 0 /* doesn't work properly on some laptops */ | ||
560 | /* use recommended ref_div for ss */ | 558 | /* use recommended ref_div for ss */ |
561 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | 559 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
562 | if (ss_enabled) { | 560 | if (ss_enabled) { |
563 | if (ss->refdiv) { | 561 | if (ss->refdiv) { |
562 | pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; | ||
564 | pll->flags |= RADEON_PLL_USE_REF_DIV; | 563 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
565 | pll->reference_div = ss->refdiv; | 564 | pll->reference_div = ss->refdiv; |
565 | if (ASIC_IS_AVIVO(rdev)) | ||
566 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; | ||
566 | } | 567 | } |
567 | } | 568 | } |
568 | } | 569 | } |
569 | #endif | 570 | |
570 | if (ASIC_IS_AVIVO(rdev)) { | 571 | if (ASIC_IS_AVIVO(rdev)) { |
571 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ | 572 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
572 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) | 573 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
573 | adjusted_clock = mode->clock * 2; | 574 | adjusted_clock = mode->clock * 2; |
574 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | 575 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
575 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; | 576 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
576 | /* rv515 needs more testing with this option */ | 577 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
577 | if (rdev->family != CHIP_RV515) { | 578 | pll->flags |= RADEON_PLL_IS_LCD; |
578 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | ||
579 | pll->flags |= RADEON_PLL_IS_LCD; | ||
580 | } | ||
581 | } else { | 579 | } else { |
582 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | 580 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
583 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; | 581 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
@@ -664,10 +662,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
664 | index, (uint32_t *)&args); | 662 | index, (uint32_t *)&args); |
665 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; | 663 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
666 | if (args.v3.sOutput.ucRefDiv) { | 664 | if (args.v3.sOutput.ucRefDiv) { |
665 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; | ||
667 | pll->flags |= RADEON_PLL_USE_REF_DIV; | 666 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
668 | pll->reference_div = args.v3.sOutput.ucRefDiv; | 667 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
669 | } | 668 | } |
670 | if (args.v3.sOutput.ucPostDiv) { | 669 | if (args.v3.sOutput.ucPostDiv) { |
670 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; | ||
671 | pll->flags |= RADEON_PLL_USE_POST_DIV; | 671 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
672 | pll->post_div = args.v3.sOutput.ucPostDiv; | 672 | pll->post_div = args.v3.sOutput.ucPostDiv; |
673 | } | 673 | } |
@@ -721,14 +721,14 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, | |||
721 | * SetPixelClock provides the dividers | 721 | * SetPixelClock provides the dividers |
722 | */ | 722 | */ |
723 | args.v5.ucCRTC = ATOM_CRTC_INVALID; | 723 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
724 | args.v5.usPixelClock = dispclk; | 724 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
725 | args.v5.ucPpll = ATOM_DCPLL; | 725 | args.v5.ucPpll = ATOM_DCPLL; |
726 | break; | 726 | break; |
727 | case 6: | 727 | case 6: |
728 | /* if the default dcpll clock is specified, | 728 | /* if the default dcpll clock is specified, |
729 | * SetPixelClock provides the dividers | 729 | * SetPixelClock provides the dividers |
730 | */ | 730 | */ |
731 | args.v6.ulDispEngClkFreq = dispclk; | 731 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
732 | args.v6.ucPpll = ATOM_DCPLL; | 732 | args.v6.ucPpll = ATOM_DCPLL; |
733 | break; | 733 | break; |
734 | default: | 734 | default: |
@@ -957,11 +957,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode | |||
957 | /* adjust pixel clock as needed */ | 957 | /* adjust pixel clock as needed */ |
958 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); | 958 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); |
959 | 959 | ||
960 | /* rv515 seems happier with the old algo */ | 960 | if (ASIC_IS_AVIVO(rdev)) |
961 | if (rdev->family == CHIP_RV515) | ||
962 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, | ||
963 | &ref_div, &post_div); | ||
964 | else if (ASIC_IS_AVIVO(rdev)) | ||
965 | radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, | 961 | radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
966 | &ref_div, &post_div); | 962 | &ref_div, &post_div); |
967 | else | 963 | else |
@@ -995,9 +991,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode | |||
995 | } | 991 | } |
996 | } | 992 | } |
997 | 993 | ||
998 | static int evergreen_crtc_do_set_base(struct drm_crtc *crtc, | 994 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
999 | struct drm_framebuffer *fb, | 995 | struct drm_framebuffer *fb, |
1000 | int x, int y, int atomic) | 996 | int x, int y, int atomic) |
1001 | { | 997 | { |
1002 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 998 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1003 | struct drm_device *dev = crtc->dev; | 999 | struct drm_device *dev = crtc->dev; |
@@ -1137,12 +1133,6 @@ static int evergreen_crtc_do_set_base(struct drm_crtc *crtc, | |||
1137 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, | 1133 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1138 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); | 1134 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
1139 | 1135 | ||
1140 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) | ||
1141 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, | ||
1142 | EVERGREEN_INTERLEAVE_EN); | ||
1143 | else | ||
1144 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | ||
1145 | |||
1146 | if (!atomic && fb && fb != crtc->fb) { | 1136 | if (!atomic && fb && fb != crtc->fb) { |
1147 | radeon_fb = to_radeon_framebuffer(fb); | 1137 | radeon_fb = to_radeon_framebuffer(fb); |
1148 | rbo = radeon_fb->obj->driver_private; | 1138 | rbo = radeon_fb->obj->driver_private; |
@@ -1300,12 +1290,6 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, | |||
1300 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, | 1290 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1301 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); | 1291 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
1302 | 1292 | ||
1303 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) | ||
1304 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | ||
1305 | AVIVO_D1MODE_INTERLEAVE_EN); | ||
1306 | else | ||
1307 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | ||
1308 | |||
1309 | if (!atomic && fb && fb != crtc->fb) { | 1293 | if (!atomic && fb && fb != crtc->fb) { |
1310 | radeon_fb = to_radeon_framebuffer(fb); | 1294 | radeon_fb = to_radeon_framebuffer(fb); |
1311 | rbo = radeon_fb->obj->driver_private; | 1295 | rbo = radeon_fb->obj->driver_private; |
@@ -1329,7 +1313,7 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |||
1329 | struct radeon_device *rdev = dev->dev_private; | 1313 | struct radeon_device *rdev = dev->dev_private; |
1330 | 1314 | ||
1331 | if (ASIC_IS_DCE4(rdev)) | 1315 | if (ASIC_IS_DCE4(rdev)) |
1332 | return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0); | 1316 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1333 | else if (ASIC_IS_AVIVO(rdev)) | 1317 | else if (ASIC_IS_AVIVO(rdev)) |
1334 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); | 1318 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1335 | else | 1319 | else |
@@ -1344,7 +1328,7 @@ int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, | |||
1344 | struct radeon_device *rdev = dev->dev_private; | 1328 | struct radeon_device *rdev = dev->dev_private; |
1345 | 1329 | ||
1346 | if (ASIC_IS_DCE4(rdev)) | 1330 | if (ASIC_IS_DCE4(rdev)) |
1347 | return evergreen_crtc_do_set_base(crtc, fb, x, y, 1); | 1331 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
1348 | else if (ASIC_IS_AVIVO(rdev)) | 1332 | else if (ASIC_IS_AVIVO(rdev)) |
1349 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); | 1333 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
1350 | else | 1334 | else |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index ffdc8332b76e..d270b3ff896b 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1192,7 +1192,11 @@ void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |||
1192 | radeon_ring_write(rdev, 1); | 1192 | radeon_ring_write(rdev, 1); |
1193 | /* FIXME: implement */ | 1193 | /* FIXME: implement */ |
1194 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 1194 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
1195 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | 1195 | radeon_ring_write(rdev, |
1196 | #ifdef __BIG_ENDIAN | ||
1197 | (2 << 0) | | ||
1198 | #endif | ||
1199 | (ib->gpu_addr & 0xFFFFFFFC)); | ||
1196 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | 1200 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); |
1197 | radeon_ring_write(rdev, ib->length_dw); | 1201 | radeon_ring_write(rdev, ib->length_dw); |
1198 | } | 1202 | } |
@@ -1207,7 +1211,11 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev) | |||
1207 | return -EINVAL; | 1211 | return -EINVAL; |
1208 | 1212 | ||
1209 | r700_cp_stop(rdev); | 1213 | r700_cp_stop(rdev); |
1210 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); | 1214 | WREG32(CP_RB_CNTL, |
1215 | #ifdef __BIG_ENDIAN | ||
1216 | BUF_SWAP_32BIT | | ||
1217 | #endif | ||
1218 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | ||
1211 | 1219 | ||
1212 | fw_data = (const __be32 *)rdev->pfp_fw->data; | 1220 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
1213 | WREG32(CP_PFP_UCODE_ADDR, 0); | 1221 | WREG32(CP_PFP_UCODE_ADDR, 0); |
@@ -1326,7 +1334,11 @@ int evergreen_cp_resume(struct radeon_device *rdev) | |||
1326 | WREG32(CP_RB_WPTR, 0); | 1334 | WREG32(CP_RB_WPTR, 0); |
1327 | 1335 | ||
1328 | /* set the wb address wether it's enabled or not */ | 1336 | /* set the wb address wether it's enabled or not */ |
1329 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 1337 | WREG32(CP_RB_RPTR_ADDR, |
1338 | #ifdef __BIG_ENDIAN | ||
1339 | RB_RPTR_SWAP(2) | | ||
1340 | #endif | ||
1341 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); | ||
1330 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | 1342 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1331 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | 1343 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
1332 | 1344 | ||
@@ -2627,8 +2639,8 @@ restart_ih: | |||
2627 | while (rptr != wptr) { | 2639 | while (rptr != wptr) { |
2628 | /* wptr/rptr are in bytes! */ | 2640 | /* wptr/rptr are in bytes! */ |
2629 | ring_index = rptr / 4; | 2641 | ring_index = rptr / 4; |
2630 | src_id = rdev->ih.ring[ring_index] & 0xff; | 2642 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
2631 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | 2643 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; |
2632 | 2644 | ||
2633 | switch (src_id) { | 2645 | switch (src_id) { |
2634 | case 1: /* D1 vblank/vline */ | 2646 | case 1: /* D1 vblank/vline */ |
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c index a1ba4b3053d0..2adfb03f479b 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c | |||
@@ -55,7 +55,7 @@ set_render_target(struct radeon_device *rdev, int format, | |||
55 | if (h < 8) | 55 | if (h < 8) |
56 | h = 8; | 56 | h = 8; |
57 | 57 | ||
58 | cb_color_info = ((format << 2) | (1 << 24)); | 58 | cb_color_info = ((format << 2) | (1 << 24) | (1 << 8)); |
59 | pitch = (w / 8) - 1; | 59 | pitch = (w / 8) - 1; |
60 | slice = ((w * h) / 64) - 1; | 60 | slice = ((w * h) / 64) - 1; |
61 | 61 | ||
@@ -133,6 +133,9 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) | |||
133 | 133 | ||
134 | /* high addr, stride */ | 134 | /* high addr, stride */ |
135 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); | 135 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
136 | #ifdef __BIG_ENDIAN | ||
137 | sq_vtx_constant_word2 |= (2 << 30); | ||
138 | #endif | ||
136 | /* xyzw swizzles */ | 139 | /* xyzw swizzles */ |
137 | sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12); | 140 | sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12); |
138 | 141 | ||
@@ -173,7 +176,7 @@ set_tex_resource(struct radeon_device *rdev, | |||
173 | sq_tex_resource_word0 = (1 << 0); /* 2D */ | 176 | sq_tex_resource_word0 = (1 << 0); /* 2D */ |
174 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | | 177 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | |
175 | ((w - 1) << 18)); | 178 | ((w - 1) << 18)); |
176 | sq_tex_resource_word1 = ((h - 1) << 0); | 179 | sq_tex_resource_word1 = ((h - 1) << 0) | (1 << 28); |
177 | /* xyzw swizzles */ | 180 | /* xyzw swizzles */ |
178 | sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25); | 181 | sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25); |
179 | 182 | ||
@@ -221,7 +224,11 @@ draw_auto(struct radeon_device *rdev) | |||
221 | radeon_ring_write(rdev, DI_PT_RECTLIST); | 224 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
222 | 225 | ||
223 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); | 226 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
224 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); | 227 | radeon_ring_write(rdev, |
228 | #ifdef __BIG_ENDIAN | ||
229 | (2 << 2) | | ||
230 | #endif | ||
231 | DI_INDEX_SIZE_16_BIT); | ||
225 | 232 | ||
226 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); | 233 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
227 | radeon_ring_write(rdev, 1); | 234 | radeon_ring_write(rdev, 1); |
@@ -541,7 +548,7 @@ static inline uint32_t i2f(uint32_t input) | |||
541 | int evergreen_blit_init(struct radeon_device *rdev) | 548 | int evergreen_blit_init(struct radeon_device *rdev) |
542 | { | 549 | { |
543 | u32 obj_size; | 550 | u32 obj_size; |
544 | int r, dwords; | 551 | int i, r, dwords; |
545 | void *ptr; | 552 | void *ptr; |
546 | u32 packet2s[16]; | 553 | u32 packet2s[16]; |
547 | int num_packet2s = 0; | 554 | int num_packet2s = 0; |
@@ -557,7 +564,7 @@ int evergreen_blit_init(struct radeon_device *rdev) | |||
557 | 564 | ||
558 | dwords = rdev->r600_blit.state_len; | 565 | dwords = rdev->r600_blit.state_len; |
559 | while (dwords & 0xf) { | 566 | while (dwords & 0xf) { |
560 | packet2s[num_packet2s++] = PACKET2(0); | 567 | packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
561 | dwords++; | 568 | dwords++; |
562 | } | 569 | } |
563 | 570 | ||
@@ -598,8 +605,10 @@ int evergreen_blit_init(struct radeon_device *rdev) | |||
598 | if (num_packet2s) | 605 | if (num_packet2s) |
599 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), | 606 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
600 | packet2s, num_packet2s * 4); | 607 | packet2s, num_packet2s * 4); |
601 | memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4); | 608 | for (i = 0; i < evergreen_vs_size; i++) |
602 | memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4); | 609 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); |
610 | for (i = 0; i < evergreen_ps_size; i++) | ||
611 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); | ||
603 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); | 612 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
604 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | 613 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
605 | 614 | ||
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c index ef1d28c07fbf..3a10399e0066 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c | |||
@@ -311,11 +311,19 @@ const u32 evergreen_vs[] = | |||
311 | 0x00000000, | 311 | 0x00000000, |
312 | 0x3c000000, | 312 | 0x3c000000, |
313 | 0x67961001, | 313 | 0x67961001, |
314 | #ifdef __BIG_ENDIAN | ||
315 | 0x000a0000, | ||
316 | #else | ||
314 | 0x00080000, | 317 | 0x00080000, |
318 | #endif | ||
315 | 0x00000000, | 319 | 0x00000000, |
316 | 0x1c000000, | 320 | 0x1c000000, |
317 | 0x67961000, | 321 | 0x67961000, |
322 | #ifdef __BIG_ENDIAN | ||
323 | 0x00020008, | ||
324 | #else | ||
318 | 0x00000008, | 325 | 0x00000008, |
326 | #endif | ||
319 | 0x00000000, | 327 | 0x00000000, |
320 | }; | 328 | }; |
321 | 329 | ||
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index afec1aca2a73..eb4acf4528ff 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
@@ -98,6 +98,7 @@ | |||
98 | #define BUF_SWAP_32BIT (2 << 16) | 98 | #define BUF_SWAP_32BIT (2 << 16) |
99 | #define CP_RB_RPTR 0x8700 | 99 | #define CP_RB_RPTR 0x8700 |
100 | #define CP_RB_RPTR_ADDR 0xC10C | 100 | #define CP_RB_RPTR_ADDR 0xC10C |
101 | #define RB_RPTR_SWAP(x) ((x) << 0) | ||
101 | #define CP_RB_RPTR_ADDR_HI 0xC110 | 102 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
102 | #define CP_RB_RPTR_WR 0xC108 | 103 | #define CP_RB_RPTR_WR 0xC108 |
103 | #define CP_RB_WPTR 0xC114 | 104 | #define CP_RB_WPTR 0xC114 |
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c index 607241c6a8a9..5a82b6b75849 100644 --- a/drivers/gpu/drm/radeon/mkregtable.c +++ b/drivers/gpu/drm/radeon/mkregtable.c | |||
@@ -673,8 +673,10 @@ static int parser_auth(struct table *t, const char *filename) | |||
673 | last_reg = strtol(last_reg_s, NULL, 16); | 673 | last_reg = strtol(last_reg_s, NULL, 16); |
674 | 674 | ||
675 | do { | 675 | do { |
676 | if (fgets(buf, 1024, file) == NULL) | 676 | if (fgets(buf, 1024, file) == NULL) { |
677 | fclose(file); | ||
677 | return -1; | 678 | return -1; |
679 | } | ||
678 | len = strlen(buf); | 680 | len = strlen(buf); |
679 | if (ftell(file) == end) | 681 | if (ftell(file) == end) |
680 | done = 1; | 682 | done = 1; |
@@ -685,6 +687,7 @@ static int parser_auth(struct table *t, const char *filename) | |||
685 | fprintf(stderr, | 687 | fprintf(stderr, |
686 | "Error matching regular expression %d in %s\n", | 688 | "Error matching regular expression %d in %s\n", |
687 | r, filename); | 689 | r, filename); |
690 | fclose(file); | ||
688 | return -1; | 691 | return -1; |
689 | } else { | 692 | } else { |
690 | buf[match[0].rm_eo] = 0; | 693 | buf[match[0].rm_eo] = 0; |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 5f15820efe12..56deae5bf02e 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -1427,6 +1427,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1427 | } | 1427 | } |
1428 | track->zb.robj = reloc->robj; | 1428 | track->zb.robj = reloc->robj; |
1429 | track->zb.offset = idx_value; | 1429 | track->zb.offset = idx_value; |
1430 | track->zb_dirty = true; | ||
1430 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1431 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1431 | break; | 1432 | break; |
1432 | case RADEON_RB3D_COLOROFFSET: | 1433 | case RADEON_RB3D_COLOROFFSET: |
@@ -1439,6 +1440,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1439 | } | 1440 | } |
1440 | track->cb[0].robj = reloc->robj; | 1441 | track->cb[0].robj = reloc->robj; |
1441 | track->cb[0].offset = idx_value; | 1442 | track->cb[0].offset = idx_value; |
1443 | track->cb_dirty = true; | ||
1442 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1444 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1443 | break; | 1445 | break; |
1444 | case RADEON_PP_TXOFFSET_0: | 1446 | case RADEON_PP_TXOFFSET_0: |
@@ -1454,6 +1456,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1454 | } | 1456 | } |
1455 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1457 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1456 | track->textures[i].robj = reloc->robj; | 1458 | track->textures[i].robj = reloc->robj; |
1459 | track->tex_dirty = true; | ||
1457 | break; | 1460 | break; |
1458 | case RADEON_PP_CUBIC_OFFSET_T0_0: | 1461 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
1459 | case RADEON_PP_CUBIC_OFFSET_T0_1: | 1462 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
@@ -1471,6 +1474,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1471 | track->textures[0].cube_info[i].offset = idx_value; | 1474 | track->textures[0].cube_info[i].offset = idx_value; |
1472 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1475 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1473 | track->textures[0].cube_info[i].robj = reloc->robj; | 1476 | track->textures[0].cube_info[i].robj = reloc->robj; |
1477 | track->tex_dirty = true; | ||
1474 | break; | 1478 | break; |
1475 | case RADEON_PP_CUBIC_OFFSET_T1_0: | 1479 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
1476 | case RADEON_PP_CUBIC_OFFSET_T1_1: | 1480 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
@@ -1488,6 +1492,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1488 | track->textures[1].cube_info[i].offset = idx_value; | 1492 | track->textures[1].cube_info[i].offset = idx_value; |
1489 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1493 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1490 | track->textures[1].cube_info[i].robj = reloc->robj; | 1494 | track->textures[1].cube_info[i].robj = reloc->robj; |
1495 | track->tex_dirty = true; | ||
1491 | break; | 1496 | break; |
1492 | case RADEON_PP_CUBIC_OFFSET_T2_0: | 1497 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
1493 | case RADEON_PP_CUBIC_OFFSET_T2_1: | 1498 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
@@ -1505,9 +1510,12 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1505 | track->textures[2].cube_info[i].offset = idx_value; | 1510 | track->textures[2].cube_info[i].offset = idx_value; |
1506 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 1511 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1507 | track->textures[2].cube_info[i].robj = reloc->robj; | 1512 | track->textures[2].cube_info[i].robj = reloc->robj; |
1513 | track->tex_dirty = true; | ||
1508 | break; | 1514 | break; |
1509 | case RADEON_RE_WIDTH_HEIGHT: | 1515 | case RADEON_RE_WIDTH_HEIGHT: |
1510 | track->maxy = ((idx_value >> 16) & 0x7FF); | 1516 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1517 | track->cb_dirty = true; | ||
1518 | track->zb_dirty = true; | ||
1511 | break; | 1519 | break; |
1512 | case RADEON_RB3D_COLORPITCH: | 1520 | case RADEON_RB3D_COLORPITCH: |
1513 | r = r100_cs_packet_next_reloc(p, &reloc); | 1521 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1528,9 +1536,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1528 | ib[idx] = tmp; | 1536 | ib[idx] = tmp; |
1529 | 1537 | ||
1530 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; | 1538 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1539 | track->cb_dirty = true; | ||
1531 | break; | 1540 | break; |
1532 | case RADEON_RB3D_DEPTHPITCH: | 1541 | case RADEON_RB3D_DEPTHPITCH: |
1533 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; | 1542 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1543 | track->zb_dirty = true; | ||
1534 | break; | 1544 | break; |
1535 | case RADEON_RB3D_CNTL: | 1545 | case RADEON_RB3D_CNTL: |
1536 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { | 1546 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
@@ -1555,6 +1565,8 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1555 | return -EINVAL; | 1565 | return -EINVAL; |
1556 | } | 1566 | } |
1557 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); | 1567 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1568 | track->cb_dirty = true; | ||
1569 | track->zb_dirty = true; | ||
1558 | break; | 1570 | break; |
1559 | case RADEON_RB3D_ZSTENCILCNTL: | 1571 | case RADEON_RB3D_ZSTENCILCNTL: |
1560 | switch (idx_value & 0xf) { | 1572 | switch (idx_value & 0xf) { |
@@ -1572,6 +1584,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1572 | default: | 1584 | default: |
1573 | break; | 1585 | break; |
1574 | } | 1586 | } |
1587 | track->zb_dirty = true; | ||
1575 | break; | 1588 | break; |
1576 | case RADEON_RB3D_ZPASS_ADDR: | 1589 | case RADEON_RB3D_ZPASS_ADDR: |
1577 | r = r100_cs_packet_next_reloc(p, &reloc); | 1590 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1588,6 +1601,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1588 | uint32_t temp = idx_value >> 4; | 1601 | uint32_t temp = idx_value >> 4; |
1589 | for (i = 0; i < track->num_texture; i++) | 1602 | for (i = 0; i < track->num_texture; i++) |
1590 | track->textures[i].enabled = !!(temp & (1 << i)); | 1603 | track->textures[i].enabled = !!(temp & (1 << i)); |
1604 | track->tex_dirty = true; | ||
1591 | } | 1605 | } |
1592 | break; | 1606 | break; |
1593 | case RADEON_SE_VF_CNTL: | 1607 | case RADEON_SE_VF_CNTL: |
@@ -1602,12 +1616,14 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1602 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; | 1616 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
1603 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; | 1617 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1604 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | 1618 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
1619 | track->tex_dirty = true; | ||
1605 | break; | 1620 | break; |
1606 | case RADEON_PP_TEX_PITCH_0: | 1621 | case RADEON_PP_TEX_PITCH_0: |
1607 | case RADEON_PP_TEX_PITCH_1: | 1622 | case RADEON_PP_TEX_PITCH_1: |
1608 | case RADEON_PP_TEX_PITCH_2: | 1623 | case RADEON_PP_TEX_PITCH_2: |
1609 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; | 1624 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
1610 | track->textures[i].pitch = idx_value + 32; | 1625 | track->textures[i].pitch = idx_value + 32; |
1626 | track->tex_dirty = true; | ||
1611 | break; | 1627 | break; |
1612 | case RADEON_PP_TXFILTER_0: | 1628 | case RADEON_PP_TXFILTER_0: |
1613 | case RADEON_PP_TXFILTER_1: | 1629 | case RADEON_PP_TXFILTER_1: |
@@ -1621,6 +1637,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1621 | tmp = (idx_value >> 27) & 0x7; | 1637 | tmp = (idx_value >> 27) & 0x7; |
1622 | if (tmp == 2 || tmp == 6) | 1638 | if (tmp == 2 || tmp == 6) |
1623 | track->textures[i].roundup_h = false; | 1639 | track->textures[i].roundup_h = false; |
1640 | track->tex_dirty = true; | ||
1624 | break; | 1641 | break; |
1625 | case RADEON_PP_TXFORMAT_0: | 1642 | case RADEON_PP_TXFORMAT_0: |
1626 | case RADEON_PP_TXFORMAT_1: | 1643 | case RADEON_PP_TXFORMAT_1: |
@@ -1673,6 +1690,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1673 | } | 1690 | } |
1674 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); | 1691 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1675 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); | 1692 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
1693 | track->tex_dirty = true; | ||
1676 | break; | 1694 | break; |
1677 | case RADEON_PP_CUBIC_FACES_0: | 1695 | case RADEON_PP_CUBIC_FACES_0: |
1678 | case RADEON_PP_CUBIC_FACES_1: | 1696 | case RADEON_PP_CUBIC_FACES_1: |
@@ -1683,6 +1701,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1683 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | 1701 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
1684 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); | 1702 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
1685 | } | 1703 | } |
1704 | track->tex_dirty = true; | ||
1686 | break; | 1705 | break; |
1687 | default: | 1706 | default: |
1688 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | 1707 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
@@ -3318,9 +3337,9 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) | |||
3318 | unsigned long size; | 3337 | unsigned long size; |
3319 | unsigned prim_walk; | 3338 | unsigned prim_walk; |
3320 | unsigned nverts; | 3339 | unsigned nverts; |
3321 | unsigned num_cb = track->num_cb; | 3340 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; |
3322 | 3341 | ||
3323 | if (!track->zb_cb_clear && !track->color_channel_mask && | 3342 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
3324 | !track->blend_read_enable) | 3343 | !track->blend_read_enable) |
3325 | num_cb = 0; | 3344 | num_cb = 0; |
3326 | 3345 | ||
@@ -3341,7 +3360,9 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) | |||
3341 | return -EINVAL; | 3360 | return -EINVAL; |
3342 | } | 3361 | } |
3343 | } | 3362 | } |
3344 | if (track->z_enabled) { | 3363 | track->cb_dirty = false; |
3364 | |||
3365 | if (track->zb_dirty && track->z_enabled) { | ||
3345 | if (track->zb.robj == NULL) { | 3366 | if (track->zb.robj == NULL) { |
3346 | DRM_ERROR("[drm] No buffer for z buffer !\n"); | 3367 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
3347 | return -EINVAL; | 3368 | return -EINVAL; |
@@ -3358,6 +3379,28 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) | |||
3358 | return -EINVAL; | 3379 | return -EINVAL; |
3359 | } | 3380 | } |
3360 | } | 3381 | } |
3382 | track->zb_dirty = false; | ||
3383 | |||
3384 | if (track->aa_dirty && track->aaresolve) { | ||
3385 | if (track->aa.robj == NULL) { | ||
3386 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); | ||
3387 | return -EINVAL; | ||
3388 | } | ||
3389 | /* I believe the format comes from colorbuffer0. */ | ||
3390 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; | ||
3391 | size += track->aa.offset; | ||
3392 | if (size > radeon_bo_size(track->aa.robj)) { | ||
3393 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " | ||
3394 | "(need %lu have %lu) !\n", i, size, | ||
3395 | radeon_bo_size(track->aa.robj)); | ||
3396 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", | ||
3397 | i, track->aa.pitch, track->cb[0].cpp, | ||
3398 | track->aa.offset, track->maxy); | ||
3399 | return -EINVAL; | ||
3400 | } | ||
3401 | } | ||
3402 | track->aa_dirty = false; | ||
3403 | |||
3361 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; | 3404 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
3362 | if (track->vap_vf_cntl & (1 << 14)) { | 3405 | if (track->vap_vf_cntl & (1 << 14)) { |
3363 | nverts = track->vap_alt_nverts; | 3406 | nverts = track->vap_alt_nverts; |
@@ -3417,13 +3460,23 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) | |||
3417 | prim_walk); | 3460 | prim_walk); |
3418 | return -EINVAL; | 3461 | return -EINVAL; |
3419 | } | 3462 | } |
3420 | return r100_cs_track_texture_check(rdev, track); | 3463 | |
3464 | if (track->tex_dirty) { | ||
3465 | track->tex_dirty = false; | ||
3466 | return r100_cs_track_texture_check(rdev, track); | ||
3467 | } | ||
3468 | return 0; | ||
3421 | } | 3469 | } |
3422 | 3470 | ||
3423 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) | 3471 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
3424 | { | 3472 | { |
3425 | unsigned i, face; | 3473 | unsigned i, face; |
3426 | 3474 | ||
3475 | track->cb_dirty = true; | ||
3476 | track->zb_dirty = true; | ||
3477 | track->tex_dirty = true; | ||
3478 | track->aa_dirty = true; | ||
3479 | |||
3427 | if (rdev->family < CHIP_R300) { | 3480 | if (rdev->family < CHIP_R300) { |
3428 | track->num_cb = 1; | 3481 | track->num_cb = 1; |
3429 | if (rdev->family <= CHIP_RS200) | 3482 | if (rdev->family <= CHIP_RS200) |
@@ -3437,6 +3490,8 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track | |||
3437 | track->num_texture = 16; | 3490 | track->num_texture = 16; |
3438 | track->maxy = 4096; | 3491 | track->maxy = 4096; |
3439 | track->separate_cube = 0; | 3492 | track->separate_cube = 0; |
3493 | track->aaresolve = true; | ||
3494 | track->aa.robj = NULL; | ||
3440 | } | 3495 | } |
3441 | 3496 | ||
3442 | for (i = 0; i < track->num_cb; i++) { | 3497 | for (i = 0; i < track->num_cb; i++) { |
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h index af65600e6564..2fef9de7f363 100644 --- a/drivers/gpu/drm/radeon/r100_track.h +++ b/drivers/gpu/drm/radeon/r100_track.h | |||
@@ -52,14 +52,7 @@ struct r100_cs_track_texture { | |||
52 | unsigned compress_format; | 52 | unsigned compress_format; |
53 | }; | 53 | }; |
54 | 54 | ||
55 | struct r100_cs_track_limits { | ||
56 | unsigned num_cb; | ||
57 | unsigned num_texture; | ||
58 | unsigned max_levels; | ||
59 | }; | ||
60 | |||
61 | struct r100_cs_track { | 55 | struct r100_cs_track { |
62 | struct radeon_device *rdev; | ||
63 | unsigned num_cb; | 56 | unsigned num_cb; |
64 | unsigned num_texture; | 57 | unsigned num_texture; |
65 | unsigned maxy; | 58 | unsigned maxy; |
@@ -73,11 +66,17 @@ struct r100_cs_track { | |||
73 | struct r100_cs_track_array arrays[11]; | 66 | struct r100_cs_track_array arrays[11]; |
74 | struct r100_cs_track_cb cb[R300_MAX_CB]; | 67 | struct r100_cs_track_cb cb[R300_MAX_CB]; |
75 | struct r100_cs_track_cb zb; | 68 | struct r100_cs_track_cb zb; |
69 | struct r100_cs_track_cb aa; | ||
76 | struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; | 70 | struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; |
77 | bool z_enabled; | 71 | bool z_enabled; |
78 | bool separate_cube; | 72 | bool separate_cube; |
79 | bool zb_cb_clear; | 73 | bool zb_cb_clear; |
80 | bool blend_read_enable; | 74 | bool blend_read_enable; |
75 | bool cb_dirty; | ||
76 | bool zb_dirty; | ||
77 | bool tex_dirty; | ||
78 | bool aa_dirty; | ||
79 | bool aaresolve; | ||
81 | }; | 80 | }; |
82 | 81 | ||
83 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); | 82 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); |
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c index d2408c395619..f24058300413 100644 --- a/drivers/gpu/drm/radeon/r200.c +++ b/drivers/gpu/drm/radeon/r200.c | |||
@@ -184,6 +184,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
184 | } | 184 | } |
185 | track->zb.robj = reloc->robj; | 185 | track->zb.robj = reloc->robj; |
186 | track->zb.offset = idx_value; | 186 | track->zb.offset = idx_value; |
187 | track->zb_dirty = true; | ||
187 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 188 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
188 | break; | 189 | break; |
189 | case RADEON_RB3D_COLOROFFSET: | 190 | case RADEON_RB3D_COLOROFFSET: |
@@ -196,6 +197,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
196 | } | 197 | } |
197 | track->cb[0].robj = reloc->robj; | 198 | track->cb[0].robj = reloc->robj; |
198 | track->cb[0].offset = idx_value; | 199 | track->cb[0].offset = idx_value; |
200 | track->cb_dirty = true; | ||
199 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 201 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
200 | break; | 202 | break; |
201 | case R200_PP_TXOFFSET_0: | 203 | case R200_PP_TXOFFSET_0: |
@@ -214,6 +216,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
214 | } | 216 | } |
215 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 217 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
216 | track->textures[i].robj = reloc->robj; | 218 | track->textures[i].robj = reloc->robj; |
219 | track->tex_dirty = true; | ||
217 | break; | 220 | break; |
218 | case R200_PP_CUBIC_OFFSET_F1_0: | 221 | case R200_PP_CUBIC_OFFSET_F1_0: |
219 | case R200_PP_CUBIC_OFFSET_F2_0: | 222 | case R200_PP_CUBIC_OFFSET_F2_0: |
@@ -257,9 +260,12 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
257 | track->textures[i].cube_info[face - 1].offset = idx_value; | 260 | track->textures[i].cube_info[face - 1].offset = idx_value; |
258 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 261 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
259 | track->textures[i].cube_info[face - 1].robj = reloc->robj; | 262 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
263 | track->tex_dirty = true; | ||
260 | break; | 264 | break; |
261 | case RADEON_RE_WIDTH_HEIGHT: | 265 | case RADEON_RE_WIDTH_HEIGHT: |
262 | track->maxy = ((idx_value >> 16) & 0x7FF); | 266 | track->maxy = ((idx_value >> 16) & 0x7FF); |
267 | track->cb_dirty = true; | ||
268 | track->zb_dirty = true; | ||
263 | break; | 269 | break; |
264 | case RADEON_RB3D_COLORPITCH: | 270 | case RADEON_RB3D_COLORPITCH: |
265 | r = r100_cs_packet_next_reloc(p, &reloc); | 271 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -280,9 +286,11 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
280 | ib[idx] = tmp; | 286 | ib[idx] = tmp; |
281 | 287 | ||
282 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; | 288 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
289 | track->cb_dirty = true; | ||
283 | break; | 290 | break; |
284 | case RADEON_RB3D_DEPTHPITCH: | 291 | case RADEON_RB3D_DEPTHPITCH: |
285 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; | 292 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
293 | track->zb_dirty = true; | ||
286 | break; | 294 | break; |
287 | case RADEON_RB3D_CNTL: | 295 | case RADEON_RB3D_CNTL: |
288 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { | 296 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
@@ -312,6 +320,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
312 | } | 320 | } |
313 | 321 | ||
314 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); | 322 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
323 | track->cb_dirty = true; | ||
324 | track->zb_dirty = true; | ||
315 | break; | 325 | break; |
316 | case RADEON_RB3D_ZSTENCILCNTL: | 326 | case RADEON_RB3D_ZSTENCILCNTL: |
317 | switch (idx_value & 0xf) { | 327 | switch (idx_value & 0xf) { |
@@ -329,6 +339,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
329 | default: | 339 | default: |
330 | break; | 340 | break; |
331 | } | 341 | } |
342 | track->zb_dirty = true; | ||
332 | break; | 343 | break; |
333 | case RADEON_RB3D_ZPASS_ADDR: | 344 | case RADEON_RB3D_ZPASS_ADDR: |
334 | r = r100_cs_packet_next_reloc(p, &reloc); | 345 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -345,6 +356,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
345 | uint32_t temp = idx_value >> 4; | 356 | uint32_t temp = idx_value >> 4; |
346 | for (i = 0; i < track->num_texture; i++) | 357 | for (i = 0; i < track->num_texture; i++) |
347 | track->textures[i].enabled = !!(temp & (1 << i)); | 358 | track->textures[i].enabled = !!(temp & (1 << i)); |
359 | track->tex_dirty = true; | ||
348 | } | 360 | } |
349 | break; | 361 | break; |
350 | case RADEON_SE_VF_CNTL: | 362 | case RADEON_SE_VF_CNTL: |
@@ -369,6 +381,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
369 | i = (reg - R200_PP_TXSIZE_0) / 32; | 381 | i = (reg - R200_PP_TXSIZE_0) / 32; |
370 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; | 382 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
371 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | 383 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
384 | track->tex_dirty = true; | ||
372 | break; | 385 | break; |
373 | case R200_PP_TXPITCH_0: | 386 | case R200_PP_TXPITCH_0: |
374 | case R200_PP_TXPITCH_1: | 387 | case R200_PP_TXPITCH_1: |
@@ -378,6 +391,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
378 | case R200_PP_TXPITCH_5: | 391 | case R200_PP_TXPITCH_5: |
379 | i = (reg - R200_PP_TXPITCH_0) / 32; | 392 | i = (reg - R200_PP_TXPITCH_0) / 32; |
380 | track->textures[i].pitch = idx_value + 32; | 393 | track->textures[i].pitch = idx_value + 32; |
394 | track->tex_dirty = true; | ||
381 | break; | 395 | break; |
382 | case R200_PP_TXFILTER_0: | 396 | case R200_PP_TXFILTER_0: |
383 | case R200_PP_TXFILTER_1: | 397 | case R200_PP_TXFILTER_1: |
@@ -394,6 +408,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
394 | tmp = (idx_value >> 27) & 0x7; | 408 | tmp = (idx_value >> 27) & 0x7; |
395 | if (tmp == 2 || tmp == 6) | 409 | if (tmp == 2 || tmp == 6) |
396 | track->textures[i].roundup_h = false; | 410 | track->textures[i].roundup_h = false; |
411 | track->tex_dirty = true; | ||
397 | break; | 412 | break; |
398 | case R200_PP_TXMULTI_CTL_0: | 413 | case R200_PP_TXMULTI_CTL_0: |
399 | case R200_PP_TXMULTI_CTL_1: | 414 | case R200_PP_TXMULTI_CTL_1: |
@@ -432,6 +447,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
432 | track->textures[i].tex_coord_type = 1; | 447 | track->textures[i].tex_coord_type = 1; |
433 | break; | 448 | break; |
434 | } | 449 | } |
450 | track->tex_dirty = true; | ||
435 | break; | 451 | break; |
436 | case R200_PP_TXFORMAT_0: | 452 | case R200_PP_TXFORMAT_0: |
437 | case R200_PP_TXFORMAT_1: | 453 | case R200_PP_TXFORMAT_1: |
@@ -488,6 +504,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
488 | } | 504 | } |
489 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); | 505 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
490 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); | 506 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
507 | track->tex_dirty = true; | ||
491 | break; | 508 | break; |
492 | case R200_PP_CUBIC_FACES_0: | 509 | case R200_PP_CUBIC_FACES_0: |
493 | case R200_PP_CUBIC_FACES_1: | 510 | case R200_PP_CUBIC_FACES_1: |
@@ -501,6 +518,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
501 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | 518 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
502 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); | 519 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
503 | } | 520 | } |
521 | track->tex_dirty = true; | ||
504 | break; | 522 | break; |
505 | default: | 523 | default: |
506 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | 524 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 55fe5ba7def3..069efa8c8ecf 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -667,6 +667,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
667 | } | 667 | } |
668 | track->cb[i].robj = reloc->robj; | 668 | track->cb[i].robj = reloc->robj; |
669 | track->cb[i].offset = idx_value; | 669 | track->cb[i].offset = idx_value; |
670 | track->cb_dirty = true; | ||
670 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 671 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
671 | break; | 672 | break; |
672 | case R300_ZB_DEPTHOFFSET: | 673 | case R300_ZB_DEPTHOFFSET: |
@@ -679,6 +680,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
679 | } | 680 | } |
680 | track->zb.robj = reloc->robj; | 681 | track->zb.robj = reloc->robj; |
681 | track->zb.offset = idx_value; | 682 | track->zb.offset = idx_value; |
683 | track->zb_dirty = true; | ||
682 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 684 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
683 | break; | 685 | break; |
684 | case R300_TX_OFFSET_0: | 686 | case R300_TX_OFFSET_0: |
@@ -717,6 +719,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
717 | tmp |= tile_flags; | 719 | tmp |= tile_flags; |
718 | ib[idx] = tmp; | 720 | ib[idx] = tmp; |
719 | track->textures[i].robj = reloc->robj; | 721 | track->textures[i].robj = reloc->robj; |
722 | track->tex_dirty = true; | ||
720 | break; | 723 | break; |
721 | /* Tracked registers */ | 724 | /* Tracked registers */ |
722 | case 0x2084: | 725 | case 0x2084: |
@@ -743,6 +746,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
743 | if (p->rdev->family < CHIP_RV515) { | 746 | if (p->rdev->family < CHIP_RV515) { |
744 | track->maxy -= 1440; | 747 | track->maxy -= 1440; |
745 | } | 748 | } |
749 | track->cb_dirty = true; | ||
750 | track->zb_dirty = true; | ||
746 | break; | 751 | break; |
747 | case 0x4E00: | 752 | case 0x4E00: |
748 | /* RB3D_CCTL */ | 753 | /* RB3D_CCTL */ |
@@ -752,6 +757,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
752 | return -EINVAL; | 757 | return -EINVAL; |
753 | } | 758 | } |
754 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; | 759 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
760 | track->cb_dirty = true; | ||
755 | break; | 761 | break; |
756 | case 0x4E38: | 762 | case 0x4E38: |
757 | case 0x4E3C: | 763 | case 0x4E3C: |
@@ -814,6 +820,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
814 | ((idx_value >> 21) & 0xF)); | 820 | ((idx_value >> 21) & 0xF)); |
815 | return -EINVAL; | 821 | return -EINVAL; |
816 | } | 822 | } |
823 | track->cb_dirty = true; | ||
817 | break; | 824 | break; |
818 | case 0x4F00: | 825 | case 0x4F00: |
819 | /* ZB_CNTL */ | 826 | /* ZB_CNTL */ |
@@ -822,6 +829,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
822 | } else { | 829 | } else { |
823 | track->z_enabled = false; | 830 | track->z_enabled = false; |
824 | } | 831 | } |
832 | track->zb_dirty = true; | ||
825 | break; | 833 | break; |
826 | case 0x4F10: | 834 | case 0x4F10: |
827 | /* ZB_FORMAT */ | 835 | /* ZB_FORMAT */ |
@@ -838,6 +846,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
838 | (idx_value & 0xF)); | 846 | (idx_value & 0xF)); |
839 | return -EINVAL; | 847 | return -EINVAL; |
840 | } | 848 | } |
849 | track->zb_dirty = true; | ||
841 | break; | 850 | break; |
842 | case 0x4F24: | 851 | case 0x4F24: |
843 | /* ZB_DEPTHPITCH */ | 852 | /* ZB_DEPTHPITCH */ |
@@ -861,14 +870,17 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
861 | ib[idx] = tmp; | 870 | ib[idx] = tmp; |
862 | 871 | ||
863 | track->zb.pitch = idx_value & 0x3FFC; | 872 | track->zb.pitch = idx_value & 0x3FFC; |
873 | track->zb_dirty = true; | ||
864 | break; | 874 | break; |
865 | case 0x4104: | 875 | case 0x4104: |
876 | /* TX_ENABLE */ | ||
866 | for (i = 0; i < 16; i++) { | 877 | for (i = 0; i < 16; i++) { |
867 | bool enabled; | 878 | bool enabled; |
868 | 879 | ||
869 | enabled = !!(idx_value & (1 << i)); | 880 | enabled = !!(idx_value & (1 << i)); |
870 | track->textures[i].enabled = enabled; | 881 | track->textures[i].enabled = enabled; |
871 | } | 882 | } |
883 | track->tex_dirty = true; | ||
872 | break; | 884 | break; |
873 | case 0x44C0: | 885 | case 0x44C0: |
874 | case 0x44C4: | 886 | case 0x44C4: |
@@ -898,6 +910,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
898 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; | 910 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
899 | break; | 911 | break; |
900 | case R300_TX_FORMAT_X16: | 912 | case R300_TX_FORMAT_X16: |
913 | case R300_TX_FORMAT_FL_I16: | ||
901 | case R300_TX_FORMAT_Y8X8: | 914 | case R300_TX_FORMAT_Y8X8: |
902 | case R300_TX_FORMAT_Z5Y6X5: | 915 | case R300_TX_FORMAT_Z5Y6X5: |
903 | case R300_TX_FORMAT_Z6Y5X5: | 916 | case R300_TX_FORMAT_Z6Y5X5: |
@@ -910,6 +923,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
910 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; | 923 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
911 | break; | 924 | break; |
912 | case R300_TX_FORMAT_Y16X16: | 925 | case R300_TX_FORMAT_Y16X16: |
926 | case R300_TX_FORMAT_FL_I16A16: | ||
913 | case R300_TX_FORMAT_Z11Y11X10: | 927 | case R300_TX_FORMAT_Z11Y11X10: |
914 | case R300_TX_FORMAT_Z10Y11X11: | 928 | case R300_TX_FORMAT_Z10Y11X11: |
915 | case R300_TX_FORMAT_W8Z8Y8X8: | 929 | case R300_TX_FORMAT_W8Z8Y8X8: |
@@ -951,8 +965,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
951 | DRM_ERROR("Invalid texture format %u\n", | 965 | DRM_ERROR("Invalid texture format %u\n", |
952 | (idx_value & 0x1F)); | 966 | (idx_value & 0x1F)); |
953 | return -EINVAL; | 967 | return -EINVAL; |
954 | break; | ||
955 | } | 968 | } |
969 | track->tex_dirty = true; | ||
956 | break; | 970 | break; |
957 | case 0x4400: | 971 | case 0x4400: |
958 | case 0x4404: | 972 | case 0x4404: |
@@ -980,6 +994,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
980 | if (tmp == 2 || tmp == 4 || tmp == 6) { | 994 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
981 | track->textures[i].roundup_h = false; | 995 | track->textures[i].roundup_h = false; |
982 | } | 996 | } |
997 | track->tex_dirty = true; | ||
983 | break; | 998 | break; |
984 | case 0x4500: | 999 | case 0x4500: |
985 | case 0x4504: | 1000 | case 0x4504: |
@@ -1017,6 +1032,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1017 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); | 1032 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
1018 | return -EINVAL; | 1033 | return -EINVAL; |
1019 | } | 1034 | } |
1035 | track->tex_dirty = true; | ||
1020 | break; | 1036 | break; |
1021 | case 0x4480: | 1037 | case 0x4480: |
1022 | case 0x4484: | 1038 | case 0x4484: |
@@ -1046,6 +1062,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1046 | track->textures[i].use_pitch = !!tmp; | 1062 | track->textures[i].use_pitch = !!tmp; |
1047 | tmp = (idx_value >> 22) & 0xF; | 1063 | tmp = (idx_value >> 22) & 0xF; |
1048 | track->textures[i].txdepth = tmp; | 1064 | track->textures[i].txdepth = tmp; |
1065 | track->tex_dirty = true; | ||
1049 | break; | 1066 | break; |
1050 | case R300_ZB_ZPASS_ADDR: | 1067 | case R300_ZB_ZPASS_ADDR: |
1051 | r = r100_cs_packet_next_reloc(p, &reloc); | 1068 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1060,6 +1077,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1060 | case 0x4e0c: | 1077 | case 0x4e0c: |
1061 | /* RB3D_COLOR_CHANNEL_MASK */ | 1078 | /* RB3D_COLOR_CHANNEL_MASK */ |
1062 | track->color_channel_mask = idx_value; | 1079 | track->color_channel_mask = idx_value; |
1080 | track->cb_dirty = true; | ||
1063 | break; | 1081 | break; |
1064 | case 0x43a4: | 1082 | case 0x43a4: |
1065 | /* SC_HYPERZ_EN */ | 1083 | /* SC_HYPERZ_EN */ |
@@ -1073,6 +1091,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1073 | case 0x4f1c: | 1091 | case 0x4f1c: |
1074 | /* ZB_BW_CNTL */ | 1092 | /* ZB_BW_CNTL */ |
1075 | track->zb_cb_clear = !!(idx_value & (1 << 5)); | 1093 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
1094 | track->cb_dirty = true; | ||
1095 | track->zb_dirty = true; | ||
1076 | if (p->rdev->hyperz_filp != p->filp) { | 1096 | if (p->rdev->hyperz_filp != p->filp) { |
1077 | if (idx_value & (R300_HIZ_ENABLE | | 1097 | if (idx_value & (R300_HIZ_ENABLE | |
1078 | R300_RD_COMP_ENABLE | | 1098 | R300_RD_COMP_ENABLE | |
@@ -1084,8 +1104,28 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1084 | case 0x4e04: | 1104 | case 0x4e04: |
1085 | /* RB3D_BLENDCNTL */ | 1105 | /* RB3D_BLENDCNTL */ |
1086 | track->blend_read_enable = !!(idx_value & (1 << 2)); | 1106 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
1107 | track->cb_dirty = true; | ||
1108 | break; | ||
1109 | case R300_RB3D_AARESOLVE_OFFSET: | ||
1110 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1111 | if (r) { | ||
1112 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
1113 | idx, reg); | ||
1114 | r100_cs_dump_packet(p, pkt); | ||
1115 | return r; | ||
1116 | } | ||
1117 | track->aa.robj = reloc->robj; | ||
1118 | track->aa.offset = idx_value; | ||
1119 | track->aa_dirty = true; | ||
1120 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | ||
1121 | break; | ||
1122 | case R300_RB3D_AARESOLVE_PITCH: | ||
1123 | track->aa.pitch = idx_value & 0x3FFE; | ||
1124 | track->aa_dirty = true; | ||
1087 | break; | 1125 | break; |
1088 | case 0x4f28: /* ZB_DEPTHCLEARVALUE */ | 1126 | case R300_RB3D_AARESOLVE_CTL: |
1127 | track->aaresolve = idx_value & 0x1; | ||
1128 | track->aa_dirty = true; | ||
1089 | break; | 1129 | break; |
1090 | case 0x4f30: /* ZB_MASK_OFFSET */ | 1130 | case 0x4f30: /* ZB_MASK_OFFSET */ |
1091 | case 0x4f34: /* ZB_ZMASK_PITCH */ | 1131 | case 0x4f34: /* ZB_ZMASK_PITCH */ |
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index 1a0d5362cd79..f0bce399c9f3 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h | |||
@@ -1371,6 +1371,8 @@ | |||
1371 | #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ | 1371 | #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ |
1372 | #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ | 1372 | #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ |
1373 | 1373 | ||
1374 | #define R300_RB3D_AARESOLVE_OFFSET 0x4E80 | ||
1375 | #define R300_RB3D_AARESOLVE_PITCH 0x4E84 | ||
1374 | #define R300_RB3D_AARESOLVE_CTL 0x4E88 | 1376 | #define R300_RB3D_AARESOLVE_CTL 0x4E88 |
1375 | /* gap */ | 1377 | /* gap */ |
1376 | 1378 | ||
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 650672a0f5ad..de88624d5f87 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2105,7 +2105,11 @@ static int r600_cp_load_microcode(struct radeon_device *rdev) | |||
2105 | 2105 | ||
2106 | r600_cp_stop(rdev); | 2106 | r600_cp_stop(rdev); |
2107 | 2107 | ||
2108 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | 2108 | WREG32(CP_RB_CNTL, |
2109 | #ifdef __BIG_ENDIAN | ||
2110 | BUF_SWAP_32BIT | | ||
2111 | #endif | ||
2112 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | ||
2109 | 2113 | ||
2110 | /* Reset cp */ | 2114 | /* Reset cp */ |
2111 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | 2115 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
@@ -2192,7 +2196,11 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2192 | WREG32(CP_RB_WPTR, 0); | 2196 | WREG32(CP_RB_WPTR, 0); |
2193 | 2197 | ||
2194 | /* set the wb address whether it's enabled or not */ | 2198 | /* set the wb address whether it's enabled or not */ |
2195 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 2199 | WREG32(CP_RB_RPTR_ADDR, |
2200 | #ifdef __BIG_ENDIAN | ||
2201 | RB_RPTR_SWAP(2) | | ||
2202 | #endif | ||
2203 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); | ||
2196 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | 2204 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2197 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | 2205 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
2198 | 2206 | ||
@@ -2628,7 +2636,11 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |||
2628 | { | 2636 | { |
2629 | /* FIXME: implement */ | 2637 | /* FIXME: implement */ |
2630 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 2638 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2631 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | 2639 | radeon_ring_write(rdev, |
2640 | #ifdef __BIG_ENDIAN | ||
2641 | (2 << 0) | | ||
2642 | #endif | ||
2643 | (ib->gpu_addr & 0xFFFFFFFC)); | ||
2632 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | 2644 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); |
2633 | radeon_ring_write(rdev, ib->length_dw); | 2645 | radeon_ring_write(rdev, ib->length_dw); |
2634 | } | 2646 | } |
@@ -3297,8 +3309,8 @@ restart_ih: | |||
3297 | while (rptr != wptr) { | 3309 | while (rptr != wptr) { |
3298 | /* wptr/rptr are in bytes! */ | 3310 | /* wptr/rptr are in bytes! */ |
3299 | ring_index = rptr / 4; | 3311 | ring_index = rptr / 4; |
3300 | src_id = rdev->ih.ring[ring_index] & 0xff; | 3312 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
3301 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | 3313 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; |
3302 | 3314 | ||
3303 | switch (src_id) { | 3315 | switch (src_id) { |
3304 | case 1: /* D1 vblank/vline */ | 3316 | case 1: /* D1 vblank/vline */ |
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c index ca5c29f70779..7f1043448d25 100644 --- a/drivers/gpu/drm/radeon/r600_blit.c +++ b/drivers/gpu/drm/radeon/r600_blit.c | |||
@@ -137,9 +137,9 @@ set_shaders(struct drm_device *dev) | |||
137 | ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); | 137 | ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); |
138 | 138 | ||
139 | for (i = 0; i < r6xx_vs_size; i++) | 139 | for (i = 0; i < r6xx_vs_size; i++) |
140 | vs[i] = r6xx_vs[i]; | 140 | vs[i] = cpu_to_le32(r6xx_vs[i]); |
141 | for (i = 0; i < r6xx_ps_size; i++) | 141 | for (i = 0; i < r6xx_ps_size; i++) |
142 | ps[i] = r6xx_ps[i]; | 142 | ps[i] = cpu_to_le32(r6xx_ps[i]); |
143 | 143 | ||
144 | dev_priv->blit_vb->used = 512; | 144 | dev_priv->blit_vb->used = 512; |
145 | 145 | ||
@@ -192,6 +192,9 @@ set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr) | |||
192 | DRM_DEBUG("\n"); | 192 | DRM_DEBUG("\n"); |
193 | 193 | ||
194 | sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); | 194 | sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8)); |
195 | #ifdef __BIG_ENDIAN | ||
196 | sq_vtx_constant_word2 |= (2 << 30); | ||
197 | #endif | ||
195 | 198 | ||
196 | BEGIN_RING(9); | 199 | BEGIN_RING(9); |
197 | OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); | 200 | OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); |
@@ -291,7 +294,11 @@ draw_auto(drm_radeon_private_t *dev_priv) | |||
291 | OUT_RING(DI_PT_RECTLIST); | 294 | OUT_RING(DI_PT_RECTLIST); |
292 | 295 | ||
293 | OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); | 296 | OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0)); |
297 | #ifdef __BIG_ENDIAN | ||
298 | OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT); | ||
299 | #else | ||
294 | OUT_RING(DI_INDEX_SIZE_16_BIT); | 300 | OUT_RING(DI_INDEX_SIZE_16_BIT); |
301 | #endif | ||
295 | 302 | ||
296 | OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); | 303 | OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0)); |
297 | OUT_RING(1); | 304 | OUT_RING(1); |
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index 86e5aa07f0db..41f7aafc97c4 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c | |||
@@ -54,7 +54,7 @@ set_render_target(struct radeon_device *rdev, int format, | |||
54 | if (h < 8) | 54 | if (h < 8) |
55 | h = 8; | 55 | h = 8; |
56 | 56 | ||
57 | cb_color_info = ((format << 2) | (1 << 27)); | 57 | cb_color_info = ((format << 2) | (1 << 27) | (1 << 8)); |
58 | pitch = (w / 8) - 1; | 58 | pitch = (w / 8) - 1; |
59 | slice = ((w * h) / 64) - 1; | 59 | slice = ((w * h) / 64) - 1; |
60 | 60 | ||
@@ -165,6 +165,9 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) | |||
165 | u32 sq_vtx_constant_word2; | 165 | u32 sq_vtx_constant_word2; |
166 | 166 | ||
167 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); | 167 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
168 | #ifdef __BIG_ENDIAN | ||
169 | sq_vtx_constant_word2 |= (2 << 30); | ||
170 | #endif | ||
168 | 171 | ||
169 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); | 172 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
170 | radeon_ring_write(rdev, 0x460); | 173 | radeon_ring_write(rdev, 0x460); |
@@ -199,7 +202,7 @@ set_tex_resource(struct radeon_device *rdev, | |||
199 | if (h < 1) | 202 | if (h < 1) |
200 | h = 1; | 203 | h = 1; |
201 | 204 | ||
202 | sq_tex_resource_word0 = (1 << 0); | 205 | sq_tex_resource_word0 = (1 << 0) | (1 << 3); |
203 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | | 206 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | |
204 | ((w - 1) << 19)); | 207 | ((w - 1) << 19)); |
205 | 208 | ||
@@ -253,7 +256,11 @@ draw_auto(struct radeon_device *rdev) | |||
253 | radeon_ring_write(rdev, DI_PT_RECTLIST); | 256 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
254 | 257 | ||
255 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); | 258 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
256 | radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT); | 259 | radeon_ring_write(rdev, |
260 | #ifdef __BIG_ENDIAN | ||
261 | (2 << 2) | | ||
262 | #endif | ||
263 | DI_INDEX_SIZE_16_BIT); | ||
257 | 264 | ||
258 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); | 265 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
259 | radeon_ring_write(rdev, 1); | 266 | radeon_ring_write(rdev, 1); |
@@ -424,7 +431,11 @@ set_default_state(struct radeon_device *rdev) | |||
424 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); | 431 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
425 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; | 432 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
426 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 433 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
427 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); | 434 | radeon_ring_write(rdev, |
435 | #ifdef __BIG_ENDIAN | ||
436 | (2 << 0) | | ||
437 | #endif | ||
438 | (gpu_addr & 0xFFFFFFFC)); | ||
428 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); | 439 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
429 | radeon_ring_write(rdev, dwords); | 440 | radeon_ring_write(rdev, dwords); |
430 | 441 | ||
@@ -467,7 +478,7 @@ static inline uint32_t i2f(uint32_t input) | |||
467 | int r600_blit_init(struct radeon_device *rdev) | 478 | int r600_blit_init(struct radeon_device *rdev) |
468 | { | 479 | { |
469 | u32 obj_size; | 480 | u32 obj_size; |
470 | int r, dwords; | 481 | int i, r, dwords; |
471 | void *ptr; | 482 | void *ptr; |
472 | u32 packet2s[16]; | 483 | u32 packet2s[16]; |
473 | int num_packet2s = 0; | 484 | int num_packet2s = 0; |
@@ -486,7 +497,7 @@ int r600_blit_init(struct radeon_device *rdev) | |||
486 | 497 | ||
487 | dwords = rdev->r600_blit.state_len; | 498 | dwords = rdev->r600_blit.state_len; |
488 | while (dwords & 0xf) { | 499 | while (dwords & 0xf) { |
489 | packet2s[num_packet2s++] = PACKET2(0); | 500 | packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
490 | dwords++; | 501 | dwords++; |
491 | } | 502 | } |
492 | 503 | ||
@@ -529,8 +540,10 @@ int r600_blit_init(struct radeon_device *rdev) | |||
529 | if (num_packet2s) | 540 | if (num_packet2s) |
530 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), | 541 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
531 | packet2s, num_packet2s * 4); | 542 | packet2s, num_packet2s * 4); |
532 | memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4); | 543 | for (i = 0; i < r6xx_vs_size; i++) |
533 | memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); | 544 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]); |
545 | for (i = 0; i < r6xx_ps_size; i++) | ||
546 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); | ||
534 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); | 547 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
535 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | 548 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
536 | 549 | ||
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c index e8151c1d55b2..2d1f6c5ee2a7 100644 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c | |||
@@ -684,7 +684,11 @@ const u32 r6xx_vs[] = | |||
684 | 0x00000000, | 684 | 0x00000000, |
685 | 0x3c000000, | 685 | 0x3c000000, |
686 | 0x68cd1000, | 686 | 0x68cd1000, |
687 | #ifdef __BIG_ENDIAN | ||
688 | 0x000a0000, | ||
689 | #else | ||
687 | 0x00080000, | 690 | 0x00080000, |
691 | #endif | ||
688 | 0x00000000, | 692 | 0x00000000, |
689 | }; | 693 | }; |
690 | 694 | ||
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 4f4cd8b286d5..c3ab959bdc7c 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c | |||
@@ -396,6 +396,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) | |||
396 | r600_do_cp_stop(dev_priv); | 396 | r600_do_cp_stop(dev_priv); |
397 | 397 | ||
398 | RADEON_WRITE(R600_CP_RB_CNTL, | 398 | RADEON_WRITE(R600_CP_RB_CNTL, |
399 | #ifdef __BIG_ENDIAN | ||
400 | R600_BUF_SWAP_32BIT | | ||
401 | #endif | ||
399 | R600_RB_NO_UPDATE | | 402 | R600_RB_NO_UPDATE | |
400 | R600_RB_BLKSZ(15) | | 403 | R600_RB_BLKSZ(15) | |
401 | R600_RB_BUFSZ(3)); | 404 | R600_RB_BUFSZ(3)); |
@@ -486,9 +489,12 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) | |||
486 | r600_do_cp_stop(dev_priv); | 489 | r600_do_cp_stop(dev_priv); |
487 | 490 | ||
488 | RADEON_WRITE(R600_CP_RB_CNTL, | 491 | RADEON_WRITE(R600_CP_RB_CNTL, |
492 | #ifdef __BIG_ENDIAN | ||
493 | R600_BUF_SWAP_32BIT | | ||
494 | #endif | ||
489 | R600_RB_NO_UPDATE | | 495 | R600_RB_NO_UPDATE | |
490 | (15 << 8) | | 496 | R600_RB_BLKSZ(15) | |
491 | (3 << 0)); | 497 | R600_RB_BUFSZ(3)); |
492 | 498 | ||
493 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | 499 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); |
494 | RADEON_READ(R600_GRBM_SOFT_RESET); | 500 | RADEON_READ(R600_GRBM_SOFT_RESET); |
@@ -550,8 +556,12 @@ static void r600_test_writeback(drm_radeon_private_t *dev_priv) | |||
550 | 556 | ||
551 | if (!dev_priv->writeback_works) { | 557 | if (!dev_priv->writeback_works) { |
552 | /* Disable writeback to avoid unnecessary bus master transfer */ | 558 | /* Disable writeback to avoid unnecessary bus master transfer */ |
553 | RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | | 559 | RADEON_WRITE(R600_CP_RB_CNTL, |
554 | RADEON_RB_NO_UPDATE); | 560 | #ifdef __BIG_ENDIAN |
561 | R600_BUF_SWAP_32BIT | | ||
562 | #endif | ||
563 | RADEON_READ(R600_CP_RB_CNTL) | | ||
564 | R600_RB_NO_UPDATE); | ||
555 | RADEON_WRITE(R600_SCRATCH_UMSK, 0); | 565 | RADEON_WRITE(R600_SCRATCH_UMSK, 0); |
556 | } | 566 | } |
557 | } | 567 | } |
@@ -575,7 +585,11 @@ int r600_do_engine_reset(struct drm_device *dev) | |||
575 | 585 | ||
576 | RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); | 586 | RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); |
577 | cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); | 587 | cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); |
578 | RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); | 588 | RADEON_WRITE(R600_CP_RB_CNTL, |
589 | #ifdef __BIG_ENDIAN | ||
590 | R600_BUF_SWAP_32BIT | | ||
591 | #endif | ||
592 | R600_RB_RPTR_WR_ENA); | ||
579 | 593 | ||
580 | RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); | 594 | RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); |
581 | RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); | 595 | RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); |
@@ -1838,7 +1852,10 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, | |||
1838 | + dev_priv->gart_vm_start; | 1852 | + dev_priv->gart_vm_start; |
1839 | } | 1853 | } |
1840 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR, | 1854 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR, |
1841 | rptr_addr & 0xffffffff); | 1855 | #ifdef __BIG_ENDIAN |
1856 | (2 << 0) | | ||
1857 | #endif | ||
1858 | (rptr_addr & 0xfffffffc)); | ||
1842 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, | 1859 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, |
1843 | upper_32_bits(rptr_addr)); | 1860 | upper_32_bits(rptr_addr)); |
1844 | 1861 | ||
@@ -1889,7 +1906,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, | |||
1889 | { | 1906 | { |
1890 | u64 scratch_addr; | 1907 | u64 scratch_addr; |
1891 | 1908 | ||
1892 | scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); | 1909 | scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC; |
1893 | scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; | 1910 | scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; |
1894 | scratch_addr += R600_SCRATCH_REG_OFFSET; | 1911 | scratch_addr += R600_SCRATCH_REG_OFFSET; |
1895 | scratch_addr >>= 8; | 1912 | scratch_addr >>= 8; |
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 7831e0890210..153095fba62f 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -295,17 +295,18 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
295 | } | 295 | } |
296 | 296 | ||
297 | if (!IS_ALIGNED(pitch, pitch_align)) { | 297 | if (!IS_ALIGNED(pitch, pitch_align)) { |
298 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | 298 | dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", |
299 | __func__, __LINE__, pitch); | 299 | __func__, __LINE__, pitch, pitch_align, array_mode); |
300 | return -EINVAL; | 300 | return -EINVAL; |
301 | } | 301 | } |
302 | if (!IS_ALIGNED(height, height_align)) { | 302 | if (!IS_ALIGNED(height, height_align)) { |
303 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | 303 | dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", |
304 | __func__, __LINE__, height); | 304 | __func__, __LINE__, height, height_align, array_mode); |
305 | return -EINVAL; | 305 | return -EINVAL; |
306 | } | 306 | } |
307 | if (!IS_ALIGNED(base_offset, base_align)) { | 307 | if (!IS_ALIGNED(base_offset, base_align)) { |
308 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | 308 | dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, |
309 | base_offset, base_align, array_mode); | ||
309 | return -EINVAL; | 310 | return -EINVAL; |
310 | } | 311 | } |
311 | 312 | ||
@@ -320,7 +321,10 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
320 | * broken userspace. | 321 | * broken userspace. |
321 | */ | 322 | */ |
322 | } else { | 323 | } else { |
323 | dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); | 324 | dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i, |
325 | array_mode, | ||
326 | track->cb_color_bo_offset[i], tmp, | ||
327 | radeon_bo_size(track->cb_color_bo[i])); | ||
324 | return -EINVAL; | 328 | return -EINVAL; |
325 | } | 329 | } |
326 | } | 330 | } |
@@ -455,17 +459,18 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
455 | } | 459 | } |
456 | 460 | ||
457 | if (!IS_ALIGNED(pitch, pitch_align)) { | 461 | if (!IS_ALIGNED(pitch, pitch_align)) { |
458 | dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", | 462 | dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", |
459 | __func__, __LINE__, pitch); | 463 | __func__, __LINE__, pitch, pitch_align, array_mode); |
460 | return -EINVAL; | 464 | return -EINVAL; |
461 | } | 465 | } |
462 | if (!IS_ALIGNED(height, height_align)) { | 466 | if (!IS_ALIGNED(height, height_align)) { |
463 | dev_warn(p->dev, "%s:%d db height (%d) invalid\n", | 467 | dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", |
464 | __func__, __LINE__, height); | 468 | __func__, __LINE__, height, height_align, array_mode); |
465 | return -EINVAL; | 469 | return -EINVAL; |
466 | } | 470 | } |
467 | if (!IS_ALIGNED(base_offset, base_align)) { | 471 | if (!IS_ALIGNED(base_offset, base_align)) { |
468 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | 472 | dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i, |
473 | base_offset, base_align, array_mode); | ||
469 | return -EINVAL; | 474 | return -EINVAL; |
470 | } | 475 | } |
471 | 476 | ||
@@ -473,9 +478,10 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
473 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; | 478 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; |
474 | tmp = ntiles * bpe * 64 * nviews; | 479 | tmp = ntiles * bpe * 64 * nviews; |
475 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { | 480 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { |
476 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n", | 481 | dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", |
477 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, | 482 | array_mode, |
478 | radeon_bo_size(track->db_bo)); | 483 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, |
484 | radeon_bo_size(track->db_bo)); | ||
479 | return -EINVAL; | 485 | return -EINVAL; |
480 | } | 486 | } |
481 | } | 487 | } |
@@ -1227,18 +1233,18 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i | |||
1227 | /* XXX check height as well... */ | 1233 | /* XXX check height as well... */ |
1228 | 1234 | ||
1229 | if (!IS_ALIGNED(pitch, pitch_align)) { | 1235 | if (!IS_ALIGNED(pitch, pitch_align)) { |
1230 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", | 1236 | dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", |
1231 | __func__, __LINE__, pitch); | 1237 | __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); |
1232 | return -EINVAL; | 1238 | return -EINVAL; |
1233 | } | 1239 | } |
1234 | if (!IS_ALIGNED(base_offset, base_align)) { | 1240 | if (!IS_ALIGNED(base_offset, base_align)) { |
1235 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n", | 1241 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", |
1236 | __func__, __LINE__, base_offset); | 1242 | __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); |
1237 | return -EINVAL; | 1243 | return -EINVAL; |
1238 | } | 1244 | } |
1239 | if (!IS_ALIGNED(mip_offset, base_align)) { | 1245 | if (!IS_ALIGNED(mip_offset, base_align)) { |
1240 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n", | 1246 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", |
1241 | __func__, __LINE__, mip_offset); | 1247 | __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); |
1242 | return -EINVAL; | 1248 | return -EINVAL; |
1243 | } | 1249 | } |
1244 | 1250 | ||
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index a5d898b4bad2..04bac0bbd3ec 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
@@ -154,13 +154,14 @@ | |||
154 | #define ROQ_IB2_START(x) ((x) << 8) | 154 | #define ROQ_IB2_START(x) ((x) << 8) |
155 | #define CP_RB_BASE 0xC100 | 155 | #define CP_RB_BASE 0xC100 |
156 | #define CP_RB_CNTL 0xC104 | 156 | #define CP_RB_CNTL 0xC104 |
157 | #define RB_BUFSZ(x) ((x)<<0) | 157 | #define RB_BUFSZ(x) ((x) << 0) |
158 | #define RB_BLKSZ(x) ((x)<<8) | 158 | #define RB_BLKSZ(x) ((x) << 8) |
159 | #define RB_NO_UPDATE (1<<27) | 159 | #define RB_NO_UPDATE (1 << 27) |
160 | #define RB_RPTR_WR_ENA (1<<31) | 160 | #define RB_RPTR_WR_ENA (1 << 31) |
161 | #define BUF_SWAP_32BIT (2 << 16) | 161 | #define BUF_SWAP_32BIT (2 << 16) |
162 | #define CP_RB_RPTR 0x8700 | 162 | #define CP_RB_RPTR 0x8700 |
163 | #define CP_RB_RPTR_ADDR 0xC10C | 163 | #define CP_RB_RPTR_ADDR 0xC10C |
164 | #define RB_RPTR_SWAP(x) ((x) << 0) | ||
164 | #define CP_RB_RPTR_ADDR_HI 0xC110 | 165 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
165 | #define CP_RB_RPTR_WR 0xC108 | 166 | #define CP_RB_RPTR_WR 0xC108 |
166 | #define CP_RB_WPTR 0xC114 | 167 | #define CP_RB_WPTR 0xC114 |
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 5c1cc7ad9a15..02d5c415f499 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -88,7 +88,7 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev | |||
88 | /* some evergreen boards have bad data for this entry */ | 88 | /* some evergreen boards have bad data for this entry */ |
89 | if (ASIC_IS_DCE4(rdev)) { | 89 | if (ASIC_IS_DCE4(rdev)) { |
90 | if ((i == 7) && | 90 | if ((i == 7) && |
91 | (gpio->usClkMaskRegisterIndex == 0x1936) && | 91 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && |
92 | (gpio->sucI2cId.ucAccess == 0)) { | 92 | (gpio->sucI2cId.ucAccess == 0)) { |
93 | gpio->sucI2cId.ucAccess = 0x97; | 93 | gpio->sucI2cId.ucAccess = 0x97; |
94 | gpio->ucDataMaskShift = 8; | 94 | gpio->ucDataMaskShift = 8; |
@@ -101,7 +101,7 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev | |||
101 | /* some DCE3 boards have bad data for this entry */ | 101 | /* some DCE3 boards have bad data for this entry */ |
102 | if (ASIC_IS_DCE3(rdev)) { | 102 | if (ASIC_IS_DCE3(rdev)) { |
103 | if ((i == 4) && | 103 | if ((i == 4) && |
104 | (gpio->usClkMaskRegisterIndex == 0x1fda) && | 104 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && |
105 | (gpio->sucI2cId.ucAccess == 0x94)) | 105 | (gpio->sucI2cId.ucAccess == 0x94)) |
106 | gpio->sucI2cId.ucAccess = 0x14; | 106 | gpio->sucI2cId.ucAccess = 0x14; |
107 | } | 107 | } |
@@ -172,7 +172,7 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev) | |||
172 | /* some evergreen boards have bad data for this entry */ | 172 | /* some evergreen boards have bad data for this entry */ |
173 | if (ASIC_IS_DCE4(rdev)) { | 173 | if (ASIC_IS_DCE4(rdev)) { |
174 | if ((i == 7) && | 174 | if ((i == 7) && |
175 | (gpio->usClkMaskRegisterIndex == 0x1936) && | 175 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && |
176 | (gpio->sucI2cId.ucAccess == 0)) { | 176 | (gpio->sucI2cId.ucAccess == 0)) { |
177 | gpio->sucI2cId.ucAccess = 0x97; | 177 | gpio->sucI2cId.ucAccess = 0x97; |
178 | gpio->ucDataMaskShift = 8; | 178 | gpio->ucDataMaskShift = 8; |
@@ -185,7 +185,7 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev) | |||
185 | /* some DCE3 boards have bad data for this entry */ | 185 | /* some DCE3 boards have bad data for this entry */ |
186 | if (ASIC_IS_DCE3(rdev)) { | 186 | if (ASIC_IS_DCE3(rdev)) { |
187 | if ((i == 4) && | 187 | if ((i == 4) && |
188 | (gpio->usClkMaskRegisterIndex == 0x1fda) && | 188 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && |
189 | (gpio->sucI2cId.ucAccess == 0x94)) | 189 | (gpio->sucI2cId.ucAccess == 0x94)) |
190 | gpio->sucI2cId.ucAccess = 0x14; | 190 | gpio->sucI2cId.ucAccess = 0x14; |
191 | } | 191 | } |
@@ -252,7 +252,7 @@ static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rd | |||
252 | pin = &gpio_info->asGPIO_Pin[i]; | 252 | pin = &gpio_info->asGPIO_Pin[i]; |
253 | if (id == pin->ucGPIO_ID) { | 253 | if (id == pin->ucGPIO_ID) { |
254 | gpio.id = pin->ucGPIO_ID; | 254 | gpio.id = pin->ucGPIO_ID; |
255 | gpio.reg = pin->usGpioPin_AIndex * 4; | 255 | gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; |
256 | gpio.mask = (1 << pin->ucGpioPinBitShift); | 256 | gpio.mask = (1 << pin->ucGpioPinBitShift); |
257 | gpio.valid = true; | 257 | gpio.valid = true; |
258 | break; | 258 | break; |
@@ -1274,11 +1274,11 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev) | |||
1274 | data_offset); | 1274 | data_offset); |
1275 | switch (crev) { | 1275 | switch (crev) { |
1276 | case 1: | 1276 | case 1: |
1277 | if (igp_info->info.ulBootUpMemoryClock) | 1277 | if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) |
1278 | return true; | 1278 | return true; |
1279 | break; | 1279 | break; |
1280 | case 2: | 1280 | case 2: |
1281 | if (igp_info->info_2.ulBootUpSidePortClock) | 1281 | if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) |
1282 | return true; | 1282 | return true; |
1283 | break; | 1283 | break; |
1284 | default: | 1284 | default: |
@@ -1442,7 +1442,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, | |||
1442 | 1442 | ||
1443 | for (i = 0; i < num_indices; i++) { | 1443 | for (i = 0; i < num_indices; i++) { |
1444 | if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && | 1444 | if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && |
1445 | (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) { | 1445 | (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) { |
1446 | ss->percentage = | 1446 | ss->percentage = |
1447 | le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); | 1447 | le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); |
1448 | ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; | 1448 | ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; |
@@ -1456,7 +1456,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, | |||
1456 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); | 1456 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); |
1457 | for (i = 0; i < num_indices; i++) { | 1457 | for (i = 0; i < num_indices; i++) { |
1458 | if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && | 1458 | if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && |
1459 | (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) { | 1459 | (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) { |
1460 | ss->percentage = | 1460 | ss->percentage = |
1461 | le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); | 1461 | le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); |
1462 | ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; | 1462 | ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; |
@@ -1470,7 +1470,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, | |||
1470 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); | 1470 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); |
1471 | for (i = 0; i < num_indices; i++) { | 1471 | for (i = 0; i < num_indices; i++) { |
1472 | if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && | 1472 | if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && |
1473 | (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) { | 1473 | (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) { |
1474 | ss->percentage = | 1474 | ss->percentage = |
1475 | le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); | 1475 | le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); |
1476 | ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; | 1476 | ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; |
@@ -1553,8 +1553,8 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct | |||
1553 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | 1553 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
1554 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; | 1554 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; |
1555 | 1555 | ||
1556 | lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize; | 1556 | lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); |
1557 | lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize; | 1557 | lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); |
1558 | 1558 | ||
1559 | /* set crtc values */ | 1559 | /* set crtc values */ |
1560 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); | 1560 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
@@ -1569,13 +1569,13 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct | |||
1569 | lvds->linkb = false; | 1569 | lvds->linkb = false; |
1570 | 1570 | ||
1571 | /* parse the lcd record table */ | 1571 | /* parse the lcd record table */ |
1572 | if (lvds_info->info.usModePatchTableOffset) { | 1572 | if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { |
1573 | ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; | 1573 | ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; |
1574 | ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; | 1574 | ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; |
1575 | bool bad_record = false; | 1575 | bool bad_record = false; |
1576 | u8 *record = (u8 *)(mode_info->atom_context->bios + | 1576 | u8 *record = (u8 *)(mode_info->atom_context->bios + |
1577 | data_offset + | 1577 | data_offset + |
1578 | lvds_info->info.usModePatchTableOffset); | 1578 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); |
1579 | while (*record != ATOM_RECORD_END_TYPE) { | 1579 | while (*record != ATOM_RECORD_END_TYPE) { |
1580 | switch (*record) { | 1580 | switch (*record) { |
1581 | case LCD_MODE_PATCH_RECORD_MODE_TYPE: | 1581 | case LCD_MODE_PATCH_RECORD_MODE_TYPE: |
@@ -2189,7 +2189,7 @@ static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev) | |||
2189 | firmware_info = | 2189 | firmware_info = |
2190 | (union firmware_info *)(mode_info->atom_context->bios + | 2190 | (union firmware_info *)(mode_info->atom_context->bios + |
2191 | data_offset); | 2191 | data_offset); |
2192 | vddc = firmware_info->info_14.usBootUpVDDCVoltage; | 2192 | vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); |
2193 | } | 2193 | } |
2194 | 2194 | ||
2195 | return vddc; | 2195 | return vddc; |
@@ -2284,7 +2284,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, | |||
2284 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | 2284 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
2285 | VOLTAGE_SW; | 2285 | VOLTAGE_SW; |
2286 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | 2286 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
2287 | clock_info->evergreen.usVDDC; | 2287 | le16_to_cpu(clock_info->evergreen.usVDDC); |
2288 | } else { | 2288 | } else { |
2289 | sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); | 2289 | sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); |
2290 | sclk |= clock_info->r600.ucEngineClockHigh << 16; | 2290 | sclk |= clock_info->r600.ucEngineClockHigh << 16; |
@@ -2295,7 +2295,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, | |||
2295 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | 2295 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
2296 | VOLTAGE_SW; | 2296 | VOLTAGE_SW; |
2297 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | 2297 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
2298 | clock_info->r600.usVDDC; | 2298 | le16_to_cpu(clock_info->r600.usVDDC); |
2299 | } | 2299 | } |
2300 | 2300 | ||
2301 | if (rdev->flags & RADEON_IS_IGP) { | 2301 | if (rdev->flags & RADEON_IS_IGP) { |
@@ -2408,13 +2408,13 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) | |||
2408 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); | 2408 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); |
2409 | state_array = (struct StateArray *) | 2409 | state_array = (struct StateArray *) |
2410 | (mode_info->atom_context->bios + data_offset + | 2410 | (mode_info->atom_context->bios + data_offset + |
2411 | power_info->pplib.usStateArrayOffset); | 2411 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
2412 | clock_info_array = (struct ClockInfoArray *) | 2412 | clock_info_array = (struct ClockInfoArray *) |
2413 | (mode_info->atom_context->bios + data_offset + | 2413 | (mode_info->atom_context->bios + data_offset + |
2414 | power_info->pplib.usClockInfoArrayOffset); | 2414 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
2415 | non_clock_info_array = (struct NonClockInfoArray *) | 2415 | non_clock_info_array = (struct NonClockInfoArray *) |
2416 | (mode_info->atom_context->bios + data_offset + | 2416 | (mode_info->atom_context->bios + data_offset + |
2417 | power_info->pplib.usNonClockInfoArrayOffset); | 2417 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
2418 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * | 2418 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * |
2419 | state_array->ucNumEntries, GFP_KERNEL); | 2419 | state_array->ucNumEntries, GFP_KERNEL); |
2420 | if (!rdev->pm.power_state) | 2420 | if (!rdev->pm.power_state) |
@@ -2533,7 +2533,7 @@ uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) | |||
2533 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); | 2533 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); |
2534 | 2534 | ||
2535 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | 2535 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
2536 | return args.ulReturnEngineClock; | 2536 | return le32_to_cpu(args.ulReturnEngineClock); |
2537 | } | 2537 | } |
2538 | 2538 | ||
2539 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) | 2539 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) |
@@ -2542,7 +2542,7 @@ uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) | |||
2542 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); | 2542 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); |
2543 | 2543 | ||
2544 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | 2544 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
2545 | return args.ulReturnMemoryClock; | 2545 | return le32_to_cpu(args.ulReturnMemoryClock); |
2546 | } | 2546 | } |
2547 | 2547 | ||
2548 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, | 2548 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
@@ -2551,7 +2551,7 @@ void radeon_atom_set_engine_clock(struct radeon_device *rdev, | |||
2551 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | 2551 | SET_ENGINE_CLOCK_PS_ALLOCATION args; |
2552 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); | 2552 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); |
2553 | 2553 | ||
2554 | args.ulTargetEngineClock = eng_clock; /* 10 khz */ | 2554 | args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ |
2555 | 2555 | ||
2556 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | 2556 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
2557 | } | 2557 | } |
@@ -2565,7 +2565,7 @@ void radeon_atom_set_memory_clock(struct radeon_device *rdev, | |||
2565 | if (rdev->flags & RADEON_IS_IGP) | 2565 | if (rdev->flags & RADEON_IS_IGP) |
2566 | return; | 2566 | return; |
2567 | 2567 | ||
2568 | args.ulTargetMemoryClock = mem_clock; /* 10 khz */ | 2568 | args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ |
2569 | 2569 | ||
2570 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | 2570 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
2571 | } | 2571 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index d27ef74590cd..cf7c8d5b4ec2 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c | |||
@@ -1504,6 +1504,11 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) | |||
1504 | (rdev->pdev->subsystem_device == 0x4a48)) { | 1504 | (rdev->pdev->subsystem_device == 0x4a48)) { |
1505 | /* Mac X800 */ | 1505 | /* Mac X800 */ |
1506 | rdev->mode_info.connector_table = CT_MAC_X800; | 1506 | rdev->mode_info.connector_table = CT_MAC_X800; |
1507 | } else if ((rdev->pdev->device == 0x4150) && | ||
1508 | (rdev->pdev->subsystem_vendor == 0x1002) && | ||
1509 | (rdev->pdev->subsystem_device == 0x4150)) { | ||
1510 | /* Mac G5 9600 */ | ||
1511 | rdev->mode_info.connector_table = CT_MAC_G5_9600; | ||
1507 | } else | 1512 | } else |
1508 | #endif /* CONFIG_PPC_PMAC */ | 1513 | #endif /* CONFIG_PPC_PMAC */ |
1509 | #ifdef CONFIG_PPC64 | 1514 | #ifdef CONFIG_PPC64 |
@@ -2022,6 +2027,48 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) | |||
2022 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, | 2027 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
2023 | &hpd); | 2028 | &hpd); |
2024 | break; | 2029 | break; |
2030 | case CT_MAC_G5_9600: | ||
2031 | DRM_INFO("Connector Table: %d (mac g5 9600)\n", | ||
2032 | rdev->mode_info.connector_table); | ||
2033 | /* DVI - tv dac, dvo */ | ||
2034 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); | ||
2035 | hpd.hpd = RADEON_HPD_1; /* ??? */ | ||
2036 | radeon_add_legacy_encoder(dev, | ||
2037 | radeon_get_encoder_enum(dev, | ||
2038 | ATOM_DEVICE_DFP2_SUPPORT, | ||
2039 | 0), | ||
2040 | ATOM_DEVICE_DFP2_SUPPORT); | ||
2041 | radeon_add_legacy_encoder(dev, | ||
2042 | radeon_get_encoder_enum(dev, | ||
2043 | ATOM_DEVICE_CRT2_SUPPORT, | ||
2044 | 2), | ||
2045 | ATOM_DEVICE_CRT2_SUPPORT); | ||
2046 | radeon_add_legacy_connector(dev, 0, | ||
2047 | ATOM_DEVICE_DFP2_SUPPORT | | ||
2048 | ATOM_DEVICE_CRT2_SUPPORT, | ||
2049 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, | ||
2050 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, | ||
2051 | &hpd); | ||
2052 | /* ADC - primary dac, internal tmds */ | ||
2053 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); | ||
2054 | hpd.hpd = RADEON_HPD_2; /* ??? */ | ||
2055 | radeon_add_legacy_encoder(dev, | ||
2056 | radeon_get_encoder_enum(dev, | ||
2057 | ATOM_DEVICE_DFP1_SUPPORT, | ||
2058 | 0), | ||
2059 | ATOM_DEVICE_DFP1_SUPPORT); | ||
2060 | radeon_add_legacy_encoder(dev, | ||
2061 | radeon_get_encoder_enum(dev, | ||
2062 | ATOM_DEVICE_CRT1_SUPPORT, | ||
2063 | 1), | ||
2064 | ATOM_DEVICE_CRT1_SUPPORT); | ||
2065 | radeon_add_legacy_connector(dev, 1, | ||
2066 | ATOM_DEVICE_DFP1_SUPPORT | | ||
2067 | ATOM_DEVICE_CRT1_SUPPORT, | ||
2068 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, | ||
2069 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, | ||
2070 | &hpd); | ||
2071 | break; | ||
2025 | default: | 2072 | default: |
2026 | DRM_INFO("Connector table: %d (invalid)\n", | 2073 | DRM_INFO("Connector table: %d (invalid)\n", |
2027 | rdev->mode_info.connector_table); | 2074 | rdev->mode_info.connector_table); |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 0d478932b1a9..4954e2d6ffa2 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -936,8 +936,11 @@ int radeon_resume_kms(struct drm_device *dev) | |||
936 | int radeon_gpu_reset(struct radeon_device *rdev) | 936 | int radeon_gpu_reset(struct radeon_device *rdev) |
937 | { | 937 | { |
938 | int r; | 938 | int r; |
939 | int resched; | ||
939 | 940 | ||
940 | radeon_save_bios_scratch_regs(rdev); | 941 | radeon_save_bios_scratch_regs(rdev); |
942 | /* block TTM */ | ||
943 | resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); | ||
941 | radeon_suspend(rdev); | 944 | radeon_suspend(rdev); |
942 | 945 | ||
943 | r = radeon_asic_reset(rdev); | 946 | r = radeon_asic_reset(rdev); |
@@ -946,6 +949,7 @@ int radeon_gpu_reset(struct radeon_device *rdev) | |||
946 | radeon_resume(rdev); | 949 | radeon_resume(rdev); |
947 | radeon_restore_bios_scratch_regs(rdev); | 950 | radeon_restore_bios_scratch_regs(rdev); |
948 | drm_helper_resume_force_mode(rdev->ddev); | 951 | drm_helper_resume_force_mode(rdev->ddev); |
952 | ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); | ||
949 | return 0; | 953 | return 0; |
950 | } | 954 | } |
951 | /* bad news, how to tell it to userspace ? */ | 955 | /* bad news, how to tell it to userspace ? */ |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 2eff98cfd728..0e657095de7c 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
@@ -793,6 +793,11 @@ static void avivo_get_fb_div(struct radeon_pll *pll, | |||
793 | tmp *= target_clock; | 793 | tmp *= target_clock; |
794 | *fb_div = tmp / pll->reference_freq; | 794 | *fb_div = tmp / pll->reference_freq; |
795 | *frac_fb_div = tmp % pll->reference_freq; | 795 | *frac_fb_div = tmp % pll->reference_freq; |
796 | |||
797 | if (*fb_div > pll->max_feedback_div) | ||
798 | *fb_div = pll->max_feedback_div; | ||
799 | else if (*fb_div < pll->min_feedback_div) | ||
800 | *fb_div = pll->min_feedback_div; | ||
796 | } | 801 | } |
797 | 802 | ||
798 | static u32 avivo_get_post_div(struct radeon_pll *pll, | 803 | static u32 avivo_get_post_div(struct radeon_pll *pll, |
@@ -826,6 +831,11 @@ static u32 avivo_get_post_div(struct radeon_pll *pll, | |||
826 | post_div--; | 831 | post_div--; |
827 | } | 832 | } |
828 | 833 | ||
834 | if (post_div > pll->max_post_div) | ||
835 | post_div = pll->max_post_div; | ||
836 | else if (post_div < pll->min_post_div) | ||
837 | post_div = pll->min_post_div; | ||
838 | |||
829 | return post_div; | 839 | return post_div; |
830 | } | 840 | } |
831 | 841 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 448eba89d1e6..5cba46b9779a 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h | |||
@@ -1524,6 +1524,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
1524 | #define R600_CP_RB_CNTL 0xc104 | 1524 | #define R600_CP_RB_CNTL 0xc104 |
1525 | # define R600_RB_BUFSZ(x) ((x) << 0) | 1525 | # define R600_RB_BUFSZ(x) ((x) << 0) |
1526 | # define R600_RB_BLKSZ(x) ((x) << 8) | 1526 | # define R600_RB_BLKSZ(x) ((x) << 8) |
1527 | # define R600_BUF_SWAP_32BIT (2 << 16) | ||
1527 | # define R600_RB_NO_UPDATE (1 << 27) | 1528 | # define R600_RB_NO_UPDATE (1 << 27) |
1528 | # define R600_RB_RPTR_WR_ENA (1 << 31) | 1529 | # define R600_RB_RPTR_WR_ENA (1 << 31) |
1529 | #define R600_CP_RB_RPTR_WR 0xc108 | 1530 | #define R600_CP_RB_RPTR_WR 0xc108 |
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index d4a542247618..b4274883227f 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -910,7 +910,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
910 | 910 | ||
911 | args.v1.ucAction = action; | 911 | args.v1.ucAction = action; |
912 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | 912 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
913 | args.v1.usInitInfo = connector_object_id; | 913 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
914 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | 914 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
915 | args.v1.asMode.ucLaneSel = lane_num; | 915 | args.v1.asMode.ucLaneSel = lane_num; |
916 | args.v1.asMode.ucLaneSet = lane_set; | 916 | args.v1.asMode.ucLaneSet = lane_set; |
@@ -1140,7 +1140,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, | |||
1140 | case 3: | 1140 | case 3: |
1141 | args.v3.sExtEncoder.ucAction = action; | 1141 | args.v3.sExtEncoder.ucAction = action; |
1142 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) | 1142 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) |
1143 | args.v3.sExtEncoder.usConnectorId = connector_object_id; | 1143 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
1144 | else | 1144 | else |
1145 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 1145 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
1146 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | 1146 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); |
@@ -1570,11 +1570,21 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |||
1570 | } | 1570 | } |
1571 | 1571 | ||
1572 | /* set scaler clears this on some chips */ | 1572 | /* set scaler clears this on some chips */ |
1573 | /* XXX check DCE4 */ | 1573 | if (ASIC_IS_AVIVO(rdev) && |
1574 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { | 1574 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
1575 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) | 1575 | if (ASIC_IS_DCE4(rdev)) { |
1576 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | 1576 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
1577 | AVIVO_D1MODE_INTERLEAVE_EN); | 1577 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
1578 | EVERGREEN_INTERLEAVE_EN); | ||
1579 | else | ||
1580 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | ||
1581 | } else { | ||
1582 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | ||
1583 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | ||
1584 | AVIVO_D1MODE_INTERLEAVE_EN); | ||
1585 | else | ||
1586 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | ||
1587 | } | ||
1578 | } | 1588 | } |
1579 | } | 1589 | } |
1580 | 1590 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 6794cdf91f28..a670caaee29e 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -209,6 +209,7 @@ enum radeon_connector_table { | |||
209 | CT_EMAC, | 209 | CT_EMAC, |
210 | CT_RN50_POWER, | 210 | CT_RN50_POWER, |
211 | CT_MAC_X800, | 211 | CT_MAC_X800, |
212 | CT_MAC_G5_9600, | ||
212 | }; | 213 | }; |
213 | 214 | ||
214 | enum radeon_dvo_chip { | 215 | enum radeon_dvo_chip { |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 1272e4b6a1d4..e5b2cf10cbf4 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -787,9 +787,9 @@ static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | |||
787 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; | 787 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; |
788 | radeon_mem_types_list[i].driver_features = 0; | 788 | radeon_mem_types_list[i].driver_features = 0; |
789 | if (i == 0) | 789 | if (i == 0) |
790 | radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].priv; | 790 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; |
791 | else | 791 | else |
792 | radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].priv; | 792 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; |
793 | 793 | ||
794 | } | 794 | } |
795 | /* Add ttm page pool to debugfs */ | 795 | /* Add ttm page pool to debugfs */ |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300 index b506ec1cab4b..e8a1786b6426 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r300 +++ b/drivers/gpu/drm/radeon/reg_srcs/r300 | |||
@@ -683,9 +683,7 @@ r300 0x4f60 | |||
683 | 0x4DF4 US_ALU_CONST_G_31 | 683 | 0x4DF4 US_ALU_CONST_G_31 |
684 | 0x4DF8 US_ALU_CONST_B_31 | 684 | 0x4DF8 US_ALU_CONST_B_31 |
685 | 0x4DFC US_ALU_CONST_A_31 | 685 | 0x4DFC US_ALU_CONST_A_31 |
686 | 0x4E04 RB3D_BLENDCNTL_R3 | ||
687 | 0x4E08 RB3D_ABLENDCNTL_R3 | 686 | 0x4E08 RB3D_ABLENDCNTL_R3 |
688 | 0x4E0C RB3D_COLOR_CHANNEL_MASK | ||
689 | 0x4E10 RB3D_CONSTANT_COLOR | 687 | 0x4E10 RB3D_CONSTANT_COLOR |
690 | 0x4E14 RB3D_COLOR_CLEAR_VALUE | 688 | 0x4E14 RB3D_COLOR_CLEAR_VALUE |
691 | 0x4E18 RB3D_ROPCNTL_R3 | 689 | 0x4E18 RB3D_ROPCNTL_R3 |
@@ -706,13 +704,11 @@ r300 0x4f60 | |||
706 | 0x4E74 RB3D_CMASK_WRINDEX | 704 | 0x4E74 RB3D_CMASK_WRINDEX |
707 | 0x4E78 RB3D_CMASK_DWORD | 705 | 0x4E78 RB3D_CMASK_DWORD |
708 | 0x4E7C RB3D_CMASK_RDINDEX | 706 | 0x4E7C RB3D_CMASK_RDINDEX |
709 | 0x4E80 RB3D_AARESOLVE_OFFSET | ||
710 | 0x4E84 RB3D_AARESOLVE_PITCH | ||
711 | 0x4E88 RB3D_AARESOLVE_CTL | ||
712 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD | 707 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD |
713 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD | 708 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD |
714 | 0x4F04 ZB_ZSTENCILCNTL | 709 | 0x4F04 ZB_ZSTENCILCNTL |
715 | 0x4F08 ZB_STENCILREFMASK | 710 | 0x4F08 ZB_STENCILREFMASK |
716 | 0x4F14 ZB_ZTOP | 711 | 0x4F14 ZB_ZTOP |
717 | 0x4F18 ZB_ZCACHE_CTLSTAT | 712 | 0x4F18 ZB_ZCACHE_CTLSTAT |
713 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
718 | 0x4F58 ZB_ZPASS_DATA | 714 | 0x4F58 ZB_ZPASS_DATA |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420 index 8c1214c2390f..722074e21e2f 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/r420 +++ b/drivers/gpu/drm/radeon/reg_srcs/r420 | |||
@@ -130,7 +130,6 @@ r420 0x4f60 | |||
130 | 0x401C GB_SELECT | 130 | 0x401C GB_SELECT |
131 | 0x4020 GB_AA_CONFIG | 131 | 0x4020 GB_AA_CONFIG |
132 | 0x4024 GB_FIFO_SIZE | 132 | 0x4024 GB_FIFO_SIZE |
133 | 0x4028 GB_Z_PEQ_CONFIG | ||
134 | 0x4100 TX_INVALTAGS | 133 | 0x4100 TX_INVALTAGS |
135 | 0x4200 GA_POINT_S0 | 134 | 0x4200 GA_POINT_S0 |
136 | 0x4204 GA_POINT_T0 | 135 | 0x4204 GA_POINT_T0 |
@@ -750,9 +749,7 @@ r420 0x4f60 | |||
750 | 0x4DF4 US_ALU_CONST_G_31 | 749 | 0x4DF4 US_ALU_CONST_G_31 |
751 | 0x4DF8 US_ALU_CONST_B_31 | 750 | 0x4DF8 US_ALU_CONST_B_31 |
752 | 0x4DFC US_ALU_CONST_A_31 | 751 | 0x4DFC US_ALU_CONST_A_31 |
753 | 0x4E04 RB3D_BLENDCNTL_R3 | ||
754 | 0x4E08 RB3D_ABLENDCNTL_R3 | 752 | 0x4E08 RB3D_ABLENDCNTL_R3 |
755 | 0x4E0C RB3D_COLOR_CHANNEL_MASK | ||
756 | 0x4E10 RB3D_CONSTANT_COLOR | 753 | 0x4E10 RB3D_CONSTANT_COLOR |
757 | 0x4E14 RB3D_COLOR_CLEAR_VALUE | 754 | 0x4E14 RB3D_COLOR_CLEAR_VALUE |
758 | 0x4E18 RB3D_ROPCNTL_R3 | 755 | 0x4E18 RB3D_ROPCNTL_R3 |
@@ -773,13 +770,11 @@ r420 0x4f60 | |||
773 | 0x4E74 RB3D_CMASK_WRINDEX | 770 | 0x4E74 RB3D_CMASK_WRINDEX |
774 | 0x4E78 RB3D_CMASK_DWORD | 771 | 0x4E78 RB3D_CMASK_DWORD |
775 | 0x4E7C RB3D_CMASK_RDINDEX | 772 | 0x4E7C RB3D_CMASK_RDINDEX |
776 | 0x4E80 RB3D_AARESOLVE_OFFSET | ||
777 | 0x4E84 RB3D_AARESOLVE_PITCH | ||
778 | 0x4E88 RB3D_AARESOLVE_CTL | ||
779 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD | 773 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD |
780 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD | 774 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD |
781 | 0x4F04 ZB_ZSTENCILCNTL | 775 | 0x4F04 ZB_ZSTENCILCNTL |
782 | 0x4F08 ZB_STENCILREFMASK | 776 | 0x4F08 ZB_STENCILREFMASK |
783 | 0x4F14 ZB_ZTOP | 777 | 0x4F14 ZB_ZTOP |
784 | 0x4F18 ZB_ZCACHE_CTLSTAT | 778 | 0x4F18 ZB_ZCACHE_CTLSTAT |
779 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
785 | 0x4F58 ZB_ZPASS_DATA | 780 | 0x4F58 ZB_ZPASS_DATA |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600 index 0828d80396f2..d9f62866bbc1 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rs600 +++ b/drivers/gpu/drm/radeon/reg_srcs/rs600 | |||
@@ -749,9 +749,7 @@ rs600 0x6d40 | |||
749 | 0x4DF4 US_ALU_CONST_G_31 | 749 | 0x4DF4 US_ALU_CONST_G_31 |
750 | 0x4DF8 US_ALU_CONST_B_31 | 750 | 0x4DF8 US_ALU_CONST_B_31 |
751 | 0x4DFC US_ALU_CONST_A_31 | 751 | 0x4DFC US_ALU_CONST_A_31 |
752 | 0x4E04 RB3D_BLENDCNTL_R3 | ||
753 | 0x4E08 RB3D_ABLENDCNTL_R3 | 752 | 0x4E08 RB3D_ABLENDCNTL_R3 |
754 | 0x4E0C RB3D_COLOR_CHANNEL_MASK | ||
755 | 0x4E10 RB3D_CONSTANT_COLOR | 753 | 0x4E10 RB3D_CONSTANT_COLOR |
756 | 0x4E14 RB3D_COLOR_CLEAR_VALUE | 754 | 0x4E14 RB3D_COLOR_CLEAR_VALUE |
757 | 0x4E18 RB3D_ROPCNTL_R3 | 755 | 0x4E18 RB3D_ROPCNTL_R3 |
@@ -772,13 +770,11 @@ rs600 0x6d40 | |||
772 | 0x4E74 RB3D_CMASK_WRINDEX | 770 | 0x4E74 RB3D_CMASK_WRINDEX |
773 | 0x4E78 RB3D_CMASK_DWORD | 771 | 0x4E78 RB3D_CMASK_DWORD |
774 | 0x4E7C RB3D_CMASK_RDINDEX | 772 | 0x4E7C RB3D_CMASK_RDINDEX |
775 | 0x4E80 RB3D_AARESOLVE_OFFSET | ||
776 | 0x4E84 RB3D_AARESOLVE_PITCH | ||
777 | 0x4E88 RB3D_AARESOLVE_CTL | ||
778 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD | 773 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD |
779 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD | 774 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD |
780 | 0x4F04 ZB_ZSTENCILCNTL | 775 | 0x4F04 ZB_ZSTENCILCNTL |
781 | 0x4F08 ZB_STENCILREFMASK | 776 | 0x4F08 ZB_STENCILREFMASK |
782 | 0x4F14 ZB_ZTOP | 777 | 0x4F14 ZB_ZTOP |
783 | 0x4F18 ZB_ZCACHE_CTLSTAT | 778 | 0x4F18 ZB_ZCACHE_CTLSTAT |
779 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
784 | 0x4F58 ZB_ZPASS_DATA | 780 | 0x4F58 ZB_ZPASS_DATA |
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515 index ef422bbacfc1..911a8fbd32bb 100644 --- a/drivers/gpu/drm/radeon/reg_srcs/rv515 +++ b/drivers/gpu/drm/radeon/reg_srcs/rv515 | |||
@@ -164,7 +164,6 @@ rv515 0x6d40 | |||
164 | 0x401C GB_SELECT | 164 | 0x401C GB_SELECT |
165 | 0x4020 GB_AA_CONFIG | 165 | 0x4020 GB_AA_CONFIG |
166 | 0x4024 GB_FIFO_SIZE | 166 | 0x4024 GB_FIFO_SIZE |
167 | 0x4028 GB_Z_PEQ_CONFIG | ||
168 | 0x4100 TX_INVALTAGS | 167 | 0x4100 TX_INVALTAGS |
169 | 0x4114 SU_TEX_WRAP_PS3 | 168 | 0x4114 SU_TEX_WRAP_PS3 |
170 | 0x4118 PS3_ENABLE | 169 | 0x4118 PS3_ENABLE |
@@ -461,9 +460,7 @@ rv515 0x6d40 | |||
461 | 0x4DF4 US_ALU_CONST_G_31 | 460 | 0x4DF4 US_ALU_CONST_G_31 |
462 | 0x4DF8 US_ALU_CONST_B_31 | 461 | 0x4DF8 US_ALU_CONST_B_31 |
463 | 0x4DFC US_ALU_CONST_A_31 | 462 | 0x4DFC US_ALU_CONST_A_31 |
464 | 0x4E04 RB3D_BLENDCNTL_R3 | ||
465 | 0x4E08 RB3D_ABLENDCNTL_R3 | 463 | 0x4E08 RB3D_ABLENDCNTL_R3 |
466 | 0x4E0C RB3D_COLOR_CHANNEL_MASK | ||
467 | 0x4E10 RB3D_CONSTANT_COLOR | 464 | 0x4E10 RB3D_CONSTANT_COLOR |
468 | 0x4E14 RB3D_COLOR_CLEAR_VALUE | 465 | 0x4E14 RB3D_COLOR_CLEAR_VALUE |
469 | 0x4E18 RB3D_ROPCNTL_R3 | 466 | 0x4E18 RB3D_ROPCNTL_R3 |
@@ -484,9 +481,6 @@ rv515 0x6d40 | |||
484 | 0x4E74 RB3D_CMASK_WRINDEX | 481 | 0x4E74 RB3D_CMASK_WRINDEX |
485 | 0x4E78 RB3D_CMASK_DWORD | 482 | 0x4E78 RB3D_CMASK_DWORD |
486 | 0x4E7C RB3D_CMASK_RDINDEX | 483 | 0x4E7C RB3D_CMASK_RDINDEX |
487 | 0x4E80 RB3D_AARESOLVE_OFFSET | ||
488 | 0x4E84 RB3D_AARESOLVE_PITCH | ||
489 | 0x4E88 RB3D_AARESOLVE_CTL | ||
490 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD | 484 | 0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD |
491 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD | 485 | 0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD |
492 | 0x4EF8 RB3D_CONSTANT_COLOR_AR | 486 | 0x4EF8 RB3D_CONSTANT_COLOR_AR |
@@ -496,4 +490,5 @@ rv515 0x6d40 | |||
496 | 0x4F14 ZB_ZTOP | 490 | 0x4F14 ZB_ZTOP |
497 | 0x4F18 ZB_ZCACHE_CTLSTAT | 491 | 0x4F18 ZB_ZCACHE_CTLSTAT |
498 | 0x4F58 ZB_ZPASS_DATA | 492 | 0x4F58 ZB_ZPASS_DATA |
493 | 0x4F28 ZB_DEPTHCLEARVALUE | ||
499 | 0x4FD4 ZB_STENCILREFMASK_BF | 494 | 0x4FD4 ZB_STENCILREFMASK_BF |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 0137d3e3728d..6638c8e4c81b 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -77,9 +77,9 @@ void rs690_pm_info(struct radeon_device *rdev) | |||
77 | switch (crev) { | 77 | switch (crev) { |
78 | case 1: | 78 | case 1: |
79 | tmp.full = dfixed_const(100); | 79 | tmp.full = dfixed_const(100); |
80 | rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock); | 80 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); |
81 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); | 81 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
82 | if (info->info.usK8MemoryClock) | 82 | if (le16_to_cpu(info->info.usK8MemoryClock)) |
83 | rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); | 83 | rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); |
84 | else if (rdev->clock.default_mclk) { | 84 | else if (rdev->clock.default_mclk) { |
85 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); | 85 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); |
@@ -91,16 +91,16 @@ void rs690_pm_info(struct radeon_device *rdev) | |||
91 | break; | 91 | break; |
92 | case 2: | 92 | case 2: |
93 | tmp.full = dfixed_const(100); | 93 | tmp.full = dfixed_const(100); |
94 | rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock); | 94 | rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); |
95 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); | 95 | rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); |
96 | if (info->info_v2.ulBootUpUMAClock) | 96 | if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) |
97 | rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock); | 97 | rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); |
98 | else if (rdev->clock.default_mclk) | 98 | else if (rdev->clock.default_mclk) |
99 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); | 99 | rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); |
100 | else | 100 | else |
101 | rdev->pm.igp_system_mclk.full = dfixed_const(66700); | 101 | rdev->pm.igp_system_mclk.full = dfixed_const(66700); |
102 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); | 102 | rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); |
103 | rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq); | 103 | rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); |
104 | rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); | 104 | rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); |
105 | rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); | 105 | rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); |
106 | break; | 106 | break; |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 2211a323db41..d8ba67690656 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -321,7 +321,11 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev) | |||
321 | return -EINVAL; | 321 | return -EINVAL; |
322 | 322 | ||
323 | r700_cp_stop(rdev); | 323 | r700_cp_stop(rdev); |
324 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); | 324 | WREG32(CP_RB_CNTL, |
325 | #ifdef __BIG_ENDIAN | ||
326 | BUF_SWAP_32BIT | | ||
327 | #endif | ||
328 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | ||
325 | 329 | ||
326 | /* Reset cp */ | 330 | /* Reset cp */ |
327 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | 331 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index abc8cf5a3672..79fa588e9ed5 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h | |||
@@ -76,10 +76,10 @@ | |||
76 | #define ROQ_IB1_START(x) ((x) << 0) | 76 | #define ROQ_IB1_START(x) ((x) << 0) |
77 | #define ROQ_IB2_START(x) ((x) << 8) | 77 | #define ROQ_IB2_START(x) ((x) << 8) |
78 | #define CP_RB_CNTL 0xC104 | 78 | #define CP_RB_CNTL 0xC104 |
79 | #define RB_BUFSZ(x) ((x)<<0) | 79 | #define RB_BUFSZ(x) ((x) << 0) |
80 | #define RB_BLKSZ(x) ((x)<<8) | 80 | #define RB_BLKSZ(x) ((x) << 8) |
81 | #define RB_NO_UPDATE (1<<27) | 81 | #define RB_NO_UPDATE (1 << 27) |
82 | #define RB_RPTR_WR_ENA (1<<31) | 82 | #define RB_RPTR_WR_ENA (1 << 31) |
83 | #define BUF_SWAP_32BIT (2 << 16) | 83 | #define BUF_SWAP_32BIT (2 << 16) |
84 | #define CP_RB_RPTR 0x8700 | 84 | #define CP_RB_RPTR 0x8700 |
85 | #define CP_RB_RPTR_ADDR 0xC10C | 85 | #define CP_RB_RPTR_ADDR 0xC10C |