63 files changed, 1946 insertions, 776 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f831ea159291..96eddd17e050 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -92,6 +92,7 @@ config DRM_I830
 config DRM_I915
        tristate "i915 driver"
        depends on AGP_INTEL
+        select SHMEM
        select DRM_KMS_HELPER
        select FB_CFB_FILLRECT
        select FB_CFB_COPYAREA
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 1fe4e1d344fd..bbfd110a7168 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -331,6 +331,7 @@ create_mode:
                            cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
                            cmdline_mode->rb, cmdline_mode->interlace,
                            cmdline_mode->margins);
+        drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
        list_add(&mode->head, &connector->modes);
        return mode;
 }
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index cea665d86dd3..b54ba63d506e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -662,6 +662,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
                return NULL;
        }
+        /* Some EDIDs have bogus h/vtotal values */
+        if (mode->hsync_end > mode->htotal)
+                mode->htotal = mode->hsync_end + 1;
+        if (mode->vsync_end > mode->vtotal)
+                mode->vtotal = mode->vsync_end + 1;
        drm_mode_set_name(mode);
        if (pt->misc & DRM_EDID_PT_INTERLACED)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 9c924614c418..65ef011fa8ba 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -599,7 +599,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
        struct drm_framebuffer *fb = fb_helper->fb;
        int depth;
-        if (var->pixclock == -1 || !var->pixclock)
+        if (var->pixclock != 0)
                return -EINVAL;
        /* Need to resize the fb object !!! */
@@ -691,7 +691,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
        int ret;
        int i;
-        if (var->pixclock != -1) {
+        if (var->pixclock != 0) {
                DRM_ERROR("PIXEL CLCOK SET\n");
                return -EINVAL;
        }
@@ -707,7 +707,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
                if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) {
                        mutex_lock(&dev->mode_config.mutex);
-                        ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set);
+                        ret = crtc->funcs->set_config(&fb_helper->crtc_info[i].mode_set);
                        mutex_unlock(&dev->mode_config.mutex);
                        if (ret)
                                return ret;
@@ -904,7 +904,7 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev,
        fb_helper->fb = fb;
        if (new_fb) {
-                info->var.pixclock = -1;
+                info->var.pixclock = 0;
                if (register_framebuffer(info) < 0)
                        return -EINVAL;
        } else {
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 80391995bdec..e9dbb481c469 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -552,7 +552,7 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
        vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND;
        vma->vm_ops = obj->dev->driver->gem_vm_ops;
        vma->vm_private_data = map->handle;
-        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+        vma->vm_page_prot =  pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
        /* Take a ref for this mapping of the object, so that the fault
         * handler can dereference the mmap offset's pointer to the object.
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index c861d80fd779..97dc5a4f0de4 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -103,6 +103,11 @@ static struct drm_mm_node *drm_mm_kmalloc(struct drm_mm *mm, int atomic)
        return child;
 }
+/* drm_mm_pre_get() - pre allocate drm_mm_node structure
+ * drm_mm:      memory manager struct we are pre-allocating for
+ *
+ * Returns 0 on success or -ENOMEM if allocation fails.
+ */
 int drm_mm_pre_get(struct drm_mm *mm)
 {
        struct drm_mm_node *node;
@@ -253,12 +258,14 @@ void drm_mm_put_block(struct drm_mm_node *cur)
                                prev_node->size += next_node->size;
                                list_del(&next_node->ml_entry);
                                list_del(&next_node->fl_entry);
+                                spin_lock(&mm->unused_lock);
                                if (mm->num_unused < MM_UNUSED_TARGET) {
                                        list_add(&next_node->fl_entry,
                                                 &mm->unused_nodes);
                                        ++mm->num_unused;
                                } else
                                        kfree(next_node);
+                                spin_unlock(&mm->unused_lock);
                        } else {
                                next_node->size += cur->size;
                                next_node->start = cur->start;
@@ -271,11 +278,13 @@ void drm_mm_put_block(struct drm_mm_node *cur)
                list_add(&cur->fl_entry, &mm->fl_entry);
        } else {
                list_del(&cur->ml_entry);
+                spin_lock(&mm->unused_lock);
                if (mm->num_unused < MM_UNUSED_TARGET) {
                        list_add(&cur->fl_entry, &mm->unused_nodes);
                        ++mm->num_unused;
                } else
                        kfree(cur);
+                spin_unlock(&mm->unused_lock);
        }
 }
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f8ce9a3a420d..26bf0552b3cb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -267,10 +267,10 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
        uint32_t *mem;
        for (page = 0; page < page_count; page++) {
-                mem = kmap(pages[page]);
+                mem = kmap_atomic(pages[page], KM_USER0);
                for (i = 0; i < PAGE_SIZE; i += 4)
                        seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
-                kunmap(pages[page]);
+                kunmap_atomic(pages[page], KM_USER0);
        }
 }
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 92aeb918e0c0..e5b138be45fa 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1227,8 +1227,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
                goto out;
        /* Try to set up FBC with a reasonable compressed buffer size */
-        if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) &&
+        if (I915_HAS_FBC(dev) && i915_powersave) {
-            i915_powersave) {
                int cfb_size;
                /* Try to get an 8M buffer... */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b93814c0d3e2..7f436ec075f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -89,7 +89,8 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
                pci_set_power_state(dev->pdev, PCI_D3hot);
        }
-        dev_priv->suspended = 1;
+        /* Modeset on resume, not lid events */
+        dev_priv->modeset_on_lid = 0;
        return 0;
 }
@@ -124,7 +125,7 @@ static int i915_resume(struct drm_device *dev)
                drm_helper_resume_force_mode(dev);
        }
-        dev_priv->suspended = 0;
+        dev_priv->modeset_on_lid = 0;
        return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6035d3dae851..a725f6591192 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -274,7 +274,7 @@ typedef struct drm_i915_private {
        struct drm_i915_display_funcs display;
        /* Register state */
-        bool suspended;
+        bool modeset_on_lid;
        u8 saveLBB;
        u32 saveDSPACNTR;
        u32 saveDSPBCNTR;
@@ -296,6 +296,13 @@ typedef struct drm_i915_private {
        u32 saveVBLANK_A;
        u32 saveVSYNC_A;
        u32 saveBCLRPAT_A;
+        u32 saveTRANSACONF;
+        u32 saveTRANS_HTOTAL_A;
+        u32 saveTRANS_HBLANK_A;
+        u32 saveTRANS_HSYNC_A;
+        u32 saveTRANS_VTOTAL_A;
+        u32 saveTRANS_VBLANK_A;
+        u32 saveTRANS_VSYNC_A;
        u32 savePIPEASTAT;
        u32 saveDSPASTRIDE;
        u32 saveDSPASIZE;
@@ -304,8 +311,11 @@ typedef struct drm_i915_private {
        u32 saveDSPASURF;
        u32 saveDSPATILEOFF;
        u32 savePFIT_PGM_RATIOS;
+        u32 saveBLC_HIST_CTL;
        u32 saveBLC_PWM_CTL;
        u32 saveBLC_PWM_CTL2;
+        u32 saveBLC_CPU_PWM_CTL;
+        u32 saveBLC_CPU_PWM_CTL2;
        u32 saveFPB0;
        u32 saveFPB1;
        u32 saveDPLL_B;
@@ -317,6 +327,13 @@ typedef struct drm_i915_private {
        u32 saveVBLANK_B;
        u32 saveVSYNC_B;
        u32 saveBCLRPAT_B;
+        u32 saveTRANSBCONF;
+        u32 saveTRANS_HTOTAL_B;
+        u32 saveTRANS_HBLANK_B;
+        u32 saveTRANS_HSYNC_B;
+        u32 saveTRANS_VTOTAL_B;
+        u32 saveTRANS_VBLANK_B;
+        u32 saveTRANS_VSYNC_B;
        u32 savePIPEBSTAT;
        u32 saveDSPBSTRIDE;
        u32 saveDSPBSIZE;
@@ -342,6 +359,7 @@ typedef struct drm_i915_private {
        u32 savePFIT_CONTROL;
        u32 save_palette_a[256];
        u32 save_palette_b[256];
+        u32 saveDPFC_CB_BASE;
        u32 saveFBC_CFB_BASE;
        u32 saveFBC_LL_BASE;
        u32 saveFBC_CONTROL;
@@ -349,6 +367,12 @@ typedef struct drm_i915_private {
        u32 saveIER;
        u32 saveIIR;
        u32 saveIMR;
+        u32 saveDEIER;
+        u32 saveDEIMR;
+        u32 saveGTIER;
+        u32 saveGTIMR;
+        u32 saveFDI_RXA_IMR;
+        u32 saveFDI_RXB_IMR;
        u32 saveCACHE_MODE_0;
        u32 saveD_STATE;
        u32 saveDSPCLK_GATE_D;
@@ -382,6 +406,26 @@ typedef struct drm_i915_private {
        u32 savePIPEB_DP_LINK_M;
        u32 savePIPEA_DP_LINK_N;
        u32 savePIPEB_DP_LINK_N;
+        u32 saveFDI_RXA_CTL;
+        u32 saveFDI_TXA_CTL;
+        u32 saveFDI_RXB_CTL;
+        u32 saveFDI_TXB_CTL;
+        u32 savePFA_CTL_1;
+        u32 savePFB_CTL_1;
+        u32 savePFA_WIN_SZ;
+        u32 savePFB_WIN_SZ;
+        u32 savePFA_WIN_POS;
+        u32 savePFB_WIN_POS;
+        u32 savePCH_DREF_CONTROL;
+        u32 saveDISP_ARB_CTL;
+        u32 savePIPEA_DATA_M1;
+        u32 savePIPEA_DATA_N1;
+        u32 savePIPEA_LINK_M1;
+        u32 savePIPEA_LINK_N1;
+        u32 savePIPEB_DATA_M1;
+        u32 savePIPEB_DATA_N1;
+        u32 savePIPEB_LINK_M1;
+        u32 savePIPEB_LINK_N1;
        struct {
                struct drm_mm gtt_space;
@@ -492,6 +536,8 @@ typedef struct drm_i915_private {
                struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
        } mm;
        struct sdvo_device_mapping sdvo_mappings[2];
+        /* indicate whether the LVDS_BORDER should be enabled or not */
+        unsigned int lvds_border_bits;
        /* Reclocking support */
        bool render_reclock_avail;
@@ -981,7 +1027,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
-#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)))
+#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
+                           (IS_I9XX(dev) || IS_GM45(dev)) && \
+                           !IS_IGD(dev) && \
+                           !IS_IGDNG(dev))
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c3ceffa46ea0..aa7fd82aa6eb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -254,10 +254,15 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        int ret = IRQ_NONE;
-        u32 de_iir, gt_iir;
+        u32 de_iir, gt_iir, de_ier;
        u32 new_de_iir, new_gt_iir;
        struct drm_i915_master_private *master_priv;
+        /* disable master interrupt before clearing iir  */
+        de_ier = I915_READ(DEIER);
+        I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+        (void)I915_READ(DEIER);
        de_iir = I915_READ(DEIIR);
        gt_iir = I915_READ(GTIIR);
@@ -290,6 +295,9 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
                gt_iir = new_gt_iir;
        }
+        I915_WRITE(DEIER, de_ier);
+        (void)I915_READ(DEIER);
        return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0466ddbeba32..1687edf68795 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -968,6 +968,8 @@
 #define   LVDS_PORT_EN                  (1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT             (1 << 30)
+/* Enable border for unscaled (or aspect-scaled) display */
+#define   LVDS_BORDER_ENABLE            (1 << 15)
 /*
 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
 * pixel.
@@ -1078,6 +1080,8 @@
 #define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
 #define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
+#define BLC_HIST_CTL            0x61260
 /* TV port control */
 #define TV_CTL                  0x68000
 /** Enables the TV encoder */
@@ -1780,6 +1784,11 @@
 #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL<<2) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL<<1)
 #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL<<0)
+#define   PIPE_BPC_MASK                         (7 << 5) /* Ironlake */
+#define   PIPE_8BPC                             (0 << 5)
+#define   PIPE_10BPC                            (1 << 5)
+#define   PIPE_6BPC                             (2 << 5)
+#define   PIPE_12BPC                            (3 << 5)
 #define DSPARB                  0x70030
 #define   DSPARB_CSTART_MASK    (0x7f << 7)
@@ -1790,17 +1799,29 @@
 #define   DSPARB_AEND_SHIFT     0
 #define DSPFW1                  0x70034
+#define   DSPFW_SR_SHIFT        23
+#define   DSPFW_CURSORB_SHIFT   16
+#define   DSPFW_PLANEB_SHIFT    8
 #define DSPFW2                  0x70038
+#define   DSPFW_CURSORA_MASK    0x00003f00
+#define   DSPFW_CURSORA_SHIFT   16
 #define DSPFW3                  0x7003c
+#define   DSPFW_HPLL_SR_EN      (1<<31)
+#define   DSPFW_CURSOR_SR_SHIFT 24
 #define   IGD_SELF_REFRESH_EN   (1<<30)
 /* FIFO watermark sizes etc */
+#define G4X_FIFO_LINE_SIZE      64
 #define I915_FIFO_LINE_SIZE     64
 #define I830_FIFO_LINE_SIZE     32
+#define G4X_FIFO_SIZE           127
 #define I945_FIFO_SIZE          127 /* 945 & 965 */
 #define I915_FIFO_SIZE          95
 #define I855GM_FIFO_SIZE        127 /* In cachelines */
 #define I830_FIFO_SIZE          95
+#define G4X_MAX_WM              0x3f
 #define I915_MAX_WM             0x3f
 #define IGD_DISPLAY_FIFO        512 /* in 64byte unit */
@@ -2030,6 +2051,11 @@
 #define PFA_CTL_1               0x68080
 #define PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define  PF_FILTER_MASK         (3<<23)
+#define  PF_FILTER_PROGRAMMED   (0<<23)
+#define  PF_FILTER_MED_3x3      (1<<23)
+#define  PF_FILTER_EDGE_ENHANCE (2<<23)
+#define  PF_FILTER_EDGE_SOFTEN  (3<<23)
 #define PFA_WIN_SZ              0x68074
 #define PFB_WIN_SZ              0x68874
 #define PFA_WIN_POS             0x68070
@@ -2149,11 +2175,11 @@
 #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3<<13)
 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
-#define  DREF_SSC_SOURCE_MASK                   (2<<11)
+#define  DREF_SSC_SOURCE_MASK                   (3<<11)
 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
 #define  DREF_NONSPREAD_CK505_ENABLE            (1<<9)
 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
-#define  DREF_NONSPREAD_SOURCE_MASK             (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK             (3<<9)
 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bd6d8d91ca9f..6eec8171a44e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,11 +32,15 @@
 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32     dpll_reg;
-        if (pipe == PIPE_A)
+        if (IS_IGDNG(dev)) {
-                return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
+                dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
-        else
+        } else {
-                return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
+                dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
+        }
+        return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
 }
 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
@@ -49,6 +53,9 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
        if (!i915_pipe_enabled(dev, pipe))
                return;
+        if (IS_IGDNG(dev))
+                reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
        if (pipe == PIPE_A)
                array = dev_priv->save_palette_a;
        else
@@ -68,6 +75,9 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
        if (!i915_pipe_enabled(dev, pipe))
                return;
+        if (IS_IGDNG(dev))
+                reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
        if (pipe == PIPE_A)
                array = dev_priv->save_palette_a;
        else
@@ -229,13 +239,24 @@ static void i915_save_modeset_reg(struct drm_device *dev)
        if (drm_core_check_feature(dev, DRIVER_MODESET))
                return;
+        if (IS_IGDNG(dev)) {
+                dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
+                dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
+        }
        /* Pipe & plane A info */
        dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
        dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
-        dev_priv->saveFPA0 = I915_READ(FPA0);
+        if (IS_IGDNG(dev)) {
-        dev_priv->saveFPA1 = I915_READ(FPA1);
+                dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
-        dev_priv->saveDPLL_A = I915_READ(DPLL_A);
+                dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
-        if (IS_I965G(dev))
+                dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
+        } else {
+                dev_priv->saveFPA0 = I915_READ(FPA0);
+                dev_priv->saveFPA1 = I915_READ(FPA1);
+                dev_priv->saveDPLL_A = I915_READ(DPLL_A);
+        }
+        if (IS_I965G(dev) && !IS_IGDNG(dev))
                dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
        dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
        dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
@@ -243,7 +264,30 @@ static void i915_save_modeset_reg(struct drm_device *dev)
        dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
        dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
        dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
-        dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
+        if (!IS_IGDNG(dev))
+                dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
+        if (IS_IGDNG(dev)) {
+                dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
+                dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
+                dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
+                dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
+                dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
+                dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
+                dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
+                dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
+                dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
+                dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
+                dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
+                dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
+                dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
+                dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
+                dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
+                dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
+        }
        dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
        dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
@@ -260,10 +304,16 @@ static void i915_save_modeset_reg(struct drm_device *dev)
        /* Pipe & plane B info */
        dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
        dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
-        dev_priv->saveFPB0 = I915_READ(FPB0);
+        if (IS_IGDNG(dev)) {
-        dev_priv->saveFPB1 = I915_READ(FPB1);
+                dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
-        dev_priv->saveDPLL_B = I915_READ(DPLL_B);
+                dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
-        if (IS_I965G(dev))
+                dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
+        } else {
+                dev_priv->saveFPB0 = I915_READ(FPB0);
+                dev_priv->saveFPB1 = I915_READ(FPB1);
+                dev_priv->saveDPLL_B = I915_READ(DPLL_B);
+        }
+        if (IS_I965G(dev) && !IS_IGDNG(dev))
                dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
        dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
        dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
@@ -271,7 +321,30 @@ static void i915_save_modeset_reg(struct drm_device *dev)
        dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
        dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
        dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
-        dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
+        if (!IS_IGDNG(dev))
+                dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
+        if (IS_IGDNG(dev)) {
+                dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
+                dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
+                dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
+                dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
+                dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
+                dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
+                dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
+                dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
+                dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
+                dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
+                dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
+                dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
+                dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
+                dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
+                dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
+                dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
+        }
        dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
        dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
@@ -290,23 +363,46 @@ static void i915_save_modeset_reg(struct drm_device *dev)
 static void i915_restore_modeset_reg(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+        int dpll_a_reg, fpa0_reg, fpa1_reg;
+        int dpll_b_reg, fpb0_reg, fpb1_reg;
        if (drm_core_check_feature(dev, DRIVER_MODESET))
                return;
+        if (IS_IGDNG(dev)) {
+                dpll_a_reg = PCH_DPLL_A;
+                dpll_b_reg = PCH_DPLL_B;
+                fpa0_reg = PCH_FPA0;
+                fpb0_reg = PCH_FPB0;
+                fpa1_reg = PCH_FPA1;
+                fpb1_reg = PCH_FPB1;
+        } else {
+                dpll_a_reg = DPLL_A;
+                dpll_b_reg = DPLL_B;
+                fpa0_reg = FPA0;
+                fpb0_reg = FPB0;
+                fpa1_reg = FPA1;
+                fpb1_reg = FPB1;
+        }
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
+                I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
+        }
        /* Pipe & plane A info */
        /* Prime the clock */
        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
-                I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
+                I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
                           ~DPLL_VCO_ENABLE);
                DRM_UDELAY(150);
        }
-        I915_WRITE(FPA0, dev_priv->saveFPA0);
+        I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
-        I915_WRITE(FPA1, dev_priv->saveFPA1);
+        I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
        /* Actually enable it */
-        I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
+        I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
        DRM_UDELAY(150);
-        if (IS_I965G(dev))
+        if (IS_I965G(dev) && !IS_IGDNG(dev))
                I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
        DRM_UDELAY(150);
@@ -317,7 +413,30 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
        I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
        I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
-        I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
+        if (!IS_IGDNG(dev))
+                I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
+                I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
+                I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
+                I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
+                I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
+                I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
+                I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
+                I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
+                I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
+                I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
+                I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
+                I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
+                I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
+                I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
+                I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
+                I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
+        }
        /* Restore plane info */
        I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
@@ -339,16 +458,16 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        /* Pipe & plane B info */
        if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
-                I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
+                I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
                           ~DPLL_VCO_ENABLE);
                DRM_UDELAY(150);
        }
-        I915_WRITE(FPB0, dev_priv->saveFPB0);
+        I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
-        I915_WRITE(FPB1, dev_priv->saveFPB1);
+        I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
        /* Actually enable it */
-        I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
+        I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
        DRM_UDELAY(150);
-        if (IS_I965G(dev))
+        if (IS_I965G(dev) && !IS_IGDNG(dev))
                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
        DRM_UDELAY(150);
@@ -359,7 +478,30 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
        I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
        I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
-        I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
+        if (!IS_IGDNG(dev))
+                I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
+                I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
+                I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
+                I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
+                I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
+                I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
+                I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
+                I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
+                I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
+                I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
+                I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
+                I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
+                I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
+                I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
+                I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
+                I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
+        }
        /* Restore plane info */
        I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
@@ -404,21 +546,43 @@ void i915_save_display(struct drm_device *dev)
                dev_priv->saveCURSIZE = I915_READ(CURSIZE);
        /* CRT state */
-        dev_priv->saveADPA = I915_READ(ADPA);
+        if (IS_IGDNG(dev)) {
+                dev_priv->saveADPA = I915_READ(PCH_ADPA);
+        } else {
+                dev_priv->saveADPA = I915_READ(ADPA);
+        }
        /* LVDS state */
-        dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
+        if (IS_IGDNG(dev)) {
-        dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
+                dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
-        dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
+                dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
-        if (IS_I965G(dev))
+                dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
-                dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
+                dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
-        if (IS_MOBILE(dev) && !IS_I830(dev))
+                dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
-                dev_priv->saveLVDS = I915_READ(LVDS);
+                dev_priv->saveLVDS = I915_READ(PCH_LVDS);
-        if (!IS_I830(dev) && !IS_845G(dev))
+        } else {
+                dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
+                dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
+                dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
+                dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
+                if (IS_I965G(dev))
+                        dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
+                if (IS_MOBILE(dev) && !IS_I830(dev))
+                        dev_priv->saveLVDS = I915_READ(LVDS);
+        }
+        if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
                dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
-        dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
-        dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
+        if (IS_IGDNG(dev)) {
-        dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
+                dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
+                dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
+                dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
+        } else {
+                dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
+                dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
+                dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
+        }
        /* Display Port state */
        if (SUPPORTS_INTEGRATED_DP(dev)) {
@@ -437,16 +601,23 @@ void i915_save_display(struct drm_device *dev)
        /* FIXME: save TV & SDVO state */
        /* FBC state */
-        dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
+        if (IS_GM45(dev)) {
-        dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
+                dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
-        dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
+        } else {
-        dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+                dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
+                dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
+                dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
+                dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+        }
        /* VGA state */
        dev_priv->saveVGA0 = I915_READ(VGA0);
        dev_priv->saveVGA1 = I915_READ(VGA1);
        dev_priv->saveVGA_PD = I915_READ(VGA_PD);
-        dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
+        if (IS_IGDNG(dev))
+                dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
+        else
+                dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
        i915_save_vga(dev);
 }
@@ -485,22 +656,41 @@ void i915_restore_display(struct drm_device *dev)
                I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
        /* CRT state */
-        I915_WRITE(ADPA, dev_priv->saveADPA);
+        if (IS_IGDNG(dev))
+                I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
+        else
+                I915_WRITE(ADPA, dev_priv->saveADPA);
        /* LVDS state */
-        if (IS_I965G(dev))
+        if (IS_I965G(dev) && !IS_IGDNG(dev))
                I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
-        if (IS_MOBILE(dev) && !IS_I830(dev))
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
+        } else if (IS_MOBILE(dev) && !IS_I830(dev))
                I915_WRITE(LVDS, dev_priv->saveLVDS);
-        if (!IS_I830(dev) && !IS_845G(dev))
+        if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
                I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
-        I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
+        if (IS_IGDNG(dev)) {
-        I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
+                I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
-        I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
+                I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
-        I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
+                I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
-        I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
+                I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
-        I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
+                I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
+                I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
+                I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
+                I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
+        } else {
+                I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
+                I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
+                I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
+                I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
+                I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
+                I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
+                I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
+        }
        /* Display Port state */
        if (SUPPORTS_INTEGRATED_DP(dev)) {
@@ -511,13 +701,22 @@ void i915_restore_display(struct drm_device *dev)
        /* FIXME: restore TV & SDVO state */
        /* FBC info */
-        I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
+        if (IS_GM45(dev)) {
-        I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
+                g4x_disable_fbc(dev);
-        I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
+                I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
-        I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+        } else {
+                i8xx_disable_fbc(dev);
+                I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
+                I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
+                I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
+                I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+        }
        /* VGA state */
-        I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
+        if (IS_IGDNG(dev))
+                I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
+        else
+                I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
        I915_WRITE(VGA0, dev_priv->saveVGA0);
        I915_WRITE(VGA1, dev_priv->saveVGA1);
        I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@ -543,8 +742,17 @@ int i915_save_state(struct drm_device *dev)
        i915_save_display(dev);
        /* Interrupt state */
-        dev_priv->saveIER = I915_READ(IER);
+        if (IS_IGDNG(dev)) {
-        dev_priv->saveIMR = I915_READ(IMR);
+                dev_priv->saveDEIER = I915_READ(DEIER);
+                dev_priv->saveDEIMR = I915_READ(DEIMR);
+                dev_priv->saveGTIER = I915_READ(GTIER);
+                dev_priv->saveGTIMR = I915_READ(GTIMR);
+                dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
+                dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
+        } else {
+                dev_priv->saveIER = I915_READ(IER);
+                dev_priv->saveIMR = I915_READ(IMR);
+        }
        /* Clock gating state */
        dev_priv->saveD_STATE = I915_READ(D_STATE);
@@ -609,8 +817,17 @@ int i915_restore_state(struct drm_device *dev)
        i915_restore_display(dev);
        /* Interrupt state */
-        I915_WRITE (IER, dev_priv->saveIER);
+        if (IS_IGDNG(dev)) {
-        I915_WRITE (IMR,  dev_priv->saveIMR);
+                I915_WRITE(DEIER, dev_priv->saveDEIER);
+                I915_WRITE(DEIMR, dev_priv->saveDEIMR);
+                I915_WRITE(GTIER, dev_priv->saveGTIER);
+                I915_WRITE(GTIMR, dev_priv->saveGTIMR);
+                I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
+                I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
+        } else {
+                I915_WRITE (IER, dev_priv->saveIER);
+                I915_WRITE (IMR,  dev_priv->saveIMR);
+        }
        /* Clock gating state */
        I915_WRITE (D_STATE, dev_priv->saveD_STATE);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 4337414846b6..96cd256e60e6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -351,20 +351,18 @@ parse_driver_features(struct drm_i915_private *dev_priv,
        struct drm_device *dev = dev_priv->dev;
        struct bdb_driver_features *driver;
-        /* set default for chips without eDP */
-        if (!SUPPORTS_EDP(dev)) {
-                dev_priv->edp_support = 0;
-                return;
-        }
        driver = find_section(bdb, BDB_DRIVER_FEATURES);
        if (!driver)
                return;
-        if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
+        if (driver && SUPPORTS_EDP(dev) &&
+            driver->lvds_config == BDB_DRIVER_FEATURE_EDP) {
                dev_priv->edp_support = 1;
+        } else {
+                dev_priv->edp_support = 0;
+        }
-        if (driver->dual_frequency)
+        if (driver && driver->dual_frequency)
                dev_priv->render_reclock_avail = true;
 }
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 212e22740fc1..e5051446c48e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -262,8 +262,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
                } while (time_after(timeout, jiffies));
        }
-        if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) ==
+        if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
-            CRT_HOTPLUG_MONITOR_COLOR)
+            CRT_HOTPLUG_MONITOR_NONE)
                return true;
        return false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c14240cc002..099f420de57a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -863,10 +863,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        intel_clock_t clock;
-        int max_n;
-        bool found;
        int err_most = 47;
-        found = false;
+        int err_min = 10000;
        /* eDP has only 2 clock choice, no n/m/p setting */
        if (HAS_eDP)
@@ -890,10 +888,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
        }
        memset(best_clock, 0, sizeof(*best_clock));
-        max_n = limit->n.max;
        for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
                /* based on hardware requriment prefer smaller n to precision */
-                for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
+                for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
                        /* based on hardware requirment prefere larger m1,m2 */
                        for (clock.m1 = limit->m1.max;
                             clock.m1 >= limit->m1.min; clock.m1--) {
@@ -907,18 +904,18 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                                        this_err = abs((10000 - (target*10000/clock.dot)));
                                        if (this_err < err_most) {
                                                *best_clock = clock;
-                                                err_most = this_err;
-                                                max_n = clock.n;
-                                                found = true;
                                                /* found on first matching */
                                                goto out;
+                                        } else if (this_err < err_min) {
+                                                *best_clock = clock;
+                                                err_min = this_err;
                                        }
                                }
                        }
                }
        }
 out:
-        return found;
+        return true;
 }
 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
@@ -943,6 +940,7 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
    clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
    clock.p = (clock.p1 * clock.p2);
    clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
+    clock.vco = 0;
    memcpy(best_clock, &clock, sizeof(intel_clock_t));
    return true;
 }
@@ -1260,9 +1258,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                return ret;
        }
-        /* Pre-i965 needs to install a fence for tiled scan-out */
+        /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
-        if (!IS_I965G(dev) &&
+         * whereas 965+ only requires a fence if using framebuffer compression.
-            obj_priv->fence_reg == I915_FENCE_REG_NONE &&
+         * For simplicity, we always install a fence as the cost is not that onerous.
+         */
+        if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
            obj_priv->tiling_mode != I915_TILING_NONE) {
                ret = i915_gem_object_get_fence_reg(obj);
                if (ret != 0) {
@@ -1513,7 +1513,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                /* Enable panel fitting for LVDS */
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                        temp = I915_READ(pf_ctl_reg);
-                        I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
+                        I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
                        /* currently full aspect */
                        I915_WRITE(pf_win_pos, 0);
@@ -1801,6 +1801,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
        case DRM_MODE_DPMS_ON:
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
+                intel_update_watermarks(dev);
                /* Enable the DPLL */
                temp = I915_READ(dpll_reg);
                if ((temp & DPLL_VCO_ENABLE) == 0) {
@@ -1838,7 +1840,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                /* Give the overlay scaler a chance to enable if it's on this pipe */
                //intel_crtc_dpms_video(crtc, true); TODO
-                intel_update_watermarks(dev);
        break;
        case DRM_MODE_DPMS_OFF:
                intel_update_watermarks(dev);
@@ -2082,7 +2083,7 @@ fdi_reduce_ratio(u32 *num, u32 *den)
 #define LINK_N 0x80000
 static void
-igdng_compute_m_n(int bytes_per_pixel, int nlanes,
+igdng_compute_m_n(int bits_per_pixel, int nlanes,
                int pixel_clock, int link_clock,
                struct fdi_m_n *m_n)
 {
@@ -2092,7 +2093,8 @@ igdng_compute_m_n(int bytes_per_pixel, int nlanes,
        temp = (u64) DATA_N * pixel_clock;
        temp = div_u64(temp, link_clock);
-        m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
+        m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
+        m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
        m_n->gmch_n = DATA_N;
        fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
@@ -2140,6 +2142,13 @@ static struct intel_watermark_params igd_cursor_hplloff_wm = {
        IGD_CURSOR_GUARD_WM,
        IGD_FIFO_LINE_SIZE
 };
+static struct intel_watermark_params g4x_wm_info = {
+        G4X_FIFO_SIZE,
+        G4X_MAX_WM,
+        G4X_MAX_WM,
+        2,
+        G4X_FIFO_LINE_SIZE,
+};
 static struct intel_watermark_params i945_wm_info = {
        I945_FIFO_SIZE,
        I915_MAX_WM,
@@ -2430,17 +2439,74 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
        return size;
 }
-static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
+static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
-                          int unused3, int unused4)
+                          int planeb_clock, int sr_hdisplay, int pixel_size)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 fw_blc_self = I915_READ(FW_BLC_SELF);
+        int total_size, cacheline_size;
+        int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
+        struct intel_watermark_params planea_params, planeb_params;
+        unsigned long line_time_us;
+        int sr_clock, sr_entries = 0, entries_required;
-        if (i915_powersave)
+        /* Create copies of the base settings for each pipe */
-                fw_blc_self |= FW_BLC_SELF_EN;
+        planea_params = planeb_params = g4x_wm_info;
-        else
-                fw_blc_self &= ~FW_BLC_SELF_EN;
+        /* Grab a couple of global values before we overwrite them */
-        I915_WRITE(FW_BLC_SELF, fw_blc_self);
+        total_size = planea_params.fifo_size;
+        cacheline_size = planea_params.cacheline_size;
+        /*
+         * Note: we need to make sure we don't overflow for various clock &
+         * latency values.
+         * clocks go from a few thousand to several hundred thousand.
+         * latency is usually a few thousand
+         */
+        entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
+                1000;
+        entries_required /= G4X_FIFO_LINE_SIZE;
+        planea_wm = entries_required + planea_params.guard_size;
+        entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
+                1000;
+        entries_required /= G4X_FIFO_LINE_SIZE;
+        planeb_wm = entries_required + planeb_params.guard_size;
+        cursora_wm = cursorb_wm = 16;
+        cursor_sr = 32;
+        DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
+        /* Calc sr entries for one plane configs */
+        if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
+                /* self-refresh has much higher latency */
+                const static int sr_latency_ns = 12000;
+                sr_clock = planea_clock ? planea_clock : planeb_clock;
+                line_time_us = ((sr_hdisplay * 1000) / sr_clock);
+                /* Use ns/us then divide to preserve precision */
+                sr_entries = (((sr_latency_ns / line_time_us) + 1) *
+                              pixel_size * sr_hdisplay) / 1000;
+                sr_entries = roundup(sr_entries / cacheline_size, 1);
+                DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+        }
+        DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
+                  planea_wm, planeb_wm, sr_entries);
+        planea_wm &= 0x3f;
+        planeb_wm &= 0x3f;
+        I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
+                   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
+                   (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
+        I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
+                   (cursora_wm << DSPFW_CURSORA_SHIFT));
+        /* HPLL off in SR has some issues on G4x... disable it */
+        I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
+                   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
@@ -2586,6 +2652,9 @@ static void intel_update_watermarks(struct drm_device *dev)
        unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
        int enabled = 0, pixel_size = 0;
+        if (!dev_priv->display.update_wm)
+                return;
        /* Get the clock config from both planes */
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                intel_crtc = to_intel_crtc(crtc);
@@ -2763,7 +2832,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        /* FDI link */
        if (IS_IGDNG(dev)) {
-                int lane, link_bw;
+                int lane, link_bw, bpp;
                /* eDP doesn't require FDI link, so just set DP M/N
                   according to current link config */
                if (is_edp) {
@@ -2782,10 +2851,72 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                        lane = 4;
                        link_bw = 270000;
                }
-                igdng_compute_m_n(3, lane, target_clock,
+                /* determine panel color depth */
+                temp = I915_READ(pipeconf_reg);
+                switch (temp & PIPE_BPC_MASK) {
+                case PIPE_8BPC:
+                        bpp = 24;
+                        break;
+                case PIPE_10BPC:
+                        bpp = 30;
+                        break;
+                case PIPE_6BPC:
+                        bpp = 18;
+                        break;
+                case PIPE_12BPC:
+                        bpp = 36;
+                        break;
+                default:
+                        DRM_ERROR("unknown pipe bpc value\n");
+                        bpp = 24;
+                }
+                igdng_compute_m_n(bpp, lane, target_clock,
                                  link_bw, &m_n);
        }
+        /* Ironlake: try to setup display ref clock before DPLL
+         * enabling. This is only under driver's control after
+         * PCH B stepping, previous chipset stepping should be
+         * ignoring this setting.
+         */
+        if (IS_IGDNG(dev)) {
+                temp = I915_READ(PCH_DREF_CONTROL);
+                /* Always enable nonspread source */
+                temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+                temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+                I915_WRITE(PCH_DREF_CONTROL, temp);
+                POSTING_READ(PCH_DREF_CONTROL);
+                temp &= ~DREF_SSC_SOURCE_MASK;
+                temp |= DREF_SSC_SOURCE_ENABLE;
+                I915_WRITE(PCH_DREF_CONTROL, temp);
+                POSTING_READ(PCH_DREF_CONTROL);
+                udelay(200);
+                if (is_edp) {
+                        if (dev_priv->lvds_use_ssc) {
+                                temp |= DREF_SSC1_ENABLE;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+                                POSTING_READ(PCH_DREF_CONTROL);
+                                udelay(200);
+                                temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+                                temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+                                POSTING_READ(PCH_DREF_CONTROL);
+                        } else {
+                                temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+                                POSTING_READ(PCH_DREF_CONTROL);
+                        }
+                }
+        }
        if (IS_IGD(dev)) {
                fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
                if (has_reduced_clock)
@@ -2936,6 +3067,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                lvds = I915_READ(lvds_reg);
                lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
+                /* set the corresponsding LVDS_BORDER bit */
+                lvds |= dev_priv->lvds_border_bits;
                /* Set the B0-B3 data pairs corresponding to whether we're going to
                 * set the DPLLs for dual-channel mode or not.
                 */
@@ -4124,7 +4257,9 @@ void intel_init_clock_gating(struct drm_device *dev)
         * Disable clock gating reported to work incorrectly according to the
         * specs, but enable as much else as we can.
         */
-        if (IS_G4X(dev)) {
+        if (IS_IGDNG(dev)) {
+                return;
+        } else if (IS_G4X(dev)) {
                uint32_t dspclk_gate;
                I915_WRITE(RENCLK_GATE_D1, 0);
                I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -4212,7 +4347,9 @@ static void intel_init_display(struct drm_device *dev)
                        i830_get_display_clock_speed;
        /* For FIFO watermark updates */
-        if (IS_G4X(dev))
+        if (IS_IGDNG(dev))
+                dev_priv->display.update_wm = NULL;
+        else if (IS_G4X(dev))
                dev_priv->display.update_wm = g4x_update_wm;
        else if (IS_I965G(dev))
                dev_priv->display.update_wm = i965_update_wm;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f4856a510476..d83447557f9b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -400,7 +400,7 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
 {
        struct intel_dp_priv   *dp_priv = intel_output->dev_priv;
-        DRM_ERROR("i2c_init %s\n", name);
+        DRM_DEBUG_KMS("i2c_init %s\n", name);
        dp_priv->algo.running = false;
        dp_priv->algo.address = 0;
        dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 663ab6de0b58..c33451aec1bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -77,14 +77,32 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
        struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
        u32 temp;
-        if (mode != DRM_MODE_DPMS_ON) {
+        temp = I915_READ(hdmi_priv->sdvox_reg);
-                temp = I915_READ(hdmi_priv->sdvox_reg);
+        /* HW workaround, need to toggle enable bit off and on for 12bpc, but
+         * we do this anyway which shows more stable in testing.
+         */
+        if (IS_IGDNG(dev)) {
                I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);
+                POSTING_READ(hdmi_priv->sdvox_reg);
+        }
+        if (mode != DRM_MODE_DPMS_ON) {
+                temp &= ~SDVO_ENABLE;
        } else {
-                temp = I915_READ(hdmi_priv->sdvox_reg);
+                temp |= SDVO_ENABLE;
-                I915_WRITE(hdmi_priv->sdvox_reg, temp | SDVO_ENABLE);
        }
+        I915_WRITE(hdmi_priv->sdvox_reg, temp);
        POSTING_READ(hdmi_priv->sdvox_reg);
+        /* HW workaround, need to write this twice for issue that may result
+         * in first write getting masked.
+         */
+        if (IS_IGDNG(dev)) {
+                I915_WRITE(hdmi_priv->sdvox_reg, temp);
+                POSTING_READ(hdmi_priv->sdvox_reg);
+        }
 }
 static void intel_hdmi_save(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 98ae3d73577e..05598ae10c4b 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -380,7 +380,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
                                adjusted_mode->crtc_vblank_start + vsync_pos;
                /* keep the vsync width constant */
                adjusted_mode->crtc_vsync_end =
-                                adjusted_mode->crtc_vblank_start + vsync_width;
+                                adjusted_mode->crtc_vsync_start + vsync_width;
                border = 1;
                break;
        case DRM_MODE_SCALE_ASPECT:
@@ -526,6 +526,14 @@ out:
        lvds_priv->pfit_control = pfit_control;
        lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
        /*
+         * When there exists the border, it means that the LVDS_BORDR
+         * should be enabled.
+         */
+        if (border)
+                dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE;
+        else
+                dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE);
+        /*
         * XXX: It would be nice to support lower refresh rates on the
         * panels to reduce power consumption, and perhaps match the
         * user's requested refresh rate.
@@ -656,6 +664,15 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
        return 0;
 }
+/*
+ * Lid events. Note the use of 'modeset_on_lid':
+ *  - we set it on lid close, and reset it on open
+ *  - we use it as a "only once" bit (ie we ignore
+ *    duplicate events where it was already properly
+ *    set/reset)
+ *  - the suspend/resume paths will also set it to
+ *    zero, since they restore the mode ("lid open").
+ */
 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
                            void *unused)
 {
@@ -663,13 +680,19 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
                container_of(nb, struct drm_i915_private, lid_notifier);
        struct drm_device *dev = dev_priv->dev;
-        if (acpi_lid_open() && !dev_priv->suspended) {
+        if (!acpi_lid_open()) {
-                mutex_lock(&dev->mode_config.mutex);
+                dev_priv->modeset_on_lid = 1;
-                drm_helper_resume_force_mode(dev);
+                return NOTIFY_OK;
-                mutex_unlock(&dev->mode_config.mutex);
        }
-        drm_sysfs_hotplug_event(dev_priv->dev);
+        if (!dev_priv->modeset_on_lid)
+                return NOTIFY_OK;
+        dev_priv->modeset_on_lid = 0;
+        mutex_lock(&dev->mode_config.mutex);
+        drm_helper_resume_force_mode(dev);
+        mutex_unlock(&dev->mode_config.mutex);
        return NOTIFY_OK;
 }
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 09a28923f46e..b5713eedd6e1 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -49,7 +49,7 @@ radeon-y += radeon_device.o radeon_kms.o \
        radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
        rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
        r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
-        r600_blit_kms.o
+        r600_blit_kms.o radeon_pm.o
 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 901befe03da2..d67c42555ab9 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -107,6 +107,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
                        base += 3;
                        break;
                case ATOM_IIO_WRITE:
+                        (void)ctx->card->reg_read(ctx->card, CU16(base + 1));
                        ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
                        base += 3;
                        break;
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 5d402086bc47..c11ddddfb3b6 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -2314,7 +2314,7 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT {
        UCHAR ucSS_Step;
        UCHAR ucSS_Delay;
        UCHAR ucSS_Id;
-        UCHAR ucRecommandedRef_Div;
+        UCHAR ucRecommendedRef_Div;
        UCHAR ucSS_Range;       /* it was reserved for V11 */
 } ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 14fa9701aeb3..c15287a590ff 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -31,10 +31,6 @@
 #include "atom.h"
 #include "atom-bits.h"
-/* evil but including atombios.h is much worse */
-bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
-                                SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
-                                int32_t *pixel_clock);
 static void atombios_overscan_setup(struct drm_crtc *crtc,
                                    struct drm_display_mode *mode,
                                    struct drm_display_mode *adjusted_mode)
@@ -248,18 +244,18 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
        switch (mode) {
        case DRM_MODE_DPMS_ON:
+                atombios_enable_crtc(crtc, 1);
                if (ASIC_IS_DCE3(rdev))
                        atombios_enable_crtc_memreq(crtc, 1);
-                atombios_enable_crtc(crtc, 1);
                atombios_blank_crtc(crtc, 0);
                break;
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
        case DRM_MODE_DPMS_OFF:
                atombios_blank_crtc(crtc, 1);
-                atombios_enable_crtc(crtc, 0);
                if (ASIC_IS_DCE3(rdev))
                        atombios_enable_crtc_memreq(crtc, 0);
+                atombios_enable_crtc(crtc, 0);
                break;
        }
@@ -270,59 +266,147 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 static void
 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
-                             SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
+                             struct drm_display_mode *mode)
 {
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct drm_device *dev = crtc->dev;
        struct radeon_device *rdev = dev->dev_private;
-        SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
+        SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
        int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
+        u16 misc = 0;
-        conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
+        memset(&args, 0, sizeof(args));
-        conv_param.usH_Blanking_Time =
+        args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
-            cpu_to_le16(crtc_param->usH_Blanking_Time);
+        args.usH_Blanking_Time =
-        conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
+                cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
-        conv_param.usV_Blanking_Time =
+        args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
-            cpu_to_le16(crtc_param->usV_Blanking_Time);
+        args.usV_Blanking_Time =
-        conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
+            cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
-        conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+        args.usH_SyncOffset =
-        conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
+                cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
-        conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
+        args.usH_SyncWidth =
-        conv_param.susModeMiscInfo.usAccess =
+                cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
-            cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+        args.usV_SyncOffset =
-        conv_param.ucCRTC = crtc_param->ucCRTC;
+                cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
+        args.usV_SyncWidth =
+                cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
+        /*args.ucH_Border = mode->hborder;*/
+        /*args.ucV_Border = mode->vborder;*/
+        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+                misc |= ATOM_VSYNC_POLARITY;
+        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+                misc |= ATOM_HSYNC_POLARITY;
+        if (mode->flags & DRM_MODE_FLAG_CSYNC)
+                misc |= ATOM_COMPOSITESYNC;
+        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+                misc |= ATOM_INTERLACE;
+        if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+                misc |= ATOM_DOUBLE_CLOCK_MODE;
+        args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
+        args.ucCRTC = radeon_crtc->crtc_id;
        printk("executing set crtc dtd timing\n");
-        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
-void atombios_crtc_set_timing(struct drm_crtc *crtc,
+static void atombios_crtc_set_timing(struct drm_crtc *crtc,
-                              SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
+                                     struct drm_display_mode *mode)
-                              crtc_param)
 {
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct drm_device *dev = crtc->dev;
        struct radeon_device *rdev = dev->dev_private;
-        SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
+        SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
        int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+        u16 misc = 0;
-        conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
+        memset(&args, 0, sizeof(args));
-        conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
+        args.usH_Total = cpu_to_le16(mode->crtc_htotal);
-        conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
+        args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
-        conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+        args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
-        conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
+        args.usH_SyncWidth =
-        conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
+                cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
-        conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
+        args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
-        conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
+        args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
-        conv_param.susModeMiscInfo.usAccess =
+        args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
-            cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+        args.usV_SyncWidth =
-        conv_param.ucCRTC = crtc_param->ucCRTC;
+                cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
-        conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
-        conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
+        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
-        conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
+                misc |= ATOM_VSYNC_POLARITY;
-        conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
+        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
-        conv_param.ucReserved = crtc_param->ucReserved;
+                misc |= ATOM_HSYNC_POLARITY;
+        if (mode->flags & DRM_MODE_FLAG_CSYNC)
+                misc |= ATOM_COMPOSITESYNC;
+        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+                misc |= ATOM_INTERLACE;
+        if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+                misc |= ATOM_DOUBLE_CLOCK_MODE;
+        args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
+        args.ucCRTC = radeon_crtc->crtc_id;
        printk("executing set crtc timing\n");
-        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+static void atombios_set_ss(struct drm_crtc *crtc, int enable)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *encoder = NULL;
+        struct radeon_encoder *radeon_encoder = NULL;
+        struct radeon_encoder_atom_dig *dig = NULL;
+        int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
+        ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args;
+        ENABLE_LVDS_SS_PARAMETERS legacy_args;
+        uint16_t percentage = 0;
+        uint8_t type = 0, step = 0, delay = 0, range = 0;
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                if (encoder->crtc == crtc) {
+                        radeon_encoder = to_radeon_encoder(encoder);
+                        /* only enable spread spectrum on LVDS */
+                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                                dig = radeon_encoder->enc_priv;
+                                if (dig && dig->ss) {
+                                        percentage = dig->ss->percentage;
+                                        type = dig->ss->type;
+                                        step = dig->ss->step;
+                                        delay = dig->ss->delay;
+                                        range = dig->ss->range;
+                                } else if (enable)
+                                        return;
+                        } else if (enable)
+                                return;
+                        break;
+                }
+        }
+        if (!radeon_encoder)
+                return;
+        if (ASIC_IS_AVIVO(rdev)) {
+                memset(&args, 0, sizeof(args));
+                args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
+                args.ucSpreadSpectrumType = type;
+                args.ucSpreadSpectrumStep = step;
+                args.ucSpreadSpectrumDelay = delay;
+                args.ucSpreadSpectrumRange = range;
+                args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+                args.ucEnable = enable;
+                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+        } else {
+                memset(&legacy_args, 0, sizeof(legacy_args));
+                legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
+                legacy_args.ucSpreadSpectrumType = type;
+                legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
+                legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
+                legacy_args.ucEnable = enable;
+                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args);
+        }
 }
 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
@@ -333,12 +417,13 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        struct drm_encoder *encoder = NULL;
        struct radeon_encoder *radeon_encoder = NULL;
        uint8_t frev, crev;
-        int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+        int index;
        SET_PIXEL_CLOCK_PS_ALLOCATION args;
        PIXEL_CLOCK_PARAMETERS *spc1_ptr;
        PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
        PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
-        uint32_t sclock = mode->clock;
+        uint32_t pll_clock = mode->clock;
+        uint32_t adjusted_clock;
        uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
        struct radeon_pll *pll;
        int pll_flags = 0;
@@ -346,8 +431,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        memset(&args, 0, sizeof(args));
        if (ASIC_IS_AVIVO(rdev)) {
-                uint32_t ss_cntl;
                if ((rdev->family == CHIP_RS600) ||
                    (rdev->family == CHIP_RS690) ||
                    (rdev->family == CHIP_RS740))
@@ -358,15 +441,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                        pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
                else
                        pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
-                /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
-                if (radeon_crtc->crtc_id == 0) {
-                        ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
-                        WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
-                } else {
-                        ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
-                        WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
-                }
        } else {
                pll_flags |= RADEON_PLL_LEGACY;
@@ -393,14 +467,43 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                }
        }
+        /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
+         * accordingly based on the encoder/transmitter to work around
+         * special hw requirements.
+         */
+        if (ASIC_IS_DCE3(rdev)) {
+                ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
+                if (!encoder)
+                        return;
+                memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
+                adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
+                adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
+                adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
+                index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+                atom_execute_table(rdev->mode_info.atom_context,
+                                   index, (uint32_t *)&adjust_pll_args);
+                adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
+        } else {
+                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
+                if (ASIC_IS_AVIVO(rdev) &&
+                    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
+                        adjusted_clock = mode->clock * 2;
+                else
+                        adjusted_clock = mode->clock;
+        }
        if (radeon_crtc->crtc_id == 0)
                pll = &rdev->clock.p1pll;
        else
                pll = &rdev->clock.p2pll;
-        radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
+        radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
                           &ref_div, &post_div, pll_flags);
+        index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
                              &crev);
@@ -409,7 +512,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                switch (crev) {
                case 1:
                        spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
-                        spc1_ptr->usPixelClock = cpu_to_le16(sclock);
+                        spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
                        spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
                        spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
                        spc1_ptr->ucFracFbDiv = frac_fb_div;
@@ -422,7 +525,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                case 2:
                        spc2_ptr =
                            (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
-                        spc2_ptr->usPixelClock = cpu_to_le16(sclock);
+                        spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
                        spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
                        spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
                        spc2_ptr->ucFracFbDiv = frac_fb_div;
@@ -437,7 +540,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                                return;
                        spc3_ptr =
                            (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
-                        spc3_ptr->usPixelClock = cpu_to_le16(sclock);
+                        spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
                        spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
                        spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
                        spc3_ptr->ucFracFbDiv = frac_fb_div;
@@ -527,6 +630,16 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                WREG32(AVIVO_D1VGA_CONTROL, 0);
        else
                WREG32(AVIVO_D2VGA_CONTROL, 0);
+        if (rdev->family >= CHIP_RV770) {
+                if (radeon_crtc->crtc_id) {
+                        WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
+                        WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
+                } else {
+                        WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
+                        WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
+                }
+        }
        WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
               (u32) fb_location);
        WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
@@ -563,6 +676,10 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                radeon_fb = to_radeon_framebuffer(old_fb);
                radeon_gem_object_unpin(radeon_fb->obj);
        }
+        /* Bytes per pixel may have changed */
+        radeon_bandwidth_update(rdev);
        return 0;
 }
@@ -574,134 +691,24 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct drm_device *dev = crtc->dev;
        struct radeon_device *rdev = dev->dev_private;
-        struct drm_encoder *encoder;
-        SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
-        int need_tv_timings = 0;
-        bool ret;
        /* TODO color tiling */
-        memset(&crtc_timing, 0, sizeof(crtc_timing));
-        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-                /* find tv std */
-                if (encoder->crtc == crtc) {
-                        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-                        if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
-                                struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
-                                if (tv_dac) {
-                                        if (tv_dac->tv_std == TV_STD_NTSC ||
-                                            tv_dac->tv_std == TV_STD_NTSC_J ||
-                                            tv_dac->tv_std == TV_STD_PAL_M)
-                                                need_tv_timings = 1;
-                                        else
-                                                need_tv_timings = 2;
-                                        break;
-                                }
-                        }
-                }
-        }
-        crtc_timing.ucCRTC = radeon_crtc->crtc_id;
-        if (need_tv_timings) {
-                ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
-                                                 &crtc_timing, &adjusted_mode->clock);
-                if (ret == false)
-                        need_tv_timings = 0;
-        }
-        if (!need_tv_timings) {
-                crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
-                crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
-                crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
-                crtc_timing.usH_SyncWidth =
-                        adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
-                crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
-                crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
-                crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
-                crtc_timing.usV_SyncWidth =
-                        adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
-                if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-                        crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
-                if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-                        crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
-                if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
-                        crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
-                if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-                        crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
-                if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
-                        crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
-        }
+        atombios_set_ss(crtc, 0);
        atombios_crtc_set_pll(crtc, adjusted_mode);
-        atombios_crtc_set_timing(crtc, &crtc_timing);
+        atombios_set_ss(crtc, 1);
+        atombios_crtc_set_timing(crtc, adjusted_mode);
        if (ASIC_IS_AVIVO(rdev))
                atombios_crtc_set_base(crtc, x, y, old_fb);
        else {
-                if (radeon_crtc->crtc_id == 0) {
+                if (radeon_crtc->crtc_id == 0)
-                        SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
+                        atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
-                        memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
-                        /* setup FP shadow regs on R4xx */
-                        crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
-                        crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
-                        crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
-                        crtc_dtd_timing.usH_Blanking_Time =
-                            adjusted_mode->crtc_hblank_end -
-                            adjusted_mode->crtc_hdisplay;
-                        crtc_dtd_timing.usV_Blanking_Time =
-                            adjusted_mode->crtc_vblank_end -
-                            adjusted_mode->crtc_vdisplay;
-                        crtc_dtd_timing.usH_SyncOffset =
-                            adjusted_mode->crtc_hsync_start -
-                            adjusted_mode->crtc_hdisplay;
-                        crtc_dtd_timing.usV_SyncOffset =
-                            adjusted_mode->crtc_vsync_start -
-                            adjusted_mode->crtc_vdisplay;
-                        crtc_dtd_timing.usH_SyncWidth =
-                            adjusted_mode->crtc_hsync_end -
-                            adjusted_mode->crtc_hsync_start;
-                        crtc_dtd_timing.usV_SyncWidth =
-                            adjusted_mode->crtc_vsync_end -
-                            adjusted_mode->crtc_vsync_start;
-                        /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
-                        /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
-                        if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
-                                    ATOM_VSYNC_POLARITY;
-                        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
-                                    ATOM_HSYNC_POLARITY;
-                        if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
-                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
-                                    ATOM_COMPOSITESYNC;
-                        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
-                                    ATOM_INTERLACE;
-                        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
-                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
-                                    ATOM_DOUBLE_CLOCK_MODE;
-                        atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
-                }
                radeon_crtc_set_base(crtc, x, y, old_fb);
                radeon_legacy_atom_set_surface(crtc);
        }
        atombios_overscan_setup(crtc, mode, adjusted_mode);
        atombios_scaler_setup(crtc);
-        radeon_bandwidth_update(rdev);
        return 0;
 }
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index fb211e585dea..0d79577c1576 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -561,7 +561,7 @@ struct table {
        char *gpu_prefix;
 };
-struct offset *offset_new(unsigned o)
+static struct offset *offset_new(unsigned o)
 {
        struct offset *offset;
@@ -573,12 +573,12 @@ struct offset *offset_new(unsigned o)
        return offset;
 }
-void table_offset_add(struct table *t, struct offset *offset)
+static void table_offset_add(struct table *t, struct offset *offset)
 {
        list_add_tail(&offset->list, &t->offsets);
 }
-void table_init(struct table *t)
+static void table_init(struct table *t)
 {
        INIT_LIST_HEAD(&t->offsets);
        t->offset_max = 0;
@@ -586,7 +586,7 @@ void table_init(struct table *t)
        t->table = NULL;
 }
-void table_print(struct table *t)
+static void table_print(struct table *t)
 {
        unsigned nlloop, i, j, n, c, id;
@@ -611,7 +611,7 @@ void table_print(struct table *t)
        printf("};\n");
 }
-int table_build(struct table *t)
+static int table_build(struct table *t)
 {
        struct offset *offset;
        unsigned i, m;
@@ -631,7 +631,7 @@ int table_build(struct table *t)
 }
 static char gpu_name[10];
-int parser_auth(struct table *t, const char *filename)
+static int parser_auth(struct table *t, const char *filename)
 {
        FILE *file;
        regex_t mask_rex;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 161094c07d94..c9e93eabcf16 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -186,7 +186,7 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 int r100_irq_process(struct radeon_device *rdev)
 {
-        uint32_t status;
+        uint32_t status, msi_rearm;
        status = r100_irq_ack(rdev);
        if (!status) {
@@ -209,6 +209,21 @@ int r100_irq_process(struct radeon_device *rdev)
                }
                status = r100_irq_ack(rdev);
        }
+        if (rdev->msi_enabled) {
+                switch (rdev->family) {
+                case CHIP_RS400:
+                case CHIP_RS480:
+                        msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
+                        WREG32(RADEON_AIC_CNTL, msi_rearm);
+                        WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
+                        break;
+                default:
+                        msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
+                        WREG32(RADEON_MSI_REARM_EN, msi_rearm);
+                        WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
+                        break;
+                }
+        }
        return IRQ_HANDLED;
 }
@@ -240,7 +255,7 @@ int r100_wb_init(struct radeon_device *rdev)
        int r;
        if (rdev->wb.wb_obj == NULL) {
-                r = radeon_object_create(rdev, NULL, 4096,
+                r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
                                         true,
                                         RADEON_GEM_DOMAIN_GTT,
                                         false, &rdev->wb.wb_obj);
@@ -563,19 +578,19 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        indirect1_start = 16;
        /* cp setup */
        WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
-        WREG32(RADEON_CP_RB_CNTL,
+        tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
-#ifdef __BIG_ENDIAN
-               RADEON_BUF_SWAP_32BIT |
-#endif
-               REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
               REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
               REG_SET(RADEON_MAX_FETCH, max_fetch) |
               RADEON_RB_NO_UPDATE);
+#ifdef __BIG_ENDIAN
+        tmp |= RADEON_BUF_SWAP_32BIT;
+#endif
+        WREG32(RADEON_CP_RB_CNTL, tmp);
        /* Set ring address */
        DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
        WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
        /* Force read & write ptr to 0 */
-        tmp = RREG32(RADEON_CP_RB_CNTL);
        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
        WREG32(RADEON_CP_RB_RPTR_WR, 0);
        WREG32(RADEON_CP_RB_WPTR, 0);
@@ -2364,7 +2379,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
        /*
          Find the total latency for the display data.
        */
-        disp_latency_overhead.full = rfixed_const(80);
+        disp_latency_overhead.full = rfixed_const(8);
        disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
        mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
        mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
@@ -2562,8 +2577,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
 {
        DRM_ERROR("pitch                      %d\n", t->pitch);
+        DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
        DRM_ERROR("width                      %d\n", t->width);
+        DRM_ERROR("width_11                   %d\n", t->width_11);
        DRM_ERROR("height                     %d\n", t->height);
+        DRM_ERROR("height_11                  %d\n", t->height_11);
        DRM_ERROR("num levels                 %d\n", t->num_levels);
        DRM_ERROR("depth                      %d\n", t->txdepth);
        DRM_ERROR("bpp                        %d\n", t->cpp);
@@ -2623,15 +2641,17 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
                                else
                                        w = track->textures[u].pitch / (1 << i);
                        } else {
-                                w = track->textures[u].width / (1 << i);
+                                w = track->textures[u].width;
                                if (rdev->family >= CHIP_RV515)
                                        w |= track->textures[u].width_11;
+                                w = w / (1 << i);
                                if (track->textures[u].roundup_w)
                                        w = roundup_pow_of_two(w);
                        }
-                        h = track->textures[u].height / (1 << i);
+                        h = track->textures[u].height;
                        if (rdev->family >= CHIP_RV515)
                                h |= track->textures[u].height_11;
+                        h = h / (1 << i);
                        if (track->textures[u].roundup_h)
                                h = roundup_pow_of_two(h);
                        size += w * h;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index e08c4a8974ca..2f43ee8e4048 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -113,7 +113,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
        tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
        WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
-        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
        WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
        WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
        WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 5c7fe52de30e..1cefdbcc0850 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -311,6 +311,8 @@ int r420_init(struct radeon_device *rdev)
        }
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Get vram informations */
        r300_vram_info(rdev);
        /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 868add6e166d..7baa73955563 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -384,9 +384,16 @@
 #       define AVIVO_D1GRPH_TILED                               (1 << 20)
 #       define AVIVO_D1GRPH_MACRO_ADDRESS_MODE                  (1 << 21)
+/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
+ * block and vice versa.  This applies to GRPH, CUR, etc.
+ */
 #define AVIVO_D1GRPH_LUT_SEL                                    0x6108
 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS                    0x6110
+#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x6914
+#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x6114
 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS                  0x6118
+#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x691c
+#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x611c
 #define AVIVO_D1GRPH_PITCH                                      0x6120
 #define AVIVO_D1GRPH_SURFACE_OFFSET_X                           0x6124
 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y                           0x6128
@@ -404,6 +411,8 @@
 #       define AVIVO_D1CURSOR_MODE_MASK         (3 << 8)
 #       define AVIVO_D1CURSOR_MODE_24BPP        2
 #define AVIVO_D1CUR_SURFACE_ADDRESS             0x6408
+#define R700_D1CUR_SURFACE_ADDRESS_HIGH         0x6c0c
+#define R700_D2CUR_SURFACE_ADDRESS_HIGH         0x640c
 #define AVIVO_D1CUR_SIZE                        0x6410
 #define AVIVO_D1CUR_POSITION                    0x6414
 #define AVIVO_D1CUR_HOT_SPOT                    0x6418
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index a555b7b19b48..f7435185c0a6 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -260,6 +260,8 @@ int r520_init(struct radeon_device *rdev)
        }
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Get vram informations */
        r520_vram_info(rdev);
        /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 609719490ec2..278f646bc18e 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -339,11 +339,10 @@ int r600_mc_init(struct radeon_device *rdev)
 {
        fixed20_12 a;
        u32 tmp;
-        int chansize;
+        int chansize, numchan;
        int r;
        /* Get VRAM informations */
-        rdev->mc.vram_width = 128;
        rdev->mc.vram_is_ddr = true;
        tmp = RREG32(RAMCFG);
        if (tmp & CHANSIZE_OVERRIDE) {
@@ -353,17 +352,23 @@ int r600_mc_init(struct radeon_device *rdev)
        } else {
                chansize = 32;
        }
-        if (rdev->family == CHIP_R600) {
+        tmp = RREG32(CHMAP);
-                rdev->mc.vram_width = 8 * chansize;
+        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
-        } else if (rdev->family == CHIP_RV670) {
+        case 0:
-                rdev->mc.vram_width = 4 * chansize;
+        default:
-        } else if ((rdev->family == CHIP_RV610) ||
+                numchan = 1;
-                        (rdev->family == CHIP_RV620)) {
+                break;
-                rdev->mc.vram_width = chansize;
+        case 1:
-        } else if ((rdev->family == CHIP_RV630) ||
+                numchan = 2;
-                        (rdev->family == CHIP_RV635)) {
+                break;
-                rdev->mc.vram_width = 2 * chansize;
+        case 2:
+                numchan = 4;
+                break;
+        case 3:
+                numchan = 8;
+                break;
        }
+        rdev->mc.vram_width = numchan * chansize;
        /* Could aper size report 0 ? */
        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
@@ -404,35 +409,29 @@ int r600_mc_init(struct radeon_device *rdev)
                        rdev->mc.gtt_location = rdev->mc.mc_vram_size;
                }
        } else {
-                if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+                rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
-                        rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
+                rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
-                                                                0xFFFF) << 24;
+                                                        0xFFFF) << 24;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
-                        tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+                if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
-                        if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
+                        /* Enough place after vram */
-                                /* Enough place after vram */
+                        rdev->mc.gtt_location = tmp;
-                                rdev->mc.gtt_location = tmp;
+                } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
-                        } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
+                        /* Enough place before vram */
-                                /* Enough place before vram */
+                        rdev->mc.gtt_location = 0;
+                } else {
+                        /* Not enough place after or before shrink
+                         * gart size
+                         */
+                        if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
                                rdev->mc.gtt_location = 0;
+                                rdev->mc.gtt_size = rdev->mc.vram_location;
                        } else {
-                                /* Not enough place after or before shrink
+                                rdev->mc.gtt_location = tmp;
-                                 * gart size
+                                rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
-                                 */
-                                if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
-                                        rdev->mc.gtt_location = 0;
-                                        rdev->mc.gtt_size = rdev->mc.vram_location;
-                                } else {
-                                        rdev->mc.gtt_location = tmp;
-                                        rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
-                                }
                        }
-                        rdev->mc.gtt_location = rdev->mc.mc_vram_size;
-                } else {
-                        rdev->mc.vram_location = 0x00000000UL;
-                        rdev->mc.gtt_location = rdev->mc.mc_vram_size;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
                }
+                rdev->mc.gtt_location = rdev->mc.mc_vram_size;
        }
        rdev->mc.vram_start = rdev->mc.vram_location;
        rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
@@ -859,7 +858,8 @@ void r600_gpu_init(struct radeon_device *rdev)
            ((rdev->family) == CHIP_RV630) ||
            ((rdev->family) == CHIP_RV610) ||
            ((rdev->family) == CHIP_RV620) ||
-            ((rdev->family) == CHIP_RS780)) {
+            ((rdev->family) == CHIP_RS780) ||
+            ((rdev->family) == CHIP_RS880)) {
                WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
        } else {
                WREG32(DB_DEBUG, 0);
@@ -876,7 +876,8 @@ void r600_gpu_init(struct radeon_device *rdev)
        tmp = RREG32(SQ_MS_FIFO_SIZES);
        if (((rdev->family) == CHIP_RV610) ||
            ((rdev->family) == CHIP_RV620) ||
-            ((rdev->family) == CHIP_RS780)) {
+            ((rdev->family) == CHIP_RS780) ||
+            ((rdev->family) == CHIP_RS880)) {
                tmp = (CACHE_FIFO_SIZE(0xa) |
                       FETCH_FIFO_HIWATER(0xa) |
                       DONE_FIFO_HIWATER(0xe0) |
@@ -919,7 +920,8 @@ void r600_gpu_init(struct radeon_device *rdev)
                                            NUM_ES_STACK_ENTRIES(0));
        } else if (((rdev->family) == CHIP_RV610) ||
                   ((rdev->family) == CHIP_RV620) ||
-                   ((rdev->family) == CHIP_RS780)) {
+                   ((rdev->family) == CHIP_RS780) ||
+                   ((rdev->family) == CHIP_RS880)) {
                /* no vertex cache */
                sq_config &= ~VC_ENABLE;
@@ -976,7 +978,8 @@ void r600_gpu_init(struct radeon_device *rdev)
        if (((rdev->family) == CHIP_RV610) ||
            ((rdev->family) == CHIP_RV620) ||
-            ((rdev->family) == CHIP_RS780)) {
+            ((rdev->family) == CHIP_RS780) ||
+            ((rdev->family) == CHIP_RS880)) {
                WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
        } else {
                WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
@@ -1002,8 +1005,9 @@ void r600_gpu_init(struct radeon_device *rdev)
        tmp = rdev->config.r600.max_pipes * 16;
        switch (rdev->family) {
        case CHIP_RV610:
-        case CHIP_RS780:
        case CHIP_RV620:
+        case CHIP_RS780:
+        case CHIP_RS880:
                tmp += 32;
                break;
        case CHIP_RV670:
@@ -1044,8 +1048,9 @@ void r600_gpu_init(struct radeon_device *rdev)
        switch (rdev->family) {
        case CHIP_RV610:
-        case CHIP_RS780:
        case CHIP_RV620:
+        case CHIP_RS780:
+        case CHIP_RS880:
                tmp = TC_L2_SIZE(8);
                break;
        case CHIP_RV630:
@@ -1267,19 +1272,17 @@ int r600_cp_resume(struct radeon_device *rdev)
        /* Set ring buffer size */
        rb_bufsz = drm_order(rdev->cp.ring_size / 8);
+        tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
-        WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
+        tmp |= BUF_SWAP_32BIT;
-                (drm_order(4096/8) << 8) | rb_bufsz);
-#else
-        WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
 #endif
+        WREG32(CP_RB_CNTL, tmp);
        WREG32(CP_SEM_WAIT_TIMER, 0x4);
        /* Set the write pointer delay */
        WREG32(CP_RB_WPTR_DELAY, 0);
        /* Initialize the ring buffer's read and write pointers */
-        tmp = RREG32(CP_RB_CNTL);
        WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
        WREG32(CP_RB_RPTR_WR, 0);
        WREG32(CP_RB_WPTR, 0);
@@ -1400,7 +1403,7 @@ int r600_wb_enable(struct radeon_device *rdev)
        int r;
        if (rdev->wb.wb_obj == NULL) {
-                r = radeon_object_create(rdev, NULL, 4096, true,
+                r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
                                RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
                if (r) {
                        dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
@@ -1450,8 +1453,8 @@ int r600_copy_blit(struct radeon_device *rdev,
                   uint64_t src_offset, uint64_t dst_offset,
                   unsigned num_pages, struct radeon_fence *fence)
 {
-        r600_blit_prepare_copy(rdev, num_pages * 4096);
+        r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
-        r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
+        r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
        r600_blit_done_copy(rdev, fence);
        return 0;
 }
@@ -1632,10 +1635,13 @@ int r600_init(struct radeon_device *rdev)
        r600_scratch_init(rdev);
        /* Initialize surface registers */
        radeon_surface_init(rdev);
+        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
        r = radeon_clocks_init(rdev);
        if (r)
                return r;
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Fence driver */
        r = radeon_fence_driver_init(rdev);
        if (r)
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index dec501081608..5ea432347589 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -582,6 +582,8 @@ r600_blit_copy(struct drm_device *dev,
        u64 vb_addr;
        u32 *vb;
+        vb = r600_nomm_get_vb_ptr(dev);
        if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
                max_bytes = 8192;
@@ -617,8 +619,8 @@ r600_blit_copy(struct drm_device *dev,
                                if (!dev_priv->blit_vb)
                                        return;
                                set_shaders(dev);
+                                vb = r600_nomm_get_vb_ptr(dev);
                        }
-                        vb = r600_nomm_get_vb_ptr(dev);
                        vb[0] = i2f(dst_x);
                        vb[1] = 0;
@@ -706,8 +708,8 @@ r600_blit_copy(struct drm_device *dev,
                                        return;
                                set_shaders(dev);
+                                vb = r600_nomm_get_vb_ptr(dev);
                        }
-                        vb = r600_nomm_get_vb_ptr(dev);
                        vb[0] = i2f(dst_x / 4);
                        vb[1] = 0;
@@ -772,6 +774,7 @@ r600_blit_swap(struct drm_device *dev,
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
        int cb_format, tex_format;
+        int sx2, sy2, dx2, dy2;
        u64 vb_addr;
        u32 *vb;
@@ -786,16 +789,10 @@ r600_blit_swap(struct drm_device *dev,
        }
        vb = r600_nomm_get_vb_ptr(dev);
-        if (cpp == 4) {
+        sx2 = sx + w;
-                cb_format = COLOR_8_8_8_8;
+        sy2 = sy + h;
-                tex_format = FMT_8_8_8_8;
+        dx2 = dx + w;
-        } else if (cpp == 2) {
+        dy2 = dy + h;
-                cb_format = COLOR_5_6_5;
-                tex_format = FMT_5_6_5;
-        } else {
-                cb_format = COLOR_8;
-                tex_format = FMT_8;
-        }
        vb[0] = i2f(dx);
        vb[1] = i2f(dy);
@@ -803,31 +800,46 @@ r600_blit_swap(struct drm_device *dev,
        vb[3] = i2f(sy);
        vb[4] = i2f(dx);
-        vb[5] = i2f(dy + h);
+        vb[5] = i2f(dy2);
        vb[6] = i2f(sx);
-        vb[7] = i2f(sy + h);
+        vb[7] = i2f(sy2);
+        vb[8] = i2f(dx2);
+        vb[9] = i2f(dy2);
+        vb[10] = i2f(sx2);
+        vb[11] = i2f(sy2);
-        vb[8] = i2f(dx + w);
+        switch(cpp) {
-        vb[9] = i2f(dy + h);
+        case 4:
-        vb[10] = i2f(sx + w);
+                cb_format = COLOR_8_8_8_8;
-        vb[11] = i2f(sy + h);
+                tex_format = FMT_8_8_8_8;
+                break;
+        case 2:
+                cb_format = COLOR_5_6_5;
+                tex_format = FMT_5_6_5;
+                break;
+        default:
+                cb_format = COLOR_8;
+                tex_format = FMT_8;
+                break;
+        }
        /* src */
        set_tex_resource(dev_priv, tex_format,
                         src_pitch / cpp,
-                         sy + h, src_pitch / cpp,
+                         sy2, src_pitch / cpp,
                         src_gpu_addr);
        cp_set_surface_sync(dev_priv,
-                            R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr);
+                            R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
        /* dst */
        set_render_target(dev_priv, cb_format,
-                          dst_pitch / cpp, dy + h,
+                          dst_pitch / cpp, dy2,
                          dst_gpu_addr);
        /* scissors */
-        set_scissors(dev_priv, dx, dy, dx + w, dy + h);
+        set_scissors(dev_priv, dx, dy, dx2, dy2);
        /* Vertex buffer setup */
        vb_addr = dev_priv->gart_buffers_offset +
@@ -840,7 +852,7 @@ r600_blit_swap(struct drm_device *dev,
        cp_set_surface_sync(dev_priv,
                            R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
-                            dst_pitch * (dy + h), dst_gpu_addr);
+                            dst_pitch * dy2, dst_gpu_addr);
        dev_priv->blit_vb->used += 12 * 4;
 }
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 93108bb31d1d..dbf716e1fbf3 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -368,7 +368,7 @@ set_default_state(struct radeon_device *rdev)
        if ((rdev->family == CHIP_RV610) ||
            (rdev->family == CHIP_RV620) ||
            (rdev->family == CHIP_RS780) ||
-            (rdev->family == CHIP_RS780) ||
+            (rdev->family == CHIP_RS880) ||
            (rdev->family == CHIP_RV710))
                sq_config = 0;
        else
@@ -610,6 +610,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
        DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
                  size_bytes, rdev->r600_blit.vb_used);
+        vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
        if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
                max_bytes = 8192;
@@ -652,7 +653,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
                                vb = r600_nomm_get_vb_ptr(dev);
 #endif
                        }
-                        vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
                        vb[0] = i2f(dst_x);
                        vb[1] = 0;
@@ -747,7 +747,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
                                vb = r600_nomm_get_vb_ptr(dev);
                        }
 #endif
-                        vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
                        vb[0] = i2f(dst_x / 4);
                        vb[1] = 0;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 17e42195c632..0d820764f340 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -466,6 +466,23 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                for (i = 0; i < pkt->count; i++) {
                        reg = start_reg + (4 * i);
                        switch (reg) {
+                        case SQ_ESGS_RING_BASE:
+                        case SQ_GSVS_RING_BASE:
+                        case SQ_ESTMP_RING_BASE:
+                        case SQ_GSTMP_RING_BASE:
+                        case SQ_VSTMP_RING_BASE:
+                        case SQ_PSTMP_RING_BASE:
+                        case SQ_FBUF_RING_BASE:
+                        case SQ_REDUC_RING_BASE:
+                        case SX_MEMORY_EXPORT_BASE:
+                                r = r600_cs_packet_next_reloc(p, &reloc);
+                                if (r) {
+                                        DRM_ERROR("bad SET_CONFIG_REG "
+                                                        "0x%04X\n", reg);
+                                        return -EINVAL;
+                                }
+                                ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                break;
                        case CP_COHER_BASE:
                                /* use PACKET3_SURFACE_SYNC */
                                return -EINVAL;
@@ -487,6 +504,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        reg = start_reg + (4 * i);
                        switch (reg) {
                        case DB_DEPTH_BASE:
+                        case DB_HTILE_DATA_BASE:
                        case CB_COLOR0_BASE:
                        case CB_COLOR1_BASE:
                        case CB_COLOR2_BASE:
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 9b64d47f1f82..27ab428b149b 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -119,6 +119,7 @@
 #define DB_DEBUG                                        0x9830
 #define         PREZ_MUST_WAIT_FOR_POSTZ_DONE                   (1 << 31)
 #define DB_DEPTH_BASE                                   0x2800C
+#define DB_HTILE_DATA_BASE                              0x28014
 #define DB_WATERMARKS                                   0x9838
 #define         DEPTH_FREE(x)                                   ((x) << 0)
 #define         DEPTH_FLUSH(x)                                  ((x) << 5)
@@ -171,6 +172,14 @@
 #define SQ_STACK_RESOURCE_MGMT_2                          0x8c14
 #       define NUM_GS_STACK_ENTRIES(x)                    ((x) << 0)
 #       define NUM_ES_STACK_ENTRIES(x)                    ((x) << 16)
+#define SQ_ESGS_RING_BASE                               0x8c40
+#define SQ_GSVS_RING_BASE                               0x8c48
+#define SQ_ESTMP_RING_BASE                              0x8c50
+#define SQ_GSTMP_RING_BASE                              0x8c58
+#define SQ_VSTMP_RING_BASE                              0x8c60
+#define SQ_PSTMP_RING_BASE                              0x8c68
+#define SQ_FBUF_RING_BASE                               0x8c70
+#define SQ_REDUC_RING_BASE                              0x8c78
 #define GRBM_CNTL                                       0x8000
 #       define GRBM_READ_TIMEOUT(x)                     ((x) << 0)
@@ -271,6 +280,10 @@
 #define PCIE_PORT_INDEX                                 0x0038
 #define PCIE_PORT_DATA                                  0x003C
+#define CHMAP                                           0x2004
+#define         NOOFCHAN_SHIFT                                  12
+#define         NOOFCHAN_MASK                                   0x00003000
 #define RAMCFG                                          0x2408
 #define         NOOFBANK_SHIFT                                  0
 #define         NOOFBANK_MASK                                   0x00000001
@@ -352,6 +365,7 @@
 #define SX_MISC                                         0x28350
+#define SX_MEMORY_EXPORT_BASE                           0x9010
 #define SX_DEBUG_1                                      0x9054
 #define         SMX_EVENT_RELEASE                               (1 << 0)
 #define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5ab35b81c86b..224506a2f7b1 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -139,6 +139,10 @@ struct radeon_clock {
        uint32_t default_sclk;
 };
+/*
+ * Power management
+ */
+int radeon_pm_init(struct radeon_device *rdev);
 /*
 * Fences.
@@ -276,6 +280,8 @@ union radeon_gart_table {
        struct radeon_gart_table_vram   vram;
 };
+#define RADEON_GPU_PAGE_SIZE 4096
 struct radeon_gart {
        dma_addr_t                      table_addr;
        unsigned                        num_gpu_pages;
@@ -513,6 +519,7 @@ typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 * AGP
 */
 int radeon_agp_init(struct radeon_device *rdev);
+void radeon_agp_resume(struct radeon_device *rdev);
 void radeon_agp_fini(struct radeon_device *rdev);
@@ -621,7 +628,9 @@ struct radeon_asic {
                    uint64_t dst_offset,
                    unsigned num_pages,
                    struct radeon_fence *fence);
+        uint32_t (*get_engine_clock)(struct radeon_device *rdev);
        void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
+        uint32_t (*get_memory_clock)(struct radeon_device *rdev);
        void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
        void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
        void (*set_clock_gating)(struct radeon_device *rdev, int enable);
@@ -783,6 +792,7 @@ struct radeon_device {
        const struct firmware *me_fw;   /* all family ME firmware */
        const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
        struct r600_blit r600_blit;
+        int msi_enabled; /* msi enabled */
 };
 int radeon_device_init(struct radeon_device *rdev,
@@ -952,7 +962,9 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
+#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
+#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 23ea9955ac59..54bf49a6d676 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -237,6 +237,18 @@ int radeon_agp_init(struct radeon_device *rdev)
 #endif
 }
+void radeon_agp_resume(struct radeon_device *rdev)
+{
+#if __OS_HAS_AGP
+        int r;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r)
+                        dev_warn(rdev->dev, "radeon AGP reinit failed\n");
+        }
+#endif
+}
 void radeon_agp_fini(struct radeon_device *rdev)
 {
 #if __OS_HAS_AGP
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c3532c7a6f3f..c18fbee387d7 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -31,10 +31,13 @@
 /*
 * common functions
 */
+uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
+uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
+uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
@@ -95,7 +98,9 @@ static struct radeon_asic r100_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = NULL,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = NULL,
        .set_memory_clock = NULL,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -148,7 +153,9 @@ static struct radeon_asic r300_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = NULL,
        .set_memory_clock = NULL,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -185,7 +192,9 @@ static struct radeon_asic r420_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -227,7 +236,9 @@ static struct radeon_asic rs400_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = NULL,
        .set_memory_clock = NULL,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -273,7 +284,9 @@ static struct radeon_asic rs600_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -312,7 +325,9 @@ static struct radeon_asic rs690_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r300_copy_dma,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -357,7 +372,9 @@ static struct radeon_asic rv515_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -393,7 +410,9 @@ static struct radeon_asic r520_asic = {
        .copy_blit = &r100_copy_blit,
        .copy_dma = &r300_copy_dma,
        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = &rv370_set_pcie_lanes,
        .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -456,7 +475,9 @@ static struct radeon_asic r600_asic = {
        .copy_blit = &r600_copy_blit,
        .copy_dma = &r600_copy_blit,
        .copy = &r600_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -493,7 +514,9 @@ static struct radeon_asic rv770_asic = {
        .copy_blit = &r600_copy_blit,
        .copy_dma = &r600_copy_blit,
        .copy = &r600_copy_blit,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
        .set_memory_clock = &radeon_atom_set_memory_clock,
        .set_pcie_lanes = NULL,
        .set_clock_gating = &radeon_atom_set_clock_gating,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5b6c08cee40e..2ed88a820935 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -46,7 +46,8 @@ radeon_add_atom_connector(struct drm_device *dev,
                          uint32_t supported_device,
                          int connector_type,
                          struct radeon_i2c_bus_rec *i2c_bus,
-                          bool linkb, uint32_t igp_lane_info);
+                          bool linkb, uint32_t igp_lane_info,
+                          uint16_t connector_object_id);
 /* from radeon_legacy_encoder.c */
 extern void
@@ -193,6 +194,23 @@ const int supported_devices_connector_convert[] = {
        DRM_MODE_CONNECTOR_DisplayPort
 };
+const uint16_t supported_devices_connector_object_id_convert[] = {
+        CONNECTOR_OBJECT_ID_NONE,
+        CONNECTOR_OBJECT_ID_VGA,
+        CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
+        CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
+        CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
+        CONNECTOR_OBJECT_ID_COMPOSITE,
+        CONNECTOR_OBJECT_ID_SVIDEO,
+        CONNECTOR_OBJECT_ID_LVDS,
+        CONNECTOR_OBJECT_ID_9PIN_DIN,
+        CONNECTOR_OBJECT_ID_9PIN_DIN,
+        CONNECTOR_OBJECT_ID_DISPLAYPORT,
+        CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
+        CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
+        CONNECTOR_OBJECT_ID_SVIDEO
+};
 const int object_connector_convert[] = {
        DRM_MODE_CONNECTOR_Unknown,
        DRM_MODE_CONNECTOR_DVII,
@@ -229,7 +247,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
        ATOM_OBJECT_HEADER *obj_header;
        int i, j, path_size, device_support;
        int connector_type;
-        uint16_t igp_lane_info, conn_id;
+        uint16_t igp_lane_info, conn_id, connector_object_id;
        bool linkb;
        struct radeon_i2c_bus_rec ddc_bus;
@@ -277,7 +295,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                ATOM_DEVICE_CV_SUPPORT)
                                continue;
-                        if ((rdev->family == CHIP_RS780) &&
+                        /* IGP chips */
+                        if ((rdev->flags & RADEON_IS_IGP) &&
                            (con_obj_id ==
                             CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
                                uint16_t igp_offset = 0;
@@ -311,6 +330,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                                connector_type =
                                                    object_connector_convert
                                                    [ct];
+                                                connector_object_id = ct;
                                                igp_lane_info =
                                                    slot_config & 0xffff;
                                        } else
@@ -321,6 +341,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                igp_lane_info = 0;
                                connector_type =
                                    object_connector_convert[con_obj_id];
+                                connector_object_id = con_obj_id;
                        }
                        if (connector_type == DRM_MODE_CONNECTOR_Unknown)
@@ -425,7 +446,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                                  le16_to_cpu(path->
                                                              usDeviceTag),
                                                  connector_type, &ddc_bus,
-                                                  linkb, igp_lane_info);
+                                                  linkb, igp_lane_info,
+                                                  connector_object_id);
                }
        }
@@ -435,6 +457,45 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
        return true;
 }
+static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
+                                                 int connector_type,
+                                                 uint16_t devices)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        if (rdev->flags & RADEON_IS_IGP) {
+                return supported_devices_connector_object_id_convert
+                        [connector_type];
+        } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
+                    (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
+                   (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
+                struct radeon_mode_info *mode_info = &rdev->mode_info;
+                struct atom_context *ctx = mode_info->atom_context;
+                int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
+                uint16_t size, data_offset;
+                uint8_t frev, crev;
+                ATOM_XTMDS_INFO *xtmds;
+                atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+                xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
+                if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
+                        if (connector_type == DRM_MODE_CONNECTOR_DVII)
+                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
+                        else
+                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
+                } else {
+                        if (connector_type == DRM_MODE_CONNECTOR_DVII)
+                                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
+                        else
+                                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
+                }
+        } else {
+                return supported_devices_connector_object_id_convert
+                        [connector_type];
+        }
+}
 struct bios_connector {
        bool valid;
        uint16_t line_mux;
@@ -593,14 +654,20 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
        /* add the connectors */
        for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
-                if (bios_connectors[i].valid)
+                if (bios_connectors[i].valid) {
+                        uint16_t connector_object_id =
+                                atombios_get_connector_object_id(dev,
+                                                      bios_connectors[i].connector_type,
+                                                      bios_connectors[i].devices);
                        radeon_add_atom_connector(dev,
                                                  bios_connectors[i].line_mux,
                                                  bios_connectors[i].devices,
                                                  bios_connectors[i].
                                                  connector_type,
                                                  &bios_connectors[i].ddc_bus,
-                                                  false, 0);
+                                                  false, 0,
+                                                  connector_object_id);
+                }
        }
        radeon_link_encoder_connector(dev);
@@ -641,8 +708,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                    le16_to_cpu(firmware_info->info.usReferenceClock);
                p1pll->reference_div = 0;
-                p1pll->pll_out_min =
+                if (crev < 2)
-                    le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
+                        p1pll->pll_out_min =
+                                le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
+                else
+                        p1pll->pll_out_min =
+                                le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
                p1pll->pll_out_max =
                    le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
@@ -651,6 +722,16 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                                p1pll->pll_out_min = 64800;
                        else
                                p1pll->pll_out_min = 20000;
+                } else if (p1pll->pll_out_min > 64800) {
+                        /* Limiting the pll output range is a good thing generally as
+                         * it limits the number of possible pll combinations for a given
+                         * frequency presumably to the ones that work best on each card.
+                         * However, certain duallink DVI monitors seem to like
+                         * pll combinations that would be limited by this at least on
+                         * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
+                         * family.
+                         */
+                        p1pll->pll_out_min = 64800;
                }
                p1pll->pll_in_min =
@@ -767,6 +848,46 @@ bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
        return false;
 }
+static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
+                                                          radeon_encoder
+                                                          *encoder,
+                                                          int id)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
+        uint16_t data_offset;
+        struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
+        uint8_t frev, crev;
+        struct radeon_atom_ss *ss = NULL;
+        if (id > ATOM_MAX_SS_ENTRY)
+                return NULL;
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+                               &crev, &data_offset);
+        ss_info =
+            (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
+        if (ss_info) {
+                ss =
+                    kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
+                if (!ss)
+                        return NULL;
+                ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
+                ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
+                ss->step = ss_info->asSS_Info[id].ucSS_Step;
+                ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
+                ss->range = ss_info->asSS_Info[id].ucSS_Range;
+                ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
+        }
+        return ss;
+}
 union lvds_info {
        struct _ATOM_LVDS_INFO info;
        struct _ATOM_LVDS_INFO_V12 info_12;
@@ -798,27 +919,31 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
                if (!lvds)
                        return NULL;
-                lvds->native_mode.dotclock =
+                lvds->native_mode.clock =
                    le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
-                lvds->native_mode.panel_xres =
+                lvds->native_mode.hdisplay =
                    le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
-                lvds->native_mode.panel_yres =
+                lvds->native_mode.vdisplay =
                    le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
-                lvds->native_mode.hblank =
+                lvds->native_mode.htotal = lvds->native_mode.hdisplay +
-                    le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
+                        le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
-                lvds->native_mode.hoverplus =
+                lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
-                    le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
+                        le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
-                lvds->native_mode.hsync_width =
+                lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
-                    le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
+                        le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
-                lvds->native_mode.vblank =
+                lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
-                    le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
+                        le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
-                lvds->native_mode.voverplus =
+                lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
-                    le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
+                        le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
-                lvds->native_mode.vsync_width =
+                lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
-                    le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
+                        le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
                lvds->panel_pwr_delay =
                    le16_to_cpu(lvds_info->info.usOffDelayInMs);
                lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
+                /* set crtc values */
+                drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
+                lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
                encoder->native_mode = lvds->native_mode;
        }
@@ -857,8 +982,7 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
 }
 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
-                                SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
+                                struct drm_display_mode *mode)
-                                int32_t *pixel_clock)
 {
        struct radeon_mode_info *mode_info = &rdev->mode_info;
        ATOM_ANALOG_TV_INFO *tv_info;
@@ -866,7 +990,7 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
        ATOM_DTD_FORMAT *dtd_timings;
        int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
        u8 frev, crev;
-        uint16_t data_offset;
+        u16 data_offset, misc;
        atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
@@ -876,28 +1000,37 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
                if (index > MAX_SUPPORTED_TV_TIMING)
                        return false;
-                crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
+                mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
-                crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
+                mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
-                crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
+                mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
-                crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
+                mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
+                        le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
-                crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
-                crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
+                mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
-                crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
+                mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
-                crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
+                mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
+                mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
-                crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
+                        le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
-                crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
+                mode->flags = 0;
-                crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
+                misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
-                crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
+                if (misc & ATOM_VSYNC_POLARITY)
-                crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
+                        mode->flags |= DRM_MODE_FLAG_NVSYNC;
-                *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
+                if (misc & ATOM_HSYNC_POLARITY)
+                        mode->flags |= DRM_MODE_FLAG_NHSYNC;
+                if (misc & ATOM_COMPOSITESYNC)
+                        mode->flags |= DRM_MODE_FLAG_CSYNC;
+                if (misc & ATOM_INTERLACE)
+                        mode->flags |= DRM_MODE_FLAG_INTERLACE;
+                if (misc & ATOM_DOUBLE_CLOCK_MODE)
+                        mode->flags |= DRM_MODE_FLAG_DBLSCAN;
+                mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
                if (index == 1) {
                        /* PAL timings appear to have wrong values for totals */
-                        crtc_timing->usH_Total -= 1;
+                        mode->crtc_htotal -= 1;
-                        crtc_timing->usV_Total -= 1;
+                        mode->crtc_vtotal -= 1;
                }
                break;
        case 2:
@@ -906,17 +1039,36 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
                        return false;
                dtd_timings = &tv_info_v1_2->aModeTimings[index];
-                crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
+                mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
-                crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
+                        le16_to_cpu(dtd_timings->usHBlanking_Time);
-                crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
+                mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
-                crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
+                mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
-                crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
+                        le16_to_cpu(dtd_timings->usHSyncOffset);
-                crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
+                mode->crtc_hsync_end = mode->crtc_hsync_start +
-                crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
+                        le16_to_cpu(dtd_timings->usHSyncWidth);
-                crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
+                mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
-                crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
+                        le16_to_cpu(dtd_timings->usVBlanking_Time);
-                *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
+                mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
+                mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
+                        le16_to_cpu(dtd_timings->usVSyncOffset);
+                mode->crtc_vsync_end = mode->crtc_vsync_start +
+                        le16_to_cpu(dtd_timings->usVSyncWidth);
+                mode->flags = 0;
+                misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
+                if (misc & ATOM_VSYNC_POLARITY)
+                        mode->flags |= DRM_MODE_FLAG_NVSYNC;
+                if (misc & ATOM_HSYNC_POLARITY)
+                        mode->flags |= DRM_MODE_FLAG_NHSYNC;
+                if (misc & ATOM_COMPOSITESYNC)
+                        mode->flags |= DRM_MODE_FLAG_CSYNC;
+                if (misc & ATOM_INTERLACE)
+                        mode->flags |= DRM_MODE_FLAG_INTERLACE;
+                if (misc & ATOM_DOUBLE_CLOCK_MODE)
+                        mode->flags |= DRM_MODE_FLAG_DBLSCAN;
+                mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
                break;
        }
        return true;
@@ -981,6 +1133,24 @@ void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
+uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
+{
+        GET_ENGINE_CLOCK_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+        return args.ulReturnEngineClock;
+}
+uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
+{
+        GET_MEMORY_CLOCK_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+        return args.ulReturnMemoryClock;
+}
 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
                                  uint32_t eng_clock)
 {
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 2e938f7496fb..10bd50a7db87 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -63,7 +63,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
                if (r) {
                        goto out_cleanup;
                }
-                r = radeon_copy_dma(rdev, saddr, daddr, size / 4096, fence);
+                r = radeon_copy_dma(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence);
                if (r) {
                        goto out_cleanup;
                }
@@ -88,7 +88,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
                if (r) {
                        goto out_cleanup;
                }
-                r = radeon_copy_blit(rdev, saddr, daddr, size / 4096, fence);
+                r = radeon_copy_blit(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence);
                if (r) {
                        goto out_cleanup;
                }
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 34a9b9119518..906921740c60 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -50,19 +50,16 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
        vram_base = drm_get_resource_start(rdev->ddev, 0);
        bios = ioremap(vram_base, size);
        if (!bios) {
-                DRM_ERROR("Unable to mmap vram\n");
                return false;
        }
        if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
                iounmap(bios);
-                DRM_ERROR("bad rom signature\n");
                return false;
        }
        rdev->bios = kmalloc(size, GFP_KERNEL);
        if (rdev->bios == NULL) {
                iounmap(bios);
-                DRM_ERROR("kmalloc failed\n");
                return false;
        }
        memcpy(rdev->bios, bios, size);
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index f5c32a766b10..a81354167621 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -32,7 +32,7 @@
 #include "atom.h"
 /* 10 khz */
-static uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
+uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
 {
        struct radeon_pll *spll = &rdev->clock.spll;
        uint32_t fb_div, ref_div, post_div, sclk;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 748265a105b3..5253cbf6db1f 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -49,7 +49,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
                            uint32_t connector_id,
                            uint32_t supported_device,
                            int connector_type,
-                            struct radeon_i2c_bus_rec *i2c_bus);
+                            struct radeon_i2c_bus_rec *i2c_bus,
+                            uint16_t connector_object_id);
 /* from radeon_legacy_encoder.c */
 extern void
@@ -808,25 +809,25 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
        lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
        if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
-                lvds->native_mode.panel_yres =
+                lvds->native_mode.vdisplay =
                    ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
                     RADEON_VERT_PANEL_SHIFT) + 1;
        else
-                lvds->native_mode.panel_yres =
+                lvds->native_mode.vdisplay =
                    (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
        if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
-                lvds->native_mode.panel_xres =
+                lvds->native_mode.hdisplay =
                    (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
                      RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
        else
-                lvds->native_mode.panel_xres =
+                lvds->native_mode.hdisplay =
                    ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
-        if ((lvds->native_mode.panel_xres < 640) ||
+        if ((lvds->native_mode.hdisplay < 640) ||
-            (lvds->native_mode.panel_yres < 480)) {
+            (lvds->native_mode.vdisplay < 480)) {
-                lvds->native_mode.panel_xres = 640;
+                lvds->native_mode.hdisplay = 640;
-                lvds->native_mode.panel_yres = 480;
+                lvds->native_mode.vdisplay = 480;
        }
        ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
@@ -846,8 +847,8 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
        lvds->panel_vcc_delay = 200;
        DRM_INFO("Panel info derived from registers\n");
-        DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
+        DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
-                 lvds->native_mode.panel_yres);
+                 lvds->native_mode.vdisplay);
        return lvds;
 }
@@ -882,11 +883,11 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
                DRM_INFO("Panel ID String: %s\n", stmp);
-                lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
+                lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
-                lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
+                lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
-                DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
+                DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
-                         lvds->native_mode.panel_yres);
+                         lvds->native_mode.vdisplay);
                lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
                if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
@@ -944,27 +945,25 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
                        if (tmp == 0)
                                break;
-                        if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
+                        if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
                            (RBIOS16(tmp + 2) ==
-                             lvds->native_mode.panel_yres)) {
+                             lvds->native_mode.vdisplay)) {
-                                lvds->native_mode.hblank =
+                                lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
-                                    (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
+                                lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
-                                lvds->native_mode.hoverplus =
+                                lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
-                                    (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
+                                                               RBIOS16(tmp + 21)) * 8;
-                                     1) * 8;
-                                lvds->native_mode.hsync_width =
+                                lvds->native_mode.vtotal = RBIOS16(tmp + 24);
-                                    RBIOS8(tmp + 23) * 8;
+                                lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
+                                lvds->native_mode.vsync_end =
-                                lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
+                                        ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
-                                                            RBIOS16(tmp + 26));
+                                        (RBIOS16(tmp + 28) & 0x7ff);
-                                lvds->native_mode.voverplus =
-                                    ((RBIOS16(tmp + 28) & 0x7ff) -
+                                lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
-                                     RBIOS16(tmp + 26));
-                                lvds->native_mode.vsync_width =
-                                    ((RBIOS16(tmp + 28) & 0xf800) >> 11);
-                                lvds->native_mode.dotclock =
-                                    RBIOS16(tmp + 9) * 10;
                                lvds->native_mode.flags = 0;
+                                /* set crtc values */
+                                drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
                        }
                }
        } else {
@@ -1178,7 +1177,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                        radeon_add_legacy_connector(dev, 0,
                                                    ATOM_DEVICE_CRT1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_VGA,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_VGA);
                } else if (rdev->flags & RADEON_IS_MOBILITY) {
                        /* LVDS */
                        ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
@@ -1190,7 +1190,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                        radeon_add_legacy_connector(dev, 0,
                                                    ATOM_DEVICE_LCD1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_LVDS,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_LVDS);
                        /* VGA - primary dac */
                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
@@ -1202,7 +1203,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                        radeon_add_legacy_connector(dev, 1,
                                                    ATOM_DEVICE_CRT1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_VGA,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_VGA);
                } else {
                        /* DVI-I - tv dac, int tmds */
                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
@@ -1220,7 +1222,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                    ATOM_DEVICE_DFP1_SUPPORT |
                                                    ATOM_DEVICE_CRT2_SUPPORT,
                                                    DRM_MODE_CONNECTOR_DVII,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
                        /* VGA - primary dac */
                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
@@ -1232,7 +1235,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                        radeon_add_legacy_connector(dev, 1,
                                                    ATOM_DEVICE_CRT1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_VGA,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_VGA);
                }
                if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
@@ -1245,7 +1249,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                        radeon_add_legacy_connector(dev, 2,
                                                    ATOM_DEVICE_TV1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_SVIDEO,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_SVIDEO);
                }
                break;
        case CT_IBOOK:
@@ -1259,7 +1264,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                0),
                                          ATOM_DEVICE_LCD1_SUPPORT);
                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_LVDS);
                /* VGA - TV DAC */
                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
                radeon_add_legacy_encoder(dev,
@@ -1268,7 +1274,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                2),
                                          ATOM_DEVICE_CRT2_SUPPORT);
                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
-                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1277,7 +1284,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_POWERBOOK_EXTERNAL:
                DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
@@ -1290,7 +1298,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                0),
                                          ATOM_DEVICE_LCD1_SUPPORT);
                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_LVDS);
                /* DVI-I - primary dac, ext tmds */
                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
                radeon_add_legacy_encoder(dev,
@@ -1303,10 +1312,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                ATOM_DEVICE_CRT1_SUPPORT,
                                                                1),
                                          ATOM_DEVICE_CRT1_SUPPORT);
+                /* XXX some are SL */
                radeon_add_legacy_connector(dev, 1,
                                            ATOM_DEVICE_DFP2_SUPPORT |
                                            ATOM_DEVICE_CRT1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1315,7 +1326,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_POWERBOOK_INTERNAL:
                DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
@@ -1328,7 +1340,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                0),
                                          ATOM_DEVICE_LCD1_SUPPORT);
                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_LVDS);
                /* DVI-I - primary dac, int tmds */
                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
                radeon_add_legacy_encoder(dev,
@@ -1344,7 +1357,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                radeon_add_legacy_connector(dev, 1,
                                            ATOM_DEVICE_DFP1_SUPPORT |
                                            ATOM_DEVICE_CRT1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1353,7 +1367,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_POWERBOOK_VGA:
                DRM_INFO("Connector Table: %d (powerbook vga)\n",
@@ -1366,7 +1381,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                0),
                                          ATOM_DEVICE_LCD1_SUPPORT);
                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_LVDS);
                /* VGA - primary dac */
                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
                radeon_add_legacy_encoder(dev,
@@ -1375,7 +1391,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                1),
                                          ATOM_DEVICE_CRT1_SUPPORT);
                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1384,7 +1401,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_MINI_EXTERNAL:
                DRM_INFO("Connector Table: %d (mini external tmds)\n",
@@ -1401,10 +1419,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                ATOM_DEVICE_CRT2_SUPPORT,
                                                                2),
                                          ATOM_DEVICE_CRT2_SUPPORT);
+                /* XXX are any DL? */
                radeon_add_legacy_connector(dev, 0,
                                            ATOM_DEVICE_DFP2_SUPPORT |
                                            ATOM_DEVICE_CRT2_SUPPORT,
-                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1413,7 +1433,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_MINI_INTERNAL:
                DRM_INFO("Connector Table: %d (mini internal tmds)\n",
@@ -1433,7 +1454,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                radeon_add_legacy_connector(dev, 0,
                                            ATOM_DEVICE_DFP1_SUPPORT |
                                            ATOM_DEVICE_CRT2_SUPPORT,
-                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1442,7 +1464,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_IMAC_G5_ISIGHT:
                DRM_INFO("Connector Table: %d (imac g5 isight)\n",
@@ -1455,7 +1478,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                0),
                                          ATOM_DEVICE_DFP1_SUPPORT);
                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
                /* VGA - tv dac */
                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
                radeon_add_legacy_encoder(dev,
@@ -1464,7 +1488,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                2),
                                          ATOM_DEVICE_CRT2_SUPPORT);
                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
-                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1473,7 +1498,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        case CT_EMAC:
                DRM_INFO("Connector Table: %d (emac)\n",
@@ -1486,7 +1512,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                1),
                                          ATOM_DEVICE_CRT1_SUPPORT);
                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
-                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA);
                /* VGA - tv dac */
                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
                radeon_add_legacy_encoder(dev,
@@ -1495,7 +1522,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                                                2),
                                          ATOM_DEVICE_CRT2_SUPPORT);
                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
-                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA);
                /* TV - TV DAC */
                radeon_add_legacy_encoder(dev,
                                          radeon_get_encoder_id(dev,
@@ -1504,7 +1532,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                          ATOM_DEVICE_TV1_SUPPORT);
                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
                                            DRM_MODE_CONNECTOR_SVIDEO,
-                                            &ddc_i2c);
+                                            &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SVIDEO);
                break;
        default:
                DRM_INFO("Connector table: %d (invalid)\n",
@@ -1581,11 +1610,63 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
        return true;
 }
+static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
+{
+        /* Acer 5102 has non-existent TV port */
+        if (dev->pdev->device == 0x5975 &&
+            dev->pdev->subsystem_vendor == 0x1025 &&
+            dev->pdev->subsystem_device == 0x009f)
+                return false;
+        /* HP dc5750 has non-existent TV port */
+        if (dev->pdev->device == 0x5974 &&
+            dev->pdev->subsystem_vendor == 0x103c &&
+            dev->pdev->subsystem_device == 0x280a)
+                return false;
+        return true;
+}
+static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t ext_tmds_info;
+        if (rdev->flags & RADEON_IS_IGP) {
+                if (is_dvi_d)
+                        return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
+                else
+                        return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
+        }
+        ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
+        if (ext_tmds_info) {
+                uint8_t rev = RBIOS8(ext_tmds_info);
+                uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
+                if (rev >= 3) {
+                        if (is_dvi_d)
+                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
+                        else
+                                return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
+                } else {
+                        if (flags & 1) {
+                                if (is_dvi_d)
+                                        return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
+                                else
+                                        return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
+                        }
+                }
+        }
+        if (is_dvi_d)
+                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
+        else
+                return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
+}
 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
 {
        struct radeon_device *rdev = dev->dev_private;
        uint32_t conn_info, entry, devices;
-        uint16_t tmp;
+        uint16_t tmp, connector_object_id;
        enum radeon_combios_ddc ddc_type;
        enum radeon_combios_connector connector;
        int i = 0;
@@ -1628,8 +1709,9 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                break;
                        }
-                        radeon_apply_legacy_quirks(dev, i, &connector,
+                        if (!radeon_apply_legacy_quirks(dev, i, &connector,
-                                                   &ddc_i2c);
+                                                       &ddc_i2c))
+                                continue;
                        switch (connector) {
                        case CONNECTOR_PROPRIETARY_LEGACY:
@@ -1644,7 +1726,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                radeon_add_legacy_connector(dev, i, devices,
                                                            legacy_connector_convert
                                                            [connector],
-                                                            &ddc_i2c);
+                                                            &ddc_i2c,
+                                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
                                break;
                        case CONNECTOR_CRT_LEGACY:
                                if (tmp & 0x1) {
@@ -1669,7 +1752,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                                            devices,
                                                            legacy_connector_convert
                                                            [connector],
-                                                            &ddc_i2c);
+                                                            &ddc_i2c,
+                                                            CONNECTOR_OBJECT_ID_VGA);
                                break;
                        case CONNECTOR_DVI_I_LEGACY:
                                devices = 0;
@@ -1698,6 +1782,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                                                   ATOM_DEVICE_DFP2_SUPPORT,
                                                                   0),
                                                                  ATOM_DEVICE_DFP2_SUPPORT);
+                                        connector_object_id = combios_check_dl_dvi(dev, 0);
                                } else {
                                        devices |= ATOM_DEVICE_DFP1_SUPPORT;
                                        radeon_add_legacy_encoder(dev,
@@ -1706,19 +1791,24 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                                                   ATOM_DEVICE_DFP1_SUPPORT,
                                                                   0),
                                                                  ATOM_DEVICE_DFP1_SUPPORT);
+                                        connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
                                }
                                radeon_add_legacy_connector(dev,
                                                            i,
                                                            devices,
                                                            legacy_connector_convert
                                                            [connector],
-                                                            &ddc_i2c);
+                                                            &ddc_i2c,
+                                                            connector_object_id);
                                break;
                        case CONNECTOR_DVI_D_LEGACY:
-                                if ((tmp >> 4) & 0x1)
+                                if ((tmp >> 4) & 0x1) {
                                        devices = ATOM_DEVICE_DFP2_SUPPORT;
-                                else
+                                        connector_object_id = combios_check_dl_dvi(dev, 1);
+                                } else {
                                        devices = ATOM_DEVICE_DFP1_SUPPORT;
+                                        connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
+                                }
                                radeon_add_legacy_encoder(dev,
                                                          radeon_get_encoder_id
                                                          (dev, devices, 0),
@@ -1726,7 +1816,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                radeon_add_legacy_connector(dev, i, devices,
                                                            legacy_connector_convert
                                                            [connector],
-                                                            &ddc_i2c);
+                                                            &ddc_i2c,
+                                                            connector_object_id);
                                break;
                        case CONNECTOR_CTV_LEGACY:
                        case CONNECTOR_STV_LEGACY:
@@ -1740,7 +1831,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                                            ATOM_DEVICE_TV1_SUPPORT,
                                                            legacy_connector_convert
                                                            [connector],
-                                                            &ddc_i2c);
+                                                            &ddc_i2c,
+                                                            CONNECTOR_OBJECT_ID_SVIDEO);
                                break;
                        default:
                                DRM_ERROR("Unknown connector type: %d\n",
@@ -1772,10 +1864,29 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                                    ATOM_DEVICE_CRT1_SUPPORT |
                                                    ATOM_DEVICE_DFP1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_DVII,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
                } else {
-                        DRM_DEBUG("No connector info found\n");
+                        uint16_t crt_info =
-                        return false;
+                                combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
+                        DRM_DEBUG("Found CRT table, assuming VGA connector\n");
+                        if (crt_info) {
+                                radeon_add_legacy_encoder(dev,
+                                                          radeon_get_encoder_id(dev,
+                                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                                1),
+                                                          ATOM_DEVICE_CRT1_SUPPORT);
+                                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                                radeon_add_legacy_connector(dev,
+                                                            0,
+                                                            ATOM_DEVICE_CRT1_SUPPORT,
+                                                            DRM_MODE_CONNECTOR_VGA,
+                                                            &ddc_i2c,
+                                                            CONNECTOR_OBJECT_ID_VGA);
+                        } else {
+                                DRM_DEBUG("No connector info found\n");
+                                return false;
+                        }
                }
        }
@@ -1870,7 +1981,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                                                    5,
                                                    ATOM_DEVICE_LCD1_SUPPORT,
                                                    DRM_MODE_CONNECTOR_LVDS,
-                                                    &ddc_i2c);
+                                                    &ddc_i2c,
+                                                    CONNECTOR_OBJECT_ID_LVDS);
                }
        }
@@ -1880,16 +1992,19 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
                    combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
                if (tv_info) {
                        if (RBIOS8(tv_info + 6) == 'T') {
-                                radeon_add_legacy_encoder(dev,
+                                if (radeon_apply_legacy_tv_quirks(dev)) {
-                                                          radeon_get_encoder_id
+                                        radeon_add_legacy_encoder(dev,
-                                                          (dev,
+                                                                  radeon_get_encoder_id
-                                                           ATOM_DEVICE_TV1_SUPPORT,
+                                                                  (dev,
-                                                           2),
+                                                                   ATOM_DEVICE_TV1_SUPPORT,
-                                                          ATOM_DEVICE_TV1_SUPPORT);
+                                                                   2),
-                                radeon_add_legacy_connector(dev, 6,
+                                                                  ATOM_DEVICE_TV1_SUPPORT);
-                                                            ATOM_DEVICE_TV1_SUPPORT,
+                                        radeon_add_legacy_connector(dev, 6,
-                                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                                                    ATOM_DEVICE_TV1_SUPPORT,
-                                                            &ddc_i2c);
+                                                                    DRM_MODE_CONNECTOR_SVIDEO,
+                                                                    &ddc_i2c,
+                                                                    CONNECTOR_OBJECT_ID_SVIDEO);
+                                }
                        }
                }
        }
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index e376be47a4a0..29763ceae3af 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -178,25 +178,12 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
        struct drm_device *dev = encoder->dev;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        struct drm_display_mode *mode = NULL;
-        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+        struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
-        if (native_mode->panel_xres != 0 &&
-            native_mode->panel_yres != 0 &&
-            native_mode->dotclock != 0) {
-                mode = drm_mode_create(dev);
-                mode->hdisplay = native_mode->panel_xres;
-                mode->vdisplay = native_mode->panel_yres;
-                mode->htotal = mode->hdisplay + native_mode->hblank;
-                mode->hsync_start = mode->hdisplay + native_mode->hoverplus;
-                mode->hsync_end = mode->hsync_start + native_mode->hsync_width;
-                mode->vtotal = mode->vdisplay + native_mode->vblank;
-                mode->vsync_start = mode->vdisplay + native_mode->voverplus;
-                mode->vsync_end = mode->vsync_start + native_mode->vsync_width;
-                mode->clock = native_mode->dotclock;
-                mode->flags = 0;
+        if (native_mode->hdisplay != 0 &&
+            native_mode->vdisplay != 0 &&
+            native_mode->clock != 0) {
+                mode = drm_mode_duplicate(dev, native_mode);
                mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
                drm_mode_set_name(mode);
@@ -210,7 +197,7 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
        struct drm_device *dev = encoder->dev;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        struct drm_display_mode *mode = NULL;
-        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+        struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
        int i;
        struct mode_size {
                int w;
@@ -236,11 +223,16 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
        };
        for (i = 0; i < 17; i++) {
+                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
+                        if (common_modes[i].w > 1024 ||
+                            common_modes[i].h > 768)
+                                continue;
+                }
                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
-                        if (common_modes[i].w > native_mode->panel_xres ||
+                        if (common_modes[i].w > native_mode->hdisplay ||
-                            common_modes[i].h > native_mode->panel_yres ||
+                            common_modes[i].h > native_mode->vdisplay ||
-                            (common_modes[i].w == native_mode->panel_xres &&
+                            (common_modes[i].w == native_mode->hdisplay &&
-                             common_modes[i].h == native_mode->panel_yres))
+                             common_modes[i].h == native_mode->vdisplay))
                                continue;
                }
                if (common_modes[i].w < 320 || common_modes[i].h < 200)
@@ -344,28 +336,23 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
                                          struct drm_connector *connector)
 {
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+        struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
        /* Try to get native mode details from EDID if necessary */
-        if (!native_mode->dotclock) {
+        if (!native_mode->clock) {
                struct drm_display_mode *t, *mode;
                list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
-                        if (mode->hdisplay == native_mode->panel_xres &&
+                        if (mode->hdisplay == native_mode->hdisplay &&
-                            mode->vdisplay == native_mode->panel_yres) {
+                            mode->vdisplay == native_mode->vdisplay) {
-                                native_mode->hblank = mode->htotal - mode->hdisplay;
+                                *native_mode = *mode;
-                                native_mode->hoverplus = mode->hsync_start - mode->hdisplay;
+                                drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
-                                native_mode->hsync_width = mode->hsync_end - mode->hsync_start;
-                                native_mode->vblank = mode->vtotal - mode->vdisplay;
-                                native_mode->voverplus = mode->vsync_start - mode->vdisplay;
-                                native_mode->vsync_width = mode->vsync_end - mode->vsync_start;
-                                native_mode->dotclock = mode->clock;
                                DRM_INFO("Determined LVDS native mode details from EDID\n");
                                break;
                        }
                }
        }
-        if (!native_mode->dotclock) {
+        if (!native_mode->clock) {
                DRM_INFO("No LVDS native mode details, disabling RMX\n");
                radeon_encoder->rmx_type = RMX_OFF;
        }
@@ -410,13 +397,64 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
 static int radeon_lvds_mode_valid(struct drm_connector *connector,
                                  struct drm_display_mode *mode)
 {
+        struct drm_encoder *encoder = radeon_best_single_encoder(connector);
+        if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
+                return MODE_PANEL;
+        if (encoder) {
+                struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+                struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
+                /* AVIVO hardware supports downscaling modes larger than the panel
+                 * to the panel size, but I'm not sure this is desirable.
+                 */
+                if ((mode->hdisplay > native_mode->hdisplay) ||
+                    (mode->vdisplay > native_mode->vdisplay))
+                        return MODE_PANEL;
+                /* if scaling is disabled, block non-native modes */
+                if (radeon_encoder->rmx_type == RMX_OFF) {
+                        if ((mode->hdisplay != native_mode->hdisplay) ||
+                            (mode->vdisplay != native_mode->vdisplay))
+                                return MODE_PANEL;
+                }
+        }
        return MODE_OK;
 }
 static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector)
 {
-        enum drm_connector_status ret = connector_status_connected;
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        struct drm_encoder *encoder = radeon_best_single_encoder(connector);
+        enum drm_connector_status ret = connector_status_disconnected;
+        if (encoder) {
+                struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+                struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
+                /* check if panel is valid */
+                if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
+                        ret = connector_status_connected;
+        }
+        /* check for edid as well */
+        if (radeon_connector->edid)
+                ret = connector_status_connected;
+        else {
+                if (radeon_connector->ddc_bus) {
+                        radeon_i2c_do_lock(radeon_connector, 1);
+                        radeon_connector->edid = drm_get_edid(&radeon_connector->base,
+                                                              &radeon_connector->ddc_bus->adapter);
+                        radeon_i2c_do_lock(radeon_connector, 0);
+                        if (radeon_connector->edid)
+                                ret = connector_status_connected;
+                }
+        }
        /* check acpi lid status ??? */
        radeon_connector_update_scratch_regs(connector, ret);
        return ret;
 }
@@ -427,6 +465,8 @@ static void radeon_connector_destroy(struct drm_connector *connector)
        if (radeon_connector->ddc_bus)
                radeon_i2c_destroy(radeon_connector->ddc_bus);
+        if (radeon_connector->edid)
+                kfree(radeon_connector->edid);
        kfree(radeon_connector->con_priv);
        drm_sysfs_connector_remove(connector);
        drm_connector_cleanup(connector);
@@ -496,6 +536,8 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
 static int radeon_vga_mode_valid(struct drm_connector *connector,
                                  struct drm_display_mode *mode)
 {
+        /* XXX check mode bandwidth */
+        /* XXX verify against max DAC output frequency */
        return MODE_OK;
 }
@@ -514,9 +556,33 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
        radeon_i2c_do_lock(radeon_connector, 1);
        dret = radeon_ddc_probe(radeon_connector);
        radeon_i2c_do_lock(radeon_connector, 0);
-        if (dret)
+        if (dret) {
-                ret = connector_status_connected;
+                if (radeon_connector->edid) {
-        else {
+                        kfree(radeon_connector->edid);
+                        radeon_connector->edid = NULL;
+                }
+                radeon_i2c_do_lock(radeon_connector, 1);
+                radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+                radeon_i2c_do_lock(radeon_connector, 0);
+                if (!radeon_connector->edid) {
+                        DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
+                                        drm_get_connector_name(connector));
+                        ret = connector_status_connected;
+                } else {
+                        radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
+                        /* some oems have boards with separate digital and analog connectors
+                         * with a shared ddc line (often vga + hdmi)
+                         */
+                        if (radeon_connector->use_digital && radeon_connector->shared_ddc) {
+                                kfree(radeon_connector->edid);
+                                radeon_connector->edid = NULL;
+                                ret = connector_status_disconnected;
+                        } else
+                                ret = connector_status_connected;
+                }
+        } else {
                if (radeon_connector->dac_load_detect) {
                        encoder_funcs = encoder->helper_private;
                        ret = encoder_funcs->detect(encoder, connector);
@@ -570,6 +636,8 @@ static int radeon_tv_get_modes(struct drm_connector *connector)
 static int radeon_tv_mode_valid(struct drm_connector *connector,
                                struct drm_display_mode *mode)
 {
+        if ((mode->hdisplay > 1024) || (mode->vdisplay > 768))
+                return MODE_CLOCK_RANGE;
        return MODE_OK;
 }
@@ -644,20 +712,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
        dret = radeon_ddc_probe(radeon_connector);
        radeon_i2c_do_lock(radeon_connector, 0);
        if (dret) {
+                if (radeon_connector->edid) {
+                        kfree(radeon_connector->edid);
+                        radeon_connector->edid = NULL;
+                }
                radeon_i2c_do_lock(radeon_connector, 1);
                radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
                radeon_i2c_do_lock(radeon_connector, 0);
                if (!radeon_connector->edid) {
-                        DRM_ERROR("DDC responded but not EDID found for %s\n",
+                        DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
-                                  drm_get_connector_name(connector));
+                                        drm_get_connector_name(connector));
                } else {
                        radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
-                        /* if this isn't a digital monitor
+                        /* some oems have boards with separate digital and analog connectors
-                           then we need to make sure we don't have any
+                         * with a shared ddc line (often vga + hdmi)
-                           TV conflicts */
+                         */
-                        ret = connector_status_connected;
+                        if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) {
+                                kfree(radeon_connector->edid);
+                                radeon_connector->edid = NULL;
+                                ret = connector_status_disconnected;
+                        } else
+                                ret = connector_status_connected;
                }
        }
@@ -753,9 +830,27 @@ static void radeon_dvi_force(struct drm_connector *connector)
                radeon_connector->use_digital = true;
 }
+static int radeon_dvi_mode_valid(struct drm_connector *connector,
+                                  struct drm_display_mode *mode)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        /* XXX check mode bandwidth */
+        if (radeon_connector->use_digital && (mode->clock > 165000)) {
+                if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
+                    (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
+                    (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
+                        return MODE_OK;
+                else
+                        return MODE_CLOCK_HIGH;
+        }
+        return MODE_OK;
+}
 struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = {
        .get_modes = radeon_dvi_get_modes,
-        .mode_valid = radeon_vga_mode_valid,
+        .mode_valid = radeon_dvi_mode_valid,
        .best_encoder = radeon_dvi_encoder,
 };
@@ -775,13 +870,15 @@ radeon_add_atom_connector(struct drm_device *dev,
                          int connector_type,
                          struct radeon_i2c_bus_rec *i2c_bus,
                          bool linkb,
-                          uint32_t igp_lane_info)
+                          uint32_t igp_lane_info,
+                          uint16_t connector_object_id)
 {
        struct radeon_device *rdev = dev->dev_private;
        struct drm_connector *connector;
        struct radeon_connector *radeon_connector;
        struct radeon_connector_atom_dig *radeon_dig_connector;
        uint32_t subpixel_order = SubPixelNone;
+        bool shared_ddc = false;
        int ret;
        /* fixme - tv/cv/din */
@@ -795,6 +892,13 @@ radeon_add_atom_connector(struct drm_device *dev,
                        radeon_connector->devices |= supported_device;
                        return;
                }
+                if (radeon_connector->ddc_bus && i2c_bus->valid) {
+                        if (memcmp(&radeon_connector->ddc_bus->rec, i2c_bus,
+                                    sizeof(struct radeon_i2c_bus_rec)) == 0) {
+                                radeon_connector->shared_ddc = true;
+                                shared_ddc = true;
+                        }
+                }
        }
        radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
@@ -805,6 +909,8 @@ radeon_add_atom_connector(struct drm_device *dev,
        radeon_connector->connector_id = connector_id;
        radeon_connector->devices = supported_device;
+        radeon_connector->shared_ddc = shared_ddc;
+        radeon_connector->connector_object_id = connector_object_id;
        switch (connector_type) {
        case DRM_MODE_CONNECTOR_VGA:
                drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -956,7 +1062,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
                            uint32_t connector_id,
                            uint32_t supported_device,
                            int connector_type,
-                            struct radeon_i2c_bus_rec *i2c_bus)
+                            struct radeon_i2c_bus_rec *i2c_bus,
+                            uint16_t connector_object_id)
 {
        struct radeon_device *rdev = dev->dev_private;
        struct drm_connector *connector;
@@ -985,6 +1092,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
        radeon_connector->connector_id = connector_id;
        radeon_connector->devices = supported_device;
+        radeon_connector->connector_object_id = connector_object_id;
        switch (connector_type) {
        case DRM_MODE_CONNECTOR_VGA:
                drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -1042,6 +1150,13 @@ radeon_add_legacy_connector(struct drm_device *dev,
                        if (ret)
                                goto failed;
                        radeon_connector->dac_load_detect = true;
+                        /* RS400,RC410,RS480 chipset seems to report a lot
+                         * of false positive on load detect, we haven't yet
+                         * found a way to make load detect reliable on those
+                         * chipset, thus just disable it for TV.
+                         */
+                        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
+                                radeon_connector->dac_load_detect = false;
                        drm_connector_attach_property(&radeon_connector->base,
                                                      rdev->mode_info.load_detect_property,
                                                      1);
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index b13c79e38bc0..28772a37009c 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -109,9 +109,15 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct radeon_device *rdev = crtc->dev->dev_private;
-        if (ASIC_IS_AVIVO(rdev))
+        if (ASIC_IS_AVIVO(rdev)) {
+                if (rdev->family >= CHIP_RV770) {
+                        if (radeon_crtc->crtc_id)
+                                WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0);
+                        else
+                                WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0);
+                }
                WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
-        else {
+        } else {
                radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
                /* offset is from DISP(2)_BASE_ADDRESS */
                WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index df988142e6b0..41bb76fbe734 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -444,20 +444,24 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
        return r;
 }
-static struct card_info atom_card_info = {
-        .dev = NULL,
-        .reg_read = cail_reg_read,
-        .reg_write = cail_reg_write,
-        .mc_read = cail_mc_read,
-        .mc_write = cail_mc_write,
-        .pll_read = cail_pll_read,
-        .pll_write = cail_pll_write,
-};
 int radeon_atombios_init(struct radeon_device *rdev)
 {
-        atom_card_info.dev = rdev->ddev;
+        struct card_info *atom_card_info =
-        rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
+            kzalloc(sizeof(struct card_info), GFP_KERNEL);
+        if (!atom_card_info)
+                return -ENOMEM;
+        rdev->mode_info.atom_card_info = atom_card_info;
+        atom_card_info->dev = rdev->ddev;
+        atom_card_info->reg_read = cail_reg_read;
+        atom_card_info->reg_write = cail_reg_write;
+        atom_card_info->mc_read = cail_mc_read;
+        atom_card_info->mc_write = cail_mc_write;
+        atom_card_info->pll_read = cail_pll_read;
+        atom_card_info->pll_write = cail_pll_write;
+        rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
        radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
        return 0;
 }
@@ -465,6 +469,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
 void radeon_atombios_fini(struct radeon_device *rdev)
 {
        kfree(rdev->mode_info.atom_context);
+        kfree(rdev->mode_info.atom_card_info);
 }
 int radeon_combios_init(struct radeon_device *rdev)
@@ -683,6 +688,8 @@ int radeon_resume_kms(struct drm_device *dev)
                return -1;
        }
        pci_set_master(dev->pdev);
+        /* resume AGP if in use */
+        radeon_agp_resume(rdev);
        radeon_resume(rdev);
        radeon_restore_bios_scratch_regs(rdev);
        fb_set_suspend(rdev->fbdev_info, 0);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 3655d91993a6..c85df4afcb7a 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -137,9 +137,6 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
        if (size != 256) {
                return;
        }
-        if (crtc->fb == NULL) {
-                return;
-        }
        /* userspace palettes are always correct as is */
        for (i = 0; i < 256; i++) {
@@ -147,7 +144,6 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                radeon_crtc->lut_g[i] = green[i] >> 6;
                radeon_crtc->lut_b[i] = blue[i] >> 6;
        }
        radeon_crtc_load_lut(crtc);
 }
@@ -338,27 +334,19 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 {
-        struct edid *edid;
        int ret = 0;
        if (!radeon_connector->ddc_bus)
                return -1;
        if (!radeon_connector->edid) {
                radeon_i2c_do_lock(radeon_connector, 1);
-                edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+                radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
                radeon_i2c_do_lock(radeon_connector, 0);
-        } else
+        }
-                edid = radeon_connector->edid;
-        if (edid) {
+        if (radeon_connector->edid) {
-                /* update digital bits here */
+                drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
-                if (edid->input & DRM_EDID_INPUT_DIGITAL)
+                ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
-                        radeon_connector->use_digital = 1;
-                else
-                        radeon_connector->use_digital = 0;
-                drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
-                ret = drm_add_edid_modes(&radeon_connector->base, edid);
-                kfree(edid);
                return ret;
        }
        drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
@@ -765,7 +753,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
                        radeon_crtc->rmx_type = radeon_encoder->rmx_type;
                        memcpy(&radeon_crtc->native_mode,
                                &radeon_encoder->native_mode,
-                                sizeof(struct radeon_native_mode));
+                                sizeof(struct drm_display_mode));
                        first = false;
                } else {
                        if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
@@ -783,10 +771,10 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
        if (radeon_crtc->rmx_type != RMX_OFF) {
                fixed20_12 a, b;
                a.full = rfixed_const(crtc->mode.vdisplay);
-                b.full = rfixed_const(radeon_crtc->native_mode.panel_xres);
+                b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
                radeon_crtc->vsc.full = rfixed_div(a, b);
                a.full = rfixed_const(crtc->mode.hdisplay);
-                b.full = rfixed_const(radeon_crtc->native_mode.panel_yres);
+                b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
                radeon_crtc->hsc.full = rfixed_div(a, b);
        } else {
                radeon_crtc->vsc.full = rfixed_const(1);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index a65ab1a0dad2..d42bc512d75a 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -31,6 +31,10 @@
 extern int atom_debug;
+/* evil but including atombios.h is much worse */
+bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
+                                struct drm_display_mode *mode);
 uint32_t
 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
 {
@@ -167,49 +171,17 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
-        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+        struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
-        if (mode->hdisplay < native_mode->panel_xres ||
+        if (mode->hdisplay < native_mode->hdisplay ||
-            mode->vdisplay < native_mode->panel_yres) {
+            mode->vdisplay < native_mode->vdisplay) {
-                if (ASIC_IS_AVIVO(rdev)) {
+                int mode_id = adjusted_mode->base.id;
-                        adjusted_mode->hdisplay = native_mode->panel_xres;
+                *adjusted_mode = *native_mode;
-                        adjusted_mode->vdisplay = native_mode->panel_yres;
+                if (!ASIC_IS_AVIVO(rdev)) {
-                        adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
+                        adjusted_mode->hdisplay = mode->hdisplay;
-                        adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
+                        adjusted_mode->vdisplay = mode->vdisplay;
-                        adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
-                        adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
-                        adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
-                        adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
-                        /* update crtc values */
-                        drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
-                        /* adjust crtc values */
-                        adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
-                        adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
-                        adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
-                        adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
-                        adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
-                        adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
-                        adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
-                        adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
-                } else {
-                        adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
-                        adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
-                        adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
-                        adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
-                        adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
-                        adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
-                        /* update crtc values */
-                        drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
-                        /* adjust crtc values */
-                        adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
-                        adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
-                        adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
-                        adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
-                        adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
-                        adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
                }
-                adjusted_mode->flags = native_mode->flags;
+                adjusted_mode->base.id = mode_id;
-                adjusted_mode->clock = native_mode->dotclock;
        }
 }
@@ -219,7 +191,11 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
                                   struct drm_display_mode *adjusted_mode)
 {
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        /* set the active encoder to connector routing */
+        radeon_encoder_set_active_device(encoder);
        drm_mode_set_crtcinfo(adjusted_mode, 0);
        if (radeon_encoder->rmx_type != RMX_OFF)
@@ -230,6 +206,18 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
            && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
                adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
+        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
+                struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
+                if (tv_dac) {
+                        if (tv_dac->tv_std == TV_STD_NTSC ||
+                            tv_dac->tv_std == TV_STD_NTSC_J ||
+                            tv_dac->tv_std == TV_STD_PAL_M)
+                                radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
+                        else
+                                radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
+                }
+        }
        return true;
 }
@@ -461,7 +449,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                case 1:
                        args.v1.ucMisc = 0;
                        args.v1.ucAction = action;
-                        if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                        if (drm_detect_hdmi_monitor(radeon_connector->edid))
                                args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
@@ -486,7 +474,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                                if (dig->coherent_mode)
                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
                        }
-                        if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                        if (drm_detect_hdmi_monitor(radeon_connector->edid))
                                args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
                        args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
                        args.v2.ucTruncate = 0;
@@ -544,7 +532,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
        switch (connector->connector_type) {
        case DRM_MODE_CONNECTOR_DVII:
        case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
-                if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                if (drm_detect_hdmi_monitor(radeon_connector->edid))
                        return ATOM_ENCODER_MODE_HDMI;
                else if (radeon_connector->use_digital)
                        return ATOM_ENCODER_MODE_DVI;
@@ -554,7 +542,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
        case DRM_MODE_CONNECTOR_DVID:
        case DRM_MODE_CONNECTOR_HDMIA:
        default:
-                if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                if (drm_detect_hdmi_monitor(radeon_connector->edid))
                        return ATOM_ENCODER_MODE_HDMI;
                else
                        return ATOM_ENCODER_MODE_DVI;
@@ -566,7 +554,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                /*if (radeon_output->MonType == MT_DP)
                  return ATOM_ENCODER_MODE_DP;
                  else*/
-                if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                if (drm_detect_hdmi_monitor(radeon_connector->edid))
                        return ATOM_ENCODER_MODE_HDMI;
                else
                        return ATOM_ENCODER_MODE_DVI;
@@ -734,14 +722,17 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
        args.v1.ucAction = action;
+        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+                args.v1.usInitInfo = radeon_connector->connector_object_id;
+        } else {
+                if (radeon_encoder->pixel_clock > 165000)
+                        args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
+                else
+                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+        }
        if (ASIC_IS_DCE32(rdev)) {
-                if (radeon_encoder->pixel_clock > 165000) {
+                if (radeon_encoder->pixel_clock > 165000)
-                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
+                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
-                        args.v2.acConfig.fDualLinkConnector = 1;
-                } else {
-                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
-                }
                if (dig->dig_block)
                        args.v2.acConfig.ucEncoderSel = 1;
@@ -766,7 +757,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
                }
        } else {
                args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
-                args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
                switch (radeon_encoder->encoder_id) {
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
@@ -874,16 +864,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
        DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
        int index = 0;
        bool is_dig = false;
-        int devices;
        memset(&args, 0, sizeof(args));
-        /* on DPMS off we have no idea if active device is meaningful */
-        if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
-                devices = radeon_encoder->devices;
-        else
-                devices = radeon_encoder->active_device;
        DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
                  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
                  radeon_encoder->active_device);
@@ -914,18 +897,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-                if (devices & (ATOM_DEVICE_TV_SUPPORT))
+                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
-                else if (devices & (ATOM_DEVICE_CV_SUPPORT))
+                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
                else
                        index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-                if (devices & (ATOM_DEVICE_TV_SUPPORT))
+                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
-                else if (devices & (ATOM_DEVICE_CV_SUPPORT))
+                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
                else
                        index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
@@ -1104,8 +1087,11 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
        }
        /* set scaler clears this on some chips */
-        if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
+        if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
-                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
+                if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
+                        WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
+                               AVIVO_D1MODE_INTERLEAVE_EN);
+        }
 }
 static void
@@ -1153,6 +1139,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
                /* setup and enable the encoder and transmitter */
                atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
+                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT);
                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
                break;
@@ -1268,8 +1255,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 {
        radeon_atom_output_lock(encoder, true);
        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
-        radeon_encoder_set_active_device(encoder);
 }
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index a931af065dd4..a68d7566178c 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -140,15 +140,15 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
                WARN(1, "trying to unbind memory to unitialized GART !\n");
                return;
        }
-        t = offset / 4096;
+        t = offset / RADEON_GPU_PAGE_SIZE;
-        p = t / (PAGE_SIZE / 4096);
+        p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
        for (i = 0; i < pages; i++, p++) {
                if (rdev->gart.pages[p]) {
                        pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
                                       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
                        rdev->gart.pages[p] = NULL;
                        rdev->gart.pages_addr[p] = 0;
-                        for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) {
+                        for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
                                radeon_gart_set_page(rdev, t, 0);
                        }
                }
@@ -169,8 +169,8 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
                DRM_ERROR("trying to bind memory to unitialized GART !\n");
                return -EINVAL;
        }
-        t = offset / 4096;
+        t = offset / RADEON_GPU_PAGE_SIZE;
-        p = t / (PAGE_SIZE / 4096);
+        p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
        for (i = 0; i < pages; i++, p++) {
                /* we need to support large memory configurations */
@@ -185,9 +185,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
                }
                rdev->gart.pages[p] = pagelist[i];
                page_base = rdev->gart.pages_addr[p];
-                for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) {
+                for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
                        radeon_gart_set_page(rdev, t, page_base);
-                        page_base += 4096;
+                        page_base += RADEON_GPU_PAGE_SIZE;
                }
        }
        mb();
@@ -200,14 +200,14 @@ int radeon_gart_init(struct radeon_device *rdev)
        if (rdev->gart.pages) {
                return 0;
        }
-        /* We need PAGE_SIZE >= 4096 */
+        /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
-        if (PAGE_SIZE < 4096) {
+        if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
                DRM_ERROR("Page size is smaller than GPU page size!\n");
                return -EINVAL;
        }
        /* Compute table size */
        rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
-        rdev->gart.num_gpu_pages = rdev->mc.gtt_size / 4096;
+        rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
        DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
                 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
        /* Allocate pages table */
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 8e0a8759e428..a0fe6232dcb6 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -92,6 +92,13 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
        if (r) {
                return r;
        }
+        /* enable msi */
+        rdev->msi_enabled = 0;
+        if (rdev->family >= CHIP_RV380) {
+                int ret = pci_enable_msi(rdev->pdev);
+                if (!ret)
+                        rdev->msi_enabled = 1;
+        }
        drm_irq_install(rdev->ddev);
        rdev->irq.installed = true;
        DRM_INFO("radeon: irq initialized.\n");
@@ -103,5 +110,7 @@ void radeon_irq_kms_fini(struct radeon_device *rdev)
        if (rdev->irq.installed) {
                rdev->irq.installed = false;
                drm_irq_uninstall(rdev->ddev);
+                if (rdev->msi_enabled)
+                        pci_disable_msi(rdev->pdev);
        }
 }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 36410f85d705..8d0b7aa87fa4 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -48,7 +48,7 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
        u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
        u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
        u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
-        struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
+        struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
        fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
                (RADEON_VERT_STRETCH_RESERVED |
@@ -95,19 +95,19 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
        fp_horz_vert_active = 0;
-        if (native_mode->panel_xres == 0 ||
+        if (native_mode->hdisplay == 0 ||
-            native_mode->panel_yres == 0) {
+            native_mode->vdisplay == 0) {
                hscale = false;
                vscale = false;
        } else {
-                if (xres > native_mode->panel_xres)
+                if (xres > native_mode->hdisplay)
-                        xres = native_mode->panel_xres;
+                        xres = native_mode->hdisplay;
-                if (yres > native_mode->panel_yres)
+                if (yres > native_mode->vdisplay)
-                        yres = native_mode->panel_yres;
+                        yres = native_mode->vdisplay;
-                if (xres == native_mode->panel_xres)
+                if (xres == native_mode->hdisplay)
                        hscale = false;
-                if (yres == native_mode->panel_yres)
+                if (yres == native_mode->vdisplay)
                        vscale = false;
        }
@@ -119,11 +119,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
                else {
                        inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
                        scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
-                                / native_mode->panel_xres + 1;
+                                / native_mode->hdisplay + 1;
                        fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
                                        RADEON_HORZ_STRETCH_BLEND |
                                        RADEON_HORZ_STRETCH_ENABLE |
-                                        ((native_mode->panel_xres/8-1) << 16));
+                                        ((native_mode->hdisplay/8-1) << 16));
                }
                if (!vscale)
@@ -131,11 +131,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
                else {
                        inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
                        scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
-                                / native_mode->panel_yres + 1;
+                                / native_mode->vdisplay + 1;
                        fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
                                        RADEON_VERT_STRETCH_ENABLE |
                                        RADEON_VERT_STRETCH_BLEND |
-                                        ((native_mode->panel_yres-1) << 12));
+                                        ((native_mode->vdisplay-1) << 12));
                }
                break;
        case RMX_CENTER:
@@ -175,8 +175,8 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
                                                ? RADEON_CRTC_V_SYNC_POL
                                                : 0)));
-                fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
+                fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
-                                (((native_mode->panel_xres / 8) & 0x1ff) << 16));
+                                (((native_mode->hdisplay / 8) & 0x1ff) << 16));
                break;
        case RMX_OFF:
        default:
@@ -532,6 +532,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                radeon_fb = to_radeon_framebuffer(old_fb);
                radeon_gem_object_unpin(radeon_fb->obj);
        }
+        /* Bytes per pixel may have changed */
+        radeon_bandwidth_update(rdev);
        return 0;
 }
@@ -664,6 +668,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+                WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
+                WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
        } else {
                uint32_t crtc_gen_cntl;
                uint32_t crtc_ext_cntl;
@@ -1015,14 +1022,11 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
                                 int x, int y, struct drm_framebuffer *old_fb)
 {
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
        /* TODO TV */
        radeon_crtc_set_base(crtc, x, y, old_fb);
        radeon_set_crtc_timing(crtc, adjusted_mode);
        radeon_set_pll(crtc, adjusted_mode);
-        radeon_bandwidth_update(rdev);
        if (radeon_crtc->crtc_id == 0) {
                radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
        } else {
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 6ceb958fd194..00382122869b 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -107,8 +107,6 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
        else
                radeon_combios_output_lock(encoder, true);
        radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
-        radeon_encoder_set_active_device(encoder);
 }
 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
@@ -192,6 +190,8 @@ static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 {
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        /* set the active encoder to connector routing */
+        radeon_encoder_set_active_device(encoder);
        drm_mode_set_crtcinfo(adjusted_mode, 0);
        if (radeon_encoder->rmx_type != RMX_OFF)
@@ -218,7 +218,8 @@ static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
                                                 struct drm_display_mode *mode,
                                                 struct drm_display_mode *adjusted_mode)
 {
+        /* set the active encoder to connector routing */
+        radeon_encoder_set_active_device(encoder);
        drm_mode_set_crtcinfo(adjusted_mode, 0);
        return true;
@@ -272,7 +273,6 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
        else
                radeon_combios_output_lock(encoder, true);
        radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
-        radeon_encoder_set_active_device(encoder);
 }
 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
@@ -468,7 +468,6 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
        else
                radeon_combios_output_lock(encoder, true);
        radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
-        radeon_encoder_set_active_device(encoder);
 }
 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
@@ -543,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
    fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+    fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
+                     RADEON_FP_DFP_SYNC_SEL |
+                     RADEON_FP_CRT_SYNC_SEL |
+                     RADEON_FP_CRTC_LOCK_8DOT |
+                     RADEON_FP_USE_SHADOW_EN |
+                     RADEON_FP_CRTC_USE_SHADOW_VEND |
+                     RADEON_FP_CRT_SYNC_ALT);
    if (1) /*  FIXME rgbBits == 8 */
            fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
    else
@@ -556,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
                    else
                            fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
            } else
-                    fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
+                    fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
    } else {
            if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
                    fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
@@ -593,7 +600,8 @@ static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
                                              struct drm_display_mode *mode,
                                              struct drm_display_mode *adjusted_mode)
 {
+        /* set the active encoder to connector routing */
+        radeon_encoder_set_active_device(encoder);
        drm_mode_set_crtcinfo(adjusted_mode, 0);
        return true;
@@ -636,7 +644,6 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
        else
                radeon_combios_output_lock(encoder, true);
        radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
-        radeon_encoder_set_active_device(encoder);
 }
 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
@@ -735,7 +742,8 @@ static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
                                            struct drm_display_mode *mode,
                                            struct drm_display_mode *adjusted_mode)
 {
+        /* set the active encoder to connector routing */
+        radeon_encoder_set_active_device(encoder);
        drm_mode_set_crtcinfo(adjusted_mode, 0);
        return true;
@@ -839,7 +847,6 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
        else
                radeon_combios_output_lock(encoder, true);
        radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
-        radeon_encoder_set_active_device(encoder);
 }
 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index e61226817ccf..ace726aa0d76 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -172,6 +172,7 @@ enum radeon_connector_table {
 struct radeon_mode_info {
        struct atom_context *atom_context;
+        struct card_info *atom_card_info;
        enum radeon_connector_table connector_table;
        bool mode_config_initialized;
        struct radeon_crtc *crtcs[2];
@@ -186,17 +187,6 @@ struct radeon_mode_info {
 };
-struct radeon_native_mode {
-        /* preferred mode */
-        uint32_t panel_xres, panel_yres;
-        uint32_t hoverplus, hsync_width;
-        uint32_t hblank;
-        uint32_t voverplus, vsync_width;
-        uint32_t vblank;
-        uint32_t dotclock;
-        uint32_t flags;
-};
 #define MAX_H_CODE_TIMING_LEN 32
 #define MAX_V_CODE_TIMING_LEN 32
@@ -228,7 +218,7 @@ struct radeon_crtc {
        enum radeon_rmx_type rmx_type;
        fixed20_12 vsc;
        fixed20_12 hsc;
-        struct radeon_native_mode native_mode;
+        struct drm_display_mode native_mode;
 };
 struct radeon_encoder_primary_dac {
@@ -248,7 +238,7 @@ struct radeon_encoder_lvds {
        bool     use_bios_dividers;
        uint32_t lvds_gen_cntl;
        /* panel mode */
-        struct radeon_native_mode native_mode;
+        struct drm_display_mode native_mode;
 };
 struct radeon_encoder_tv_dac {
@@ -271,6 +261,16 @@ struct radeon_encoder_int_tmds {
        struct radeon_tmds_pll tmds_pll[4];
 };
+/* spread spectrum */
+struct radeon_atom_ss {
+        uint16_t percentage;
+        uint8_t type;
+        uint8_t step;
+        uint8_t delay;
+        uint8_t range;
+        uint8_t refdiv;
+};
 struct radeon_encoder_atom_dig {
        /* atom dig */
        bool coherent_mode;
@@ -278,8 +278,9 @@ struct radeon_encoder_atom_dig {
        /* atom lvds */
        uint32_t lvds_misc;
        uint16_t panel_pwr_delay;
+        struct radeon_atom_ss *ss;
        /* panel mode */
-        struct radeon_native_mode native_mode;
+        struct drm_display_mode native_mode;
 };
 struct radeon_encoder_atom_dac {
@@ -294,7 +295,7 @@ struct radeon_encoder {
        uint32_t flags;
        uint32_t pixel_clock;
        enum radeon_rmx_type rmx_type;
-        struct radeon_native_mode native_mode;
+        struct drm_display_mode native_mode;
        void *enc_priv;
 };
@@ -308,12 +309,15 @@ struct radeon_connector {
        uint32_t connector_id;
        uint32_t devices;
        struct radeon_i2c_chan *ddc_bus;
+        /* some systems have a an hdmi and vga port with a shared ddc line */
+        bool shared_ddc;
        bool use_digital;
        /* we need to mind the EDID between detect
           and get modes due to analog/digital/tvencoder */
        struct edid *edid;
        void *con_priv;
        bool dac_load_detect;
+        uint16_t connector_object_id;
 };
 struct radeon_framebuffer {
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
new file mode 100644
index 000000000000..46146c6a2a06
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -0,0 +1,65 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Rafał Miłecki <zajec5@gmail.com>
+ */
+#include "drmP.h"
+#include "radeon.h"
+int radeon_debugfs_pm_init(struct radeon_device *rdev);
+int radeon_pm_init(struct radeon_device *rdev)
+{
+        if (radeon_debugfs_pm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for CP !\n");
+        }
+        return 0;
+}
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        seq_printf(m, "engine clock: %u0 Hz\n", radeon_get_engine_clock(rdev));
+        seq_printf(m, "memory clock: %u0 Hz\n", radeon_get_memory_clock(rdev));
+        return 0;
+}
+static struct drm_info_list radeon_pm_info_list[] = {
+        {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
+};
+#endif
+int radeon_debugfs_pm_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index bfa1ab9c93e1..29ab75903ec1 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -290,6 +290,8 @@
 #define RADEON_BUS_CNTL                     0x0030
 #       define RADEON_BUS_MASTER_DIS         (1 << 6)
 #       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12)
+#       define RS600_BUS_MASTER_DIS          (1 << 14)
+#       define RS600_MSI_REARM               (1 << 20) /* rs600/rs690/rs740 */
 #       define RADEON_BUS_RD_DISCARD_EN      (1 << 24)
 #       define RADEON_BUS_RD_ABORT_EN        (1 << 25)
 #       define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
@@ -297,6 +299,9 @@
 #       define RADEON_BUS_READ_BURST         (1 << 30)
 #define RADEON_BUS_CNTL1                    0x0034
 #       define RADEON_BUS_WAIT_ON_LOCK_EN    (1 << 4)
+/* rv370/rv380, rv410, r423/r430/r480, r5xx */
+#define RADEON_MSI_REARM_EN                 0x0160
+#       define RV370_MSI_REARM_EN            (1 << 0)
 /* #define RADEON_PCIE_INDEX                   0x0030 */
 /* #define RADEON_PCIE_DATA                    0x0034 */
@@ -3311,6 +3316,7 @@
 #define RADEON_AIC_CNTL                     0x01d0
 #       define RADEON_PCIGART_TRANSLATE_EN     (1 << 0)
 #       define RADEON_DIS_OUT_OF_PCI_GART_ACCESS     (1 << 1)
+#       define RS400_MSI_REARM                  (1 << 3) /* rs400/rs480 */
 #define RADEON_AIC_LO_ADDR                  0x01dc
 #define RADEON_AIC_PT_BASE              0x01d8
 #define RADEON_AIC_HI_ADDR              0x01e0
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 03c33cf4e14c..f8a465d9a1cf 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -42,7 +42,7 @@ void radeon_test_moves(struct radeon_device *rdev)
        /* Number of tests =
         * (Total GTT - IB pool - writeback page - ring buffer) / test size
         */
-        n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - 4096 -
+        n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE -
             rdev->cp.ring_size) / size;
        gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
@@ -102,7 +102,7 @@ void radeon_test_moves(struct radeon_device *rdev)
                        goto out_cleanup;
                }
-                r = radeon_copy(rdev, gtt_addr, vram_addr, size / 4096, fence);
+                r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence);
                if (r) {
                        DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
                        goto out_cleanup;
@@ -145,7 +145,7 @@ void radeon_test_moves(struct radeon_device *rdev)
                        goto out_cleanup;
                }
-                r = radeon_copy(rdev, vram_addr, gtt_addr, size / 4096, fence);
+                r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence);
                if (r) {
                        DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
                        goto out_cleanup;
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 765bd184b6fc..1381e06d6af3 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -295,6 +295,12 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
        if (unlikely(r)) {
                return r;
        }
+        r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
+        if (unlikely(r)) {
+                goto out_cleanup;
+        }
        r = ttm_tt_bind(bo->ttm, &tmp_mem);
        if (unlikely(r)) {
                goto out_cleanup;
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index a769c296f6a6..ca037160a582 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -418,6 +418,8 @@ int rs400_resume(struct radeon_device *rdev)
        rs400_gart_disable(rdev);
        /* Resume clock before doing reset */
        r300_clock_startup(rdev);
+        /* setup MC before calling post tables */
+        rs400_mc_program(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
        if (radeon_gpu_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 10dfa78762da..5f117cd8736a 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -242,7 +242,7 @@ void rs600_irq_disable(struct radeon_device *rdev)
 int rs600_irq_process(struct radeon_device *rdev)
 {
-        uint32_t status;
+        uint32_t status, msi_rearm;
        uint32_t r500_disp_int;
        status = rs600_irq_ack(rdev, &r500_disp_int);
@@ -260,6 +260,22 @@ int rs600_irq_process(struct radeon_device *rdev)
                        drm_handle_vblank(rdev->ddev, 1);
                status = rs600_irq_ack(rdev, &r500_disp_int);
        }
+        if (rdev->msi_enabled) {
+                switch (rdev->family) {
+                case CHIP_RS600:
+                case CHIP_RS690:
+                case CHIP_RS740:
+                        msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
+                        WREG32(RADEON_BUS_CNTL, msi_rearm);
+                        WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
+                        break;
+                default:
+                        msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
+                        WREG32(RADEON_MSI_REARM_EN, msi_rearm);
+                        WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
+                        break;
+                }
+        }
        return IRQ_HANDLED;
 }
@@ -472,6 +488,8 @@ int rs600_init(struct radeon_device *rdev)
        }
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Get vram informations */
        rs600_vram_info(rdev);
        /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 025e3225346c..27547175cf93 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -706,6 +706,8 @@ int rs690_init(struct radeon_device *rdev)
        }
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Get vram informations */
        rs690_vram_info(rdev);
        /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 41a34c23e6d8..ba68c9fe90a1 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -380,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
        save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
        /* Stop all video */
-        WREG32(R_000330_D1VGA_CONTROL, 0);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
        WREG32(R_000300_VGA_RENDER_CONTROL, 0);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -389,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
        WREG32(R_006880_D2CRTC_CONTROL, 0);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
+        WREG32(R_000330_D1VGA_CONTROL, 0);
+        WREG32(R_000338_D2VGA_CONTROL, 0);
 }
 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -402,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
        WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
        mdelay(1);
        /* Restore video state */
+        WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
+        WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
        WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
        WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
-        WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
-        WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
        WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 }
@@ -585,6 +586,8 @@ int rv515_init(struct radeon_device *rdev)
        }
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Get vram informations */
        rv515_vram_info(rdev);
        /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 595ac638039d..b0efd0ddae7a 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -529,11 +529,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        if (rdev->family == CHIP_RV770)
                gb_tiling_config |= BANK_TILING(1);
        else
-                gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
+                gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
        gb_tiling_config |= GROUP_SIZE(0);
-        if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
+        if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
                gb_tiling_config |= ROW_TILING(3);
                gb_tiling_config |= SAMPLE_SPLIT(3);
        } else {
@@ -579,14 +579,14 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        /* set HW defaults for 3D engine */
        WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
-                                                ROQ_IB2_START(0x2b)));
+                                     ROQ_IB2_START(0x2b)));
        WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
        WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
-                                        SYNC_GRADIENT |
+                             SYNC_GRADIENT |
-                                        SYNC_WALKER |
+                             SYNC_WALKER |
-                                        SYNC_ALIGNER));
+                             SYNC_ALIGNER));
        sx_debug_1 = RREG32(SX_DEBUG_1);
        sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
@@ -598,9 +598,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        WREG32(SMX_DC_CTL0, smx_dc_ctl0);
        WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
-                                          GS_FLUSH_CTL(4) |
+                               GS_FLUSH_CTL(4) |
-                                          ACK_FLUSH_CTL(3) |
+                               ACK_FLUSH_CTL(3) |
-                                          SYNC_FLUSH_CTL));
+                               SYNC_FLUSH_CTL));
        if (rdev->family == CHIP_RV770)
                WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
@@ -611,12 +611,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        }
        WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
-                                                   POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
+                                        POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
-                                                   SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
+                                        SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
        WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
-                                                 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
+                                 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
-                                                 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
+                                 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
        WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
@@ -774,14 +774,36 @@ int rv770_mc_init(struct radeon_device *rdev)
 {
        fixed20_12 a;
        u32 tmp;
+        int chansize, numchan;
        int r;
        /* Get VRAM informations */
-        /* FIXME: Don't know how to determine vram width, need to check
-         * vram_width usage
-         */
-        rdev->mc.vram_width = 128;
        rdev->mc.vram_is_ddr = true;
+        tmp = RREG32(MC_ARB_RAMCFG);
+        if (tmp & CHANSIZE_OVERRIDE) {
+                chansize = 16;
+        } else if (tmp & CHANSIZE_MASK) {
+                chansize = 64;
+        } else {
+                chansize = 32;
+        }
+        tmp = RREG32(MC_SHARED_CHMAP);
+        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+        case 0:
+        default:
+                numchan = 1;
+                break;
+        case 1:
+                numchan = 2;
+                break;
+        case 2:
+                numchan = 4;
+                break;
+        case 3:
+                numchan = 8;
+                break;
+        }
+        rdev->mc.vram_width = numchan * chansize;
        /* Could aper size report 0 ? */
        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
@@ -961,10 +983,13 @@ int rv770_init(struct radeon_device *rdev)
        r600_scratch_init(rdev);
        /* Initialize surface registers */
        radeon_surface_init(rdev);
+        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
        r = radeon_clocks_init(rdev);
        if (r)
                return r;
+        /* Initialize power management */
+        radeon_pm_init(rdev);
        /* Fence driver */
        r = radeon_fence_driver_init(rdev);
        if (r)
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 4b9c3d6396ff..a1367ab6f261 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -129,6 +129,10 @@
 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
 #define HDP_TILING_CONFIG                               0x2F3C
+#define MC_SHARED_CHMAP                                         0x2004
+#define         NOOFCHAN_SHIFT                                  12
+#define         NOOFCHAN_MASK                                   0x00003000
 #define MC_ARB_RAMCFG                                   0x2760
 #define         NOOFBANK_SHIFT                                  0
 #define         NOOFBANK_MASK                                   0x00000003
@@ -142,6 +146,7 @@
 #define         CHANSIZE_MASK                                   0x00000100
 #define         BURSTLENGTH_SHIFT                               9
 #define         BURSTLENGTH_MASK                                0x00000200
+#define         CHANSIZE_OVERRIDE                               (1 << 11)
 #define MC_VM_AGP_TOP                                   0x2028
 #define MC_VM_AGP_BOT                                   0x202C
 #define MC_VM_AGP_BASE                                  0x2030
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index a55ee1a56c16..7bcb89f39ce8 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -279,6 +279,7 @@ int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement)
        return ttm_tt_set_caching(ttm, state);
 }
+EXPORT_SYMBOL(ttm_tt_set_placement_caching);
 static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
 {