aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c14
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c6
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
5 files changed, 15 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2e493ec1042b..7df89ae8172f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -452,7 +452,7 @@ typedef struct drm_i915_private {
452 u32 savePIPEB_DATA_N1; 452 u32 savePIPEB_DATA_N1;
453 u32 savePIPEB_LINK_M1; 453 u32 savePIPEB_LINK_M1;
454 u32 savePIPEB_LINK_N1; 454 u32 savePIPEB_LINK_N1;
455 u32 saveRSTDBYCTL; 455 u32 saveMCHBAR_RENDER_STANDBY;
456 456
457 struct { 457 struct {
458 struct drm_mm gtt_space; 458 struct drm_mm gtt_space;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8b35f5e1c511..1a56ae7b5a78 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -272,23 +272,23 @@ static void i915_hotplug_work_func(struct work_struct *work)
272static void i915_handle_rps_change(struct drm_device *dev) 272static void i915_handle_rps_change(struct drm_device *dev)
273{ 273{
274 drm_i915_private_t *dev_priv = dev->dev_private; 274 drm_i915_private_t *dev_priv = dev->dev_private;
275 u32 slow_up, slow_down, max_avg, min_avg; 275 u32 busy_up, busy_down, max_avg, min_avg;
276 u16 rgvswctl; 276 u16 rgvswctl;
277 u8 new_delay = dev_priv->cur_delay; 277 u8 new_delay = dev_priv->cur_delay;
278 278
279 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG); 279 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
280 slow_up = I915_READ(RCPREVBSYTUPAVG); 280 busy_up = I915_READ(RCPREVBSYTUPAVG);
281 slow_down = I915_READ(RCPREVBSYTDNAVG); 281 busy_down = I915_READ(RCPREVBSYTDNAVG);
282 max_avg = I915_READ(RCBMAXAVG); 282 max_avg = I915_READ(RCBMAXAVG);
283 min_avg = I915_READ(RCBMINAVG); 283 min_avg = I915_READ(RCBMINAVG);
284 284
285 /* Handle RCS change request from hw */ 285 /* Handle RCS change request from hw */
286 if (slow_up > max_avg) { 286 if (busy_up > max_avg) {
287 if (dev_priv->cur_delay != dev_priv->max_delay) 287 if (dev_priv->cur_delay != dev_priv->max_delay)
288 new_delay = dev_priv->cur_delay - 1; 288 new_delay = dev_priv->cur_delay - 1;
289 if (new_delay < dev_priv->max_delay) 289 if (new_delay < dev_priv->max_delay)
290 new_delay = dev_priv->max_delay; 290 new_delay = dev_priv->max_delay;
291 } else if (slow_down < min_avg) { 291 } else if (busy_down < min_avg) {
292 if (dev_priv->cur_delay != dev_priv->min_delay) 292 if (dev_priv->cur_delay != dev_priv->min_delay)
293 new_delay = dev_priv->cur_delay + 1; 293 new_delay = dev_priv->cur_delay + 1;
294 if (new_delay > dev_priv->min_delay) 294 if (new_delay > dev_priv->min_delay)
@@ -300,8 +300,8 @@ static void i915_handle_rps_change(struct drm_device *dev)
300 300
301 rgvswctl = I915_READ(MEMSWCTL); 301 rgvswctl = I915_READ(MEMSWCTL);
302 if (rgvswctl & MEMCTL_CMD_STS) { 302 if (rgvswctl & MEMCTL_CMD_STS) {
303 DRM_ERROR("gpu slow, RCS change rejected\n"); 303 DRM_ERROR("gpu busy, RCS change rejected\n");
304 return; /* still slow with another command */ 304 return; /* still busy with another command */
305 } 305 }
306 306
307 /* Program the new state */ 307 /* Program the new state */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3948ee37c13..d344c031f188 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -907,7 +907,7 @@
907#define RCBMINAVG 0x111a0 907#define RCBMINAVG 0x111a0
908#define RCUPEI 0x111b0 908#define RCUPEI 0x111b0
909#define RCDNEI 0x111b4 909#define RCDNEI 0x111b4
910#define RSTDBYCTL 0x111b8 910#define MCHBAR_RENDER_STANDBY 0x111b8
911#define RCX_SW_EXIT (1<<23) 911#define RCX_SW_EXIT (1<<23)
912#define RSX_STATUS_MASK 0x00700000 912#define RSX_STATUS_MASK 0x00700000
913#define VIDCTL 0x111c0 913#define VIDCTL 0x111c0
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2c346645acfa..ac0d1a73ac22 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -682,7 +682,8 @@ void i915_restore_display(struct drm_device *dev)
682 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 682 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
683 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); 683 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
684 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); 684 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
685 I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL); 685 I915_WRITE(MCHBAR_RENDER_STANDBY,
686 dev_priv->saveMCHBAR_RENDER_STANDBY);
686 } else { 687 } else {
687 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 688 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
688 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 689 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
@@ -746,7 +747,8 @@ int i915_save_state(struct drm_device *dev)
746 dev_priv->saveGTIMR = I915_READ(GTIMR); 747 dev_priv->saveGTIMR = I915_READ(GTIMR);
747 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); 748 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
748 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); 749 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
749 dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL); 750 dev_priv->saveMCHBAR_RENDER_STANDBY =
751 I915_READ(MCHBAR_RENDER_STANDBY);
750 } else { 752 } else {
751 dev_priv->saveIER = I915_READ(IER); 753 dev_priv->saveIER = I915_READ(IER);
752 dev_priv->saveIMR = I915_READ(IMR); 754 dev_priv->saveIMR = I915_READ(IMR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4a93f7a0f58d..9e80020ae2fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4770,8 +4770,8 @@ void intel_init_clock_gating(struct drm_device *dev)
4770 4770
4771 if (obj_priv) { 4771 if (obj_priv) {
4772 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); 4772 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4773 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & 4773 I915_WRITE(MCHBAR_RENDER_STANDBY,
4774 ~RCX_SW_EXIT); 4774 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4775 } 4775 }
4776 } 4776 }
4777} 4777}