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-rw-r--r--drivers/gpu/drm/i915/intel_dp.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ee157091f92e..320bd61ea2f2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -317,12 +317,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
317 * Note that PCH attached eDP panels should use a 125MHz input 317 * Note that PCH attached eDP panels should use a 125MHz input
318 * clock divider. 318 * clock divider.
319 */ 319 */
320 if (is_cpu_edp(intel_dp)) { 320 if (IS_VALLEYVIEW(dev)) {
321 aux_clock_divider = 100;
322 } else if (intel_dig_port->port == PORT_A) {
321 if (HAS_DDI(dev)) 323 if (HAS_DDI(dev))
322 aux_clock_divider = DIV_ROUND_CLOSEST( 324 aux_clock_divider = DIV_ROUND_CLOSEST(
323 intel_ddi_get_cdclk_freq(dev_priv), 2000); 325 intel_ddi_get_cdclk_freq(dev_priv), 2000);
324 else if (IS_VALLEYVIEW(dev))
325 aux_clock_divider = 100;
326 else if (IS_GEN6(dev) || IS_GEN7(dev)) 326 else if (IS_GEN6(dev) || IS_GEN7(dev))
327 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ 327 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
328 else 328 else