12 files changed, 90 insertions, 231 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ce045a8cf82c..f07e4252b708 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -67,11 +67,11 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 MODULE_PARM_DESC(i915_enable_rc6,
                 "Enable power-saving render C-state 6 (default: true)");
 
-unsigned int i915_enable_fbc __read_mostly = 1;
+unsigned int i915_enable_fbc __read_mostly = -1;
 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
 MODULE_PARM_DESC(i915_enable_fbc,
                 "Enable frame buffer compression for power savings "
-                "(default: false)");
+                "(default: -1 (use per-chip default))");
 
 unsigned int i915_lvds_downclock __read_mostly = 0;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 56a8554d9039..04411ad2e779 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1799,6 +1799,7 @@ static void intel_update_fbc(struct drm_device *dev)
         struct drm_framebuffer *fb;
         struct intel_framebuffer *intel_fb;
         struct drm_i915_gem_object *obj;
+        int enable_fbc;
 
         DRM_DEBUG_KMS("\n");
 
@@ -1839,8 +1840,15 @@ static void intel_update_fbc(struct drm_device *dev)
         intel_fb = to_intel_framebuffer(fb);
         obj = intel_fb->obj;
 
-        if (!i915_enable_fbc) {
-                DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
+        enable_fbc = i915_enable_fbc;
+        if (enable_fbc < 0) {
+                DRM_DEBUG_KMS("fbc set to per-chip default\n");
+                enable_fbc = 1;
+                if (INTEL_INFO(dev)->gen <= 5)
+                        enable_fbc = 0;
+        }
+        if (!enable_fbc) {
+                DRM_DEBUG_KMS("fbc disabled per module param\n");
                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
                 goto out_disable;
         }
@@ -4687,13 +4695,13 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                 bpc = 6; /* min is 18bpp */
                 break;
         case 24:
-                bpc = min((unsigned int)8, display_bpc);
+                bpc = 8;
                 break;
         case 30:
-                bpc = min((unsigned int)10, display_bpc);
+                bpc = 10;
                 break;
         case 48:
-                bpc = min((unsigned int)12, display_bpc);
+                bpc = 12;
                 break;
         default:
                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
@@ -4701,10 +4709,12 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                 break;
         }
 
+        display_bpc = min(display_bpc, bpc);
+
         DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
                          bpc, display_bpc);
 
-        *pipe_bpp = bpc * 3;
+        *pipe_bpp = display_bpc * 3;
 
         return display_bpc != bpc;
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0b2ee9d39980..fe1099d8817e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -337,9 +337,6 @@ extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
                                            struct drm_connector *connector,
                                            struct intel_load_detect_pipe *old);
 
-extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB);
-extern int intel_sdvo_supports_hotplug(struct drm_connector *connector);
-extern void intel_sdvo_set_hotplug(struct drm_connector *connector, int enable);
 extern void intelfb_restore(void);
 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
                                     u16 blue, int regno);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 30fe554d8936..6348c499616f 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -92,6 +92,11 @@ struct intel_sdvo {
         */
         uint16_t attached_output;
 
+        /*
+         * Hotplug activation bits for this device
+         */
+        uint8_t hotplug_active[2];
+
         /**
          * This is used to select the color range of RBG outputs in HDMI mode.
          * It is only valid when using TMDS encoding and 8 bit per color mode.
@@ -1208,74 +1213,20 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in
         return true;
 }
 
-/* No use! */
-#if 0
-struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
-{
-        struct drm_connector *connector = NULL;
-        struct intel_sdvo *iout = NULL;
-        struct intel_sdvo *sdvo;
-
-        /* find the sdvo connector */
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-                iout = to_intel_sdvo(connector);
-
-                if (iout->type != INTEL_OUTPUT_SDVO)
-                        continue;
-
-                sdvo = iout->dev_priv;
-
-                if (sdvo->sdvo_reg == SDVOB && sdvoB)
-                        return connector;
-
-                if (sdvo->sdvo_reg == SDVOC && !sdvoB)
-                        return connector;
-
-        }
-
-        return NULL;
-}
-
-int intel_sdvo_supports_hotplug(struct drm_connector *connector)
+static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
 {
         u8 response[2];
-        u8 status;
-        struct intel_sdvo *intel_sdvo;
-        DRM_DEBUG_KMS("\n");
-
-        if (!connector)
-                return 0;
-
-        intel_sdvo = to_intel_sdvo(connector);
 
         return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
                                     &response, 2) && response[0];
 }
 
-void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
+static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
 {
-        u8 response[2];
-        u8 status;
-        struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
-
-        intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
-        intel_sdvo_read_response(intel_sdvo, &response, 2);
-
-        if (on) {
-                intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
-                status = intel_sdvo_read_response(intel_sdvo, &response, 2);
-
-                intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
-        } else {
-                response[0] = 0;
-                response[1] = 0;
-                intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
-        }
+        struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
 
-        intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
-        intel_sdvo_read_response(intel_sdvo, &response, 2);
+        intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
 }
-#endif
 
 static bool
 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
@@ -2045,6 +1996,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
 {
         struct drm_encoder *encoder = &intel_sdvo->base.base;
         struct drm_connector *connector;
+        struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
         struct intel_connector *intel_connector;
         struct intel_sdvo_connector *intel_sdvo_connector;
 
@@ -2062,7 +2014,17 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
 
         intel_connector = &intel_sdvo_connector->base;
         connector = &intel_connector->base;
-        connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
+        if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
+                connector->polled = DRM_CONNECTOR_POLL_HPD;
+                intel_sdvo->hotplug_active[0] |= 1 << device;
+                /* Some SDVO devices have one-shot hotplug interrupts.
+                 * Ensure that they get re-enabled when an interrupt happens.
+                 */
+                intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
+                intel_sdvo_enable_hotplug(intel_encoder);
+        }
+        else
+                connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
         encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
         connector->connector_type = DRM_MODE_CONNECTOR_DVID;
 
@@ -2569,6 +2531,14 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
         if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
                 goto err;
 
+        /* Set up hotplug command - note paranoia about contents of reply.
+         * We assume that the hardware is in a sane state, and only touch
+         * the bits we think we understand.
+         */
+        intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
+                             &intel_sdvo->hotplug_active, 2);
+        intel_sdvo->hotplug_active[0] &= ~0x3;
+
         if (intel_sdvo_output_setup(intel_sdvo,
                                     intel_sdvo->caps.output_flags) != true) {
                 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 7ad43c6b1db7..4da23889fea6 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
         u8 msg[20];
         int msg_bytes = send_bytes + 4;
         u8 ack;
+        unsigned retry;
 
         if (send_bytes > 16)
                 return -1;
@@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
         memcpy(&msg[4], send, send_bytes);
 
-        while (1) {
+        for (retry = 0; retry < 4; retry++) {
                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
                                             msg, msg_bytes, NULL, 0, delay, &ack);
                 if (ret < 0)
                         return ret;
                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
-                        break;
+                        return send_bytes;
                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
                         udelay(400);
                 else
                         return -EIO;
         }
 
-        return send_bytes;
+        return -EIO;
 }
 
 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
@@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
         int msg_bytes = 4;
         u8 ack;
         int ret;
+        unsigned retry;
 
         msg[0] = address;
         msg[1] = address >> 8;
         msg[2] = AUX_NATIVE_READ << 4;
         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 
-        while (1) {
+        for (retry = 0; retry < 4; retry++) {
                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
-                if (ret == 0)
-                        return -EPROTO;
                 if (ret < 0)
                         return ret;
                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
                         return ret;
                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
                         udelay(400);
+                else if (ret == 0)
+                        return -EPROTO;
                 else
                         return -EIO;
         }
+
+        return -EIO;
 }
 
 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e8a746712b5b..c4ffa14fb2f4 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
         return backend_map;
 }
 
-static void evergreen_program_channel_remap(struct radeon_device *rdev)
-{
-        u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
-
-        tmp = RREG32(MC_SHARED_CHMAP);
-        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        default:
-                /* default mapping */
-                mc_shared_chremap = 0x00fac688;
-                break;
-        }
-
-        switch (rdev->family) {
-        case CHIP_HEMLOCK:
-        case CHIP_CYPRESS:
-        case CHIP_BARTS:
-                tcp_chan_steer_lo = 0x54763210;
-                tcp_chan_steer_hi = 0x0000ba98;
-                break;
-        case CHIP_JUNIPER:
-        case CHIP_REDWOOD:
-        case CHIP_CEDAR:
-        case CHIP_PALM:
-        case CHIP_SUMO:
-        case CHIP_SUMO2:
-        case CHIP_TURKS:
-        case CHIP_CAICOS:
-        default:
-                tcp_chan_steer_lo = 0x76543210;
-                tcp_chan_steer_hi = 0x0000ba98;
-                break;
-        }
-
-        WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
-        WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
-        WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
-}
-
 static void evergreen_gpu_init(struct radeon_device *rdev)
 {
         u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
-        evergreen_program_channel_remap(rdev);
-
         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
 
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 99fbd793c08c..8c79ca97753d 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
         return backend_map;
 }
 
-static void cayman_program_channel_remap(struct radeon_device *rdev)
-{
-        u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
-
-        tmp = RREG32(MC_SHARED_CHMAP);
-        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        default:
-                /* default mapping */
-                mc_shared_chremap = 0x00fac688;
-                break;
-        }
-
-        switch (rdev->family) {
-        case CHIP_CAYMAN:
-        default:
-                //tcp_chan_steer_lo = 0x54763210
-                tcp_chan_steer_lo = 0x76543210;
-                tcp_chan_steer_hi = 0x0000ba98;
-                break;
-        }
-
-        WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
-        WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
-        WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
-}
-
 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
                                             u32 disable_mask_per_se,
                                             u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
-        cayman_program_channel_remap(rdev);
-
         /* primary versions */
         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 5b1837b4aacf..7fcdbbbf2979 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -773,8 +773,8 @@ int r100_copy_blit(struct radeon_device *rdev,
                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
                 radeon_ring_write(rdev, 0);
                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
-                radeon_ring_write(rdev, cur_pages);
-                radeon_ring_write(rdev, cur_pages);
+                radeon_ring_write(rdev, num_gpu_pages);
+                radeon_ring_write(rdev, num_gpu_pages);
                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
         }
         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index c4b8741dbf58..bce63fd329d4 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector)
         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
                 int saved_dpms = connector->dpms;
 
-                if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
-                    radeon_dp_needs_link_train(radeon_connector))
-                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-                else
+                /* Only turn off the display it it's physically disconnected */
+                if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+                else if (radeon_dp_needs_link_train(radeon_connector))
+                        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
                 connector->dpms = saved_dpms;
         }
 }
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 3189a7efb2e9..fde25c0d65a0 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -208,23 +208,25 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
         int xorigin = 0, yorigin = 0;
         int w = radeon_crtc->cursor_width;
 
-        if (x < 0)
-                xorigin = -x + 1;
-        if (y < 0)
-                yorigin = -y + 1;
-        if (xorigin >= CURSOR_WIDTH)
-                xorigin = CURSOR_WIDTH - 1;
-        if (yorigin >= CURSOR_HEIGHT)
-                yorigin = CURSOR_HEIGHT - 1;
-
         if (ASIC_IS_AVIVO(rdev)) {
-                int i = 0;
-                struct drm_crtc *crtc_p;
-
                 /* avivo cursor are offset into the total surface */
                 x += crtc->x;
                 y += crtc->y;
-                DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
+        }
+        DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
+
+        if (x < 0) {
+                xorigin = min(-x, CURSOR_WIDTH - 1);
+                x = 0;
+        }
+        if (y < 0) {
+                yorigin = min(-y, CURSOR_HEIGHT - 1);
+                y = 0;
+        }
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                int i = 0;
+                struct drm_crtc *crtc_p;
 
                 /* avivo cursor image can't end on 128 pixel boundary or
                  * go past the end of the frame if both crtcs are enabled
@@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 
         radeon_lock_cursor(crtc, true);
         if (ASIC_IS_DCE4(rdev)) {
-                WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
-                       ((xorigin ? 0 : x) << 16) |
-                       (yorigin ? 0 : y));
+                WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
                 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
                 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
                        ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
         } else if (ASIC_IS_AVIVO(rdev)) {
-                WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
-                             ((xorigin ? 0 : x) << 16) |
-                             (yorigin ? 0 : y));
+                WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
                 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
                 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
                        ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
@@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
                         | yorigin));
                 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
                        (RADEON_CUR_LOCK
-                        | ((xorigin ? 0 : x) << 16)
-                        | (yorigin ? 0 : y)));
+                        | (x << 16)
+                        | y));
                 /* offset is from DISP(2)_BASE_ADDRESS */
                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
                                                                       (yorigin * 256)));
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 319d85d7e759..13690f3eb4a4 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1507,7 +1507,14 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
                 switch (mode) {
                 case DRM_MODE_DPMS_ON:
                         args.ucAction = ATOM_ENABLE;
-                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+                        /* workaround for DVOOutputControl on some RS690 systems */
+                        if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
+                                u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
+                                WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
+                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+                                WREG32(RADEON_BIOS_3_SCRATCH, reg);
+                        } else
+                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
                                 args.ucAction = ATOM_LCD_BLON;
                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4720d000d440..b13c2eedc321 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
         return backend_map;
 }
 
-static void rv770_program_channel_remap(struct radeon_device *rdev)
-{
-        u32 tcp_chan_steer, mc_shared_chremap, tmp;
-        bool force_no_swizzle;
-
-        switch (rdev->family) {
-        case CHIP_RV770:
-        case CHIP_RV730:
-                force_no_swizzle = false;
-                break;
-        case CHIP_RV710:
-        case CHIP_RV740:
-        default:
-                force_no_swizzle = true;
-                break;
-        }
-
-        tmp = RREG32(MC_SHARED_CHMAP);
-        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
-        case 0:
-        case 1:
-        default:
-                /* default mapping */
-                mc_shared_chremap = 0x00fac688;
-                break;
-        case 2:
-        case 3:
-                if (force_no_swizzle)
-                        mc_shared_chremap = 0x00fac688;
-                else
-                        mc_shared_chremap = 0x00bbc298;
-                break;
-        }
-
-        if (rdev->family == CHIP_RV740)
-                tcp_chan_steer = 0x00ef2a60;
-        else
-                tcp_chan_steer = 0x00fac688;
-
-        /* RV770 CE has special chremap setup */
-        if (rdev->pdev->device == 0x944e) {
-                tcp_chan_steer = 0x00b08b08;
-                mc_shared_chremap = 0x00b08b08;
-        }
-
-        WREG32(TCP_CHAN_STEER, tcp_chan_steer);
-        WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
-}
-
 static void rv770_gpu_init(struct radeon_device *rdev)
 {
         int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 
-        rv770_program_channel_remap(rdev);
-
         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);