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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.h1
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grctx.c7
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grgpc.fuc8
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h29
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grhub.fuc3
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h16
8 files changed, 44 insertions, 24 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 07691c2eceac..83d549d50716 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -1011,6 +1011,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
1011 switch (dev_priv->chipset) { 1011 switch (dev_priv->chipset) {
1012 case 0xc1: /* known broken */ 1012 case 0xc1: /* known broken */
1013 case 0xc8: /* never tested */ 1013 case 0xc8: /* never tested */
1014 case 0xcf: /* never tested */
1014 NV_INFO(dev, "acceleration disabled by default, pass " 1015 NV_INFO(dev, "acceleration disabled by default, pass "
1015 "noaccel=0 to force enable\n"); 1016 "noaccel=0 to force enable\n");
1016 dev_priv->noaccel = true; 1017 dev_priv->noaccel = true;
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index 5b2f6f420468..84321640a071 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -864,6 +864,9 @@ nvc0_graph_create(struct drm_device *dev)
864 case 0xce: /* 4/4/0/0, 4 */ 864 case 0xce: /* 4/4/0/0, 4 */
865 priv->magic_not_rop_nr = 0x03; 865 priv->magic_not_rop_nr = 0x03;
866 break; 866 break;
867 case 0xcf: /* 4/0/0/0, 3 */
868 priv->magic_not_rop_nr = 0x03;
869 break;
867 } 870 }
868 871
869 if (!priv->magic_not_rop_nr) { 872 if (!priv->magic_not_rop_nr) {
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.h b/drivers/gpu/drm/nouveau/nvc0_graph.h
index 55689e997286..636fe9812f79 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.h
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.h
@@ -82,6 +82,7 @@ nvc0_graph_class(struct drm_device *dev)
82 case 0xc3: 82 case 0xc3:
83 case 0xc4: 83 case 0xc4:
84 case 0xce: /* guess, mmio trace shows only 0x9097 state */ 84 case 0xce: /* guess, mmio trace shows only 0x9097 state */
85 case 0xcf: /* guess, mmio trace shows only 0x9097 state */
85 return 0x9097; 86 return 0x9097;
86 case 0xc1: 87 case 0xc1:
87 return 0x9197; 88 return 0x9197;
diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
index 31018eaf5279..0c9737a49149 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grctx.c
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -1678,7 +1678,10 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
1678 nv_wr32(dev, 0x419c04, 0x00000006); 1678 nv_wr32(dev, 0x419c04, 0x00000006);
1679 nv_wr32(dev, 0x419c08, 0x00000002); 1679 nv_wr32(dev, 0x419c08, 0x00000002);
1680 nv_wr32(dev, 0x419c20, 0x00000000); 1680 nv_wr32(dev, 0x419c20, 0x00000000);
1681 nv_wr32(dev, 0x419cb0, 0x00060048); //XXX: 0xce 0x00020048 1681 if (chipset == 0xce || chipset == 0xcf)
1682 nv_wr32(dev, 0x419cb0, 0x00020048);
1683 else
1684 nv_wr32(dev, 0x419cb0, 0x00060048);
1682 nv_wr32(dev, 0x419ce8, 0x00000000); 1685 nv_wr32(dev, 0x419ce8, 0x00000000);
1683 nv_wr32(dev, 0x419cf4, 0x00000183); 1686 nv_wr32(dev, 0x419cf4, 0x00000183);
1684 nv_wr32(dev, 0x419d20, chipset != 0xc1 ? 0x02180000 : 0x12180000); 1687 nv_wr32(dev, 0x419d20, chipset != 0xc1 ? 0x02180000 : 0x12180000);
@@ -1784,7 +1787,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
1784 1787
1785 if (1) { 1788 if (1) {
1786 const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0, 1789 const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0,
1787 16, 0, 0, 0, 0, 0, 8, 0 }; 1790 16, 0, 0, 0, 0, 0, 8, 4 };
1788 u8 max = chipset_tp_max[dev_priv->chipset & 0x0f]; 1791 u8 max = chipset_tp_max[dev_priv->chipset & 0x0f];
1789 u8 tpnr[GPC_MAX]; 1792 u8 tpnr[GPC_MAX];
1790 u8 data[TP_MAX]; 1793 u8 data[TP_MAX];
diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
index 0ec2add72a76..06f5e26d1e0f 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
@@ -77,6 +77,11 @@ chipsets:
77.b16 nvc0_gpc_mmio_tail 77.b16 nvc0_gpc_mmio_tail
78.b16 nvc0_tpc_mmio_head 78.b16 nvc0_tpc_mmio_head
79.b16 nvc3_tpc_mmio_tail 79.b16 nvc3_tpc_mmio_tail
80.b8 0xcf 0 0 0
81.b16 nvc0_gpc_mmio_head
82.b16 nvc0_gpc_mmio_tail
83.b16 nvc0_tpc_mmio_head
84.b16 nvcf_tpc_mmio_tail
80.b8 0 0 0 0 85.b8 0 0 0 0
81 86
82// GPC mmio lists 87// GPC mmio lists
@@ -134,8 +139,9 @@ mmctx_data(0x000750, 2)
134nvc0_tpc_mmio_tail: 139nvc0_tpc_mmio_tail:
135mmctx_data(0x000758, 1) 140mmctx_data(0x000758, 1)
136mmctx_data(0x0002c4, 1) 141mmctx_data(0x0002c4, 1)
137mmctx_data(0x0004bc, 1)
138mmctx_data(0x0006e0, 1) 142mmctx_data(0x0006e0, 1)
143nvcf_tpc_mmio_tail:
144mmctx_data(0x0004bc, 1)
139nvc3_tpc_mmio_tail: 145nvc3_tpc_mmio_tail:
140mmctx_data(0x000544, 1) 146mmctx_data(0x000544, 1)
141nvc1_tpc_mmio_tail: 147nvc1_tpc_mmio_tail:
diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
index 1896c898f5ba..6f820324480e 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
@@ -25,23 +25,26 @@ uint32_t nvc0_grgpc_data[] = {
25 0x00000000, 25 0x00000000,
26 0x00000000, 26 0x00000000,
27 0x000000c0, 27 0x000000c0,
28 0x011000b0, 28 0x011c00bc,
29 0x01640114, 29 0x01700120,
30 0x000000c1, 30 0x000000c1,
31 0x011400b0, 31 0x012000bc,
32 0x01780114, 32 0x01840120,
33 0x000000c3, 33 0x000000c3,
34 0x011000b0, 34 0x011c00bc,
35 0x01740114, 35 0x01800120,
36 0x000000c4, 36 0x000000c4,
37 0x011000b0, 37 0x011c00bc,
38 0x01740114, 38 0x01800120,
39 0x000000c8, 39 0x000000c8,
40 0x011000b0, 40 0x011c00bc,
41 0x01640114, 41 0x01700120,
42 0x000000ce, 42 0x000000ce,
43 0x011000b0, 43 0x011c00bc,
44 0x01740114, 44 0x01800120,
45 0x000000cf,
46 0x011c00bc,
47 0x017c0120,
45 0x00000000, 48 0x00000000,
46 0x00000380, 49 0x00000380,
47 0x14000400, 50 0x14000400,
@@ -90,8 +93,8 @@ uint32_t nvc0_grgpc_data[] = {
90 0x04000750, 93 0x04000750,
91 0x00000758, 94 0x00000758,
92 0x000002c4, 95 0x000002c4,
93 0x000004bc,
94 0x000006e0, 96 0x000006e0,
97 0x000004bc,
95 0x00000544, 98 0x00000544,
96}; 99};
97 100
diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
index a1a599124cf4..e4f8c7e89ddd 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
@@ -56,6 +56,9 @@ chipsets:
56.b8 0xce 0 0 0 56.b8 0xce 0 0 0
57.b16 nvc0_hub_mmio_head 57.b16 nvc0_hub_mmio_head
58.b16 nvc0_hub_mmio_tail 58.b16 nvc0_hub_mmio_tail
59.b8 0xcf 0 0 0
60.b16 nvc0_hub_mmio_head
61.b16 nvc0_hub_mmio_tail
59.b8 0 0 0 0 62.b8 0 0 0 0
60 63
61nvc0_hub_mmio_head: 64nvc0_hub_mmio_head:
diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
index b3b541b6d044..241d3263f1e5 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
@@ -23,17 +23,19 @@ uint32_t nvc0_grhub_data[] = {
23 0x00000000, 23 0x00000000,
24 0x00000000, 24 0x00000000,
25 0x000000c0, 25 0x000000c0,
26 0x012c0090, 26 0x01340098,
27 0x000000c1, 27 0x000000c1,
28 0x01300090, 28 0x01380098,
29 0x000000c3, 29 0x000000c3,
30 0x012c0090, 30 0x01340098,
31 0x000000c4, 31 0x000000c4,
32 0x012c0090, 32 0x01340098,
33 0x000000c8, 33 0x000000c8,
34 0x012c0090, 34 0x01340098,
35 0x000000ce, 35 0x000000ce,
36 0x012c0090, 36 0x01340098,
37 0x000000cf,
38 0x01340098,
37 0x00000000, 39 0x00000000,
38 0x0417e91c, 40 0x0417e91c,
39 0x04400204, 41 0x04400204,
@@ -190,8 +192,6 @@ uint32_t nvc0_grhub_data[] = {
190 0x00000000, 192 0x00000000,
191 0x00000000, 193 0x00000000,
192 0x00000000, 194 0x00000000,
193 0x00000000,
194 0x00000000,
195}; 195};
196 196
197uint32_t nvc0_grhub_code[] = { 197uint32_t nvc0_grhub_code[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 12:39:15 -0500