54 files changed, 757 insertions, 238 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index e930d4fe29c7..1ef5ab9c9d51 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -145,6 +145,7 @@ exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
        plane->crtc = crtc;
        plane->fb = crtc->primary->fb;
+        drm_framebuffer_reference(plane->fb);
        return 0;
 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
index c786cd4f457b..2a3ad24276f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
@@ -263,7 +263,7 @@ struct drm_gem_object *exynos_dmabuf_prime_import(struct drm_device *drm_dev,
        buffer->sgt = sgt;
        exynos_gem_obj->base.import_attach = attach;
-        DRM_DEBUG_PRIME("dma_addr = 0x%x, size = 0x%lx\n", buffer->dma_addr,
+        DRM_DEBUG_PRIME("dma_addr = %pad, size = 0x%lx\n", &buffer->dma_addr,
                                                                buffer->size);
        return &exynos_gem_obj->base;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index eb73e3bf2a0c..4ac438187568 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1426,9 +1426,9 @@ static int exynos_dsi_probe(struct platform_device *pdev)
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        dsi->reg_base = devm_ioremap_resource(&pdev->dev, res);
-        if (!dsi->reg_base) {
+        if (IS_ERR(dsi->reg_base)) {
                dev_err(&pdev->dev, "failed to remap io region\n");
-                return -EADDRNOTAVAIL;
+                return PTR_ERR(dsi->reg_base);
        }
        dsi->phy = devm_phy_get(&pdev->dev, "dsim");
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 7afead9c3f30..852f2dadaebd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -220,7 +220,7 @@ static void vidi_win_commit(struct exynos_drm_manager *mgr, int zpos)
        win_data->enabled = true;
-        DRM_DEBUG_KMS("dma_addr = 0x%x\n", win_data->dma_addr);
+        DRM_DEBUG_KMS("dma_addr = %pad\n", &win_data->dma_addr);
        if (ctx->vblank_on)
                schedule_work(&ctx->work);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec82f6bff122..108e1ec2fa4b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1954,6 +1954,9 @@ struct drm_i915_cmd_table {
 #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0x00F0) == 0x0020)
+/* ULX machines are also considered ULT. */
+#define IS_HSW_ULX(dev)         ((dev)->pdev->device == 0x0A0E || \
+                                 (dev)->pdev->device == 0x0A1E)
 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
 /*
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ab5e93c30aa2..154b0f8bb88d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -34,25 +34,35 @@ static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
 {
-        if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
+        if (i915.enable_ppgtt == 0)
                return false;
        if (i915.enable_ppgtt == 1 && full)
                return false;
+        return true;
+}
+static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+{
+        if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
+                return 0;
+        if (enable_ppgtt == 1)
+                return 1;
+        if (enable_ppgtt == 2 && HAS_PPGTT(dev))
+                return 2;
 #ifdef CONFIG_INTEL_IOMMU
        /* Disable ppgtt on SNB if VT-d is on. */
        if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
                DRM_INFO("Disabling PPGTT because VT-d is on\n");
-                return false;
+                return 0;
        }
 #endif
-        /* Full ppgtt disabled by default for now due to issues. */
+        return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
-        if (full)
-                return false; /* HAS_PPGTT(dev) */
-        else
-                return HAS_ALIASING_PPGTT(dev);
 }
 #define GEN6_PPGTT_PD_ENTRIES 512
@@ -2031,6 +2041,14 @@ int i915_gem_gtt_init(struct drm_device *dev)
                 gtt->base.total >> 20);
        DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
        DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
+        /*
+         * i915.enable_ppgtt is read-only, so do an early pass to validate the
+         * user's requested state against the hardware/driver capabilities.  We
+         * do this now so that we can print out any log messages once rather
+         * than every time we check intel_enable_ppgtt().
+         */
+        i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
+        DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
        return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7753249b3a95..f98ba4e6e70b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1362,10 +1362,20 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev,
        spin_lock(&dev_priv->irq_lock);
        for (i = 1; i < HPD_NUM_PINS; i++) {
-                WARN_ONCE(hpd[i] & hotplug_trigger &&
+                if (hpd[i] & hotplug_trigger &&
-                          dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
+                    dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
-                          "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
+                        /*
-                          hotplug_trigger, i, hpd[i]);
+                         * On GMCH platforms the interrupt mask bits only
+                         * prevent irq generation, not the setting of the
+                         * hotplug bits itself. So only WARN about unexpected
+                         * interrupts on saner platforms.
+                         */
+                        WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
+                                  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
+                                  hotplug_trigger, i, hpd[i]);
+                        continue;
+                }
                if (!(hpd[i] & hotplug_trigger) ||
                    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f5b18d9d885..c77af69c2d8f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -827,6 +827,7 @@ enum punit_power_well {
 # define MI_FLUSH_ENABLE                                (1 << 12)
 # define ASYNC_FLIP_PERF_DISABLE                        (1 << 14)
 # define MODE_IDLE                                      (1 << 9)
+# define STOP_RING                                      (1 << 8)
 #define GEN6_GT_MODE    0x20d0
 #define GEN7_GT_MODE    0x7008
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dae976f51d83..48aa516a1ac0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9654,11 +9654,22 @@ intel_pipe_config_compare(struct drm_device *dev,
        PIPE_CONF_CHECK_I(pipe_src_w);
        PIPE_CONF_CHECK_I(pipe_src_h);
-        PIPE_CONF_CHECK_I(gmch_pfit.control);
+        /*
-        /* pfit ratios are autocomputed by the hw on gen4+ */
+         * FIXME: BIOS likes to set up a cloned config with lvds+external
-        if (INTEL_INFO(dev)->gen < 4)
+         * screen. Since we don't yet re-compute the pipe config when moving
-                PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
+         * just the lvds port away to another pipe the sw tracking won't match.
-        PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
+         *
+         * Proper atomic modesets with recomputed global state will fix this.
+         * Until then just don't check gmch state for inherited modes.
+         */
+        if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
+                PIPE_CONF_CHECK_I(gmch_pfit.control);
+                /* pfit ratios are autocomputed by the hw on gen4+ */
+                if (INTEL_INFO(dev)->gen < 4)
+                        PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
+                PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
+        }
        PIPE_CONF_CHECK_I(pch_pfit.enabled);
        if (current_config->pch_pfit.enabled) {
                PIPE_CONF_CHECK_I(pch_pfit.pos);
@@ -11384,15 +11395,6 @@ void intel_modeset_init(struct drm_device *dev)
        }
 }
-static void
-intel_connector_break_all_links(struct intel_connector *connector)
-{
-        connector->base.dpms = DRM_MODE_DPMS_OFF;
-        connector->base.encoder = NULL;
-        connector->encoder->connectors_active = false;
-        connector->encoder->base.crtc = NULL;
-}
 static void intel_enable_pipe_a(struct drm_device *dev)
 {
        struct intel_connector *connector;
@@ -11474,8 +11476,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
                        if (connector->encoder->base.crtc != &crtc->base)
                                continue;
-                        intel_connector_break_all_links(connector);
+                        connector->base.dpms = DRM_MODE_DPMS_OFF;
+                        connector->base.encoder = NULL;
                }
+                /* multiple connectors may have the same encoder:
+                 *  handle them and break crtc link separately */
+                list_for_each_entry(connector, &dev->mode_config.connector_list,
+                                    base.head)
+                        if (connector->encoder->base.crtc == &crtc->base) {
+                                connector->encoder->base.crtc = NULL;
+                                connector->encoder->connectors_active = false;
+                        }
                WARN_ON(crtc->active);
                crtc->base.enabled = false;
@@ -11557,6 +11568,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
                                      drm_get_encoder_name(&encoder->base));
                        encoder->disable(encoder);
                }
+                encoder->base.crtc = NULL;
+                encoder->connectors_active = false;
                /* Inconsistent output/port/pipe state happens presumably due to
                 * a bug in one of the get_hw_state functions. Or someplace else
@@ -11567,8 +11580,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
                                    base.head) {
                        if (connector->encoder != encoder)
                                continue;
+                        connector->base.dpms = DRM_MODE_DPMS_OFF;
-                        intel_connector_break_all_links(connector);
+                        connector->base.encoder = NULL;
                }
        }
        /* Enabled encoders without active connectors will be fixed in
@@ -11616,6 +11629,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                            base.head) {
                memset(&crtc->config, 0, sizeof(crtc->config));
+                crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
                crtc->active = dev_priv->display.get_pipe_config(crtc,
                                                                 &crtc->config);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d2a55884ad52..5ca68aa9f237 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
        case DP_LINK_BW_2_7:
                break;
        case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-                if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
+                if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
+                     INTEL_INFO(dev)->gen >= 8) &&
                    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
                        max_link_bw = DP_LINK_BW_5_4;
                else
@@ -3619,7 +3620,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 {
        struct drm_connector *connector = &intel_connector->base;
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-        struct drm_device *dev = intel_dig_port->base.base.dev;
+        struct intel_encoder *intel_encoder = &intel_dig_port->base;
+        struct drm_device *dev = intel_encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_display_mode *fixed_mode = NULL;
        bool has_dpcd;
@@ -3629,6 +3631,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
        if (!is_edp(intel_dp))
                return true;
+        /* The VDD bit needs a power domain reference, so if the bit is already
+         * enabled when we boot, grab this reference. */
+        if (edp_have_panel_vdd(intel_dp)) {
+                enum intel_display_power_domain power_domain;
+                power_domain = intel_display_port_power_domain(intel_encoder);
+                intel_display_power_get(dev_priv, power_domain);
+        }
        /* Cache DPCD and EDID for edp. */
        intel_edp_panel_vdd_on(intel_dp);
        has_dpcd = intel_dp_get_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0542de982260..328b1a70264b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -236,7 +236,8 @@ struct intel_crtc_config {
         * tracked with quirk flags so that fastboot and state checker can act
         * accordingly.
         */
-#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
+#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
+#define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
        unsigned long quirks;
        /* User requested mode, only valid as a starting point to
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b4d44e62f0c7..fce4a0d93c0b 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -132,6 +132,16 @@ static int intelfb_create(struct drm_fb_helper *helper,
        mutex_lock(&dev->struct_mutex);
+        if (intel_fb &&
+            (sizes->fb_width > intel_fb->base.width ||
+             sizes->fb_height > intel_fb->base.height)) {
+                DRM_DEBUG_KMS("BIOS fb too small (%dx%d), we require (%dx%d),"
+                              " releasing it\n",
+                              intel_fb->base.width, intel_fb->base.height,
+                              sizes->fb_width, sizes->fb_height);
+                drm_framebuffer_unreference(&intel_fb->base);
+                intel_fb = ifbdev->fb = NULL;
+        }
        if (!intel_fb || WARN_ON(!intel_fb->obj)) {
                DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
                ret = intelfb_alloc(helper, sizes);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b0413e190625..157267aa3561 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -821,11 +821,11 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
        }
 }
-static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
+static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 {
        struct drm_device *dev = intel_hdmi_to_dev(hdmi);
-        if (!hdmi->has_hdmi_sink || IS_G4X(dev))
+        if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
                return 165000;
        else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
                return 300000;
@@ -837,7 +837,8 @@ static enum drm_mode_status
 intel_hdmi_mode_valid(struct drm_connector *connector,
                      struct drm_display_mode *mode)
 {
-        if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
+        if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
+                                               true))
                return MODE_CLOCK_HIGH;
        if (mode->clock < 20000)
                return MODE_CLOCK_LOW;
@@ -879,7 +880,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
        struct drm_device *dev = encoder->base.dev;
        struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
        int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
-        int portclock_limit = hdmi_portclock_limit(intel_hdmi);
+        int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
        int desired_bpp;
        if (intel_hdmi->color_range_auto) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6bc68bdcf433..79fb4cc2137c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -437,32 +437,41 @@ static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
        I915_WRITE(HWS_PGA, addr);
 }
-static int init_ring_common(struct intel_ring_buffer *ring)
+static bool stop_ring(struct intel_ring_buffer *ring)
 {
-        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = to_i915(ring->dev);
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        struct drm_i915_gem_object *obj = ring->obj;
-        int ret = 0;
-        u32 head;
-        gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+        if (!IS_GEN2(ring->dev)) {
+                I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
+                if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
+                        DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
+                        return false;
+                }
+        }
-        /* Stop the ring if it's running. */
        I915_WRITE_CTL(ring, 0);
        I915_WRITE_HEAD(ring, 0);
        ring->write_tail(ring, 0);
-        if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
-                DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
-        if (I915_NEED_GFX_HWS(dev))
+        if (!IS_GEN2(ring->dev)) {
-                intel_ring_setup_status_page(ring);
+                (void)I915_READ_CTL(ring);
-        else
+                I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
-                ring_setup_phys_status_page(ring);
+        }
-        head = I915_READ_HEAD(ring) & HEAD_ADDR;
+        return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
+}
-        /* G45 ring initialization fails to reset head to zero */
+static int init_ring_common(struct intel_ring_buffer *ring)
-        if (head != 0) {
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_i915_gem_object *obj = ring->obj;
+        int ret = 0;
+        gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+        if (!stop_ring(ring)) {
+                /* G45 ring initialization often fails to reset head to zero */
                DRM_DEBUG_KMS("%s head not reset to zero "
                              "ctl %08x head %08x tail %08x start %08x\n",
                              ring->name,
@@ -471,9 +480,7 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                              I915_READ_TAIL(ring),
                              I915_READ_START(ring));
-                I915_WRITE_HEAD(ring, 0);
+                if (!stop_ring(ring)) {
-                if (I915_READ_HEAD(ring) & HEAD_ADDR) {
                        DRM_ERROR("failed to set %s head to zero "
                                  "ctl %08x head %08x tail %08x start %08x\n",
                                  ring->name,
@@ -481,9 +488,16 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                                  I915_READ_HEAD(ring),
                                  I915_READ_TAIL(ring),
                                  I915_READ_START(ring));
+                        ret = -EIO;
+                        goto out;
                }
        }
+        if (I915_NEED_GFX_HWS(dev))
+                intel_ring_setup_status_page(ring);
+        else
+                ring_setup_phys_status_page(ring);
        /* Initialize the ring. This must happen _after_ we've cleared the ring
         * registers with the above sequence (the readback of the HEAD registers
         * also enforces ordering), otherwise the hw might lose the new ring
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 270a6a973438..2b91c4b4d34b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -34,6 +34,7 @@ struct  intel_hw_status_page {
 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
+#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
 enum intel_ring_hangcheck_action {
        HANGCHECK_IDLE = 0,
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index 3e6c0f3ed592..ef9957dbac94 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -510,9 +510,8 @@ static void update_cursor(struct drm_crtc *crtc)
                                        MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
                } else {
                        /* disable cursor: */
-                        mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), 0);
+                        mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
-                        mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
+                                        mdp4_kms->blank_cursor_iova);
-                                        MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB));
                }
                /* and drop the iova ref + obj rev when done scanning out: */
@@ -574,11 +573,9 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
        if (old_bo) {
                /* drop our previous reference: */
-                msm_gem_put_iova(old_bo, mdp4_kms->id);
+                drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
-                drm_gem_object_unreference_unlocked(old_bo);
        }
-        crtc_flush(crtc);
        request_pending(crtc, PENDING_CURSOR);
        return 0;
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c
index c740ccd1cc67..8edd531cb621 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c
@@ -70,12 +70,12 @@ irqreturn_t mdp4_irq(struct msm_kms *kms)
        VERB("status=%08x", status);
+        mdp_dispatch_irqs(mdp_kms, status);
        for (id = 0; id < priv->num_crtcs; id++)
                if (status & mdp4_crtc_vblank(priv->crtcs[id]))
                        drm_handle_vblank(dev, id);
-        mdp_dispatch_irqs(mdp_kms, status);
        return IRQ_HANDLED;
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
index 272e707c9487..0bb4faa17523 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
@@ -144,6 +144,10 @@ static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 static void mdp4_destroy(struct msm_kms *kms)
 {
        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
+        if (mdp4_kms->blank_cursor_iova)
+                msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
+        if (mdp4_kms->blank_cursor_bo)
+                drm_gem_object_unreference(mdp4_kms->blank_cursor_bo);
        kfree(mdp4_kms);
 }
@@ -372,6 +376,23 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
                goto fail;
        }
+        mutex_lock(&dev->struct_mutex);
+        mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
+        mutex_unlock(&dev->struct_mutex);
+        if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
+                ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
+                dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
+                mdp4_kms->blank_cursor_bo = NULL;
+                goto fail;
+        }
+        ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
+                        &mdp4_kms->blank_cursor_iova);
+        if (ret) {
+                dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
+                goto fail;
+        }
        return kms;
 fail:
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
index 66a4d31aec80..715520c54cde 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
@@ -44,6 +44,10 @@ struct mdp4_kms {
        struct clk *lut_clk;
        struct mdp_irq error_handler;
+        /* empty/blank cursor bo to use when cursor is "disabled" */
+        struct drm_gem_object *blank_cursor_bo;
+        uint32_t blank_cursor_iova;
 };
 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index 353d494a497f..f2b985bc2adf 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -71,11 +71,11 @@ static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
        VERB("status=%08x", status);
+        mdp_dispatch_irqs(mdp_kms, status);
        for (id = 0; id < priv->num_crtcs; id++)
                if (status & mdp5_crtc_vblank(priv->crtcs[id]))
                        drm_handle_vblank(dev, id);
-        mdp_dispatch_irqs(mdp_kms, status);
 }
 irqreturn_t mdp5_irq(struct msm_kms *kms)
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index 6c6d7d4c9b4e..a752ab83b810 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -62,11 +62,8 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
        dma_addr_t paddr;
        int ret, size;
-        /* only doing ARGB32 since this is what is needed to alpha-blend
-         * with video overlays:
-         */
        sizes->surface_bpp = 32;
-        sizes->surface_depth = 32;
+        sizes->surface_depth = 24;
        DBG("create fbdev: %dx%d@%d (%dx%d)", sizes->surface_width,
                        sizes->surface_height, sizes->surface_bpp,
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 3da8264d3039..bb8026daebc9 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -118,8 +118,10 @@ static void put_pages(struct drm_gem_object *obj)
                if (iommu_present(&platform_bus_type))
                        drm_gem_put_pages(obj, msm_obj->pages, true, false);
-                else
+                else {
                        drm_mm_remove_node(msm_obj->vram_node);
+                        drm_free_large(msm_obj->pages);
+                }
                msm_obj->pages = NULL;
        }
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
index 1dc37b1ddbfa..b0d0fb2f4d08 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
@@ -863,7 +863,7 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 {
        mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
-        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
+        mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);
        mmio_list(0x40800c, 0x00000000,  8, 1);
        mmio_list(0x408010, 0x80000000,  0, 0);
@@ -877,6 +877,8 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
        mmio_list(0x418e24, 0x00000000,  8, 0);
        mmio_list(0x418e28, 0x80000030,  0, 0);
+        mmio_list(0x4064c8, 0x018002c0,  0, 0);
        mmio_list(0x418810, 0x80000000, 12, 2);
        mmio_list(0x419848, 0x10000000, 12, 2);
        mmio_list(0x419c2c, 0x10000000, 12, 2);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index fb0b6b2d1427..222e8ebb669d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -168,7 +168,8 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
         */
        i = 16;
        do {
-                if ((nv_rd32(bios, 0x300000) & 0xffff) == 0xaa55)
+                u32 data = le32_to_cpu(nv_rd32(bios, 0x300000)) & 0xffff;
+                if (data == 0xaa55)
                        break;
        } while (i--);
@@ -176,14 +177,15 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
                goto out;
        /* read entire bios image to system memory */
-        bios->size = ((nv_rd32(bios, 0x300000) >> 16) & 0xff) * 512;
+        bios->size = (le32_to_cpu(nv_rd32(bios, 0x300000)) >> 16) & 0xff;
+        bios->size = bios->size * 512;
        if (!bios->size)
                goto out;
        bios->data = kmalloc(bios->size, GFP_KERNEL);
        if (bios->data) {
-                for (i = 0; i < bios->size; i+=4)
+                for (i = 0; i < bios->size; i += 4)
-                        nv_wo32(bios, i, nv_rd32(bios, 0x300000 + i));
+                        ((u32 *)bios->data)[i/4] = nv_rd32(bios, 0x300000 + i);
        }
        /* check the PCI record header */
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 83face3f608f..279206997e5c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -389,9 +389,6 @@ bool nouveau_acpi_rom_supported(struct pci_dev *pdev)
        acpi_status status;
        acpi_handle dhandle, rom_handle;
-        if (!nouveau_dsm_priv.dsm_detected && !nouveau_dsm_priv.optimus_detected)
-                return false;
        dhandle = ACPI_HANDLE(&pdev->dev);
        if (!dhandle)
                return false;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 3ff030dc1ee3..da764a4ed958 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -764,9 +764,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
        }
        ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
-        mutex_unlock(&chan->cli->mutex);
        if (ret)
                goto fail_unreserve;
+        mutex_unlock(&chan->cli->mutex);
        /* Update the crtc struct and cleanup */
        crtc->primary->fb = fb;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index fb187c78978f..c31c12b4e666 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1177,27 +1177,43 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
                /* Set NUM_BANKS. */
                if (rdev->family >= CHIP_TAHITI) {
-                        unsigned tileb, index, num_banks, tile_split_bytes;
+                        unsigned index, num_banks;
-                        /* Calculate the macrotile mode index. */
+                        if (rdev->family >= CHIP_BONAIRE) {
-                        tile_split_bytes = 64 << tile_split;
+                                unsigned tileb, tile_split_bytes;
-                        tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
-                        tileb = min(tile_split_bytes, tileb);
-                        for (index = 0; tileb > 64; index++) {
+                                /* Calculate the macrotile mode index. */
-                                tileb >>= 1;
+                                tile_split_bytes = 64 << tile_split;
-                        }
+                                tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
+                                tileb = min(tile_split_bytes, tileb);
-                        if (index >= 16) {
+                                for (index = 0; tileb > 64; index++)
-                                DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
+                                        tileb >>= 1;
-                                          target_fb->bits_per_pixel, tile_split);
-                                return -EINVAL;
+                                if (index >= 16) {
-                        }
+                                        DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
+                                                  target_fb->bits_per_pixel, tile_split);
+                                        return -EINVAL;
+                                }
-                        if (rdev->family >= CHIP_BONAIRE)
                                num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
-                        else
+                        } else {
+                                switch (target_fb->bits_per_pixel) {
+                                case 8:
+                                        index = 10;
+                                        break;
+                                case 16:
+                                        index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
+                                        break;
+                                default:
+                                case 32:
+                                        index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
+                                        break;
+                                }
                                num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
+                        }
                        fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
                } else {
                        /* NI and older. */
@@ -1720,8 +1736,9 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
                }
                /* otherwise, pick one of the plls */
                if ((rdev->family == CHIP_KAVERI) ||
-                    (rdev->family == CHIP_KABINI)) {
+                    (rdev->family == CHIP_KABINI) ||
-                        /* KB/KV has PPLL1 and PPLL2 */
+                    (rdev->family == CHIP_MULLINS)) {
+                        /* KB/KV/ML has PPLL1 and PPLL2 */
                        pll_in_use = radeon_get_pll_use_mask(crtc);
                        if (!(pll_in_use & (1 << ATOM_PPLL2)))
                                return ATOM_PPLL2;
@@ -1885,6 +1902,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
            (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
                is_tvcv = true;
+        if (!radeon_crtc->adjusted_clock)
+                return -EINVAL;
        atombios_crtc_set_pll(crtc, adjusted_mode);
        if (ASIC_IS_DCE4(rdev))
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 15936524f226..54e4f52549af 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -209,6 +209,7 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 {
        int ret;
+        radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
        radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
        radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
        ret = drm_dp_aux_register_i2c_bus(&radeon_connector->ddc_bus->aux);
@@ -365,11 +366,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
        if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
                return;
-        if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3))
+        if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
                DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
                              buf[0], buf[1], buf[2]);
-        if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3))
+        if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
                DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
                              buf[0], buf[1], buf[2]);
 }
@@ -418,21 +419,23 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
        if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
                /* DP bridge chips */
-                drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
+                if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
-                                  DP_EDP_CONFIGURATION_CAP, &tmp);
+                                      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
-                if (tmp & 1)
+                        if (tmp & 1)
-                        panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+                                panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
-                else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
+                        else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
-                         (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
+                                 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
-                        panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+                                panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
-                else
+                        else
-                        panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+                                panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+                }
        } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
                /* eDP */
-                drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
+                if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
-                                  DP_EDP_CONFIGURATION_CAP, &tmp);
+                                      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
-                if (tmp & 1)
+                        if (tmp & 1)
-                        panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+                                panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+                }
        }
        return panel_mode;
@@ -808,11 +811,15 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
        else
                dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
-        drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp);
+        if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
-        if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
+            == 1) {
-                dp_info.tp3_supported = true;
+                if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
-        else
+                        dp_info.tp3_supported = true;
+                else
+                        dp_info.tp3_supported = false;
+        } else {
                dp_info.tp3_supported = false;
+        }
        memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
        dp_info.rdev = rdev;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 199eb194716f..d2fd98968085 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -63,6 +63,12 @@ MODULE_FIRMWARE("radeon/KABINI_ce.bin");
 MODULE_FIRMWARE("radeon/KABINI_mec.bin");
 MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
 MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
+MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
+MODULE_FIRMWARE("radeon/MULLINS_me.bin");
+MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
+MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
+MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
+MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
 extern void r600_ih_ring_fini(struct radeon_device *rdev);
@@ -1473,6 +1479,43 @@ static const u32 hawaii_mgcg_cgcg_init[] =
        0xd80c, 0xff000ff0, 0x00000100
 };
+static const u32 godavari_golden_registers[] =
+{
+        0x55e4, 0xff607fff, 0xfc000100,
+        0x6ed8, 0x00010101, 0x00010000,
+        0x9830, 0xffffffff, 0x00000000,
+        0x98302, 0xf00fffff, 0x00000400,
+        0x6130, 0xffffffff, 0x00010000,
+        0x5bb0, 0x000000f0, 0x00000070,
+        0x5bc0, 0xf0311fff, 0x80300000,
+        0x98f8, 0x73773777, 0x12010001,
+        0x98fc, 0xffffffff, 0x00000010,
+        0x8030, 0x00001f0f, 0x0000100a,
+        0x2f48, 0x73773777, 0x12010001,
+        0x2408, 0x000fffff, 0x000c007f,
+        0x8a14, 0xf000003f, 0x00000007,
+        0x8b24, 0xffffffff, 0x00ff0fff,
+        0x30a04, 0x0000ff0f, 0x00000000,
+        0x28a4c, 0x07ffffff, 0x06000000,
+        0x4d8, 0x00000fff, 0x00000100,
+        0xd014, 0x00010000, 0x00810001,
+        0xd814, 0x00010000, 0x00810001,
+        0x3e78, 0x00000001, 0x00000002,
+        0xc768, 0x00000008, 0x00000008,
+        0xc770, 0x00000f00, 0x00000800,
+        0xc774, 0x00000f00, 0x00000800,
+        0xc798, 0x00ffffff, 0x00ff7fbf,
+        0xc79c, 0x00ffffff, 0x00ff7faf,
+        0x8c00, 0x000000ff, 0x00000001,
+        0x214f8, 0x01ff01ff, 0x00000002,
+        0x21498, 0x007ff800, 0x00200000,
+        0x2015c, 0xffffffff, 0x00000f40,
+        0x88c4, 0x001f3ae3, 0x00000082,
+        0x88d4, 0x0000001f, 0x00000010,
+        0x30934, 0xffffffff, 0x00000000
+};
 static void cik_init_golden_registers(struct radeon_device *rdev)
 {
        switch (rdev->family) {
@@ -1504,6 +1547,20 @@ static void cik_init_golden_registers(struct radeon_device *rdev)
                                                 kalindi_golden_spm_registers,
                                                 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
+        case CHIP_MULLINS:
+                radeon_program_register_sequence(rdev,
+                                                 kalindi_mgcg_cgcg_init,
+                                                 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+                radeon_program_register_sequence(rdev,
+                                                 godavari_golden_registers,
+                                                 (const u32)ARRAY_SIZE(godavari_golden_registers));
+                radeon_program_register_sequence(rdev,
+                                                 kalindi_golden_common_registers,
+                                                 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+                radeon_program_register_sequence(rdev,
+                                                 kalindi_golden_spm_registers,
+                                                 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+                break;
        case CHIP_KAVERI:
                radeon_program_register_sequence(rdev,
                                                 spectre_mgcg_cgcg_init,
@@ -1834,6 +1891,15 @@ static int cik_init_microcode(struct radeon_device *rdev)
                rlc_req_size = KB_RLC_UCODE_SIZE * 4;
                sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
                break;
+        case CHIP_MULLINS:
+                chip_name = "MULLINS";
+                pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
+                me_req_size = CIK_ME_UCODE_SIZE * 4;
+                ce_req_size = CIK_CE_UCODE_SIZE * 4;
+                mec_req_size = CIK_MEC_UCODE_SIZE * 4;
+                rlc_req_size = ML_RLC_UCODE_SIZE * 4;
+                sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
+                break;
        default: BUG();
        }
@@ -3272,6 +3338,7 @@ static void cik_gpu_init(struct radeon_device *rdev)
                gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
                break;
        case CHIP_KABINI:
+        case CHIP_MULLINS:
        default:
                rdev->config.cik.max_shader_engines = 1;
                rdev->config.cik.max_tile_pipes = 2;
@@ -3702,6 +3769,7 @@ int cik_copy_cpdma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
@@ -5800,6 +5868,9 @@ static int cik_rlc_resume(struct radeon_device *rdev)
        case CHIP_KABINI:
                size = KB_RLC_UCODE_SIZE;
                break;
+        case CHIP_MULLINS:
+                size = ML_RLC_UCODE_SIZE;
+                break;
        }
        cik_rlc_stop(rdev);
@@ -6548,6 +6619,7 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
                buffer[count++] = cpu_to_le32(0x00000000);
                break;
        case CHIP_KABINI:
+        case CHIP_MULLINS:
                buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
                buffer[count++] = cpu_to_le32(0x00000000);
                break;
@@ -6693,6 +6765,19 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
                WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
                WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
        }
+        /* pflip */
+        if (rdev->num_crtc >= 2) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+        }
+        if (rdev->num_crtc >= 4) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+        }
+        if (rdev->num_crtc >= 6) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+        }
        /* dac hotplug */
        WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
@@ -7049,6 +7134,25 @@ int cik_irq_set(struct radeon_device *rdev)
                WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
        }
+        if (rdev->num_crtc >= 2) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+        }
+        if (rdev->num_crtc >= 4) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+        }
+        if (rdev->num_crtc >= 6) {
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+        }
        WREG32(DC_HPD1_INT_CONTROL, hpd1);
        WREG32(DC_HPD2_INT_CONTROL, hpd2);
        WREG32(DC_HPD3_INT_CONTROL, hpd3);
@@ -7085,6 +7189,29 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
        rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
        rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
+        rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
+                EVERGREEN_CRTC0_REGISTER_OFFSET);
+        rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
+                EVERGREEN_CRTC1_REGISTER_OFFSET);
+        if (rdev->num_crtc >= 4) {
+                rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
+                        EVERGREEN_CRTC2_REGISTER_OFFSET);
+                rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
+                        EVERGREEN_CRTC3_REGISTER_OFFSET);
+        }
+        if (rdev->num_crtc >= 6) {
+                rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
+                        EVERGREEN_CRTC4_REGISTER_OFFSET);
+                rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
+                        EVERGREEN_CRTC5_REGISTER_OFFSET);
+        }
+        if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
+                WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_CLEAR);
+        if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
+                WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_CLEAR);
        if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
                WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
        if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
@@ -7095,6 +7222,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
                WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
        if (rdev->num_crtc >= 4) {
+                if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
+                        WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
+                               GRPH_PFLIP_INT_CLEAR);
+                if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
+                        WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
+                               GRPH_PFLIP_INT_CLEAR);
                if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
                        WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
                if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
@@ -7106,6 +7239,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
        }
        if (rdev->num_crtc >= 6) {
+                if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
+                        WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
+                               GRPH_PFLIP_INT_CLEAR);
+                if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
+                        WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
+                               GRPH_PFLIP_INT_CLEAR);
                if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
                        WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
                if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
@@ -7457,6 +7596,15 @@ restart_ih:
                                break;
                        }
                        break;
+                case 8: /* D1 page flip */
+                case 10: /* D2 page flip */
+                case 12: /* D3 page flip */
+                case 14: /* D4 page flip */
+                case 16: /* D5 page flip */
+                case 18: /* D6 page flip */
+                        DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
+                        radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+                        break;
                case 42: /* HPD hotplug */
                        switch (src_data) {
                        case 0:
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 89b4afa5041c..72e464c79a88 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -562,6 +562,7 @@ int cik_copy_dma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
@@ -597,7 +598,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
        tmp = 0xCAFEDEAD;
        writel(tmp, ptr);
-        r = radeon_ring_lock(rdev, ring, 4);
+        r = radeon_ring_lock(rdev, ring, 5);
        if (r) {
                DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
                return r;
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 213873270d5f..dd7926394a8f 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -888,6 +888,15 @@
 #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
 #define DISP_INTERRUPT_STATUS_CONTINUE6                 0x6780
+/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
+#define GRPH_INT_STATUS                                 0x6858
+#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
+#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
+/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
+#define GRPH_INT_CONTROL                                0x685c
+#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
+#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
 #define DAC_AUTODETECT_INT_CONTROL                      0x67c8
 #define DC_HPD1_INT_STATUS                              0x601c
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index b406546440da..0f7a51a3694f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4371,7 +4371,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
        u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
        u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
        u32 grbm_int_cntl = 0;
-        u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
        u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
        u32 dma_cntl, dma_cntl1 = 0;
        u32 thermal_int = 0;
@@ -4554,15 +4553,21 @@ int evergreen_irq_set(struct radeon_device *rdev)
                WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
        }
-        WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
+        WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-        WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
+               GRPH_PFLIP_INT_MASK);
+        WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
+               GRPH_PFLIP_INT_MASK);
        if (rdev->num_crtc >= 4) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
        }
        if (rdev->num_crtc >= 6) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
        }
        WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -4951,6 +4956,15 @@ restart_ih:
                                break;
                        }
                        break;
+                case 8: /* D1 page flip */
+                case 10: /* D2 page flip */
+                case 12: /* D3 page flip */
+                case 14: /* D4 page flip */
+                case 16: /* D5 page flip */
+                case 18: /* D6 page flip */
+                        DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
+                        radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+                        break;
                case 42: /* HPD hotplug */
                        switch (src_data) {
                        case 0:
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c
index 287fe966d7de..478caefe0fef 100644
--- a/drivers/gpu/drm/radeon/evergreen_dma.c
+++ b/drivers/gpu/drm/radeon/evergreen_dma.c
@@ -151,6 +151,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index 16ec9d56a234..3f6e817d97ee 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -546,6 +546,52 @@ static int kv_set_divider_value(struct radeon_device *rdev,
        return 0;
 }
+static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
+                                   struct sumo_vid_mapping_table *vid_mapping_table,
+                                   u32 vid_2bit)
+{
+        struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
+                &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
+        u32 i;
+        if (vddc_sclk_table && vddc_sclk_table->count) {
+                if (vid_2bit < vddc_sclk_table->count)
+                        return vddc_sclk_table->entries[vid_2bit].v;
+                else
+                        return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
+        } else {
+                for (i = 0; i < vid_mapping_table->num_entries; i++) {
+                        if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
+                                return vid_mapping_table->entries[i].vid_7bit;
+                }
+                return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
+        }
+}
+static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
+                                   struct sumo_vid_mapping_table *vid_mapping_table,
+                                   u32 vid_7bit)
+{
+        struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
+                &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
+        u32 i;
+        if (vddc_sclk_table && vddc_sclk_table->count) {
+                for (i = 0; i < vddc_sclk_table->count; i++) {
+                        if (vddc_sclk_table->entries[i].v == vid_7bit)
+                                return i;
+                }
+                return vddc_sclk_table->count - 1;
+        } else {
+                for (i = 0; i < vid_mapping_table->num_entries; i++) {
+                        if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
+                                return vid_mapping_table->entries[i].vid_2bit;
+                }
+                return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
+        }
+}
 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
                                            u16 voltage)
 {
@@ -556,9 +602,9 @@ static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
                                            u32 vid_2bit)
 {
        struct kv_power_info *pi = kv_get_pi(rdev);
-        u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
+        u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
-                                                 &pi->sys_info.vid_mapping_table,
+                                               &pi->sys_info.vid_mapping_table,
-                                                 vid_2bit);
+                                               vid_2bit);
        return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
 }
@@ -639,7 +685,7 @@ static int kv_force_lowest_valid(struct radeon_device *rdev)
 static int kv_unforce_levels(struct radeon_device *rdev)
 {
-        if (rdev->family == CHIP_KABINI)
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
                return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
        else
                return kv_set_enabled_levels(rdev);
@@ -1362,13 +1408,20 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
        struct radeon_uvd_clock_voltage_dependency_table *table =
                &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
        int ret;
+        u32 mask;
        if (!gate) {
-                if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
+                if (table->count)
                        pi->uvd_boot_level = table->count - 1;
                else
                        pi->uvd_boot_level = 0;
+                if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
+                        mask = 1 << pi->uvd_boot_level;
+                } else {
+                        mask = 0x1f;
+                }
                ret = kv_copy_bytes_to_smc(rdev,
                                           pi->dpm_table_start +
                                           offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
@@ -1377,11 +1430,9 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
                if (ret)
                        return ret;
-                if (!pi->caps_uvd_dpm ||
+                kv_send_msg_to_smc_with_parameter(rdev,
-                    pi->caps_stable_p_state)
+                                                  PPSMC_MSG_UVDDPM_SetEnabledMask,
-                        kv_send_msg_to_smc_with_parameter(rdev,
+                                                  mask);
-                                                          PPSMC_MSG_UVDDPM_SetEnabledMask,
-                                                          (1 << pi->uvd_boot_level));
        }
        return kv_enable_uvd_dpm(rdev, !gate);
@@ -1617,7 +1668,7 @@ static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
        if (pi->acp_power_gated == gate)
                return;
-        if (rdev->family == CHIP_KABINI)
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
                return;
        pi->acp_power_gated = gate;
@@ -1786,7 +1837,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
                }
        }
-        if (rdev->family == CHIP_KABINI) {
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
                if (pi->enable_dpm) {
                        kv_set_valid_clock_range(rdev, new_ps);
                        kv_update_dfs_bypass_settings(rdev, new_ps);
@@ -1812,6 +1863,8 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
                                return ret;
                        }
                        kv_update_sclk_t(rdev);
+                        if (rdev->family == CHIP_MULLINS)
+                                kv_enable_nb_dpm(rdev);
                }
        } else {
                if (pi->enable_dpm) {
@@ -1862,7 +1915,7 @@ void kv_dpm_reset_asic(struct radeon_device *rdev)
 {
        struct kv_power_info *pi = kv_get_pi(rdev);
-        if (rdev->family == CHIP_KABINI) {
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
                kv_force_lowest_valid(rdev);
                kv_init_graphics_levels(rdev);
                kv_program_bootup_state(rdev);
@@ -1901,14 +1954,41 @@ static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
 static void kv_patch_voltage_values(struct radeon_device *rdev)
 {
        int i;
-        struct radeon_uvd_clock_voltage_dependency_table *table =
+        struct radeon_uvd_clock_voltage_dependency_table *uvd_table =
                &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
+        struct radeon_vce_clock_voltage_dependency_table *vce_table =
+                &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
+        struct radeon_clock_voltage_dependency_table *samu_table =
+                &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
+        struct radeon_clock_voltage_dependency_table *acp_table =
+                &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
-        if (table->count) {
+        if (uvd_table->count) {
-                for (i = 0; i < table->count; i++)
+                for (i = 0; i < uvd_table->count; i++)
-                        table->entries[i].v =
+                        uvd_table->entries[i].v =
                                kv_convert_8bit_index_to_voltage(rdev,
-                                                                 table->entries[i].v);
+                                                                 uvd_table->entries[i].v);
+        }
+        if (vce_table->count) {
+                for (i = 0; i < vce_table->count; i++)
+                        vce_table->entries[i].v =
+                                kv_convert_8bit_index_to_voltage(rdev,
+                                                                 vce_table->entries[i].v);
+        }
+        if (samu_table->count) {
+                for (i = 0; i < samu_table->count; i++)
+                        samu_table->entries[i].v =
+                                kv_convert_8bit_index_to_voltage(rdev,
+                                                                 samu_table->entries[i].v);
+        }
+        if (acp_table->count) {
+                for (i = 0; i < acp_table->count; i++)
+                        acp_table->entries[i].v =
+                                kv_convert_8bit_index_to_voltage(rdev,
+                                                                 acp_table->entries[i].v);
        }
 }
@@ -1941,7 +2021,7 @@ static int kv_force_dpm_highest(struct radeon_device *rdev)
                        break;
        }
-        if (rdev->family == CHIP_KABINI)
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
                return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
        else
                return kv_set_enabled_level(rdev, i);
@@ -1961,7 +2041,7 @@ static int kv_force_dpm_lowest(struct radeon_device *rdev)
                        break;
        }
-        if (rdev->family == CHIP_KABINI)
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
                return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
        else
                return kv_set_enabled_level(rdev, i);
@@ -2118,7 +2198,7 @@ static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
        else
                pi->battery_state = false;
-        if (rdev->family == CHIP_KABINI) {
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
                ps->dpm0_pg_nb_ps_lo = 0x1;
                ps->dpm0_pg_nb_ps_hi = 0x0;
                ps->dpmx_nb_ps_lo = 0x1;
@@ -2179,7 +2259,7 @@ static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
        if (pi->lowest_valid > pi->highest_valid)
                return -EINVAL;
-        if (rdev->family == CHIP_KABINI) {
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
                for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
                        pi->graphics_level[i].GnbSlow = 1;
                        pi->graphics_level[i].ForceNbPs1 = 0;
@@ -2253,9 +2333,9 @@ static void kv_init_graphics_levels(struct radeon_device *rdev)
                                break;
                        kv_set_divider_value(rdev, i, table->entries[i].clk);
-                        vid_2bit = sumo_convert_vid7_to_vid2(rdev,
+                        vid_2bit = kv_convert_vid7_to_vid2(rdev,
-                                                             &pi->sys_info.vid_mapping_table,
+                                                           &pi->sys_info.vid_mapping_table,
-                                                             table->entries[i].v);
+                                                           table->entries[i].v);
                        kv_set_vid(rdev, i, vid_2bit);
                        kv_set_at(rdev, i, pi->at[i]);
                        kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
@@ -2324,7 +2404,7 @@ static void kv_program_nbps_index_settings(struct radeon_device *rdev,
        struct kv_power_info *pi = kv_get_pi(rdev);
        u32 nbdpmconfig1;
-        if (rdev->family == CHIP_KABINI)
+        if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
                return;
        if (pi->sys_info.nb_dpm_enable) {
@@ -2631,9 +2711,6 @@ int kv_dpm_init(struct radeon_device *rdev)
        pi->sram_end = SMC_RAM_END;
-        if (rdev->family == CHIP_KABINI)
-                pi->high_voltage_t = 4001;
        pi->enable_nb_dpm = true;
        pi->caps_power_containment = true;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6e887d004eba..bbc189fd3ddc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2839,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
@@ -3505,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev)
        u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
        u32 grbm_int_cntl = 0;
        u32 hdmi0, hdmi1;
-        u32 d1grph = 0, d2grph = 0;
        u32 dma_cntl;
        u32 thermal_int = 0;
@@ -3614,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev)
        WREG32(CP_INT_CNTL, cp_int_cntl);
        WREG32(DMA_CNTL, dma_cntl);
        WREG32(DxMODE_INT_MASK, mode_int);
-        WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
+        WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
-        WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
+        WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
        WREG32(GRBM_INT_CNTL, grbm_int_cntl);
        if (ASIC_IS_DCE3(rdev)) {
                WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -3918,6 +3918,14 @@ restart_ih:
                                break;
                        }
                        break;
+                case 9: /* D1 pflip */
+                        DRM_DEBUG("IH: D1 flip\n");
+                        radeon_crtc_handle_flip(rdev, 0);
+                        break;
+                case 11: /* D2 pflip */
+                        DRM_DEBUG("IH: D2 flip\n");
+                        radeon_crtc_handle_flip(rdev, 1);
+                        break;
                case 19: /* HPD/DAC hotplug */
                        switch (src_data) {
                        case 0:
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index 53fcb28f5578..4969cef44a19 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -489,6 +489,7 @@ int r600_copy_dma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index cbf7e3269f84..9c61b74ef441 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -158,16 +158,18 @@ u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
        u32 line_time_us, vblank_lines;
        u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
-                radeon_crtc = to_radeon_crtc(crtc);
+                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-                if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
+                        radeon_crtc = to_radeon_crtc(crtc);
-                        line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
+                        if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
-                                radeon_crtc->hw_mode.clock;
+                                line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
-                        vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
+                                        radeon_crtc->hw_mode.clock;
-                                radeon_crtc->hw_mode.crtc_vdisplay +
+                                vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
-                                (radeon_crtc->v_border * 2);
+                                        radeon_crtc->hw_mode.crtc_vdisplay +
-                        vblank_time_us = vblank_lines * line_time_us;
+                                        (radeon_crtc->v_border * 2);
-                        break;
+                                vblank_time_us = vblank_lines * line_time_us;
+                                break;
+                        }
                }
        }
@@ -181,14 +183,15 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
        struct radeon_crtc *radeon_crtc;
        u32 vrefresh = 0;
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
-                radeon_crtc = to_radeon_crtc(crtc);
+                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-                if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
+                        radeon_crtc = to_radeon_crtc(crtc);
-                        vrefresh = radeon_crtc->hw_mode.vrefresh;
+                        if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
-                        break;
+                                vrefresh = radeon_crtc->hw_mode.vrefresh;
+                                break;
+                        }
                }
        }
        return vrefresh;
 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b58e1afdda76..68528619834a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -730,6 +730,12 @@ struct cik_irq_stat_regs {
        u32 disp_int_cont4;
        u32 disp_int_cont5;
        u32 disp_int_cont6;
+        u32 d1grph_int;
+        u32 d2grph_int;
+        u32 d3grph_int;
+        u32 d4grph_int;
+        u32 d5grph_int;
+        u32 d6grph_int;
 };
 union radeon_irq_stat_regs {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index b8a24a75d4ff..be20e62dac83 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2516,6 +2516,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                break;
        case CHIP_KAVERI:
        case CHIP_KABINI:
+        case CHIP_MULLINS:
                rdev->asic = &kv_asic;
                /* set num crtcs */
                if (rdev->family == CHIP_KAVERI) {
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index dedea72f48c4..a9fb0d016d38 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -528,6 +528,13 @@ static bool radeon_atpx_detect(void)
                has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
        }
+        /* some newer PX laptops mark the dGPU as a non-VGA display device */
+        while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
+                vga_count++;
+                has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
+        }
        if (has_atpx && vga_count == 2) {
                acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
                printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n",
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 511fe26198e4..0e770bbf7e29 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -99,6 +99,7 @@ static const char radeon_family_name[][16] = {
        "KAVERI",
        "KABINI",
        "HAWAII",
+        "MULLINS",
        "LAST",
 };
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 2f7cbb901fb1..408b6ac53f0b 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -284,6 +284,10 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
        u32 update_pending;
        int vpos, hpos;
+        /* can happen during initialization */
+        if (radeon_crtc == NULL)
+                return;
        spin_lock_irqsave(&rdev->ddev->event_lock, flags);
        work = radeon_crtc->unpin_work;
        if (work == NULL ||
@@ -826,20 +830,52 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
        /* make sure nominator is large enough */
        if (*nom < nom_min) {
-                tmp = (nom_min + *nom - 1) / *nom;
+                tmp = DIV_ROUND_UP(nom_min, *nom);
                *nom *= tmp;
                *den *= tmp;
        }
        /* make sure the denominator is large enough */
        if (*den < den_min) {
-                tmp = (den_min + *den - 1) / *den;
+                tmp = DIV_ROUND_UP(den_min, *den);
                *nom *= tmp;
                *den *= tmp;
        }
 }
 /**
+ * avivo_get_fb_ref_div - feedback and ref divider calculation
+ *
+ * @nom: nominator
+ * @den: denominator
+ * @post_div: post divider
+ * @fb_div_max: feedback divider maximum
+ * @ref_div_max: reference divider maximum
+ * @fb_div: resulting feedback divider
+ * @ref_div: resulting reference divider
+ *
+ * Calculate feedback and reference divider for a given post divider. Makes
+ * sure we stay within the limits.
+ */
+static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
+                                 unsigned fb_div_max, unsigned ref_div_max,
+                                 unsigned *fb_div, unsigned *ref_div)
+{
+        /* limit reference * post divider to a maximum */
+        ref_div_max = min(128 / post_div, ref_div_max);
+        /* get matching reference and feedback divider */
+        *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
+        *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
+        /* limit fb divider to its maximum */
+        if (*fb_div > fb_div_max) {
+                *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
+                *fb_div = fb_div_max;
+        }
+}
+/**
 * radeon_compute_pll_avivo - compute PLL paramaters
 *
 * @pll: information about the PLL
@@ -860,6 +896,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
                              u32 *ref_div_p,
                              u32 *post_div_p)
 {
+        unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
+                freq : freq / 10;
        unsigned fb_div_min, fb_div_max, fb_div;
        unsigned post_div_min, post_div_max, post_div;
        unsigned ref_div_min, ref_div_max, ref_div;
@@ -880,14 +919,18 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
                ref_div_min = pll->reference_div;
        else
                ref_div_min = pll->min_ref_div;
-        ref_div_max = pll->max_ref_div;
+        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
+            pll->flags & RADEON_PLL_USE_REF_DIV)
+                ref_div_max = pll->reference_div;
+        else
+                ref_div_max = pll->max_ref_div;
        /* determine allowed post divider range */
        if (pll->flags & RADEON_PLL_USE_POST_DIV) {
                post_div_min = pll->post_div;
                post_div_max = pll->post_div;
        } else {
-                unsigned target_clock = freq / 10;
                unsigned vco_min, vco_max;
                if (pll->flags & RADEON_PLL_IS_LCD) {
@@ -898,6 +941,11 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
                        vco_max = pll->pll_out_max;
                }
+                if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+                        vco_min *= 10;
+                        vco_max *= 10;
+                }
                post_div_min = vco_min / target_clock;
                if ((target_clock * post_div_min) < vco_min)
                        ++post_div_min;
@@ -912,7 +960,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
        }
        /* represent the searched ratio as fractional number */
-        nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
+        nom = target_clock;
        den = pll->reference_freq;
        /* reduce the numbers to a simpler ratio */
@@ -926,7 +974,12 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
        diff_best = ~0;
        for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
-                unsigned diff = abs(den - den / post_div * post_div);
+                unsigned diff;
+                avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
+                                     ref_div_max, &fb_div, &ref_div);
+                diff = abs(target_clock - (pll->reference_freq * fb_div) /
+                        (ref_div * post_div));
                if (diff < diff_best || (diff == diff_best &&
                    !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
@@ -936,33 +989,24 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
        }
        post_div = post_div_best;
-        /* limit reference * post divider to a maximum */
+        /* get the feedback and reference divider for the optimal value */
-        ref_div_max = min(210 / post_div, ref_div_max);
+        avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
+                             &fb_div, &ref_div);
-        /* get matching reference and feedback divider */
-        ref_div = max(DIV_ROUND_CLOSEST(den, post_div), 1u);
-        fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
-        /* we're almost done, but reference and feedback
-           divider might be to large now */
-        nom = fb_div;
-        den = ref_div;
-        if (fb_div > fb_div_max) {
-                ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
-                fb_div = fb_div_max;
-        }
-        if (ref_div > ref_div_max) {
-                ref_div = ref_div_max;
-                fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
-        }
        /* reduce the numbers to a simpler ratio once more */
        /* this also makes sure that the reference divider is large enough */
        avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
+        /* avoid high jitter with small fractional dividers */
+        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
+                fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
+                if (fb_div < fb_div_min) {
+                        unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
+                        fb_div *= tmp;
+                        ref_div *= tmp;
+                }
+        }
        /* and finally save the result */
        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
                *fb_div_p = fb_div / 10;
@@ -979,7 +1023,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
        *post_div_p = post_div;
        DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
-                      freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
+                      freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
                      ref_div, post_div);
 }
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 9da5da4ffd17..4b7b87f71a63 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -97,6 +97,7 @@ enum radeon_family {
        CHIP_KAVERI,
        CHIP_KABINI,
        CHIP_HAWAII,
+        CHIP_MULLINS,
        CHIP_LAST,
 };
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index fb3d13f693dd..0cc47f12d995 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -107,11 +107,9 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
                flags |= RADEON_IS_PCI;
        }
-        if (radeon_runtime_pm == 1)
+        if ((radeon_runtime_pm != 0) &&
-                flags |= RADEON_IS_PX;
+            radeon_has_atpx() &&
-        else if ((radeon_runtime_pm == -1) &&
+            ((flags & RADEON_IS_IGP) == 0))
-                 radeon_has_atpx() &&
-                 ((flags & RADEON_IS_IGP) == 0))
                flags |= RADEON_IS_PX;
        /* radeon_device_init should report only fatal error
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index ee738a524639..f30b8426eee2 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -603,7 +603,6 @@ static const struct attribute_group *hwmon_groups[] = {
 static int radeon_hwmon_init(struct radeon_device *rdev)
 {
        int err = 0;
-        struct device *hwmon_dev;
        switch (rdev->pm.int_thermal_type) {
        case THERMAL_TYPE_RV6XX:
@@ -616,11 +615,11 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
        case THERMAL_TYPE_KV:
                if (rdev->asic->pm.get_temperature == NULL)
                        return err;
-                hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
+                rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
-                                                              "radeon", rdev,
+                                                                           "radeon", rdev,
-                                                              hwmon_groups);
+                                                                           hwmon_groups);
-                if (IS_ERR(hwmon_dev)) {
+                if (IS_ERR(rdev->pm.int_hwmon_dev)) {
-                        err = PTR_ERR(hwmon_dev);
+                        err = PTR_ERR(rdev->pm.int_hwmon_dev);
                        dev_err(rdev->dev,
                                "Unable to register hwmon device: %d\n", err);
                }
@@ -632,6 +631,12 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
        return err;
 }
+static void radeon_hwmon_fini(struct radeon_device *rdev)
+{
+        if (rdev->pm.int_hwmon_dev)
+                hwmon_device_unregister(rdev->pm.int_hwmon_dev);
+}
 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 {
        struct radeon_device *rdev =
@@ -1257,6 +1262,7 @@ int radeon_pm_init(struct radeon_device *rdev)
        case CHIP_RV670:
        case CHIP_RS780:
        case CHIP_RS880:
+        case CHIP_RV770:
        case CHIP_BARTS:
        case CHIP_TURKS:
        case CHIP_CAICOS:
@@ -1273,7 +1279,6 @@ int radeon_pm_init(struct radeon_device *rdev)
                else
                        rdev->pm.pm_method = PM_METHOD_PROFILE;
                break;
-        case CHIP_RV770:
        case CHIP_RV730:
        case CHIP_RV710:
        case CHIP_RV740:
@@ -1295,6 +1300,7 @@ int radeon_pm_init(struct radeon_device *rdev)
        case CHIP_KABINI:
        case CHIP_KAVERI:
        case CHIP_HAWAII:
+        case CHIP_MULLINS:
                /* DPM requires the RLC, RV770+ dGPU requires SMC */
                if (!rdev->rlc_fw)
                        rdev->pm.pm_method = PM_METHOD_PROFILE;
@@ -1353,6 +1359,8 @@ static void radeon_pm_fini_old(struct radeon_device *rdev)
                device_remove_file(rdev->dev, &dev_attr_power_method);
        }
+        radeon_hwmon_fini(rdev);
        if (rdev->pm.power_state)
                kfree(rdev->pm.power_state);
 }
@@ -1372,6 +1380,8 @@ static void radeon_pm_fini_dpm(struct radeon_device *rdev)
        }
        radeon_dpm_fini(rdev);
+        radeon_hwmon_fini(rdev);
        if (rdev->pm.power_state)
                kfree(rdev->pm.power_state);
 }
@@ -1397,12 +1407,14 @@ static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
        rdev->pm.active_crtcs = 0;
        rdev->pm.active_crtc_count = 0;
-        list_for_each_entry(crtc,
+        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
-                &ddev->mode_config.crtc_list, head) {
+                list_for_each_entry(crtc,
-                radeon_crtc = to_radeon_crtc(crtc);
+                                    &ddev->mode_config.crtc_list, head) {
-                if (radeon_crtc->enabled) {
+                        radeon_crtc = to_radeon_crtc(crtc);
-                        rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
+                        if (radeon_crtc->enabled) {
-                        rdev->pm.active_crtc_count++;
+                                rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
+                                rdev->pm.active_crtc_count++;
+                        }
                }
        }
@@ -1469,12 +1481,14 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
        /* update active crtc counts */
        rdev->pm.dpm.new_active_crtcs = 0;
        rdev->pm.dpm.new_active_crtc_count = 0;
-        list_for_each_entry(crtc,
+        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
-                &ddev->mode_config.crtc_list, head) {
+                list_for_each_entry(crtc,
-                radeon_crtc = to_radeon_crtc(crtc);
+                                    &ddev->mode_config.crtc_list, head) {
-                if (crtc->enabled) {
+                        radeon_crtc = to_radeon_crtc(crtc);
-                        rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
+                        if (crtc->enabled) {
-                        rdev->pm.dpm.new_active_crtc_count++;
+                                rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
+                                rdev->pm.dpm.new_active_crtc_count++;
+                        }
                }
        }
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
index 58d12938c0b8..4e7c3269b183 100644
--- a/drivers/gpu/drm/radeon/radeon_ucode.h
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -52,6 +52,7 @@
 #define BONAIRE_RLC_UCODE_SIZE       2048
 #define KB_RLC_UCODE_SIZE            2560
 #define KV_RLC_UCODE_SIZE            2560
+#define ML_RLC_UCODE_SIZE            2560
 /* MC */
 #define BTC_MC_UCODE_SIZE            6024
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 5748bdaeacce..1b65ae2433cd 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -99,6 +99,7 @@ int radeon_uvd_init(struct radeon_device *rdev)
        case CHIP_KABINI:
        case CHIP_KAVERI:
        case CHIP_HAWAII:
+        case CHIP_MULLINS:
                fw_name = FIRMWARE_BONAIRE;
                break;
@@ -465,6 +466,10 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
        cmd = radeon_get_ib_value(p, p->idx) >> 1;
        if (cmd < 0x4) {
+                if (end <= start) {
+                        DRM_ERROR("invalid reloc offset %X!\n", offset);
+                        return -EINVAL;
+                }
                if ((end - start) < buf_sizes[cmd]) {
                        DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
                                  (unsigned)(end - start), buf_sizes[cmd]);
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c
index ced53dd03e7c..f73324c81491 100644
--- a/drivers/gpu/drm/radeon/radeon_vce.c
+++ b/drivers/gpu/drm/radeon/radeon_vce.c
@@ -66,6 +66,7 @@ int radeon_vce_init(struct radeon_device *rdev)
        case CHIP_BONAIRE:
        case CHIP_KAVERI:
        case CHIP_KABINI:
+        case CHIP_MULLINS:
                fw_name = FIRMWARE_BONAIRE;
                break;
diff --git a/drivers/gpu/drm/radeon/rv770_dma.c b/drivers/gpu/drm/radeon/rv770_dma.c
index aca8cbe8a335..bbf2e076ee45 100644
--- a/drivers/gpu/drm/radeon/rv770_dma.c
+++ b/drivers/gpu/drm/radeon/rv770_dma.c
@@ -86,6 +86,7 @@ int rv770_copy_dma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ac708e006180..22a63c98ba14 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5780,7 +5780,6 @@ int si_irq_set(struct radeon_device *rdev)
        u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
        u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
        u32 grbm_int_cntl = 0;
-        u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
        u32 dma_cntl, dma_cntl1;
        u32 thermal_int = 0;
@@ -5919,16 +5918,22 @@ int si_irq_set(struct radeon_device *rdev)
        }
        if (rdev->num_crtc >= 2) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
        }
        if (rdev->num_crtc >= 4) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
        }
        if (rdev->num_crtc >= 6) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
        }
        if (!ASIC_IS_NODCE(rdev)) {
@@ -6292,6 +6297,15 @@ restart_ih:
                                break;
                        }
                        break;
+                case 8: /* D1 page flip */
+                case 10: /* D2 page flip */
+                case 12: /* D3 page flip */
+                case 14: /* D4 page flip */
+                case 16: /* D5 page flip */
+                case 18: /* D6 page flip */
+                        DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
+                        radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+                        break;
                case 42: /* HPD hotplug */
                        switch (src_data) {
                        case 0:
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index cf0fdad8c278..de0ca070122f 100644
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -213,6 +213,7 @@ int si_copy_dma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 0a243f0e5d68..be42c8125203 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -83,7 +83,10 @@ int uvd_v1_0_init(struct radeon_device *rdev)
        int r;
        /* raise clocks while booting up the VCPU */
-        radeon_set_uvd_clocks(rdev, 53300, 40000);
+        if (rdev->family < CHIP_RV740)
+                radeon_set_uvd_clocks(rdev, 10000, 10000);
+        else
+                radeon_set_uvd_clocks(rdev, 53300, 40000);
        r = uvd_v1_0_start(rdev);
        if (r)
@@ -407,7 +410,10 @@ int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
        struct radeon_fence *fence = NULL;
        int r;
-        r = radeon_set_uvd_clocks(rdev, 53300, 40000);
+        if (rdev->family < CHIP_RV740)
+                r = radeon_set_uvd_clocks(rdev, 10000, 10000);
+        else
+                r = radeon_set_uvd_clocks(rdev, 53300, 40000);
        if (r) {
                DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
                return r;
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 36c717af6cf9..edb871d7d395 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -312,7 +312,7 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)
        struct drm_device *drm = crtc->dev;
        struct drm_plane *plane;
-        list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
+        drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
                if (plane->crtc == crtc) {
                        tegra_plane_disable(plane);
                        plane->crtc = NULL;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 931490b9cfed..87df0b3674fd 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -1214,14 +1214,36 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
                SVGA3dCmdSurfaceDMA dma;
        } *cmd;
        int ret;
+        SVGA3dCmdSurfaceDMASuffix *suffix;
+        uint32_t bo_size;
        cmd = container_of(header, struct vmw_dma_cmd, header);
+        suffix = (SVGA3dCmdSurfaceDMASuffix *)((unsigned long) &cmd->dma +
+                                               header->size - sizeof(*suffix));
+        /* Make sure device and verifier stays in sync. */
+        if (unlikely(suffix->suffixSize != sizeof(*suffix))) {
+                DRM_ERROR("Invalid DMA suffix size.\n");
+                return -EINVAL;
+        }
        ret = vmw_translate_guest_ptr(dev_priv, sw_context,
                                      &cmd->dma.guest.ptr,
                                      &vmw_bo);
        if (unlikely(ret != 0))
                return ret;
+        /* Make sure DMA doesn't cross BO boundaries. */
+        bo_size = vmw_bo->base.num_pages * PAGE_SIZE;
+        if (unlikely(cmd->dma.guest.ptr.offset > bo_size)) {
+                DRM_ERROR("Invalid DMA offset.\n");
+                return -EINVAL;
+        }
+        bo_size -= cmd->dma.guest.ptr.offset;
+        if (unlikely(suffix->maximumOffset > bo_size))
+                suffix->maximumOffset = bo_size;
        ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
                                user_surface_converter, &cmd->dma.host.sid,
                                NULL);