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-rw-r--r--drivers/gpu/drm/drm_gem.c39
-rw-r--r--drivers/gpu/drm/drm_info.c2
-rw-r--r--drivers/gpu/drm/drm_vm.c28
-rw-r--r--drivers/gpu/drm/i810/i810_dma.c2
-rw-r--r--drivers/gpu/drm/i830/i830_dma.c2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c9
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c52
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c45
-rw-r--r--drivers/gpu/drm/i915/intel_display.c62
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c19
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c5
-rw-r--r--drivers/gpu/drm/radeon/r100.c3
-rw-r--r--drivers/gpu/drm/radeon/r600.c7
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c26
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h5
-rw-r--r--drivers/gpu/drm/radeon/rs600.c1
-rw-r--r--drivers/gpu/drm/radeon/rs690.c1
-rw-r--r--drivers/gpu/drm/radeon/rv770.c2
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c83
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c145
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fb.c5
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c17
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c27
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c4
36 files changed, 432 insertions, 235 deletions
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index bf92d07510df..5663d2719063 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -148,7 +148,7 @@ int drm_gem_object_init(struct drm_device *dev,
148 return -ENOMEM; 148 return -ENOMEM;
149 149
150 kref_init(&obj->refcount); 150 kref_init(&obj->refcount);
151 kref_init(&obj->handlecount); 151 atomic_set(&obj->handle_count, 0);
152 obj->size = size; 152 obj->size = size;
153 153
154 atomic_inc(&dev->object_count); 154 atomic_inc(&dev->object_count);
@@ -462,28 +462,6 @@ drm_gem_object_free(struct kref *kref)
462} 462}
463EXPORT_SYMBOL(drm_gem_object_free); 463EXPORT_SYMBOL(drm_gem_object_free);
464 464
465/**
466 * Called after the last reference to the object has been lost.
467 * Must be called without holding struct_mutex
468 *
469 * Frees the object
470 */
471void
472drm_gem_object_free_unlocked(struct kref *kref)
473{
474 struct drm_gem_object *obj = (struct drm_gem_object *) kref;
475 struct drm_device *dev = obj->dev;
476
477 if (dev->driver->gem_free_object_unlocked != NULL)
478 dev->driver->gem_free_object_unlocked(obj);
479 else if (dev->driver->gem_free_object != NULL) {
480 mutex_lock(&dev->struct_mutex);
481 dev->driver->gem_free_object(obj);
482 mutex_unlock(&dev->struct_mutex);
483 }
484}
485EXPORT_SYMBOL(drm_gem_object_free_unlocked);
486
487static void drm_gem_object_ref_bug(struct kref *list_kref) 465static void drm_gem_object_ref_bug(struct kref *list_kref)
488{ 466{
489 BUG(); 467 BUG();
@@ -496,12 +474,8 @@ static void drm_gem_object_ref_bug(struct kref *list_kref)
496 * called before drm_gem_object_free or we'll be touching 474 * called before drm_gem_object_free or we'll be touching
497 * freed memory 475 * freed memory
498 */ 476 */
499void 477void drm_gem_object_handle_free(struct drm_gem_object *obj)
500drm_gem_object_handle_free(struct kref *kref)
501{ 478{
502 struct drm_gem_object *obj = container_of(kref,
503 struct drm_gem_object,
504 handlecount);
505 struct drm_device *dev = obj->dev; 479 struct drm_device *dev = obj->dev;
506 480
507 /* Remove any name for this object */ 481 /* Remove any name for this object */
@@ -528,6 +502,10 @@ void drm_gem_vm_open(struct vm_area_struct *vma)
528 struct drm_gem_object *obj = vma->vm_private_data; 502 struct drm_gem_object *obj = vma->vm_private_data;
529 503
530 drm_gem_object_reference(obj); 504 drm_gem_object_reference(obj);
505
506 mutex_lock(&obj->dev->struct_mutex);
507 drm_vm_open_locked(vma);
508 mutex_unlock(&obj->dev->struct_mutex);
531} 509}
532EXPORT_SYMBOL(drm_gem_vm_open); 510EXPORT_SYMBOL(drm_gem_vm_open);
533 511
@@ -535,7 +513,10 @@ void drm_gem_vm_close(struct vm_area_struct *vma)
535{ 513{
536 struct drm_gem_object *obj = vma->vm_private_data; 514 struct drm_gem_object *obj = vma->vm_private_data;
537 515
538 drm_gem_object_unreference_unlocked(obj); 516 mutex_lock(&obj->dev->struct_mutex);
517 drm_vm_close_locked(vma);
518 drm_gem_object_unreference(obj);
519 mutex_unlock(&obj->dev->struct_mutex);
539} 520}
540EXPORT_SYMBOL(drm_gem_vm_close); 521EXPORT_SYMBOL(drm_gem_vm_close);
541 522
diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c
index 2ef2c7827243..974e970ce3f8 100644
--- a/drivers/gpu/drm/drm_info.c
+++ b/drivers/gpu/drm/drm_info.c
@@ -255,7 +255,7 @@ int drm_gem_one_name_info(int id, void *ptr, void *data)
255 255
256 seq_printf(m, "%6d %8zd %7d %8d\n", 256 seq_printf(m, "%6d %8zd %7d %8d\n",
257 obj->name, obj->size, 257 obj->name, obj->size,
258 atomic_read(&obj->handlecount.refcount), 258 atomic_read(&obj->handle_count),
259 atomic_read(&obj->refcount.refcount)); 259 atomic_read(&obj->refcount.refcount));
260 return 0; 260 return 0;
261} 261}
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index fda67468e603..5df450683aab 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -433,15 +433,7 @@ static void drm_vm_open(struct vm_area_struct *vma)
433 mutex_unlock(&dev->struct_mutex); 433 mutex_unlock(&dev->struct_mutex);
434} 434}
435 435
436/** 436void drm_vm_close_locked(struct vm_area_struct *vma)
437 * \c close method for all virtual memory types.
438 *
439 * \param vma virtual memory area.
440 *
441 * Search the \p vma private data entry in drm_device::vmalist, unlink it, and
442 * free it.
443 */
444static void drm_vm_close(struct vm_area_struct *vma)
445{ 437{
446 struct drm_file *priv = vma->vm_file->private_data; 438 struct drm_file *priv = vma->vm_file->private_data;
447 struct drm_device *dev = priv->minor->dev; 439 struct drm_device *dev = priv->minor->dev;
@@ -451,7 +443,6 @@ static void drm_vm_close(struct vm_area_struct *vma)
451 vma->vm_start, vma->vm_end - vma->vm_start); 443 vma->vm_start, vma->vm_end - vma->vm_start);
452 atomic_dec(&dev->vma_count); 444 atomic_dec(&dev->vma_count);
453 445
454 mutex_lock(&dev->struct_mutex);
455 list_for_each_entry_safe(pt, temp, &dev->vmalist, head) { 446 list_for_each_entry_safe(pt, temp, &dev->vmalist, head) {
456 if (pt->vma == vma) { 447 if (pt->vma == vma) {
457 list_del(&pt->head); 448 list_del(&pt->head);
@@ -459,6 +450,23 @@ static void drm_vm_close(struct vm_area_struct *vma)
459 break; 450 break;
460 } 451 }
461 } 452 }
453}
454
455/**
456 * \c close method for all virtual memory types.
457 *
458 * \param vma virtual memory area.
459 *
460 * Search the \p vma private data entry in drm_device::vmalist, unlink it, and
461 * free it.
462 */
463static void drm_vm_close(struct vm_area_struct *vma)
464{
465 struct drm_file *priv = vma->vm_file->private_data;
466 struct drm_device *dev = priv->minor->dev;
467
468 mutex_lock(&dev->struct_mutex);
469 drm_vm_close_locked(vma);
462 mutex_unlock(&dev->struct_mutex); 470 mutex_unlock(&dev->struct_mutex);
463} 471}
464 472
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index 61b4caf220fa..fb07e73581e8 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -116,7 +116,7 @@ static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
116static const struct file_operations i810_buffer_fops = { 116static const struct file_operations i810_buffer_fops = {
117 .open = drm_open, 117 .open = drm_open,
118 .release = drm_release, 118 .release = drm_release,
119 .unlocked_ioctl = drm_ioctl, 119 .unlocked_ioctl = i810_ioctl,
120 .mmap = i810_mmap_buffers, 120 .mmap = i810_mmap_buffers,
121 .fasync = drm_fasync, 121 .fasync = drm_fasync,
122}; 122};
diff --git a/drivers/gpu/drm/i830/i830_dma.c b/drivers/gpu/drm/i830/i830_dma.c
index 671aa18415ac..cc92c7e6236f 100644
--- a/drivers/gpu/drm/i830/i830_dma.c
+++ b/drivers/gpu/drm/i830/i830_dma.c
@@ -118,7 +118,7 @@ static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
118static const struct file_operations i830_buffer_fops = { 118static const struct file_operations i830_buffer_fops = {
119 .open = drm_open, 119 .open = drm_open,
120 .release = drm_release, 120 .release = drm_release,
121 .unlocked_ioctl = drm_ioctl, 121 .unlocked_ioctl = i830_ioctl,
122 .mmap = i830_mmap_buffers, 122 .mmap = i830_mmap_buffers,
123 .fasync = drm_fasync, 123 .fasync = drm_fasync,
124}; 124};
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9d67b4853030..2dd2c93ebfa3 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1787,9 +1787,9 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1787 } 1787 }
1788 } 1788 }
1789 1789
1790 div_u64(diff, diff1); 1790 diff = div_u64(diff, diff1);
1791 ret = ((m * diff) + c); 1791 ret = ((m * diff) + c);
1792 div_u64(ret, 10); 1792 ret = div_u64(ret, 10);
1793 1793
1794 dev_priv->last_count1 = total_count; 1794 dev_priv->last_count1 = total_count;
1795 dev_priv->last_time1 = now; 1795 dev_priv->last_time1 = now;
@@ -1858,7 +1858,7 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1858 1858
1859 /* More magic constants... */ 1859 /* More magic constants... */
1860 diff = diff * 1181; 1860 diff = diff * 1181;
1861 div_u64(diff, diffms * 10); 1861 diff = div_u64(diff, diffms * 10);
1862 dev_priv->gfx_power = diff; 1862 dev_priv->gfx_power = diff;
1863} 1863}
1864 1864
@@ -2231,6 +2231,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2231 dev_priv->mchdev_lock = &mchdev_lock; 2231 dev_priv->mchdev_lock = &mchdev_lock;
2232 spin_unlock(&mchdev_lock); 2232 spin_unlock(&mchdev_lock);
2233 2233
2234 /* XXX Prevent module unload due to memory corruption bugs. */
2235 __module_get(THIS_MODULE);
2236
2234 return 0; 2237 return 0;
2235 2238
2236out_workqueue_free: 2239out_workqueue_free:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bced9b25c71e..90b1d6753b9d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -136,14 +136,12 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
136 return -ENOMEM; 136 return -ENOMEM;
137 137
138 ret = drm_gem_handle_create(file_priv, obj, &handle); 138 ret = drm_gem_handle_create(file_priv, obj, &handle);
139 /* drop reference from allocate - handle holds it now */
140 drm_gem_object_unreference_unlocked(obj);
139 if (ret) { 141 if (ret) {
140 drm_gem_object_unreference_unlocked(obj);
141 return ret; 142 return ret;
142 } 143 }
143 144
144 /* Sink the floating reference from kref_init(handlecount) */
145 drm_gem_object_handle_unreference_unlocked(obj);
146
147 args->handle = handle; 145 args->handle = handle;
148 return 0; 146 return 0;
149} 147}
@@ -471,14 +469,17 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
471 return -ENOENT; 469 return -ENOENT;
472 obj_priv = to_intel_bo(obj); 470 obj_priv = to_intel_bo(obj);
473 471
474 /* Bounds check source. 472 /* Bounds check source. */
475 * 473 if (args->offset > obj->size || args->size > obj->size - args->offset) {
476 * XXX: This could use review for overflow issues... 474 ret = -EINVAL;
477 */ 475 goto err;
478 if (args->offset > obj->size || args->size > obj->size || 476 }
479 args->offset + args->size > obj->size) { 477
480 drm_gem_object_unreference_unlocked(obj); 478 if (!access_ok(VERIFY_WRITE,
481 return -EINVAL; 479 (char __user *)(uintptr_t)args->data_ptr,
480 args->size)) {
481 ret = -EFAULT;
482 goto err;
482 } 483 }
483 484
484 if (i915_gem_object_needs_bit17_swizzle(obj)) { 485 if (i915_gem_object_needs_bit17_swizzle(obj)) {
@@ -490,8 +491,8 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
490 file_priv); 491 file_priv);
491 } 492 }
492 493
494err:
493 drm_gem_object_unreference_unlocked(obj); 495 drm_gem_object_unreference_unlocked(obj);
494
495 return ret; 496 return ret;
496} 497}
497 498
@@ -580,8 +581,6 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
580 581
581 user_data = (char __user *) (uintptr_t) args->data_ptr; 582 user_data = (char __user *) (uintptr_t) args->data_ptr;
582 remain = args->size; 583 remain = args->size;
583 if (!access_ok(VERIFY_READ, user_data, remain))
584 return -EFAULT;
585 584
586 585
587 mutex_lock(&dev->struct_mutex); 586 mutex_lock(&dev->struct_mutex);
@@ -934,14 +933,17 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
934 return -ENOENT; 933 return -ENOENT;
935 obj_priv = to_intel_bo(obj); 934 obj_priv = to_intel_bo(obj);
936 935
937 /* Bounds check destination. 936 /* Bounds check destination. */
938 * 937 if (args->offset > obj->size || args->size > obj->size - args->offset) {
939 * XXX: This could use review for overflow issues... 938 ret = -EINVAL;
940 */ 939 goto err;
941 if (args->offset > obj->size || args->size > obj->size || 940 }
942 args->offset + args->size > obj->size) { 941
943 drm_gem_object_unreference_unlocked(obj); 942 if (!access_ok(VERIFY_READ,
944 return -EINVAL; 943 (char __user *)(uintptr_t)args->data_ptr,
944 args->size)) {
945 ret = -EFAULT;
946 goto err;
945 } 947 }
946 948
947 /* We can only do the GTT pwrite on untiled buffers, as otherwise 949 /* We can only do the GTT pwrite on untiled buffers, as otherwise
@@ -975,8 +977,8 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
975 DRM_INFO("pwrite failed %d\n", ret); 977 DRM_INFO("pwrite failed %d\n", ret);
976#endif 978#endif
977 979
980err:
978 drm_gem_object_unreference_unlocked(obj); 981 drm_gem_object_unreference_unlocked(obj);
979
980 return ret; 982 return ret;
981} 983}
982 984
@@ -3258,6 +3260,8 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3258 (int) reloc->offset, 3260 (int) reloc->offset,
3259 reloc->read_domains, 3261 reloc->read_domains,
3260 reloc->write_domain); 3262 reloc->write_domain);
3263 drm_gem_object_unreference(target_obj);
3264 i915_gem_object_unpin(obj);
3261 return -EINVAL; 3265 return -EINVAL;
3262 } 3266 }
3263 if (reloc->write_domain & I915_GEM_DOMAIN_CPU || 3267 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index e85246ef691c..5c428fa3e0b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -93,7 +93,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
93{ 93{
94 drm_i915_private_t *dev_priv = dev->dev_private; 94 drm_i915_private_t *dev_priv = dev->dev_private;
95 struct list_head eviction_list, unwind_list; 95 struct list_head eviction_list, unwind_list;
96 struct drm_i915_gem_object *obj_priv, *tmp_obj_priv; 96 struct drm_i915_gem_object *obj_priv;
97 struct list_head *render_iter, *bsd_iter; 97 struct list_head *render_iter, *bsd_iter;
98 int ret = 0; 98 int ret = 0;
99 99
@@ -175,39 +175,34 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
175 return -ENOSPC; 175 return -ENOSPC;
176 176
177found: 177found:
178 /* drm_mm doesn't allow any other other operations while
179 * scanning, therefore store to be evicted objects on a
180 * temporary list. */
178 INIT_LIST_HEAD(&eviction_list); 181 INIT_LIST_HEAD(&eviction_list);
179 list_for_each_entry_safe(obj_priv, tmp_obj_priv, 182 while (!list_empty(&unwind_list)) {
180 &unwind_list, evict_list) { 183 obj_priv = list_first_entry(&unwind_list,
184 struct drm_i915_gem_object,
185 evict_list);
181 if (drm_mm_scan_remove_block(obj_priv->gtt_space)) { 186 if (drm_mm_scan_remove_block(obj_priv->gtt_space)) {
182 /* drm_mm doesn't allow any other other operations while
183 * scanning, therefore store to be evicted objects on a
184 * temporary list. */
185 list_move(&obj_priv->evict_list, &eviction_list); 187 list_move(&obj_priv->evict_list, &eviction_list);
186 } else 188 continue;
187 drm_gem_object_unreference(&obj_priv->base); 189 }
190 list_del(&obj_priv->evict_list);
191 drm_gem_object_unreference(&obj_priv->base);
188 } 192 }
189 193
190 /* Unbinding will emit any required flushes */ 194 /* Unbinding will emit any required flushes */
191 list_for_each_entry_safe(obj_priv, tmp_obj_priv, 195 while (!list_empty(&eviction_list)) {
192 &eviction_list, evict_list) { 196 obj_priv = list_first_entry(&eviction_list,
193#if WATCH_LRU 197 struct drm_i915_gem_object,
194 DRM_INFO("%s: evicting %p\n", __func__, &obj_priv->base); 198 evict_list);
195#endif 199 if (ret == 0)
196 ret = i915_gem_object_unbind(&obj_priv->base); 200 ret = i915_gem_object_unbind(&obj_priv->base);
197 if (ret) 201 list_del(&obj_priv->evict_list);
198 return ret;
199
200 drm_gem_object_unreference(&obj_priv->base); 202 drm_gem_object_unreference(&obj_priv->base);
201 } 203 }
202 204
203 /* The just created free hole should be on the top of the free stack 205 return ret;
204 * maintained by drm_mm, so this BUG_ON actually executes in O(1).
205 * Furthermore all accessed data has just recently been used, so it
206 * should be really fast, too. */
207 BUG_ON(!drm_mm_search_free(&dev_priv->mm.gtt_space, min_size,
208 alignment, 0));
209
210 return 0;
211} 206}
212 207
213int 208int
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b5bf51a4502d..979228594599 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1013,8 +1013,8 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
1013 DRM_DEBUG_KMS("vblank wait timed out\n"); 1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014} 1014}
1015 1015
1016/** 1016/*
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe 1017 * intel_wait_for_pipe_off - wait for pipe to turn off
1018 * @dev: drm device 1018 * @dev: drm device
1019 * @pipe: pipe to wait for 1019 * @pipe: pipe to wait for
1020 * 1020 *
@@ -1022,25 +1022,39 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
1022 * spinning on the vblank interrupt status bit, since we won't actually 1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled. 1023 * see an interrupt when the pipe is disabled.
1024 * 1024 *
1025 * So this function waits for the display line value to settle (it 1025 * On Gen4 and above:
1026 * usually ends up stopping at the start of the next frame). 1026 * wait for the pipe register state bit to turn off
1027 *
1028 * Otherwise:
1029 * wait for the display line value to settle (it usually
1030 * ends up stopping at the start of the next frame).
1031 *
1027 */ 1032 */
1028void intel_wait_for_vblank_off(struct drm_device *dev, int pipe) 1033static void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1029{ 1034{
1030 struct drm_i915_private *dev_priv = dev->dev_private; 1035 struct drm_i915_private *dev_priv = dev->dev_private;
1031 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL); 1036
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100); 1037 if (INTEL_INFO(dev)->gen >= 4) {
1033 u32 last_line; 1038 int pipeconf_reg = (pipe == 0 ? PIPEACONF : PIPEBCONF);
1034 1039
1035 /* Wait for the display line to settle */ 1040 /* Wait for the Pipe State to go off */
1036 do { 1041 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0,
1037 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK; 1042 100, 0))
1038 mdelay(5); 1043 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1039 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) && 1044 } else {
1040 time_after(timeout, jiffies)); 1045 u32 last_line;
1041 1046 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1042 if (time_after(jiffies, timeout)) 1047 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1043 DRM_DEBUG_KMS("vblank wait timed out\n"); 1048
1049 /* Wait for the display line to settle */
1050 do {
1051 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1052 mdelay(5);
1053 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1054 time_after(timeout, jiffies));
1055 if (time_after(jiffies, timeout))
1056 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1057 }
1044} 1058}
1045 1059
1046/* Parameters have changed, update FBC info */ 1060/* Parameters have changed, update FBC info */
@@ -2328,13 +2342,13 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2328 I915_READ(dspbase_reg); 2342 I915_READ(dspbase_reg);
2329 } 2343 }
2330 2344
2331 /* Wait for vblank for the disable to take effect */
2332 intel_wait_for_vblank_off(dev, pipe);
2333
2334 /* Don't disable pipe A or pipe A PLLs if needed */ 2345 /* Don't disable pipe A or pipe A PLLs if needed */
2335 if (pipeconf_reg == PIPEACONF && 2346 if (pipeconf_reg == PIPEACONF &&
2336 (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 2347 (dev_priv->quirks & QUIRK_PIPEA_FORCE)) {
2348 /* Wait for vblank for the disable to take effect */
2349 intel_wait_for_vblank(dev, pipe);
2337 goto skip_pipe_off; 2350 goto skip_pipe_off;
2351 }
2338 2352
2339 /* Next, disable display pipes */ 2353 /* Next, disable display pipes */
2340 temp = I915_READ(pipeconf_reg); 2354 temp = I915_READ(pipeconf_reg);
@@ -2343,8 +2357,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2343 I915_READ(pipeconf_reg); 2357 I915_READ(pipeconf_reg);
2344 } 2358 }
2345 2359
2346 /* Wait for vblank for the disable to take effect. */ 2360 /* Wait for the pipe to turn off */
2347 intel_wait_for_vblank_off(dev, pipe); 2361 intel_wait_for_pipe_off(dev, pipe);
2348 2362
2349 temp = I915_READ(dpll_reg); 2363 temp = I915_READ(dpll_reg);
2350 if ((temp & DPLL_VCO_ENABLE) != 0) { 2364 if ((temp & DPLL_VCO_ENABLE) != 0) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1a51ee07de3e..9ab8708ac6ba 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1138,18 +1138,14 @@ static bool
1138intel_dp_set_link_train(struct intel_dp *intel_dp, 1138intel_dp_set_link_train(struct intel_dp *intel_dp,
1139 uint32_t dp_reg_value, 1139 uint32_t dp_reg_value,
1140 uint8_t dp_train_pat, 1140 uint8_t dp_train_pat,
1141 uint8_t train_set[4], 1141 uint8_t train_set[4])
1142 bool first)
1143{ 1142{
1144 struct drm_device *dev = intel_dp->base.enc.dev; 1143 struct drm_device *dev = intel_dp->base.enc.dev;
1145 struct drm_i915_private *dev_priv = dev->dev_private; 1144 struct drm_i915_private *dev_priv = dev->dev_private;
1146 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
1147 int ret; 1145 int ret;
1148 1146
1149 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1147 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1150 POSTING_READ(intel_dp->output_reg); 1148 POSTING_READ(intel_dp->output_reg);
1151 if (first)
1152 intel_wait_for_vblank(dev, intel_crtc->pipe);
1153 1149
1154 intel_dp_aux_native_write_1(intel_dp, 1150 intel_dp_aux_native_write_1(intel_dp,
1155 DP_TRAINING_PATTERN_SET, 1151 DP_TRAINING_PATTERN_SET,
@@ -1174,10 +1170,15 @@ intel_dp_link_train(struct intel_dp *intel_dp)
1174 uint8_t voltage; 1170 uint8_t voltage;
1175 bool clock_recovery = false; 1171 bool clock_recovery = false;
1176 bool channel_eq = false; 1172 bool channel_eq = false;
1177 bool first = true;
1178 int tries; 1173 int tries;
1179 u32 reg; 1174 u32 reg;
1180 uint32_t DP = intel_dp->DP; 1175 uint32_t DP = intel_dp->DP;
1176 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
1177
1178 /* Enable output, wait for it to become active */
1179 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1180 POSTING_READ(intel_dp->output_reg);
1181 intel_wait_for_vblank(dev, intel_crtc->pipe);
1181 1182
1182 /* Write the link configuration data */ 1183 /* Write the link configuration data */
1183 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1184 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
@@ -1210,9 +1211,8 @@ intel_dp_link_train(struct intel_dp *intel_dp)
1210 reg = DP | DP_LINK_TRAIN_PAT_1; 1211 reg = DP | DP_LINK_TRAIN_PAT_1;
1211 1212
1212 if (!intel_dp_set_link_train(intel_dp, reg, 1213 if (!intel_dp_set_link_train(intel_dp, reg,
1213 DP_TRAINING_PATTERN_1, train_set, first)) 1214 DP_TRAINING_PATTERN_1, train_set))
1214 break; 1215 break;
1215 first = false;
1216 /* Set training pattern 1 */ 1216 /* Set training pattern 1 */
1217 1217
1218 udelay(100); 1218 udelay(100);
@@ -1266,8 +1266,7 @@ intel_dp_link_train(struct intel_dp *intel_dp)
1266 1266
1267 /* channel eq pattern */ 1267 /* channel eq pattern */
1268 if (!intel_dp_set_link_train(intel_dp, reg, 1268 if (!intel_dp_set_link_train(intel_dp, reg,
1269 DP_TRAINING_PATTERN_2, train_set, 1269 DP_TRAINING_PATTERN_2, train_set))
1270 false))
1271 break; 1270 break;
1272 1271
1273 udelay(400); 1272 udelay(400);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ad312ca6b3e5..8828b3ac6414 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -229,7 +229,6 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
229 struct drm_crtc *crtc); 229 struct drm_crtc *crtc);
230int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 230int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
231 struct drm_file *file_priv); 231 struct drm_file *file_priv);
232extern void intel_wait_for_vblank_off(struct drm_device *dev, int pipe);
233extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 232extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
234extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe); 233extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe);
235extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 234extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 7bdc96256bf5..b61966c126d3 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -237,8 +237,10 @@ int intel_fbdev_destroy(struct drm_device *dev,
237 drm_fb_helper_fini(&ifbdev->helper); 237 drm_fb_helper_fini(&ifbdev->helper);
238 238
239 drm_framebuffer_cleanup(&ifb->base); 239 drm_framebuffer_cleanup(&ifb->base);
240 if (ifb->obj) 240 if (ifb->obj) {
241 drm_gem_object_unreference(ifb->obj); 241 drm_gem_object_unreference(ifb->obj);
242 ifb->obj = NULL;
243 }
242 244
243 return 0; 245 return 0;
244} 246}
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index ead7b8fc53fc..19620a6709f5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -167,11 +167,9 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
167 goto out; 167 goto out;
168 168
169 ret = drm_gem_handle_create(file_priv, nvbo->gem, &req->info.handle); 169 ret = drm_gem_handle_create(file_priv, nvbo->gem, &req->info.handle);
170 /* drop reference from allocate - handle holds it now */
171 drm_gem_object_unreference_unlocked(nvbo->gem);
170out: 172out:
171 drm_gem_object_handle_unreference_unlocked(nvbo->gem);
172
173 if (ret)
174 drm_gem_object_unreference_unlocked(nvbo->gem);
175 return ret; 173 return ret;
176} 174}
177 175
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 79082d4398ae..2f93d46ae69a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1137,7 +1137,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1137 1137
1138 WREG32(RCU_IND_INDEX, 0x203); 1138 WREG32(RCU_IND_INDEX, 0x203);
1139 efuse_straps_3 = RREG32(RCU_IND_DATA); 1139 efuse_straps_3 = RREG32(RCU_IND_DATA);
1140 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28; 1140 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1141 1141
1142 switch(efuse_box_bit_127_124) { 1142 switch(efuse_box_bit_127_124) {
1143 case 0x0: 1143 case 0x0:
@@ -1407,6 +1407,7 @@ int evergreen_mc_init(struct radeon_device *rdev)
1407 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1407 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1408 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1408 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1409 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1409 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1410 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1410 r600_vram_gtt_location(rdev, &rdev->mc); 1411 r600_vram_gtt_location(rdev, &rdev->mc);
1411 radeon_update_bandwidth_info(rdev); 1412 radeon_update_bandwidth_info(rdev);
1412 1413
@@ -1520,7 +1521,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1520{ 1521{
1521 u32 tmp; 1522 u32 tmp;
1522 1523
1523 WREG32(CP_INT_CNTL, 0); 1524 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1524 WREG32(GRBM_INT_CNTL, 0); 1525 WREG32(GRBM_INT_CNTL, 0);
1525 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1526 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1526 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1527 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e151f16a8f86..e59422320bb6 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1030,6 +1030,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1030 return r; 1030 return r;
1031 } 1031 }
1032 rdev->cp.ready = true; 1032 rdev->cp.ready = true;
1033 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
1033 return 0; 1034 return 0;
1034} 1035}
1035 1036
@@ -1047,6 +1048,7 @@ void r100_cp_fini(struct radeon_device *rdev)
1047void r100_cp_disable(struct radeon_device *rdev) 1048void r100_cp_disable(struct radeon_device *rdev)
1048{ 1049{
1049 /* Disable ring */ 1050 /* Disable ring */
1051 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1050 rdev->cp.ready = false; 1052 rdev->cp.ready = false;
1051 WREG32(RADEON_CP_CSQ_MODE, 0); 1053 WREG32(RADEON_CP_CSQ_MODE, 0);
1052 WREG32(RADEON_CP_CSQ_CNTL, 0); 1054 WREG32(RADEON_CP_CSQ_CNTL, 0);
@@ -2295,6 +2297,7 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
2295 /* FIXME we don't use the second aperture yet when we could use it */ 2297 /* FIXME we don't use the second aperture yet when we could use it */
2296 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2298 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2297 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2299 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2300 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2298 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2301 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2299 if (rdev->flags & RADEON_IS_IGP) { 2302 if (rdev->flags & RADEON_IS_IGP) {
2300 uint32_t tom; 2303 uint32_t tom;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index ddc3adea1dda..7b65e4efe8af 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1248,6 +1248,7 @@ int r600_mc_init(struct radeon_device *rdev)
1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1250 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1250 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1251 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1251 r600_vram_gtt_location(rdev, &rdev->mc); 1252 r600_vram_gtt_location(rdev, &rdev->mc);
1252 1253
1253 if (rdev->flags & RADEON_IS_IGP) { 1254 if (rdev->flags & RADEON_IS_IGP) {
@@ -1917,6 +1918,7 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1917 */ 1918 */
1918void r600_cp_stop(struct radeon_device *rdev) 1919void r600_cp_stop(struct radeon_device *rdev)
1919{ 1920{
1921 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1920 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1922 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1921} 1923}
1922 1924
@@ -2910,7 +2912,7 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev)
2910{ 2912{
2911 u32 tmp; 2913 u32 tmp;
2912 2914
2913 WREG32(CP_INT_CNTL, 0); 2915 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2914 WREG32(GRBM_INT_CNTL, 0); 2916 WREG32(GRBM_INT_CNTL, 0);
2915 WREG32(DxMODE_INT_MASK, 0); 2917 WREG32(DxMODE_INT_MASK, 0);
2916 if (ASIC_IS_DCE3(rdev)) { 2918 if (ASIC_IS_DCE3(rdev)) {
@@ -3528,7 +3530,8 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3528 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 3530 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3529 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 3531 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3530 */ 3532 */
3531 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { 3533 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3534 rdev->vram_scratch.ptr) {
3532 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3535 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3533 u32 tmp; 3536 u32 tmp;
3534 3537
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 9ceb2a1ce799..3473c00781ff 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -532,6 +532,7 @@ int r600_blit_init(struct radeon_device *rdev)
532 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); 532 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
533 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 533 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
534 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 534 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
535 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
535 return 0; 536 return 0;
536} 537}
537 538
@@ -539,6 +540,7 @@ void r600_blit_fini(struct radeon_device *rdev)
539{ 540{
540 int r; 541 int r;
541 542
543 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
542 if (rdev->r600_blit.shader_obj == NULL) 544 if (rdev->r600_blit.shader_obj == NULL)
543 return; 545 return;
544 /* If we can't reserve the bo, unref should be enough to destroy 546 /* If we can't reserve the bo, unref should be enough to destroy
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a168d644bf9e..9ff38c99a6ea 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -344,6 +344,7 @@ struct radeon_mc {
344 * about vram size near mc fb location */ 344 * about vram size near mc fb location */
345 u64 mc_vram_size; 345 u64 mc_vram_size;
346 u64 visible_vram_size; 346 u64 visible_vram_size;
347 u64 active_vram_size;
347 u64 gtt_size; 348 u64 gtt_size;
348 u64 gtt_start; 349 u64 gtt_start;
349 u64 gtt_end; 350 u64 gtt_end;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index ebae14c4b768..8e43ddae70cc 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -317,6 +317,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
317 *connector_type = DRM_MODE_CONNECTOR_DVID; 317 *connector_type = DRM_MODE_CONNECTOR_DVID;
318 } 318 }
319 319
320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev->pdev->device == 0x796e) &&
322 (dev->pdev->subsystem_vendor == 0x1462) &&
323 (dev->pdev->subsystem_device == 0x7302)) {
324 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
325 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 return false;
327 }
328
320 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
321 if ((dev->pdev->device == 0x7941) && 330 if ((dev->pdev->device == 0x7941) &&
322 (dev->pdev->subsystem_vendor == 0x147b) && 331 (dev->pdev->subsystem_vendor == 0x147b) &&
@@ -1549,39 +1558,39 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev)
1549 switch (tv_info->ucTV_BootUpDefaultStandard) { 1558 switch (tv_info->ucTV_BootUpDefaultStandard) {
1550 case ATOM_TV_NTSC: 1559 case ATOM_TV_NTSC:
1551 tv_std = TV_STD_NTSC; 1560 tv_std = TV_STD_NTSC;
1552 DRM_INFO("Default TV standard: NTSC\n"); 1561 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1553 break; 1562 break;
1554 case ATOM_TV_NTSCJ: 1563 case ATOM_TV_NTSCJ:
1555 tv_std = TV_STD_NTSC_J; 1564 tv_std = TV_STD_NTSC_J;
1556 DRM_INFO("Default TV standard: NTSC-J\n"); 1565 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1557 break; 1566 break;
1558 case ATOM_TV_PAL: 1567 case ATOM_TV_PAL:
1559 tv_std = TV_STD_PAL; 1568 tv_std = TV_STD_PAL;
1560 DRM_INFO("Default TV standard: PAL\n"); 1569 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1561 break; 1570 break;
1562 case ATOM_TV_PALM: 1571 case ATOM_TV_PALM:
1563 tv_std = TV_STD_PAL_M; 1572 tv_std = TV_STD_PAL_M;
1564 DRM_INFO("Default TV standard: PAL-M\n"); 1573 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1565 break; 1574 break;
1566 case ATOM_TV_PALN: 1575 case ATOM_TV_PALN:
1567 tv_std = TV_STD_PAL_N; 1576 tv_std = TV_STD_PAL_N;
1568 DRM_INFO("Default TV standard: PAL-N\n"); 1577 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1569 break; 1578 break;
1570 case ATOM_TV_PALCN: 1579 case ATOM_TV_PALCN:
1571 tv_std = TV_STD_PAL_CN; 1580 tv_std = TV_STD_PAL_CN;
1572 DRM_INFO("Default TV standard: PAL-CN\n"); 1581 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1573 break; 1582 break;
1574 case ATOM_TV_PAL60: 1583 case ATOM_TV_PAL60:
1575 tv_std = TV_STD_PAL_60; 1584 tv_std = TV_STD_PAL_60;
1576 DRM_INFO("Default TV standard: PAL-60\n"); 1585 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1577 break; 1586 break;
1578 case ATOM_TV_SECAM: 1587 case ATOM_TV_SECAM:
1579 tv_std = TV_STD_SECAM; 1588 tv_std = TV_STD_SECAM;
1580 DRM_INFO("Default TV standard: SECAM\n"); 1589 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1581 break; 1590 break;
1582 default: 1591 default:
1583 tv_std = TV_STD_NTSC; 1592 tv_std = TV_STD_NTSC;
1584 DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); 1593 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1585 break; 1594 break;
1586 } 1595 }
1587 } 1596 }
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index a04b7a6ad95f..7b7ea269549c 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -913,47 +913,47 @@ radeon_combios_get_tv_info(struct radeon_device *rdev)
913 switch (RBIOS8(tv_info + 7) & 0xf) { 913 switch (RBIOS8(tv_info + 7) & 0xf) {
914 case 1: 914 case 1:
915 tv_std = TV_STD_NTSC; 915 tv_std = TV_STD_NTSC;
916 DRM_INFO("Default TV standard: NTSC\n"); 916 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
917 break; 917 break;
918 case 2: 918 case 2:
919 tv_std = TV_STD_PAL; 919 tv_std = TV_STD_PAL;
920 DRM_INFO("Default TV standard: PAL\n"); 920 DRM_DEBUG_KMS("Default TV standard: PAL\n");
921 break; 921 break;
922 case 3: 922 case 3:
923 tv_std = TV_STD_PAL_M; 923 tv_std = TV_STD_PAL_M;
924 DRM_INFO("Default TV standard: PAL-M\n"); 924 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
925 break; 925 break;
926 case 4: 926 case 4:
927 tv_std = TV_STD_PAL_60; 927 tv_std = TV_STD_PAL_60;
928 DRM_INFO("Default TV standard: PAL-60\n"); 928 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
929 break; 929 break;
930 case 5: 930 case 5:
931 tv_std = TV_STD_NTSC_J; 931 tv_std = TV_STD_NTSC_J;
932 DRM_INFO("Default TV standard: NTSC-J\n"); 932 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
933 break; 933 break;
934 case 6: 934 case 6:
935 tv_std = TV_STD_SCART_PAL; 935 tv_std = TV_STD_SCART_PAL;
936 DRM_INFO("Default TV standard: SCART-PAL\n"); 936 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
937 break; 937 break;
938 default: 938 default:
939 tv_std = TV_STD_NTSC; 939 tv_std = TV_STD_NTSC;
940 DRM_INFO 940 DRM_DEBUG_KMS
941 ("Unknown TV standard; defaulting to NTSC\n"); 941 ("Unknown TV standard; defaulting to NTSC\n");
942 break; 942 break;
943 } 943 }
944 944
945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
946 case 0: 946 case 0:
947 DRM_INFO("29.498928713 MHz TV ref clk\n"); 947 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
948 break; 948 break;
949 case 1: 949 case 1:
950 DRM_INFO("28.636360000 MHz TV ref clk\n"); 950 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
951 break; 951 break;
952 case 2: 952 case 2:
953 DRM_INFO("14.318180000 MHz TV ref clk\n"); 953 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
954 break; 954 break;
955 case 3: 955 case 3:
956 DRM_INFO("27.000000000 MHz TV ref clk\n"); 956 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
957 break; 957 break;
958 default: 958 default:
959 break; 959 break;
@@ -1324,7 +1324,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1324 1324
1325 if (tmds_info) { 1325 if (tmds_info) {
1326 ver = RBIOS8(tmds_info); 1326 ver = RBIOS8(tmds_info);
1327 DRM_INFO("DFP table revision: %d\n", ver); 1327 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1328 if (ver == 3) { 1328 if (ver == 3) {
1329 n = RBIOS8(tmds_info + 5) + 1; 1329 n = RBIOS8(tmds_info + 5) + 1;
1330 if (n > 4) 1330 if (n > 4)
@@ -1408,7 +1408,7 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1409 if (offset) { 1409 if (offset) {
1410 ver = RBIOS8(offset); 1410 ver = RBIOS8(offset);
1411 DRM_INFO("External TMDS Table revision: %d\n", ver); 1411 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1412 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1413 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1414 gpio = RBIOS8(offset + 4 + 3); 1414 gpio = RBIOS8(offset + 4 + 3);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 127a395f70fb..b92d2f2fcbed 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -349,6 +349,8 @@ static void radeon_print_display_setup(struct drm_device *dev)
349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 350 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
353 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_TV1_SUPPORT) 354 if (devices & ATOM_DEVICE_TV1_SUPPORT)
353 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 355 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
354 if (devices & ATOM_DEVICE_CV_SUPPORT) 356 if (devices & ATOM_DEVICE_CV_SUPPORT)
@@ -841,8 +843,9 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
841{ 843{
842 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 844 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
843 845
844 if (radeon_fb->obj) 846 if (radeon_fb->obj) {
845 drm_gem_object_unreference_unlocked(radeon_fb->obj); 847 drm_gem_object_unreference_unlocked(radeon_fb->obj);
848 }
846 drm_framebuffer_cleanup(fb); 849 drm_framebuffer_cleanup(fb);
847 kfree(radeon_fb); 850 kfree(radeon_fb);
848} 851}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index c74a8b20d941..40b0c087b592 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -94,6 +94,7 @@ static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
94 ret = radeon_bo_reserve(rbo, false); 94 ret = radeon_bo_reserve(rbo, false);
95 if (likely(ret == 0)) { 95 if (likely(ret == 0)) {
96 radeon_bo_kunmap(rbo); 96 radeon_bo_kunmap(rbo);
97 radeon_bo_unpin(rbo);
97 radeon_bo_unreserve(rbo); 98 radeon_bo_unreserve(rbo);
98 } 99 }
99 drm_gem_object_unreference_unlocked(gobj); 100 drm_gem_object_unreference_unlocked(gobj);
@@ -325,8 +326,6 @@ static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfb
325{ 326{
326 struct fb_info *info; 327 struct fb_info *info;
327 struct radeon_framebuffer *rfb = &rfbdev->rfb; 328 struct radeon_framebuffer *rfb = &rfbdev->rfb;
328 struct radeon_bo *rbo;
329 int r;
330 329
331 if (rfbdev->helper.fbdev) { 330 if (rfbdev->helper.fbdev) {
332 info = rfbdev->helper.fbdev; 331 info = rfbdev->helper.fbdev;
@@ -338,14 +337,8 @@ static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfb
338 } 337 }
339 338
340 if (rfb->obj) { 339 if (rfb->obj) {
341 rbo = rfb->obj->driver_private; 340 radeonfb_destroy_pinned_object(rfb->obj);
342 r = radeon_bo_reserve(rbo, false); 341 rfb->obj = NULL;
343 if (likely(r == 0)) {
344 radeon_bo_kunmap(rbo);
345 radeon_bo_unpin(rbo);
346 radeon_bo_unreserve(rbo);
347 }
348 drm_gem_object_unreference_unlocked(rfb->obj);
349 } 342 }
350 drm_fb_helper_fini(&rfbdev->helper); 343 drm_fb_helper_fini(&rfbdev->helper);
351 drm_framebuffer_cleanup(&rfb->base); 344 drm_framebuffer_cleanup(&rfb->base);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index c578f265b24c..d1e595d91723 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -201,11 +201,11 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
201 return r; 201 return r;
202 } 202 }
203 r = drm_gem_handle_create(filp, gobj, &handle); 203 r = drm_gem_handle_create(filp, gobj, &handle);
204 /* drop reference from allocate - handle holds it now */
205 drm_gem_object_unreference_unlocked(gobj);
204 if (r) { 206 if (r) {
205 drm_gem_object_unreference_unlocked(gobj);
206 return r; 207 return r;
207 } 208 }
208 drm_gem_object_handle_unreference_unlocked(gobj);
209 args->handle = handle; 209 args->handle = handle;
210 return 0; 210 return 0;
211} 211}
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 0afd1e62347d..b3b5306bb578 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -69,7 +69,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
69 u32 c = 0; 69 u32 c = 0;
70 70
71 rbo->placement.fpfn = 0; 71 rbo->placement.fpfn = 0;
72 rbo->placement.lpfn = 0; 72 rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT;
73 rbo->placement.placement = rbo->placements; 73 rbo->placement.placement = rbo->placements;
74 rbo->placement.busy_placement = rbo->placements; 74 rbo->placement.busy_placement = rbo->placements;
75 if (domain & RADEON_GEM_DOMAIN_VRAM) 75 if (domain & RADEON_GEM_DOMAIN_VRAM)
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 353998dc2c03..3481bc7f6f58 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -124,11 +124,8 @@ static inline int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
124 int r; 124 int r;
125 125
126 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 126 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
127 if (unlikely(r != 0)) { 127 if (unlikely(r != 0))
128 if (r != -ERESTARTSYS)
129 dev_err(bo->rdev->dev, "%p reserve failed for wait\n", bo);
130 return r; 128 return r;
131 }
132 spin_lock(&bo->tbo.lock); 129 spin_lock(&bo->tbo.lock);
133 if (mem_type) 130 if (mem_type)
134 *mem_type = bo->tbo.mem.mem_type; 131 *mem_type = bo->tbo.mem.mem_type;
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index cc05b230d7ef..51d5f7b5ab21 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -693,6 +693,7 @@ void rs600_mc_init(struct radeon_device *rdev)
693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
694 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 694 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
695 rdev->mc.visible_vram_size = rdev->mc.aper_size; 695 rdev->mc.visible_vram_size = rdev->mc.aper_size;
696 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
696 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 697 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
697 base = RREG32_MC(R_000004_MC_FB_LOCATION); 698 base = RREG32_MC(R_000004_MC_FB_LOCATION);
698 base = G_000004_MC_FB_START(base) << 16; 699 base = G_000004_MC_FB_START(base) << 16;
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3e3f75718be3..4dc2a87ea680 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -157,6 +157,7 @@ void rs690_mc_init(struct radeon_device *rdev)
157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 161 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 162 base = G_000100_MC_FB_START(base) << 16;
162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index bfa59db374d2..9490da700749 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -267,6 +267,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
267 */ 267 */
268void r700_cp_stop(struct radeon_device *rdev) 268void r700_cp_stop(struct radeon_device *rdev)
269{ 269{
270 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
270 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
271} 272}
272 273
@@ -992,6 +993,7 @@ int rv770_mc_init(struct radeon_device *rdev)
992 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 993 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
993 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 994 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
994 rdev->mc.visible_vram_size = rdev->mc.aper_size; 995 rdev->mc.visible_vram_size = rdev->mc.aper_size;
996 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
995 r600_vram_gtt_location(rdev, &rdev->mc); 997 r600_vram_gtt_location(rdev, &rdev->mc);
996 radeon_update_bandwidth_info(rdev); 998 radeon_update_bandwidth_info(rdev);
997 999
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index cb4cf7ef4d1e..db809e034cc4 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -442,6 +442,43 @@ out_err:
442} 442}
443 443
444/** 444/**
445 * Call bo::reserved and with the lru lock held.
446 * Will release GPU memory type usage on destruction.
447 * This is the place to put in driver specific hooks.
448 * Will release the bo::reserved lock and the
449 * lru lock on exit.
450 */
451
452static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo)
453{
454 struct ttm_bo_global *glob = bo->glob;
455
456 if (bo->ttm) {
457
458 /**
459 * Release the lru_lock, since we don't want to have
460 * an atomic requirement on ttm_tt[unbind|destroy].
461 */
462
463 spin_unlock(&glob->lru_lock);
464 ttm_tt_unbind(bo->ttm);
465 ttm_tt_destroy(bo->ttm);
466 bo->ttm = NULL;
467 spin_lock(&glob->lru_lock);
468 }
469
470 if (bo->mem.mm_node) {
471 drm_mm_put_block(bo->mem.mm_node);
472 bo->mem.mm_node = NULL;
473 }
474
475 atomic_set(&bo->reserved, 0);
476 wake_up_all(&bo->event_queue);
477 spin_unlock(&glob->lru_lock);
478}
479
480
481/**
445 * If bo idle, remove from delayed- and lru lists, and unref. 482 * If bo idle, remove from delayed- and lru lists, and unref.
446 * If not idle, and already on delayed list, do nothing. 483 * If not idle, and already on delayed list, do nothing.
447 * If not idle, and not on delayed list, put on delayed list, 484 * If not idle, and not on delayed list, put on delayed list,
@@ -456,6 +493,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
456 int ret; 493 int ret;
457 494
458 spin_lock(&bo->lock); 495 spin_lock(&bo->lock);
496retry:
459 (void) ttm_bo_wait(bo, false, false, !remove_all); 497 (void) ttm_bo_wait(bo, false, false, !remove_all);
460 498
461 if (!bo->sync_obj) { 499 if (!bo->sync_obj) {
@@ -464,31 +502,52 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
464 spin_unlock(&bo->lock); 502 spin_unlock(&bo->lock);
465 503
466 spin_lock(&glob->lru_lock); 504 spin_lock(&glob->lru_lock);
467 put_count = ttm_bo_del_from_lru(bo); 505 ret = ttm_bo_reserve_locked(bo, false, !remove_all, false, 0);
506
507 /**
508 * Someone else has the object reserved. Bail and retry.
509 */
468 510
469 ret = ttm_bo_reserve_locked(bo, false, false, false, 0); 511 if (unlikely(ret == -EBUSY)) {
470 BUG_ON(ret); 512 spin_unlock(&glob->lru_lock);
471 if (bo->ttm) 513 spin_lock(&bo->lock);
472 ttm_tt_unbind(bo->ttm); 514 goto requeue;
515 }
516
517 /**
518 * We can re-check for sync object without taking
519 * the bo::lock since setting the sync object requires
520 * also bo::reserved. A busy object at this point may
521 * be caused by another thread starting an accelerated
522 * eviction.
523 */
524
525 if (unlikely(bo->sync_obj)) {
526 atomic_set(&bo->reserved, 0);
527 wake_up_all(&bo->event_queue);
528 spin_unlock(&glob->lru_lock);
529 spin_lock(&bo->lock);
530 if (remove_all)
531 goto retry;
532 else
533 goto requeue;
534 }
535
536 put_count = ttm_bo_del_from_lru(bo);
473 537
474 if (!list_empty(&bo->ddestroy)) { 538 if (!list_empty(&bo->ddestroy)) {
475 list_del_init(&bo->ddestroy); 539 list_del_init(&bo->ddestroy);
476 ++put_count; 540 ++put_count;
477 } 541 }
478 if (bo->mem.mm_node) {
479 drm_mm_put_block(bo->mem.mm_node);
480 bo->mem.mm_node = NULL;
481 }
482 spin_unlock(&glob->lru_lock);
483 542
484 atomic_set(&bo->reserved, 0); 543 ttm_bo_cleanup_memtype_use(bo);
485 544
486 while (put_count--) 545 while (put_count--)
487 kref_put(&bo->list_kref, ttm_bo_ref_bug); 546 kref_put(&bo->list_kref, ttm_bo_ref_bug);
488 547
489 return 0; 548 return 0;
490 } 549 }
491 550requeue:
492 spin_lock(&glob->lru_lock); 551 spin_lock(&glob->lru_lock);
493 if (list_empty(&bo->ddestroy)) { 552 if (list_empty(&bo->ddestroy)) {
494 void *sync_obj = bo->sync_obj; 553 void *sync_obj = bo->sync_obj;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 72ec2e2b6e97..a96ed6d9d010 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -148,13 +148,16 @@ static struct pci_device_id vmw_pci_id_list[] = {
148 {0, 0, 0} 148 {0, 0, 0}
149}; 149};
150 150
151static char *vmw_devname = "vmwgfx"; 151static int enable_fbdev;
152 152
153static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 153static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
154static void vmw_master_init(struct vmw_master *); 154static void vmw_master_init(struct vmw_master *);
155static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 155static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
156 void *ptr); 156 void *ptr);
157 157
158MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
159module_param_named(enable_fbdev, enable_fbdev, int, 0600);
160
158static void vmw_print_capabilities(uint32_t capabilities) 161static void vmw_print_capabilities(uint32_t capabilities)
159{ 162{
160 DRM_INFO("Capabilities:\n"); 163 DRM_INFO("Capabilities:\n");
@@ -192,8 +195,6 @@ static int vmw_request_device(struct vmw_private *dev_priv)
192{ 195{
193 int ret; 196 int ret;
194 197
195 vmw_kms_save_vga(dev_priv);
196
197 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 198 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
198 if (unlikely(ret != 0)) { 199 if (unlikely(ret != 0)) {
199 DRM_ERROR("Unable to initialize FIFO.\n"); 200 DRM_ERROR("Unable to initialize FIFO.\n");
@@ -206,9 +207,35 @@ static int vmw_request_device(struct vmw_private *dev_priv)
206static void vmw_release_device(struct vmw_private *dev_priv) 207static void vmw_release_device(struct vmw_private *dev_priv)
207{ 208{
208 vmw_fifo_release(dev_priv, &dev_priv->fifo); 209 vmw_fifo_release(dev_priv, &dev_priv->fifo);
209 vmw_kms_restore_vga(dev_priv);
210} 210}
211 211
212int vmw_3d_resource_inc(struct vmw_private *dev_priv)
213{
214 int ret = 0;
215
216 mutex_lock(&dev_priv->release_mutex);
217 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
218 ret = vmw_request_device(dev_priv);
219 if (unlikely(ret != 0))
220 --dev_priv->num_3d_resources;
221 }
222 mutex_unlock(&dev_priv->release_mutex);
223 return ret;
224}
225
226
227void vmw_3d_resource_dec(struct vmw_private *dev_priv)
228{
229 int32_t n3d;
230
231 mutex_lock(&dev_priv->release_mutex);
232 if (unlikely(--dev_priv->num_3d_resources == 0))
233 vmw_release_device(dev_priv);
234 n3d = (int32_t) dev_priv->num_3d_resources;
235 mutex_unlock(&dev_priv->release_mutex);
236
237 BUG_ON(n3d < 0);
238}
212 239
213static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 240static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
214{ 241{
@@ -228,6 +255,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
228 dev_priv->last_read_sequence = (uint32_t) -100; 255 dev_priv->last_read_sequence = (uint32_t) -100;
229 mutex_init(&dev_priv->hw_mutex); 256 mutex_init(&dev_priv->hw_mutex);
230 mutex_init(&dev_priv->cmdbuf_mutex); 257 mutex_init(&dev_priv->cmdbuf_mutex);
258 mutex_init(&dev_priv->release_mutex);
231 rwlock_init(&dev_priv->resource_lock); 259 rwlock_init(&dev_priv->resource_lock);
232 idr_init(&dev_priv->context_idr); 260 idr_init(&dev_priv->context_idr);
233 idr_init(&dev_priv->surface_idr); 261 idr_init(&dev_priv->surface_idr);
@@ -244,6 +272,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
244 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 272 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
245 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 273 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
246 274
275 dev_priv->enable_fb = enable_fbdev;
276
247 mutex_lock(&dev_priv->hw_mutex); 277 mutex_lock(&dev_priv->hw_mutex);
248 278
249 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 279 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
@@ -343,17 +373,6 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
343 373
344 dev->dev_private = dev_priv; 374 dev->dev_private = dev_priv;
345 375
346 if (!dev->devname)
347 dev->devname = vmw_devname;
348
349 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
350 ret = drm_irq_install(dev);
351 if (unlikely(ret != 0)) {
352 DRM_ERROR("Failed installing irq: %d\n", ret);
353 goto out_no_irq;
354 }
355 }
356
357 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 376 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
358 dev_priv->stealth = (ret != 0); 377 dev_priv->stealth = (ret != 0);
359 if (dev_priv->stealth) { 378 if (dev_priv->stealth) {
@@ -369,26 +388,52 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
369 goto out_no_device; 388 goto out_no_device;
370 } 389 }
371 } 390 }
372 ret = vmw_request_device(dev_priv); 391 ret = vmw_kms_init(dev_priv);
373 if (unlikely(ret != 0)) 392 if (unlikely(ret != 0))
374 goto out_no_device; 393 goto out_no_kms;
375 vmw_kms_init(dev_priv);
376 vmw_overlay_init(dev_priv); 394 vmw_overlay_init(dev_priv);
377 vmw_fb_init(dev_priv); 395 if (dev_priv->enable_fb) {
396 ret = vmw_3d_resource_inc(dev_priv);
397 if (unlikely(ret != 0))
398 goto out_no_fifo;
399 vmw_kms_save_vga(dev_priv);
400 vmw_fb_init(dev_priv);
401 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
402 "Detected device 3D availability.\n" :
403 "Detected no device 3D availability.\n");
404 } else {
405 DRM_INFO("Delayed 3D detection since we're not "
406 "running the device in SVGA mode yet.\n");
407 }
408
409 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
410 ret = drm_irq_install(dev);
411 if (unlikely(ret != 0)) {
412 DRM_ERROR("Failed installing irq: %d\n", ret);
413 goto out_no_irq;
414 }
415 }
378 416
379 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 417 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
380 register_pm_notifier(&dev_priv->pm_nb); 418 register_pm_notifier(&dev_priv->pm_nb);
381 419
382 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? "Have 3D\n" : "No 3D\n");
383
384 return 0; 420 return 0;
385 421
386out_no_device:
387 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
388 drm_irq_uninstall(dev_priv->dev);
389 if (dev->devname == vmw_devname)
390 dev->devname = NULL;
391out_no_irq: 422out_no_irq:
423 if (dev_priv->enable_fb) {
424 vmw_fb_close(dev_priv);
425 vmw_kms_restore_vga(dev_priv);
426 vmw_3d_resource_dec(dev_priv);
427 }
428out_no_fifo:
429 vmw_overlay_close(dev_priv);
430 vmw_kms_close(dev_priv);
431out_no_kms:
432 if (dev_priv->stealth)
433 pci_release_region(dev->pdev, 2);
434 else
435 pci_release_regions(dev->pdev);
436out_no_device:
392 ttm_object_device_release(&dev_priv->tdev); 437 ttm_object_device_release(&dev_priv->tdev);
393out_err4: 438out_err4:
394 iounmap(dev_priv->mmio_virt); 439 iounmap(dev_priv->mmio_virt);
@@ -415,19 +460,20 @@ static int vmw_driver_unload(struct drm_device *dev)
415 460
416 unregister_pm_notifier(&dev_priv->pm_nb); 461 unregister_pm_notifier(&dev_priv->pm_nb);
417 462
418 vmw_fb_close(dev_priv); 463 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
464 drm_irq_uninstall(dev_priv->dev);
465 if (dev_priv->enable_fb) {
466 vmw_fb_close(dev_priv);
467 vmw_kms_restore_vga(dev_priv);
468 vmw_3d_resource_dec(dev_priv);
469 }
419 vmw_kms_close(dev_priv); 470 vmw_kms_close(dev_priv);
420 vmw_overlay_close(dev_priv); 471 vmw_overlay_close(dev_priv);
421 vmw_release_device(dev_priv);
422 if (dev_priv->stealth) 472 if (dev_priv->stealth)
423 pci_release_region(dev->pdev, 2); 473 pci_release_region(dev->pdev, 2);
424 else 474 else
425 pci_release_regions(dev->pdev); 475 pci_release_regions(dev->pdev);
426 476
427 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
428 drm_irq_uninstall(dev_priv->dev);
429 if (dev->devname == vmw_devname)
430 dev->devname = NULL;
431 ttm_object_device_release(&dev_priv->tdev); 477 ttm_object_device_release(&dev_priv->tdev);
432 iounmap(dev_priv->mmio_virt); 478 iounmap(dev_priv->mmio_virt);
433 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, 479 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
@@ -500,7 +546,7 @@ static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
500 struct drm_ioctl_desc *ioctl = 546 struct drm_ioctl_desc *ioctl =
501 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 547 &vmw_ioctls[nr - DRM_COMMAND_BASE];
502 548
503 if (unlikely(ioctl->cmd != cmd)) { 549 if (unlikely(ioctl->cmd_drv != cmd)) {
504 DRM_ERROR("Invalid command format, ioctl %d\n", 550 DRM_ERROR("Invalid command format, ioctl %d\n",
505 nr - DRM_COMMAND_BASE); 551 nr - DRM_COMMAND_BASE);
506 return -EINVAL; 552 return -EINVAL;
@@ -589,6 +635,16 @@ static int vmw_master_set(struct drm_device *dev,
589 struct vmw_master *vmaster = vmw_master(file_priv->master); 635 struct vmw_master *vmaster = vmw_master(file_priv->master);
590 int ret = 0; 636 int ret = 0;
591 637
638 if (!dev_priv->enable_fb) {
639 ret = vmw_3d_resource_inc(dev_priv);
640 if (unlikely(ret != 0))
641 return ret;
642 vmw_kms_save_vga(dev_priv);
643 mutex_lock(&dev_priv->hw_mutex);
644 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
645 mutex_unlock(&dev_priv->hw_mutex);
646 }
647
592 if (active) { 648 if (active) {
593 BUG_ON(active != &dev_priv->fbdev_master); 649 BUG_ON(active != &dev_priv->fbdev_master);
594 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 650 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
@@ -617,7 +673,13 @@ static int vmw_master_set(struct drm_device *dev,
617 return 0; 673 return 0;
618 674
619out_no_active_lock: 675out_no_active_lock:
620 vmw_release_device(dev_priv); 676 if (!dev_priv->enable_fb) {
677 mutex_lock(&dev_priv->hw_mutex);
678 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
679 mutex_unlock(&dev_priv->hw_mutex);
680 vmw_kms_restore_vga(dev_priv);
681 vmw_3d_resource_dec(dev_priv);
682 }
621 return ret; 683 return ret;
622} 684}
623 685
@@ -645,11 +707,23 @@ static void vmw_master_drop(struct drm_device *dev,
645 707
646 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 708 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
647 709
710 if (!dev_priv->enable_fb) {
711 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
712 if (unlikely(ret != 0))
713 DRM_ERROR("Unable to clean VRAM on master drop.\n");
714 mutex_lock(&dev_priv->hw_mutex);
715 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
716 mutex_unlock(&dev_priv->hw_mutex);
717 vmw_kms_restore_vga(dev_priv);
718 vmw_3d_resource_dec(dev_priv);
719 }
720
648 dev_priv->active_master = &dev_priv->fbdev_master; 721 dev_priv->active_master = &dev_priv->fbdev_master;
649 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 722 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
650 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 723 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
651 724
652 vmw_fb_on(dev_priv); 725 if (dev_priv->enable_fb)
726 vmw_fb_on(dev_priv);
653} 727}
654 728
655 729
@@ -722,6 +796,7 @@ static struct drm_driver driver = {
722 .irq_postinstall = vmw_irq_postinstall, 796 .irq_postinstall = vmw_irq_postinstall,
723 .irq_uninstall = vmw_irq_uninstall, 797 .irq_uninstall = vmw_irq_uninstall,
724 .irq_handler = vmw_irq_handler, 798 .irq_handler = vmw_irq_handler,
799 .get_vblank_counter = vmw_get_vblank_counter,
725 .reclaim_buffers_locked = NULL, 800 .reclaim_buffers_locked = NULL,
726 .get_map_ofs = drm_core_get_map_ofs, 801 .get_map_ofs = drm_core_get_map_ofs,
727 .get_reg_ofs = drm_core_get_reg_ofs, 802 .get_reg_ofs = drm_core_get_reg_ofs,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 429f917b60bf..58de6393f611 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -277,6 +277,7 @@ struct vmw_private {
277 277
278 bool stealth; 278 bool stealth;
279 bool is_opened; 279 bool is_opened;
280 bool enable_fb;
280 281
281 /** 282 /**
282 * Master management. 283 * Master management.
@@ -285,6 +286,9 @@ struct vmw_private {
285 struct vmw_master *active_master; 286 struct vmw_master *active_master;
286 struct vmw_master fbdev_master; 287 struct vmw_master fbdev_master;
287 struct notifier_block pm_nb; 288 struct notifier_block pm_nb;
289
290 struct mutex release_mutex;
291 uint32_t num_3d_resources;
288}; 292};
289 293
290static inline struct vmw_private *vmw_priv(struct drm_device *dev) 294static inline struct vmw_private *vmw_priv(struct drm_device *dev)
@@ -319,6 +323,9 @@ static inline uint32_t vmw_read(struct vmw_private *dev_priv,
319 return val; 323 return val;
320} 324}
321 325
326int vmw_3d_resource_inc(struct vmw_private *dev_priv);
327void vmw_3d_resource_dec(struct vmw_private *dev_priv);
328
322/** 329/**
323 * GMR utilities - vmwgfx_gmr.c 330 * GMR utilities - vmwgfx_gmr.c
324 */ 331 */
@@ -511,6 +518,7 @@ void vmw_kms_write_svga(struct vmw_private *vmw_priv,
511 unsigned bbp, unsigned depth); 518 unsigned bbp, unsigned depth);
512int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data, 519int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file_priv); 520 struct drm_file *file_priv);
521u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc);
514 522
515/** 523/**
516 * Overlay control - vmwgfx_overlay.c 524 * Overlay control - vmwgfx_overlay.c
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 870967a97c15..409e172f4abf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -615,6 +615,11 @@ int vmw_dmabuf_to_start_of_vram(struct vmw_private *vmw_priv,
615 if (unlikely(ret != 0)) 615 if (unlikely(ret != 0))
616 goto err_unlock; 616 goto err_unlock;
617 617
618 if (bo->mem.mem_type == TTM_PL_VRAM &&
619 bo->mem.mm_node->start < bo->num_pages)
620 (void) ttm_bo_validate(bo, &vmw_sys_placement, false,
621 false, false);
622
618 ret = ttm_bo_validate(bo, &ne_placement, false, false, false); 623 ret = ttm_bo_validate(bo, &ne_placement, false, false, false);
619 624
620 /* Could probably bug on */ 625 /* Could probably bug on */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index e6a1eb7ea954..0fe31766e4cf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -106,6 +106,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
106 mutex_lock(&dev_priv->hw_mutex); 106 mutex_lock(&dev_priv->hw_mutex);
107 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 107 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
108 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 108 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
109 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
109 vmw_write(dev_priv, SVGA_REG_ENABLE, 1); 110 vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
110 111
111 min = 4; 112 min = 4;
@@ -175,6 +176,8 @@ void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
175 dev_priv->config_done_state); 176 dev_priv->config_done_state);
176 vmw_write(dev_priv, SVGA_REG_ENABLE, 177 vmw_write(dev_priv, SVGA_REG_ENABLE,
177 dev_priv->enable_state); 178 dev_priv->enable_state);
179 vmw_write(dev_priv, SVGA_REG_TRACES,
180 dev_priv->traces_state);
178 181
179 mutex_unlock(&dev_priv->hw_mutex); 182 mutex_unlock(&dev_priv->hw_mutex);
180 vmw_fence_queue_takedown(&fifo->fence_queue); 183 vmw_fence_queue_takedown(&fifo->fence_queue);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 64d7f47df868..e882ba099f0c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -898,7 +898,19 @@ int vmw_kms_save_vga(struct vmw_private *vmw_priv)
898 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH); 898 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
899 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT); 899 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
900 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); 900 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
901 if (i == 0 && vmw_priv->num_displays == 1 &&
902 save->width == 0 && save->height == 0) {
903
904 /*
905 * It should be fairly safe to assume that these
906 * values are uninitialized.
907 */
908
909 save->width = vmw_priv->vga_width - save->pos_x;
910 save->height = vmw_priv->vga_height - save->pos_y;
911 }
901 } 912 }
913
902 return 0; 914 return 0;
903} 915}
904 916
@@ -984,3 +996,8 @@ out_unlock:
984 ttm_read_unlock(&vmaster->lock); 996 ttm_read_unlock(&vmaster->lock);
985 return ret; 997 return ret;
986} 998}
999
1000u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1001{
1002 return 0;
1003}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index 7083b1a24df3..11cb39e3accb 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -27,6 +27,8 @@
27 27
28#include "vmwgfx_kms.h" 28#include "vmwgfx_kms.h"
29 29
30#define VMWGFX_LDU_NUM_DU 8
31
30#define vmw_crtc_to_ldu(x) \ 32#define vmw_crtc_to_ldu(x) \
31 container_of(x, struct vmw_legacy_display_unit, base.crtc) 33 container_of(x, struct vmw_legacy_display_unit, base.crtc)
32#define vmw_encoder_to_ldu(x) \ 34#define vmw_encoder_to_ldu(x) \
@@ -536,6 +538,10 @@ static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit)
536 538
537int vmw_kms_init_legacy_display_system(struct vmw_private *dev_priv) 539int vmw_kms_init_legacy_display_system(struct vmw_private *dev_priv)
538{ 540{
541 struct drm_device *dev = dev_priv->dev;
542 int i;
543 int ret;
544
539 if (dev_priv->ldu_priv) { 545 if (dev_priv->ldu_priv) {
540 DRM_INFO("ldu system already on\n"); 546 DRM_INFO("ldu system already on\n");
541 return -EINVAL; 547 return -EINVAL;
@@ -553,23 +559,24 @@ int vmw_kms_init_legacy_display_system(struct vmw_private *dev_priv)
553 559
554 drm_mode_create_dirty_info_property(dev_priv->dev); 560 drm_mode_create_dirty_info_property(dev_priv->dev);
555 561
556 vmw_ldu_init(dev_priv, 0);
557 /* for old hardware without multimon only enable one display */
558 if (dev_priv->capabilities & SVGA_CAP_MULTIMON) { 562 if (dev_priv->capabilities & SVGA_CAP_MULTIMON) {
559 vmw_ldu_init(dev_priv, 1); 563 for (i = 0; i < VMWGFX_LDU_NUM_DU; ++i)
560 vmw_ldu_init(dev_priv, 2); 564 vmw_ldu_init(dev_priv, i);
561 vmw_ldu_init(dev_priv, 3); 565 ret = drm_vblank_init(dev, VMWGFX_LDU_NUM_DU);
562 vmw_ldu_init(dev_priv, 4); 566 } else {
563 vmw_ldu_init(dev_priv, 5); 567 /* for old hardware without multimon only enable one display */
564 vmw_ldu_init(dev_priv, 6); 568 vmw_ldu_init(dev_priv, 0);
565 vmw_ldu_init(dev_priv, 7); 569 ret = drm_vblank_init(dev, 1);
566 } 570 }
567 571
568 return 0; 572 return ret;
569} 573}
570 574
571int vmw_kms_close_legacy_display_system(struct vmw_private *dev_priv) 575int vmw_kms_close_legacy_display_system(struct vmw_private *dev_priv)
572{ 576{
577 struct drm_device *dev = dev_priv->dev;
578
579 drm_vblank_cleanup(dev);
573 if (!dev_priv->ldu_priv) 580 if (!dev_priv->ldu_priv)
574 return -ENOSYS; 581 return -ENOSYS;
575 582
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index 5f2d5df01e5c..c8c40e9979db 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -211,6 +211,7 @@ static void vmw_hw_context_destroy(struct vmw_resource *res)
211 cmd->body.cid = cpu_to_le32(res->id); 211 cmd->body.cid = cpu_to_le32(res->id);
212 212
213 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 213 vmw_fifo_commit(dev_priv, sizeof(*cmd));
214 vmw_3d_resource_dec(dev_priv);
214} 215}
215 216
216static int vmw_context_init(struct vmw_private *dev_priv, 217static int vmw_context_init(struct vmw_private *dev_priv,
@@ -247,6 +248,7 @@ static int vmw_context_init(struct vmw_private *dev_priv,
247 cmd->body.cid = cpu_to_le32(res->id); 248 cmd->body.cid = cpu_to_le32(res->id);
248 249
249 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 250 vmw_fifo_commit(dev_priv, sizeof(*cmd));
251 (void) vmw_3d_resource_inc(dev_priv);
250 vmw_resource_activate(res, vmw_hw_context_destroy); 252 vmw_resource_activate(res, vmw_hw_context_destroy);
251 return 0; 253 return 0;
252} 254}
@@ -406,6 +408,7 @@ static void vmw_hw_surface_destroy(struct vmw_resource *res)
406 cmd->body.sid = cpu_to_le32(res->id); 408 cmd->body.sid = cpu_to_le32(res->id);
407 409
408 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 410 vmw_fifo_commit(dev_priv, sizeof(*cmd));
411 vmw_3d_resource_dec(dev_priv);
409} 412}
410 413
411void vmw_surface_res_free(struct vmw_resource *res) 414void vmw_surface_res_free(struct vmw_resource *res)
@@ -473,6 +476,7 @@ int vmw_surface_init(struct vmw_private *dev_priv,
473 } 476 }
474 477
475 vmw_fifo_commit(dev_priv, submit_size); 478 vmw_fifo_commit(dev_priv, submit_size);
479 (void) vmw_3d_resource_inc(dev_priv);
476 vmw_resource_activate(res, vmw_hw_surface_destroy); 480 vmw_resource_activate(res, vmw_hw_surface_destroy);
477 return 0; 481 return 0;
478} 482}