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path: root/drivers/gpu/drm/radeon
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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c8
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c4
-rw-r--r--drivers/gpu/drm/radeon/cikd.h2
-rw-r--r--drivers/gpu/drm/radeon/dce3_1_afmt.c2
-rw-r--r--drivers/gpu/drm/radeon/kv_dpm.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_kfd.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c2
7 files changed, 36 insertions, 15 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index d59ec491dbb9..ed644a4f6f57 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1851,10 +1851,9 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1851 return pll; 1851 return pll;
1852 } 1852 }
1853 /* otherwise, pick one of the plls */ 1853 /* otherwise, pick one of the plls */
1854 if ((rdev->family == CHIP_KAVERI) || 1854 if ((rdev->family == CHIP_KABINI) ||
1855 (rdev->family == CHIP_KABINI) ||
1856 (rdev->family == CHIP_MULLINS)) { 1855 (rdev->family == CHIP_MULLINS)) {
1857 /* KB/KV/ML has PPLL1 and PPLL2 */ 1856 /* KB/ML has PPLL1 and PPLL2 */
1858 pll_in_use = radeon_get_pll_use_mask(crtc); 1857 pll_in_use = radeon_get_pll_use_mask(crtc);
1859 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1858 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1860 return ATOM_PPLL2; 1859 return ATOM_PPLL2;
@@ -1863,7 +1862,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1863 DRM_ERROR("unable to allocate a PPLL\n"); 1862 DRM_ERROR("unable to allocate a PPLL\n");
1864 return ATOM_PPLL_INVALID; 1863 return ATOM_PPLL_INVALID;
1865 } else { 1864 } else {
1866 /* CI has PPLL0, PPLL1, and PPLL2 */ 1865 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1867 pll_in_use = radeon_get_pll_use_mask(crtc); 1866 pll_in_use = radeon_get_pll_use_mask(crtc);
1868 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1867 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1869 return ATOM_PPLL2; 1868 return ATOM_PPLL2;
@@ -2155,6 +2154,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
2155 case ATOM_PPLL0: 2154 case ATOM_PPLL0:
2156 /* disable the ppll */ 2155 /* disable the ppll */
2157 if ((rdev->family == CHIP_ARUBA) || 2156 if ((rdev->family == CHIP_ARUBA) ||
2157 (rdev->family == CHIP_KAVERI) ||
2158 (rdev->family == CHIP_BONAIRE) || 2158 (rdev->family == CHIP_BONAIRE) ||
2159 (rdev->family == CHIP_HAWAII)) 2159 (rdev->family == CHIP_HAWAII))
2160 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2160 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 11ba9d21b89b..db42a670f995 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -492,6 +492,10 @@ int radeon_dp_mode_valid_helper(struct drm_connector *connector,
492 struct radeon_connector_atom_dig *dig_connector; 492 struct radeon_connector_atom_dig *dig_connector;
493 int dp_clock; 493 int dp_clock;
494 494
495 if ((mode->clock > 340000) &&
496 (!radeon_connector_is_dp12_capable(connector)))
497 return MODE_CLOCK_HIGH;
498
495 if (!radeon_connector->con_priv) 499 if (!radeon_connector->con_priv)
496 return MODE_CLOCK_HIGH; 500 return MODE_CLOCK_HIGH;
497 dig_connector = radeon_connector->con_priv; 501 dig_connector = radeon_connector->con_priv;
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index ba85986febea..03003f8a6de6 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -2156,4 +2156,6 @@
2156#define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu 2156#define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu
2157#define ATC_VM_APERTURE1_LOW_ADDR 0x3304u 2157#define ATC_VM_APERTURE1_LOW_ADDR 0x3304u
2158 2158
2159#define IH_VMID_0_LUT 0x3D40u
2160
2159#endif 2161#endif
diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c
index 2fe8cfc966d9..bafdf92a5732 100644
--- a/drivers/gpu/drm/radeon/dce3_1_afmt.c
+++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c
@@ -103,7 +103,7 @@ static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder)
103 } 103 }
104 104
105 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 105 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
106 if (sad_count < 0) { 106 if (sad_count <= 0) {
107 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 107 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
108 return; 108 return;
109 } 109 }
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index 9b42001295ba..e3e9c10cfba9 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -2745,13 +2745,11 @@ int kv_dpm_init(struct radeon_device *rdev)
2745 pi->enable_auto_thermal_throttling = true; 2745 pi->enable_auto_thermal_throttling = true;
2746 pi->disable_nb_ps3_in_battery = false; 2746 pi->disable_nb_ps3_in_battery = false;
2747 if (radeon_bapm == -1) { 2747 if (radeon_bapm == -1) {
2748 /* There are stability issues reported on with 2748 /* only enable bapm on KB, ML by default */
2749 * bapm enabled on an asrock system. 2749 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2750 */
2751 if (rdev->pdev->subsystem_vendor == 0x1849)
2752 pi->bapm_enable = false;
2753 else
2754 pi->bapm_enable = true; 2750 pi->bapm_enable = true;
2751 else
2752 pi->bapm_enable = false;
2755 } else if (radeon_bapm == 0) { 2753 } else if (radeon_bapm == 0) {
2756 pi->bapm_enable = false; 2754 pi->bapm_enable = false;
2757 } else { 2755 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c
index 242fd8b1b221..8bf87f1203cc 100644
--- a/drivers/gpu/drm/radeon/radeon_kfd.c
+++ b/drivers/gpu/drm/radeon/radeon_kfd.c
@@ -72,7 +72,7 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
72static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 72static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
73 uint32_t queue_id, uint32_t __user *wptr); 73 uint32_t queue_id, uint32_t __user *wptr);
74 74
75static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address, 75static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
76 uint32_t pipe_id, uint32_t queue_id); 76 uint32_t pipe_id, uint32_t queue_id);
77 77
78static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, 78static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
@@ -92,7 +92,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
92 .init_memory = kgd_init_memory, 92 .init_memory = kgd_init_memory,
93 .init_pipeline = kgd_init_pipeline, 93 .init_pipeline = kgd_init_pipeline,
94 .hqd_load = kgd_hqd_load, 94 .hqd_load = kgd_hqd_load,
95 .hqd_is_occupies = kgd_hqd_is_occupies, 95 .hqd_is_occupied = kgd_hqd_is_occupied,
96 .hqd_destroy = kgd_hqd_destroy, 96 .hqd_destroy = kgd_hqd_destroy,
97 .get_fw_version = get_fw_version 97 .get_fw_version = get_fw_version
98}; 98};
@@ -101,6 +101,7 @@ static const struct kgd2kfd_calls *kgd2kfd;
101 101
102bool radeon_kfd_init(void) 102bool radeon_kfd_init(void)
103{ 103{
104#if defined(CONFIG_HSA_AMD_MODULE)
104 bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*, 105 bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
105 const struct kgd2kfd_calls**); 106 const struct kgd2kfd_calls**);
106 107
@@ -117,6 +118,17 @@ bool radeon_kfd_init(void)
117 } 118 }
118 119
119 return true; 120 return true;
121#elif defined(CONFIG_HSA_AMD)
122 if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
123 kgd2kfd = NULL;
124
125 return false;
126 }
127
128 return true;
129#else
130 return false;
131#endif
120} 132}
121 133
122void radeon_kfd_fini(void) 134void radeon_kfd_fini(void)
@@ -378,6 +390,10 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
378 cpu_relax(); 390 cpu_relax();
379 write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 391 write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
380 392
393 /* Mapping vmid to pasid also for IH block */
394 write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t),
395 pasid_mapping);
396
381 return 0; 397 return 0;
382} 398}
383 399
@@ -517,7 +533,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
517 return 0; 533 return 0;
518} 534}
519 535
520static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address, 536static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
521 uint32_t pipe_id, uint32_t queue_id) 537 uint32_t pipe_id, uint32_t queue_id)
522{ 538{
523 uint32_t act; 539 uint32_t act;
@@ -556,6 +572,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
556 if (timeout == 0) { 572 if (timeout == 0) {
557 pr_err("kfd: cp queue preemption time out (%dms)\n", 573 pr_err("kfd: cp queue preemption time out (%dms)\n",
558 temp); 574 temp);
575 release_queue(kgd);
559 return -ETIME; 576 return -ETIME;
560 } 577 }
561 msleep(20); 578 msleep(20);
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 535403e0c8a2..15aee723db77 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1703,7 +1703,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1703 u32 format; 1703 u32 format;
1704 u32 *buffer; 1704 u32 *buffer;
1705 const u8 __user *data; 1705 const u8 __user *data;
1706 int size, dwords, tex_width, blit_width, spitch; 1706 unsigned int size, dwords, tex_width, blit_width, spitch;
1707 u32 height; 1707 u32 height;
1708 int i; 1708 int i;
1709 u32 texpitch, microtile; 1709 u32 texpitch, microtile;