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-rw-r--r--drivers/gpu/drm/radeon/evergreen.c31
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/r600.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c311
-rw-r--r--drivers/gpu/drm/radeon/r600d.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_benchmark.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c356
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h7
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c4
24 files changed, 611 insertions, 195 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 488c36c8f5e6..4dc5b4714c5a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1650,7 +1650,36 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1650 } 1650 }
1651 } 1651 }
1652 1652
1653 rdev->config.evergreen.tile_config = gb_addr_config; 1653 /* setup tiling info dword. gb_addr_config is not adequate since it does
1654 * not have bank info, so create a custom tiling dword.
1655 * bits 3:0 num_pipes
1656 * bits 7:4 num_banks
1657 * bits 11:8 group_size
1658 * bits 15:12 row_size
1659 */
1660 rdev->config.evergreen.tile_config = 0;
1661 switch (rdev->config.evergreen.max_tile_pipes) {
1662 case 1:
1663 default:
1664 rdev->config.evergreen.tile_config |= (0 << 0);
1665 break;
1666 case 2:
1667 rdev->config.evergreen.tile_config |= (1 << 0);
1668 break;
1669 case 4:
1670 rdev->config.evergreen.tile_config |= (2 << 0);
1671 break;
1672 case 8:
1673 rdev->config.evergreen.tile_config |= (3 << 0);
1674 break;
1675 }
1676 rdev->config.evergreen.tile_config |=
1677 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1678 rdev->config.evergreen.tile_config |=
1679 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1680 rdev->config.evergreen.tile_config |=
1681 ((gb_addr_config & 0x30000000) >> 28) << 12;
1682
1654 WREG32(GB_BACKEND_MAP, gb_backend_map); 1683 WREG32(GB_BACKEND_MAP, gb_backend_map);
1655 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1684 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1656 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1685 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index ac3b6dde23db..e0e590110dd4 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -459,7 +459,7 @@ int evergreen_blit_init(struct radeon_device *rdev)
459 obj_size += evergreen_ps_size * 4; 459 obj_size += evergreen_ps_size * 4;
460 obj_size = ALIGN(obj_size, 256); 460 obj_size = ALIGN(obj_size, 256);
461 461
462 r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM, 462 r = radeon_bo_create(rdev, NULL, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
463 &rdev->r600_blit.shader_obj); 463 &rdev->r600_blit.shader_obj);
464 if (r) { 464 if (r) {
465 DRM_ERROR("evergreen failed to allocate shader\n"); 465 DRM_ERROR("evergreen failed to allocate shader\n");
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0f806cc7dc75..a3552594ccc4 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2718,7 +2718,7 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev)
2718 /* Allocate ring buffer */ 2718 /* Allocate ring buffer */
2719 if (rdev->ih.ring_obj == NULL) { 2719 if (rdev->ih.ring_obj == NULL) {
2720 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2720 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2721 true, 2721 PAGE_SIZE, true,
2722 RADEON_GEM_DOMAIN_GTT, 2722 RADEON_GEM_DOMAIN_GTT,
2723 &rdev->ih.ring_obj); 2723 &rdev->ih.ring_obj);
2724 if (r) { 2724 if (r) {
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 8362974ef41a..86e5aa07f0db 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -501,7 +501,7 @@ int r600_blit_init(struct radeon_device *rdev)
501 obj_size += r6xx_ps_size * 4; 501 obj_size += r6xx_ps_size * 4;
502 obj_size = ALIGN(obj_size, 256); 502 obj_size = ALIGN(obj_size, 256);
503 503
504 r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM, 504 r = radeon_bo_create(rdev, NULL, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
505 &rdev->r600_blit.shader_obj); 505 &rdev->r600_blit.shader_obj);
506 if (r) { 506 if (r) {
507 DRM_ERROR("r600 failed to allocate shader\n"); 507 DRM_ERROR("r600 failed to allocate shader\n");
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 37cc2aa9f923..9bebac1ec006 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -50,6 +50,7 @@ struct r600_cs_track {
50 u32 nsamples; 50 u32 nsamples;
51 u32 cb_color_base_last[8]; 51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8]; 52 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8];
53 u32 cb_color_bo_offset[8]; 54 u32 cb_color_bo_offset[8];
54 struct radeon_bo *cb_color_frag_bo[8]; 55 struct radeon_bo *cb_color_frag_bo[8];
55 struct radeon_bo *cb_color_tile_bo[8]; 56 struct radeon_bo *cb_color_tile_bo[8];
@@ -67,6 +68,7 @@ struct r600_cs_track {
67 u32 db_depth_size; 68 u32 db_depth_size;
68 u32 db_offset; 69 u32 db_offset;
69 struct radeon_bo *db_bo; 70 struct radeon_bo *db_bo;
71 u64 db_bo_mc;
70}; 72};
71 73
72static inline int r600_bpe_from_format(u32 *bpe, u32 format) 74static inline int r600_bpe_from_format(u32 *bpe, u32 format)
@@ -140,6 +142,68 @@ static inline int r600_bpe_from_format(u32 *bpe, u32 format)
140 return 0; 142 return 0;
141} 143}
142 144
145struct array_mode_checker {
146 int array_mode;
147 u32 group_size;
148 u32 nbanks;
149 u32 npipes;
150 u32 nsamples;
151 u32 bpe;
152};
153
154/* returns alignment in pixels for pitch/height/depth and bytes for base */
155static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
156 u32 *pitch_align,
157 u32 *height_align,
158 u32 *depth_align,
159 u64 *base_align)
160{
161 u32 tile_width = 8;
162 u32 tile_height = 8;
163 u32 macro_tile_width = values->nbanks;
164 u32 macro_tile_height = values->npipes;
165 u32 tile_bytes = tile_width * tile_height * values->bpe * values->nsamples;
166 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
167
168 switch (values->array_mode) {
169 case ARRAY_LINEAR_GENERAL:
170 /* technically tile_width/_height for pitch/height */
171 *pitch_align = 1; /* tile_width */
172 *height_align = 1; /* tile_height */
173 *depth_align = 1;
174 *base_align = 1;
175 break;
176 case ARRAY_LINEAR_ALIGNED:
177 *pitch_align = max((u32)64, (u32)(values->group_size / values->bpe));
178 *height_align = tile_height;
179 *depth_align = 1;
180 *base_align = values->group_size;
181 break;
182 case ARRAY_1D_TILED_THIN1:
183 *pitch_align = max((u32)tile_width,
184 (u32)(values->group_size /
185 (tile_height * values->bpe * values->nsamples)));
186 *height_align = tile_height;
187 *depth_align = 1;
188 *base_align = values->group_size;
189 break;
190 case ARRAY_2D_TILED_THIN1:
191 *pitch_align = max((u32)macro_tile_width,
192 (u32)(((values->group_size / tile_height) /
193 (values->bpe * values->nsamples)) *
194 values->nbanks)) * tile_width;
195 *height_align = macro_tile_height * tile_height;
196 *depth_align = 1;
197 *base_align = max(macro_tile_bytes,
198 (*pitch_align) * values->bpe * (*height_align) * values->nsamples);
199 break;
200 default:
201 return -EINVAL;
202 }
203
204 return 0;
205}
206
143static void r600_cs_track_init(struct r600_cs_track *track) 207static void r600_cs_track_init(struct r600_cs_track *track)
144{ 208{
145 int i; 209 int i;
@@ -153,10 +217,12 @@ static void r600_cs_track_init(struct r600_cs_track *track)
153 track->cb_color_info[i] = 0; 217 track->cb_color_info[i] = 0;
154 track->cb_color_bo[i] = NULL; 218 track->cb_color_bo[i] = NULL;
155 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 219 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
220 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
156 } 221 }
157 track->cb_target_mask = 0xFFFFFFFF; 222 track->cb_target_mask = 0xFFFFFFFF;
158 track->cb_shader_mask = 0xFFFFFFFF; 223 track->cb_shader_mask = 0xFFFFFFFF;
159 track->db_bo = NULL; 224 track->db_bo = NULL;
225 track->db_bo_mc = 0xFFFFFFFF;
160 /* assume the biggest format and that htile is enabled */ 226 /* assume the biggest format and that htile is enabled */
161 track->db_depth_info = 7 | (1 << 25); 227 track->db_depth_info = 7 | (1 << 25);
162 track->db_depth_view = 0xFFFFC000; 228 track->db_depth_view = 0xFFFFC000;
@@ -168,7 +234,10 @@ static void r600_cs_track_init(struct r600_cs_track *track)
168static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 234static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
169{ 235{
170 struct r600_cs_track *track = p->track; 236 struct r600_cs_track *track = p->track;
171 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align; 237 u32 bpe = 0, slice_tile_max, size, tmp;
238 u32 height, height_align, pitch, pitch_align, depth_align;
239 u64 base_offset, base_align;
240 struct array_mode_checker array_check;
172 volatile u32 *ib = p->ib->ptr; 241 volatile u32 *ib = p->ib->ptr;
173 unsigned array_mode; 242 unsigned array_mode;
174 243
@@ -183,60 +252,40 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
183 i, track->cb_color_info[i]); 252 i, track->cb_color_info[i]);
184 return -EINVAL; 253 return -EINVAL;
185 } 254 }
186 /* pitch is the number of 8x8 tiles per row */ 255 /* pitch in pixels */
187 pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1; 256 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
188 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; 257 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
189 slice_tile_max *= 64; 258 slice_tile_max *= 64;
190 height = slice_tile_max / (pitch * 8); 259 height = slice_tile_max / pitch;
191 if (height > 8192) 260 if (height > 8192)
192 height = 8192; 261 height = 8192;
193 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); 262 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
263
264 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
265 array_check.array_mode = array_mode;
266 array_check.group_size = track->group_size;
267 array_check.nbanks = track->nbanks;
268 array_check.npipes = track->npipes;
269 array_check.nsamples = track->nsamples;
270 array_check.bpe = bpe;
271 if (r600_get_array_mode_alignment(&array_check,
272 &pitch_align, &height_align, &depth_align, &base_align)) {
273 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
274 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
275 track->cb_color_info[i]);
276 return -EINVAL;
277 }
194 switch (array_mode) { 278 switch (array_mode) {
195 case V_0280A0_ARRAY_LINEAR_GENERAL: 279 case V_0280A0_ARRAY_LINEAR_GENERAL:
196 /* technically height & 0x7 */
197 break; 280 break;
198 case V_0280A0_ARRAY_LINEAR_ALIGNED: 281 case V_0280A0_ARRAY_LINEAR_ALIGNED:
199 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
200 if (!IS_ALIGNED(pitch, pitch_align)) {
201 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
202 __func__, __LINE__, pitch);
203 return -EINVAL;
204 }
205 if (!IS_ALIGNED(height, 8)) {
206 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
207 __func__, __LINE__, height);
208 return -EINVAL;
209 }
210 break; 282 break;
211 case V_0280A0_ARRAY_1D_TILED_THIN1: 283 case V_0280A0_ARRAY_1D_TILED_THIN1:
212 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
213 if (!IS_ALIGNED(pitch, pitch_align)) {
214 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
215 __func__, __LINE__, pitch);
216 return -EINVAL;
217 }
218 /* avoid breaking userspace */ 284 /* avoid breaking userspace */
219 if (height > 7) 285 if (height > 7)
220 height &= ~0x7; 286 height &= ~0x7;
221 if (!IS_ALIGNED(height, 8)) {
222 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
223 __func__, __LINE__, height);
224 return -EINVAL;
225 }
226 break; 287 break;
227 case V_0280A0_ARRAY_2D_TILED_THIN1: 288 case V_0280A0_ARRAY_2D_TILED_THIN1:
228 pitch_align = max((u32)track->nbanks,
229 (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks)) / 8;
230 if (!IS_ALIGNED(pitch, pitch_align)) {
231 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
232 __func__, __LINE__, pitch);
233 return -EINVAL;
234 }
235 if (!IS_ALIGNED((height / 8), track->npipes)) {
236 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
237 __func__, __LINE__, height);
238 return -EINVAL;
239 }
240 break; 289 break;
241 default: 290 default:
242 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 291 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
@@ -244,13 +293,29 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
244 track->cb_color_info[i]); 293 track->cb_color_info[i]);
245 return -EINVAL; 294 return -EINVAL;
246 } 295 }
296
297 if (!IS_ALIGNED(pitch, pitch_align)) {
298 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
299 __func__, __LINE__, pitch);
300 return -EINVAL;
301 }
302 if (!IS_ALIGNED(height, height_align)) {
303 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
304 __func__, __LINE__, height);
305 return -EINVAL;
306 }
307 if (!IS_ALIGNED(base_offset, base_align)) {
308 dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset);
309 return -EINVAL;
310 }
311
247 /* check offset */ 312 /* check offset */
248 tmp = height * pitch * 8 * bpe; 313 tmp = height * pitch * bpe;
249 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 314 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
250 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { 315 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
251 /* the initial DDX does bad things with the CB size occasionally */ 316 /* the initial DDX does bad things with the CB size occasionally */
252 /* it rounds up height too far for slice tile max but the BO is smaller */ 317 /* it rounds up height too far for slice tile max but the BO is smaller */
253 tmp = (height - 7) * 8 * bpe; 318 tmp = (height - 7) * pitch * bpe;
254 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 319 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
255 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); 320 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
256 return -EINVAL; 321 return -EINVAL;
@@ -260,15 +325,11 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
260 return -EINVAL; 325 return -EINVAL;
261 } 326 }
262 } 327 }
263 if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
264 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
265 return -EINVAL;
266 }
267 /* limit max tile */ 328 /* limit max tile */
268 tmp = (height * pitch * 8) >> 6; 329 tmp = (height * pitch) >> 6;
269 if (tmp < slice_tile_max) 330 if (tmp < slice_tile_max)
270 slice_tile_max = tmp; 331 slice_tile_max = tmp;
271 tmp = S_028060_PITCH_TILE_MAX(pitch - 1) | 332 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
272 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 333 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
273 ib[track->cb_color_size_idx[i]] = tmp; 334 ib[track->cb_color_size_idx[i]] = tmp;
274 return 0; 335 return 0;
@@ -310,7 +371,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
310 /* Check depth buffer */ 371 /* Check depth buffer */
311 if (G_028800_STENCIL_ENABLE(track->db_depth_control) || 372 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
312 G_028800_Z_ENABLE(track->db_depth_control)) { 373 G_028800_Z_ENABLE(track->db_depth_control)) {
313 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size, slice_tile_max; 374 u32 nviews, bpe, ntiles, size, slice_tile_max;
375 u32 height, height_align, pitch, pitch_align, depth_align;
376 u64 base_offset, base_align;
377 struct array_mode_checker array_check;
378 int array_mode;
379
314 if (track->db_bo == NULL) { 380 if (track->db_bo == NULL) {
315 dev_warn(p->dev, "z/stencil with no depth buffer\n"); 381 dev_warn(p->dev, "z/stencil with no depth buffer\n");
316 return -EINVAL; 382 return -EINVAL;
@@ -353,41 +419,34 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
353 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); 419 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
354 } else { 420 } else {
355 size = radeon_bo_size(track->db_bo); 421 size = radeon_bo_size(track->db_bo);
356 pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1; 422 /* pitch in pixels */
423 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
357 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 424 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
358 slice_tile_max *= 64; 425 slice_tile_max *= 64;
359 height = slice_tile_max / (pitch * 8); 426 height = slice_tile_max / pitch;
360 if (height > 8192) 427 if (height > 8192)
361 height = 8192; 428 height = 8192;
362 switch (G_028010_ARRAY_MODE(track->db_depth_info)) { 429 base_offset = track->db_bo_mc + track->db_offset;
430 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
431 array_check.array_mode = array_mode;
432 array_check.group_size = track->group_size;
433 array_check.nbanks = track->nbanks;
434 array_check.npipes = track->npipes;
435 array_check.nsamples = track->nsamples;
436 array_check.bpe = bpe;
437 if (r600_get_array_mode_alignment(&array_check,
438 &pitch_align, &height_align, &depth_align, &base_align)) {
439 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
440 G_028010_ARRAY_MODE(track->db_depth_info),
441 track->db_depth_info);
442 return -EINVAL;
443 }
444 switch (array_mode) {
363 case V_028010_ARRAY_1D_TILED_THIN1: 445 case V_028010_ARRAY_1D_TILED_THIN1:
364 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
365 if (!IS_ALIGNED(pitch, pitch_align)) {
366 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
367 __func__, __LINE__, pitch);
368 return -EINVAL;
369 }
370 /* don't break userspace */ 446 /* don't break userspace */
371 height &= ~0x7; 447 height &= ~0x7;
372 if (!IS_ALIGNED(height, 8)) {
373 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
374 __func__, __LINE__, height);
375 return -EINVAL;
376 }
377 break; 448 break;
378 case V_028010_ARRAY_2D_TILED_THIN1: 449 case V_028010_ARRAY_2D_TILED_THIN1:
379 pitch_align = max((u32)track->nbanks,
380 (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
381 if (!IS_ALIGNED(pitch, pitch_align)) {
382 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
383 __func__, __LINE__, pitch);
384 return -EINVAL;
385 }
386 if (!IS_ALIGNED((height / 8), track->npipes)) {
387 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
388 __func__, __LINE__, height);
389 return -EINVAL;
390 }
391 break; 450 break;
392 default: 451 default:
393 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 452 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
@@ -395,15 +454,27 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
395 track->db_depth_info); 454 track->db_depth_info);
396 return -EINVAL; 455 return -EINVAL;
397 } 456 }
398 if (!IS_ALIGNED(track->db_offset, track->group_size)) { 457
399 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset); 458 if (!IS_ALIGNED(pitch, pitch_align)) {
459 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
460 __func__, __LINE__, pitch);
461 return -EINVAL;
462 }
463 if (!IS_ALIGNED(height, height_align)) {
464 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
465 __func__, __LINE__, height);
400 return -EINVAL; 466 return -EINVAL;
401 } 467 }
468 if (!IS_ALIGNED(base_offset, base_align)) {
469 dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset);
470 return -EINVAL;
471 }
472
402 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 473 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
403 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 474 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
404 tmp = ntiles * bpe * 64 * nviews; 475 tmp = ntiles * bpe * 64 * nviews;
405 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 476 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
406 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n", 477 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n",
407 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 478 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
408 radeon_bo_size(track->db_bo)); 479 radeon_bo_size(track->db_bo));
409 return -EINVAL; 480 return -EINVAL;
@@ -954,6 +1025,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
954 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1025 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
955 track->cb_color_base_last[tmp] = ib[idx]; 1026 track->cb_color_base_last[tmp] = ib[idx];
956 track->cb_color_bo[tmp] = reloc->robj; 1027 track->cb_color_bo[tmp] = reloc->robj;
1028 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
957 break; 1029 break;
958 case DB_DEPTH_BASE: 1030 case DB_DEPTH_BASE:
959 r = r600_cs_packet_next_reloc(p, &reloc); 1031 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -965,6 +1037,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
965 track->db_offset = radeon_get_ib_value(p, idx) << 8; 1037 track->db_offset = radeon_get_ib_value(p, idx) << 8;
966 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1038 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
967 track->db_bo = reloc->robj; 1039 track->db_bo = reloc->robj;
1040 track->db_bo_mc = reloc->lobj.gpu_offset;
968 break; 1041 break;
969 case DB_HTILE_DATA_BASE: 1042 case DB_HTILE_DATA_BASE:
970 case SQ_PGM_START_FS: 1043 case SQ_PGM_START_FS:
@@ -1086,16 +1159,25 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
1086static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, 1159static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1087 struct radeon_bo *texture, 1160 struct radeon_bo *texture,
1088 struct radeon_bo *mipmap, 1161 struct radeon_bo *mipmap,
1162 u64 base_offset,
1163 u64 mip_offset,
1089 u32 tiling_flags) 1164 u32 tiling_flags)
1090{ 1165{
1091 struct r600_cs_track *track = p->track; 1166 struct r600_cs_track *track = p->track;
1092 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0; 1167 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
1093 u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align; 1168 u32 word0, word1, l0_size, mipmap_size;
1169 u32 height_align, pitch, pitch_align, depth_align;
1170 u64 base_align;
1171 struct array_mode_checker array_check;
1094 1172
1095 /* on legacy kernel we don't perform advanced check */ 1173 /* on legacy kernel we don't perform advanced check */
1096 if (p->rdev == NULL) 1174 if (p->rdev == NULL)
1097 return 0; 1175 return 0;
1098 1176
1177 /* convert to bytes */
1178 base_offset <<= 8;
1179 mip_offset <<= 8;
1180
1099 word0 = radeon_get_ib_value(p, idx + 0); 1181 word0 = radeon_get_ib_value(p, idx + 0);
1100 if (tiling_flags & RADEON_TILING_MACRO) 1182 if (tiling_flags & RADEON_TILING_MACRO)
1101 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1183 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
@@ -1128,46 +1210,38 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1128 return -EINVAL; 1210 return -EINVAL;
1129 } 1211 }
1130 1212
1131 pitch = G_038000_PITCH(word0) + 1; 1213 /* pitch in texels */
1132 switch (G_038000_TILE_MODE(word0)) { 1214 pitch = (G_038000_PITCH(word0) + 1) * 8;
1133 case V_038000_ARRAY_LINEAR_GENERAL: 1215 array_check.array_mode = G_038000_TILE_MODE(word0);
1134 pitch_align = 1; 1216 array_check.group_size = track->group_size;
1135 /* XXX check height align */ 1217 array_check.nbanks = track->nbanks;
1136 break; 1218 array_check.npipes = track->npipes;
1137 case V_038000_ARRAY_LINEAR_ALIGNED: 1219 array_check.nsamples = 1;
1138 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8; 1220 array_check.bpe = bpe;
1139 if (!IS_ALIGNED(pitch, pitch_align)) { 1221 if (r600_get_array_mode_alignment(&array_check,
1140 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", 1222 &pitch_align, &height_align, &depth_align, &base_align)) {
1141 __func__, __LINE__, pitch); 1223 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1142 return -EINVAL; 1224 __func__, __LINE__, G_038000_TILE_MODE(word0));
1143 } 1225 return -EINVAL;
1144 /* XXX check height align */ 1226 }
1145 break; 1227
1146 case V_038000_ARRAY_1D_TILED_THIN1: 1228 /* XXX check height as well... */
1147 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8; 1229
1148 if (!IS_ALIGNED(pitch, pitch_align)) { 1230 if (!IS_ALIGNED(pitch, pitch_align)) {
1149 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", 1231 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1150 __func__, __LINE__, pitch); 1232 __func__, __LINE__, pitch);
1151 return -EINVAL; 1233 return -EINVAL;
1152 } 1234 }
1153 /* XXX check height align */ 1235 if (!IS_ALIGNED(base_offset, base_align)) {
1154 break; 1236 dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n",
1155 case V_038000_ARRAY_2D_TILED_THIN1: 1237 __func__, __LINE__, base_offset);
1156 pitch_align = max((u32)track->nbanks, 1238 return -EINVAL;
1157 (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8; 1239 }
1158 if (!IS_ALIGNED(pitch, pitch_align)) { 1240 if (!IS_ALIGNED(mip_offset, base_align)) {
1159 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", 1241 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n",
1160 __func__, __LINE__, pitch); 1242 __func__, __LINE__, mip_offset);
1161 return -EINVAL;
1162 }
1163 /* XXX check height align */
1164 break;
1165 default:
1166 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1167 G_038000_TILE_MODE(word0), word0);
1168 return -EINVAL; 1243 return -EINVAL;
1169 } 1244 }
1170 /* XXX check offset align */
1171 1245
1172 word0 = radeon_get_ib_value(p, idx + 4); 1246 word0 = radeon_get_ib_value(p, idx + 4);
1173 word1 = radeon_get_ib_value(p, idx + 5); 1247 word1 = radeon_get_ib_value(p, idx + 5);
@@ -1402,7 +1476,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1402 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1476 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1403 mipmap = reloc->robj; 1477 mipmap = reloc->robj;
1404 r = r600_check_texture_resource(p, idx+(i*7)+1, 1478 r = r600_check_texture_resource(p, idx+(i*7)+1,
1405 texture, mipmap, reloc->lobj.tiling_flags); 1479 texture, mipmap,
1480 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1481 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1482 reloc->lobj.tiling_flags);
1406 if (r) 1483 if (r)
1407 return r; 1484 return r;
1408 ib[idx+1+(i*7)+2] += base_offset; 1485 ib[idx+1+(i*7)+2] += base_offset;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 966a793e225b..bff4dc4f410f 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -51,6 +51,12 @@
51#define PTE_READABLE (1 << 5) 51#define PTE_READABLE (1 << 5)
52#define PTE_WRITEABLE (1 << 6) 52#define PTE_WRITEABLE (1 << 6)
53 53
54/* tiling bits */
55#define ARRAY_LINEAR_GENERAL 0x00000000
56#define ARRAY_LINEAR_ALIGNED 0x00000001
57#define ARRAY_1D_TILED_THIN1 0x00000002
58#define ARRAY_2D_TILED_THIN1 0x00000004
59
54/* Registers */ 60/* Registers */
55#define ARB_POP 0x2418 61#define ARB_POP 0x2418
56#define ENABLE_TC128 (1 << 30) 62#define ENABLE_TC128 (1 << 30)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 73f600d39ad4..3a7095743d44 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1262,6 +1262,10 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
1262 (rdev->family == CHIP_RS400) || \ 1262 (rdev->family == CHIP_RS400) || \
1263 (rdev->family == CHIP_RS480)) 1263 (rdev->family == CHIP_RS480))
1264#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1264#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1265#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1266 (rdev->family == CHIP_RS690) || \
1267 (rdev->family == CHIP_RS740) || \
1268 (rdev->family >= CHIP_R600))
1265#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1269#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1266#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1270#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1267#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1271#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 7932dc4d6b90..c558685cc637 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -41,7 +41,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
41 41
42 size = bsize; 42 size = bsize;
43 n = 1024; 43 n = 1024;
44 r = radeon_bo_create(rdev, NULL, size, true, sdomain, &sobj); 44 r = radeon_bo_create(rdev, NULL, size, PAGE_SIZE, true, sdomain, &sobj);
45 if (r) { 45 if (r) {
46 goto out_cleanup; 46 goto out_cleanup;
47 } 47 }
@@ -53,7 +53,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
53 if (r) { 53 if (r) {
54 goto out_cleanup; 54 goto out_cleanup;
55 } 55 }
56 r = radeon_bo_create(rdev, NULL, size, true, ddomain, &dobj); 56 r = radeon_bo_create(rdev, NULL, size, PAGE_SIZE, true, ddomain, &dobj);
57 if (r) { 57 if (r) {
58 goto out_cleanup; 58 goto out_cleanup;
59 } 59 }
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 7b7ea269549c..3bddea5b5295 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -571,6 +571,7 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
571 } 571 }
572 572
573 if (clk_mask && data_mask) { 573 if (clk_mask && data_mask) {
574 /* system specific masks */
574 i2c.mask_clk_mask = clk_mask; 575 i2c.mask_clk_mask = clk_mask;
575 i2c.mask_data_mask = data_mask; 576 i2c.mask_data_mask = data_mask;
576 i2c.a_clk_mask = clk_mask; 577 i2c.a_clk_mask = clk_mask;
@@ -579,7 +580,19 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
579 i2c.en_data_mask = data_mask; 580 i2c.en_data_mask = data_mask;
580 i2c.y_clk_mask = clk_mask; 581 i2c.y_clk_mask = clk_mask;
581 i2c.y_data_mask = data_mask; 582 i2c.y_data_mask = data_mask;
583 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
584 (ddc_line == RADEON_MDGPIO_MASK)) {
585 /* default gpiopad masks */
586 i2c.mask_clk_mask = (0x20 << 8);
587 i2c.mask_data_mask = 0x80;
588 i2c.a_clk_mask = (0x20 << 8);
589 i2c.a_data_mask = 0x80;
590 i2c.en_clk_mask = (0x20 << 8);
591 i2c.en_data_mask = 0x80;
592 i2c.y_clk_mask = (0x20 << 8);
593 i2c.y_data_mask = 0x80;
582 } else { 594 } else {
595 /* default masks for ddc pads */
583 i2c.mask_clk_mask = RADEON_GPIO_EN_1; 596 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
584 i2c.mask_data_mask = RADEON_GPIO_EN_0; 597 i2c.mask_data_mask = RADEON_GPIO_EN_0;
585 i2c.a_clk_mask = RADEON_GPIO_A_1; 598 i2c.a_clk_mask = RADEON_GPIO_A_1;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index fe6c74780f18..3bef9f6d66fd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1008,9 +1008,21 @@ static void radeon_dp_connector_destroy(struct drm_connector *connector)
1008static int radeon_dp_get_modes(struct drm_connector *connector) 1008static int radeon_dp_get_modes(struct drm_connector *connector)
1009{ 1009{
1010 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1010 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1011 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1011 int ret; 1012 int ret;
1012 1013
1014 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1015 if (!radeon_dig_connector->edp_on)
1016 atombios_set_edp_panel_power(connector,
1017 ATOM_TRANSMITTER_ACTION_POWER_ON);
1018 }
1013 ret = radeon_ddc_get_modes(radeon_connector); 1019 ret = radeon_ddc_get_modes(radeon_connector);
1020 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1021 if (!radeon_dig_connector->edp_on)
1022 atombios_set_edp_panel_power(connector,
1023 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1024 }
1025
1014 return ret; 1026 return ret;
1015} 1027}
1016 1028
@@ -1029,8 +1041,14 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
1029 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1041 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1030 /* eDP is always DP */ 1042 /* eDP is always DP */
1031 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1043 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1044 if (!radeon_dig_connector->edp_on)
1045 atombios_set_edp_panel_power(connector,
1046 ATOM_TRANSMITTER_ACTION_POWER_ON);
1032 if (radeon_dp_getdpcd(radeon_connector)) 1047 if (radeon_dp_getdpcd(radeon_connector))
1033 ret = connector_status_connected; 1048 ret = connector_status_connected;
1049 if (!radeon_dig_connector->edp_on)
1050 atombios_set_edp_panel_power(connector,
1051 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1034 } else { 1052 } else {
1035 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); 1053 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
1036 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1054 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 8adfedfe547f..d8ac1849180d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -180,7 +180,7 @@ int radeon_wb_init(struct radeon_device *rdev)
180 int r; 180 int r;
181 181
182 if (rdev->wb.wb_obj == NULL) { 182 if (rdev->wb.wb_obj == NULL) {
183 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, 183 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
184 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); 184 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
185 if (r) { 185 if (r) {
186 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 186 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index f678257c42e6..041943df966b 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -176,6 +176,7 @@ static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
176 return false; 176 return false;
177 } 177 }
178} 178}
179
179void 180void
180radeon_link_encoder_connector(struct drm_device *dev) 181radeon_link_encoder_connector(struct drm_device *dev)
181{ 182{
@@ -228,6 +229,27 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
228 return NULL; 229 return NULL;
229} 230}
230 231
232struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233{
234 struct drm_device *dev = encoder->dev;
235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236 struct drm_encoder *other_encoder;
237 struct radeon_encoder *other_radeon_encoder;
238
239 if (radeon_encoder->is_ext_encoder)
240 return NULL;
241
242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243 if (other_encoder == encoder)
244 continue;
245 other_radeon_encoder = to_radeon_encoder(other_encoder);
246 if (other_radeon_encoder->is_ext_encoder &&
247 (radeon_encoder->devices & other_radeon_encoder->devices))
248 return other_encoder;
249 }
250 return NULL;
251}
252
231void radeon_panel_mode_fixup(struct drm_encoder *encoder, 253void radeon_panel_mode_fixup(struct drm_encoder *encoder,
232 struct drm_display_mode *adjusted_mode) 254 struct drm_display_mode *adjusted_mode)
233{ 255{
@@ -426,52 +448,49 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
426 448
427} 449}
428 450
429void 451union dvo_encoder_control {
430atombios_external_tmds_setup(struct drm_encoder *encoder, int action) 452 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
431{ 453 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
432 struct drm_device *dev = encoder->dev; 454 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
433 struct radeon_device *rdev = dev->dev_private; 455};
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
436 int index = 0;
437
438 memset(&args, 0, sizeof(args));
439
440 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
441
442 args.sXTmdsEncoder.ucEnable = action;
443
444 if (radeon_encoder->pixel_clock > 165000)
445 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
446
447 /*if (pScrn->rgbBits == 8)*/
448 args.sXTmdsEncoder.ucMisc |= (1 << 1);
449
450 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
451
452}
453 456
454static void 457void
455atombios_ddia_setup(struct drm_encoder *encoder, int action) 458atombios_dvo_setup(struct drm_encoder *encoder, int action)
456{ 459{
457 struct drm_device *dev = encoder->dev; 460 struct drm_device *dev = encoder->dev;
458 struct radeon_device *rdev = dev->dev_private; 461 struct radeon_device *rdev = dev->dev_private;
459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
460 DVO_ENCODER_CONTROL_PS_ALLOCATION args; 463 union dvo_encoder_control args;
461 int index = 0; 464 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
462 465
463 memset(&args, 0, sizeof(args)); 466 memset(&args, 0, sizeof(args));
464 467
465 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 468 if (ASIC_IS_DCE3(rdev)) {
469 /* DCE3+ */
470 args.dvo_v3.ucAction = action;
471 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472 args.dvo_v3.ucDVOConfig = 0; /* XXX */
473 } else if (ASIC_IS_DCE2(rdev)) {
474 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
475 args.dvo.sDVOEncoder.ucAction = action;
476 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
477 /* DFP1, CRT1, TV1 depending on the type of port */
478 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
479
480 if (radeon_encoder->pixel_clock > 165000)
481 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
482 } else {
483 /* R4xx, R5xx */
484 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
466 485
467 args.sDVOEncoder.ucAction = action; 486 if (radeon_encoder->pixel_clock > 165000)
468 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 487 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
469 488
470 if (radeon_encoder->pixel_clock > 165000) 489 /*if (pScrn->rgbBits == 8)*/
471 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; 490 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
491 }
472 492
473 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
474
475} 494}
476 495
477union lvds_encoder_control { 496union lvds_encoder_control {
@@ -532,14 +551,14 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
532 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 551 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
533 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 552 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
534 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 553 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
535 args.v1.ucMisc |= (1 << 1); 554 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
536 } else { 555 } else {
537 if (dig->linkb) 556 if (dig->linkb)
538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 557 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
539 if (radeon_encoder->pixel_clock > 165000) 558 if (radeon_encoder->pixel_clock > 165000)
540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 559 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
541 /*if (pScrn->rgbBits == 8) */ 560 /*if (pScrn->rgbBits == 8) */
542 args.v1.ucMisc |= (1 << 1); 561 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
543 } 562 }
544 break; 563 break;
545 case 2: 564 case 2:
@@ -595,6 +614,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
595int 614int
596atombios_get_encoder_mode(struct drm_encoder *encoder) 615atombios_get_encoder_mode(struct drm_encoder *encoder)
597{ 616{
617 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
598 struct drm_device *dev = encoder->dev; 618 struct drm_device *dev = encoder->dev;
599 struct radeon_device *rdev = dev->dev_private; 619 struct radeon_device *rdev = dev->dev_private;
600 struct drm_connector *connector; 620 struct drm_connector *connector;
@@ -602,9 +622,20 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
602 struct radeon_connector_atom_dig *dig_connector; 622 struct radeon_connector_atom_dig *dig_connector;
603 623
604 connector = radeon_get_connector_for_encoder(encoder); 624 connector = radeon_get_connector_for_encoder(encoder);
605 if (!connector) 625 if (!connector) {
606 return 0; 626 switch (radeon_encoder->encoder_id) {
607 627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
632 return ATOM_ENCODER_MODE_DVI;
633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
635 default:
636 return ATOM_ENCODER_MODE_CRT;
637 }
638 }
608 radeon_connector = to_radeon_connector(connector); 639 radeon_connector = to_radeon_connector(connector);
609 640
610 switch (connector->connector_type) { 641 switch (connector->connector_type) {
@@ -834,6 +865,9 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
834 memset(&args, 0, sizeof(args)); 865 memset(&args, 0, sizeof(args));
835 866
836 switch (radeon_encoder->encoder_id) { 867 switch (radeon_encoder->encoder_id) {
868 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
869 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
870 break;
837 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 871 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
838 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
@@ -978,6 +1012,105 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
978 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
979} 1013}
980 1014
1015void
1016atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1017{
1018 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1019 struct drm_device *dev = radeon_connector->base.dev;
1020 struct radeon_device *rdev = dev->dev_private;
1021 union dig_transmitter_control args;
1022 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1023 uint8_t frev, crev;
1024
1025 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1026 return;
1027
1028 if (!ASIC_IS_DCE4(rdev))
1029 return;
1030
1031 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1032 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1033 return;
1034
1035 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1036 return;
1037
1038 memset(&args, 0, sizeof(args));
1039
1040 args.v1.ucAction = action;
1041
1042 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1043}
1044
1045union external_encoder_control {
1046 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1047};
1048
1049static void
1050atombios_external_encoder_setup(struct drm_encoder *encoder,
1051 struct drm_encoder *ext_encoder,
1052 int action)
1053{
1054 struct drm_device *dev = encoder->dev;
1055 struct radeon_device *rdev = dev->dev_private;
1056 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1057 union external_encoder_control args;
1058 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1059 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1060 u8 frev, crev;
1061 int dp_clock = 0;
1062 int dp_lane_count = 0;
1063 int connector_object_id = 0;
1064
1065 if (connector) {
1066 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1067 struct radeon_connector_atom_dig *dig_connector =
1068 radeon_connector->con_priv;
1069
1070 dp_clock = dig_connector->dp_clock;
1071 dp_lane_count = dig_connector->dp_lane_count;
1072 connector_object_id =
1073 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1074 }
1075
1076 memset(&args, 0, sizeof(args));
1077
1078 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1079 return;
1080
1081 switch (frev) {
1082 case 1:
1083 /* no params on frev 1 */
1084 break;
1085 case 2:
1086 switch (crev) {
1087 case 1:
1088 case 2:
1089 args.v1.sDigEncoder.ucAction = action;
1090 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1091 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1092
1093 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1094 if (dp_clock == 270000)
1095 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1096 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1097 } else if (radeon_encoder->pixel_clock > 165000)
1098 args.v1.sDigEncoder.ucLaneNum = 8;
1099 else
1100 args.v1.sDigEncoder.ucLaneNum = 4;
1101 break;
1102 default:
1103 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1104 return;
1105 }
1106 break;
1107 default:
1108 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1109 return;
1110 }
1111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112}
1113
981static void 1114static void
982atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1115atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
983{ 1116{
@@ -1021,6 +1154,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1021 struct drm_device *dev = encoder->dev; 1154 struct drm_device *dev = encoder->dev;
1022 struct radeon_device *rdev = dev->dev_private; 1155 struct radeon_device *rdev = dev->dev_private;
1023 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1157 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1024 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1158 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1025 int index = 0; 1159 int index = 0;
1026 bool is_dig = false; 1160 bool is_dig = false;
@@ -1043,9 +1177,14 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1043 break; 1177 break;
1044 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1178 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1045 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1179 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1047 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1180 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1048 break; 1181 break;
1182 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1183 if (ASIC_IS_DCE3(rdev))
1184 is_dig = true;
1185 else
1186 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1187 break;
1049 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1188 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1050 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1189 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1051 break; 1190 break;
@@ -1082,34 +1221,85 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1082 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1221 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1083 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1222 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1084 1223
1224 if (connector &&
1225 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1226 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1227 struct radeon_connector_atom_dig *radeon_dig_connector =
1228 radeon_connector->con_priv;
1229 atombios_set_edp_panel_power(connector,
1230 ATOM_TRANSMITTER_ACTION_POWER_ON);
1231 radeon_dig_connector->edp_on = true;
1232 }
1085 dp_link_train(encoder, connector); 1233 dp_link_train(encoder, connector);
1086 if (ASIC_IS_DCE4(rdev)) 1234 if (ASIC_IS_DCE4(rdev))
1087 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); 1235 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1088 } 1236 }
1237 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1238 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1089 break; 1239 break;
1090 case DRM_MODE_DPMS_STANDBY: 1240 case DRM_MODE_DPMS_STANDBY:
1091 case DRM_MODE_DPMS_SUSPEND: 1241 case DRM_MODE_DPMS_SUSPEND:
1092 case DRM_MODE_DPMS_OFF: 1242 case DRM_MODE_DPMS_OFF:
1093 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1243 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1094 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1244 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1245 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1246
1095 if (ASIC_IS_DCE4(rdev)) 1247 if (ASIC_IS_DCE4(rdev))
1096 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); 1248 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1249 if (connector &&
1250 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1251 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1252 struct radeon_connector_atom_dig *radeon_dig_connector =
1253 radeon_connector->con_priv;
1254 atombios_set_edp_panel_power(connector,
1255 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1256 radeon_dig_connector->edp_on = false;
1257 }
1097 } 1258 }
1259 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1260 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1098 break; 1261 break;
1099 } 1262 }
1100 } else { 1263 } else {
1101 switch (mode) { 1264 switch (mode) {
1102 case DRM_MODE_DPMS_ON: 1265 case DRM_MODE_DPMS_ON:
1103 args.ucAction = ATOM_ENABLE; 1266 args.ucAction = ATOM_ENABLE;
1267 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1268 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1269 args.ucAction = ATOM_LCD_BLON;
1270 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1271 }
1104 break; 1272 break;
1105 case DRM_MODE_DPMS_STANDBY: 1273 case DRM_MODE_DPMS_STANDBY:
1106 case DRM_MODE_DPMS_SUSPEND: 1274 case DRM_MODE_DPMS_SUSPEND:
1107 case DRM_MODE_DPMS_OFF: 1275 case DRM_MODE_DPMS_OFF:
1108 args.ucAction = ATOM_DISABLE; 1276 args.ucAction = ATOM_DISABLE;
1277 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1278 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1279 args.ucAction = ATOM_LCD_BLOFF;
1280 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1281 }
1109 break; 1282 break;
1110 } 1283 }
1111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112 } 1284 }
1285
1286 if (ext_encoder) {
1287 int action;
1288
1289 switch (mode) {
1290 case DRM_MODE_DPMS_ON:
1291 default:
1292 action = ATOM_ENABLE;
1293 break;
1294 case DRM_MODE_DPMS_STANDBY:
1295 case DRM_MODE_DPMS_SUSPEND:
1296 case DRM_MODE_DPMS_OFF:
1297 action = ATOM_DISABLE;
1298 break;
1299 }
1300 atombios_external_encoder_setup(encoder, ext_encoder, action);
1301 }
1302
1113 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1303 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1114 1304
1115} 1305}
@@ -1242,7 +1432,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1242 break; 1432 break;
1243 default: 1433 default:
1244 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1434 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1245 break; 1435 return;
1246 } 1436 }
1247 1437
1248 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1438 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -1357,6 +1547,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1357 struct drm_device *dev = encoder->dev; 1547 struct drm_device *dev = encoder->dev;
1358 struct radeon_device *rdev = dev->dev_private; 1548 struct radeon_device *rdev = dev->dev_private;
1359 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1549 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1550 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1360 1551
1361 radeon_encoder->pixel_clock = adjusted_mode->clock; 1552 radeon_encoder->pixel_clock = adjusted_mode->clock;
1362 1553
@@ -1400,11 +1591,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1400 } 1591 }
1401 break; 1592 break;
1402 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1593 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1403 atombios_ddia_setup(encoder, ATOM_ENABLE);
1404 break;
1405 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1594 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1406 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1407 atombios_external_tmds_setup(encoder, ATOM_ENABLE); 1596 atombios_dvo_setup(encoder, ATOM_ENABLE);
1408 break; 1597 break;
1409 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1598 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1410 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
@@ -1419,6 +1608,11 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1419 } 1608 }
1420 break; 1609 break;
1421 } 1610 }
1611
1612 if (ext_encoder) {
1613 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1614 }
1615
1422 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1616 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1423 1617
1424 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1618 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
@@ -1595,11 +1789,9 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1595 } 1789 }
1596 break; 1790 break;
1597 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1791 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1598 atombios_ddia_setup(encoder, ATOM_DISABLE);
1599 break;
1600 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1792 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1601 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1602 atombios_external_tmds_setup(encoder, ATOM_DISABLE); 1794 atombios_dvo_setup(encoder, ATOM_DISABLE);
1603 break; 1795 break;
1604 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1796 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1605 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1797 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
@@ -1621,6 +1813,53 @@ disable_done:
1621 radeon_encoder->active_device = 0; 1813 radeon_encoder->active_device = 0;
1622} 1814}
1623 1815
1816/* these are handled by the primary encoders */
1817static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1818{
1819
1820}
1821
1822static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1823{
1824
1825}
1826
1827static void
1828radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1829 struct drm_display_mode *mode,
1830 struct drm_display_mode *adjusted_mode)
1831{
1832
1833}
1834
1835static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1836{
1837
1838}
1839
1840static void
1841radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
1842{
1843
1844}
1845
1846static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
1847 struct drm_display_mode *mode,
1848 struct drm_display_mode *adjusted_mode)
1849{
1850 return true;
1851}
1852
1853static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
1854 .dpms = radeon_atom_ext_dpms,
1855 .mode_fixup = radeon_atom_ext_mode_fixup,
1856 .prepare = radeon_atom_ext_prepare,
1857 .mode_set = radeon_atom_ext_mode_set,
1858 .commit = radeon_atom_ext_commit,
1859 .disable = radeon_atom_ext_disable,
1860 /* no detect for TMDS/LVDS yet */
1861};
1862
1624static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 1863static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1625 .dpms = radeon_atom_encoder_dpms, 1864 .dpms = radeon_atom_encoder_dpms,
1626 .mode_fixup = radeon_atom_mode_fixup, 1865 .mode_fixup = radeon_atom_mode_fixup,
@@ -1730,6 +1969,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t
1730 radeon_encoder->devices = supported_device; 1969 radeon_encoder->devices = supported_device;
1731 radeon_encoder->rmx_type = RMX_OFF; 1970 radeon_encoder->rmx_type = RMX_OFF;
1732 radeon_encoder->underscan_type = UNDERSCAN_OFF; 1971 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1972 radeon_encoder->is_ext_encoder = false;
1733 1973
1734 switch (radeon_encoder->encoder_id) { 1974 switch (radeon_encoder->encoder_id) {
1735 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1975 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
@@ -1771,6 +2011,9 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t
1771 radeon_encoder->rmx_type = RMX_FULL; 2011 radeon_encoder->rmx_type = RMX_FULL;
1772 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2012 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1773 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2013 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2014 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2015 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2016 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1774 } else { 2017 } else {
1775 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2018 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1776 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2019 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
@@ -1779,5 +2022,22 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t
1779 } 2022 }
1780 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2023 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1781 break; 2024 break;
2025 case ENCODER_OBJECT_ID_SI170B:
2026 case ENCODER_OBJECT_ID_CH7303:
2027 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2028 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2029 case ENCODER_OBJECT_ID_TITFP513:
2030 case ENCODER_OBJECT_ID_VT1623:
2031 case ENCODER_OBJECT_ID_HDMI_SI1930:
2032 /* these are handled by the primary encoders */
2033 radeon_encoder->is_ext_encoder = true;
2034 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2035 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2036 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2037 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2038 else
2039 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2040 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2041 break;
1782 } 2042 }
1783} 2043}
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index e65b90317fab..65016117d95f 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -79,8 +79,8 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
79 79
80 if (rdev->gart.table.vram.robj == NULL) { 80 if (rdev->gart.table.vram.robj == NULL) {
81 r = radeon_bo_create(rdev, NULL, rdev->gart.table_size, 81 r = radeon_bo_create(rdev, NULL, rdev->gart.table_size,
82 true, RADEON_GEM_DOMAIN_VRAM, 82 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
83 &rdev->gart.table.vram.robj); 83 &rdev->gart.table.vram.robj);
84 if (r) { 84 if (r) {
85 return r; 85 return r;
86 } 86 }
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index d1e595d91723..df95eb83dac6 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -67,7 +67,7 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size,
67 if (alignment < PAGE_SIZE) { 67 if (alignment < PAGE_SIZE) {
68 alignment = PAGE_SIZE; 68 alignment = PAGE_SIZE;
69 } 69 }
70 r = radeon_bo_create(rdev, gobj, size, kernel, initial_domain, &robj); 70 r = radeon_bo_create(rdev, gobj, size, alignment, kernel, initial_domain, &robj);
71 if (r) { 71 if (r) {
72 if (r != -ERESTARTSYS) 72 if (r != -ERESTARTSYS)
73 DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n", 73 DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n",
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 0cfbba02c4d0..ded2a45bc95c 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -896,7 +896,8 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
896 ((rdev->family <= CHIP_RS480) || 896 ((rdev->family <= CHIP_RS480) ||
897 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 897 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
898 /* set the radeon hw i2c adapter */ 898 /* set the radeon hw i2c adapter */
899 sprintf(i2c->adapter.name, "Radeon i2c hw bus %s", name); 899 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
900 "Radeon i2c hw bus %s", name);
900 i2c->adapter.algo = &radeon_i2c_algo; 901 i2c->adapter.algo = &radeon_i2c_algo;
901 ret = i2c_add_adapter(&i2c->adapter); 902 ret = i2c_add_adapter(&i2c->adapter);
902 if (ret) { 903 if (ret) {
@@ -905,7 +906,8 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
905 } 906 }
906 } else { 907 } else {
907 /* set the radeon bit adapter */ 908 /* set the radeon bit adapter */
908 sprintf(i2c->adapter.name, "Radeon i2c bit bus %s", name); 909 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
910 "Radeon i2c bit bus %s", name);
909 i2c->adapter.algo_data = &i2c->algo.bit; 911 i2c->adapter.algo_data = &i2c->algo.bit;
910 i2c->algo.bit.pre_xfer = pre_xfer; 912 i2c->algo.bit.pre_xfer = pre_xfer;
911 i2c->algo.bit.post_xfer = post_xfer; 913 i2c->algo.bit.post_xfer = post_xfer;
@@ -946,6 +948,8 @@ struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
946 i2c->rec = *rec; 948 i2c->rec = *rec;
947 i2c->adapter.owner = THIS_MODULE; 949 i2c->adapter.owner = THIS_MODULE;
948 i2c->dev = dev; 950 i2c->dev = dev;
951 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
952 "Radeon aux bus %s", name);
949 i2c_set_adapdata(&i2c->adapter, i2c); 953 i2c_set_adapdata(&i2c->adapter, i2c);
950 i2c->adapter.algo_data = &i2c->algo.dp; 954 i2c->adapter.algo_data = &i2c->algo.dp;
951 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; 955 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 2f349a300195..465746bd51b7 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -76,7 +76,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
76 default: 76 default:
77 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", 77 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
78 crtc); 78 crtc);
79 return EINVAL; 79 return -EINVAL;
80 } 80 }
81 } else { 81 } else {
82 switch (crtc) { 82 switch (crtc) {
@@ -89,7 +89,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
89 default: 89 default:
90 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", 90 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
91 crtc); 91 crtc);
92 return EINVAL; 92 return -EINVAL;
93 } 93 }
94 } 94 }
95 95
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 0b8397000f4c..59f834ba283d 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -670,7 +670,7 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
670 670
671 if (rdev->is_atom_bios) { 671 if (rdev->is_atom_bios) {
672 radeon_encoder->pixel_clock = adjusted_mode->clock; 672 radeon_encoder->pixel_clock = adjusted_mode->clock;
673 atombios_external_tmds_setup(encoder, ATOM_ENABLE); 673 atombios_dvo_setup(encoder, ATOM_ENABLE);
674 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 674 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
675 } else { 675 } else {
676 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 676 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 680f57644e86..e301c6f9e059 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -375,6 +375,7 @@ struct radeon_encoder {
375 int hdmi_config_offset; 375 int hdmi_config_offset;
376 int hdmi_audio_workaround; 376 int hdmi_audio_workaround;
377 int hdmi_buffer_status; 377 int hdmi_buffer_status;
378 bool is_ext_encoder;
378}; 379};
379 380
380struct radeon_connector_atom_dig { 381struct radeon_connector_atom_dig {
@@ -385,6 +386,7 @@ struct radeon_connector_atom_dig {
385 u8 dp_sink_type; 386 u8 dp_sink_type;
386 int dp_clock; 387 int dp_clock;
387 int dp_lane_count; 388 int dp_lane_count;
389 bool edp_on;
388}; 390};
389 391
390struct radeon_gpio_rec { 392struct radeon_gpio_rec {
@@ -523,9 +525,10 @@ struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev
523struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 525struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
524struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 526struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
525struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 527struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
526extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 528extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
527extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 529extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
528extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 530extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
531extern void atombios_set_edp_panel_power(struct drm_connector *connector, int action);
529extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 532extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
530 533
531extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 534extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 8eb183466015..1d067743fee0 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -86,11 +86,12 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
86} 86}
87 87
88int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, 88int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
89 unsigned long size, bool kernel, u32 domain, 89 unsigned long size, int byte_align, bool kernel, u32 domain,
90 struct radeon_bo **bo_ptr) 90 struct radeon_bo **bo_ptr)
91{ 91{
92 struct radeon_bo *bo; 92 struct radeon_bo *bo;
93 enum ttm_bo_type type; 93 enum ttm_bo_type type;
94 int page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
94 int r; 95 int r;
95 96
96 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { 97 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
@@ -115,7 +116,7 @@ retry:
115 /* Kernel allocation are uninterruptible */ 116 /* Kernel allocation are uninterruptible */
116 mutex_lock(&rdev->vram_mutex); 117 mutex_lock(&rdev->vram_mutex);
117 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 118 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
118 &bo->placement, 0, 0, !kernel, NULL, size, 119 &bo->placement, page_align, 0, !kernel, NULL, size,
119 &radeon_ttm_bo_destroy); 120 &radeon_ttm_bo_destroy);
120 mutex_unlock(&rdev->vram_mutex); 121 mutex_unlock(&rdev->vram_mutex);
121 if (unlikely(r != 0)) { 122 if (unlikely(r != 0)) {
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 3481bc7f6f58..d143702b244a 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -137,9 +137,10 @@ static inline int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
137} 137}
138 138
139extern int radeon_bo_create(struct radeon_device *rdev, 139extern int radeon_bo_create(struct radeon_device *rdev,
140 struct drm_gem_object *gobj, unsigned long size, 140 struct drm_gem_object *gobj, unsigned long size,
141 bool kernel, u32 domain, 141 int byte_align,
142 struct radeon_bo **bo_ptr); 142 bool kernel, u32 domain,
143 struct radeon_bo **bo_ptr);
143extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr); 144extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
144extern void radeon_bo_kunmap(struct radeon_bo *bo); 145extern void radeon_bo_kunmap(struct radeon_bo *bo);
145extern void radeon_bo_unref(struct radeon_bo **bo); 146extern void radeon_bo_unref(struct radeon_bo **bo);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 6ea798ce8218..06e79822a2bf 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -176,8 +176,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
176 INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib); 176 INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
177 /* Allocate 1M object buffer */ 177 /* Allocate 1M object buffer */
178 r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, 178 r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
179 true, RADEON_GEM_DOMAIN_GTT, 179 PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
180 &rdev->ib_pool.robj); 180 &rdev->ib_pool.robj);
181 if (r) { 181 if (r) {
182 DRM_ERROR("radeon: failed to ib pool (%d).\n", r); 182 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
183 return r; 183 return r;
@@ -332,7 +332,7 @@ int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
332 rdev->cp.ring_size = ring_size; 332 rdev->cp.ring_size = ring_size;
333 /* Allocate ring buffer */ 333 /* Allocate ring buffer */
334 if (rdev->cp.ring_obj == NULL) { 334 if (rdev->cp.ring_obj == NULL) {
335 r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true, 335 r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, PAGE_SIZE, true,
336 RADEON_GEM_DOMAIN_GTT, 336 RADEON_GEM_DOMAIN_GTT,
337 &rdev->cp.ring_obj); 337 &rdev->cp.ring_obj);
338 if (r) { 338 if (r) {
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 313c96bc09da..5b44f652145c 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -52,7 +52,7 @@ void radeon_test_moves(struct radeon_device *rdev)
52 goto out_cleanup; 52 goto out_cleanup;
53 } 53 }
54 54
55 r = radeon_bo_create(rdev, NULL, size, true, RADEON_GEM_DOMAIN_VRAM, 55 r = radeon_bo_create(rdev, NULL, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
56 &vram_obj); 56 &vram_obj);
57 if (r) { 57 if (r) {
58 DRM_ERROR("Failed to create VRAM object\n"); 58 DRM_ERROR("Failed to create VRAM object\n");
@@ -71,7 +71,7 @@ void radeon_test_moves(struct radeon_device *rdev)
71 void **gtt_start, **gtt_end; 71 void **gtt_start, **gtt_end;
72 void **vram_start, **vram_end; 72 void **vram_start, **vram_end;
73 73
74 r = radeon_bo_create(rdev, NULL, size, true, 74 r = radeon_bo_create(rdev, NULL, size, PAGE_SIZE, true,
75 RADEON_GEM_DOMAIN_GTT, gtt_obj + i); 75 RADEON_GEM_DOMAIN_GTT, gtt_obj + i);
76 if (r) { 76 if (r) {
77 DRM_ERROR("Failed to create GTT object %d\n", i); 77 DRM_ERROR("Failed to create GTT object %d\n", i);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 01c2c736a1da..1272e4b6a1d4 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -529,7 +529,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
529 DRM_ERROR("Failed initializing VRAM heap.\n"); 529 DRM_ERROR("Failed initializing VRAM heap.\n");
530 return r; 530 return r;
531 } 531 }
532 r = radeon_bo_create(rdev, NULL, 256 * 1024, true, 532 r = radeon_bo_create(rdev, NULL, 256 * 1024, PAGE_SIZE, true,
533 RADEON_GEM_DOMAIN_VRAM, 533 RADEON_GEM_DOMAIN_VRAM,
534 &rdev->stollen_vga_memory); 534 &rdev->stollen_vga_memory);
535 if (r) { 535 if (r) {
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 245374e2b778..4dfead8cee33 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -915,8 +915,8 @@ static int rv770_vram_scratch_init(struct radeon_device *rdev)
915 915
916 if (rdev->vram_scratch.robj == NULL) { 916 if (rdev->vram_scratch.robj == NULL) {
917 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, 917 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
918 true, RADEON_GEM_DOMAIN_VRAM, 918 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
919 &rdev->vram_scratch.robj); 919 &rdev->vram_scratch.robj);
920 if (r) { 920 if (r) {
921 return r; 921 return r;
922 } 922 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 14:20:05 -0500