31 files changed, 298 insertions, 194 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index ed644a4f6f57..86807ee91bd1 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1405,6 +1405,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
                (x << 16) | y);
         viewport_w = crtc->mode.hdisplay;
         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
+        if ((rdev->family >= CHIP_BONAIRE) &&
+            (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
+                viewport_h *= 2;
         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
                (viewport_w << 16) | viewport_h);
 
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 5bf825dfaa09..8d74de82456e 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -178,6 +178,13 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
         switch (msg->request & ~DP_AUX_I2C_MOT) {
         case DP_AUX_NATIVE_WRITE:
         case DP_AUX_I2C_WRITE:
+                /* The atom implementation only supports writes with a max payload of
+                 * 12 bytes since it uses 4 bits for the total count (header + payload)
+                 * in the parameter space.  The atom interface supports 16 byte
+                 * payloads for reads. The hw itself supports up to 16 bytes of payload.
+                 */
+                if (WARN_ON_ONCE(msg->size > 12))
+                        return -E2BIG;
                 /* tx_size needs to be 4 even for bare address packets since the atom
                  * table needs the info in tx_buf[3].
                  */
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 7c9df1eac065..c39c1d0d9d4e 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -731,7 +731,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                 dig_connector = radeon_connector->con_priv;
                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
-                        if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
+                        if (radeon_audio != 0 &&
+                            drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
+                            ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
                                 return ATOM_ENCODER_MODE_DP_AUDIO;
                         return ATOM_ENCODER_MODE_DP;
                 } else if (radeon_audio != 0) {
@@ -747,7 +749,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                 }
                 break;
         case DRM_MODE_CONNECTOR_eDP:
-                if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
+                if (radeon_audio != 0 &&
+                    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
+                    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
                         return ATOM_ENCODER_MODE_DP_AUDIO;
                 return ATOM_ENCODER_MODE_DP;
         case DRM_MODE_CONNECTOR_DVIA:
@@ -1622,7 +1626,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
         struct radeon_connector *radeon_connector = NULL;
         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
         bool travis_quirk = false;
-        int encoder_mode;
 
         if (connector) {
                 radeon_connector = to_radeon_connector(connector);
@@ -1718,11 +1721,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
                 }
                 break;
         }
-
-        encoder_mode = atombios_get_encoder_mode(encoder);
-        if (radeon_audio != 0 &&
-                (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
-                radeon_audio_dpms(encoder, mode);
 }
 
 static void
@@ -1731,10 +1729,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+        int encoder_mode = atombios_get_encoder_mode(encoder);
 
         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
                   radeon_encoder->active_device);
+
+        if (connector && (radeon_audio != 0) &&
+            ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
+             (ENCODER_MODE_IS_DP(encoder_mode) &&
+              drm_detect_monitor_audio(radeon_connector_edid(connector)))))
+                radeon_audio_dpms(encoder, mode);
+
         switch (radeon_encoder->encoder_id) {
         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -2136,6 +2143,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
         int encoder_mode;
 
         radeon_encoder->pixel_clock = adjusted_mode->clock;
@@ -2163,10 +2171,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
                 /* handled in dpms */
-                encoder_mode = atombios_get_encoder_mode(encoder);
-                if (radeon_audio != 0 &&
-                        (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
-                        radeon_audio_mode_set(encoder, adjusted_mode);
                 break;
         case ENCODER_OBJECT_ID_INTERNAL_DDI:
         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -2188,6 +2192,13 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         }
 
         atombios_apply_encoder_quirks(encoder, adjusted_mode);
+
+        encoder_mode = atombios_get_encoder_mode(encoder);
+        if (connector && (radeon_audio != 0) &&
+            ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
+             (ENCODER_MODE_IS_DP(encoder_mode) &&
+              drm_detect_monitor_audio(radeon_connector_edid(connector)))))
+                radeon_audio_mode_set(encoder, adjusted_mode);
 }
 
 static bool
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e6a4ba236c70..3e670d344a20 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
 
@@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
         WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
         /* grbm */
         WREG32(GRBM_INT_CNTL, 0);
+        /* SRBM */
+        WREG32(SRBM_INT_CNTL, 0);
         /* vline/vblank, etc. */
         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -7551,6 +7555,9 @@ int cik_irq_set(struct radeon_device *rdev)
         WREG32(DC_HPD5_INT_CONTROL, hpd5);
         WREG32(DC_HPD6_INT_CONTROL, hpd6);
 
+        /* posting read */
+        RREG32(SRBM_STATUS);
+
         return 0;
 }
 
@@ -8046,6 +8053,10 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 03003f8a6de6..243a36c93b8f 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -482,6 +482,10 @@
 #define         SOFT_RESET_ORB                          (1 << 23)
 #define         SOFT_RESET_VCE                          (1 << 24)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define VM_L2_CNTL                                      0x1400
 #define         ENABLE_L2_CACHE                                 (1 << 0)
 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
@@ -2125,6 +2129,7 @@
 #define VCE_UENC_REG_CLOCK_GATING       0x207c0
 #define VCE_SYS_INT_EN                  0x21300
 #       define VCE_SYS_INT_TRAP_INTERRUPT_EN    (1 << 3)
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR    0x2145c
 #define VCE_LMI_CTRL2                   0x21474
 #define VCE_LMI_CTRL                    0x21498
 #define VCE_LMI_VM_CTRL                 0x214a0
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 192c80389151..3adc2afe32aa 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -26,6 +26,9 @@
 #include "radeon_audio.h"
 #include "sid.h"
 
+#define DCE8_DCCG_AUDIO_DTO1_PHASE      0x05b8
+#define DCE8_DCCG_AUDIO_DTO1_MODULE     0x05bc
+
 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
                               u32 block_offset, u32 reg)
 {
@@ -252,72 +255,67 @@ void dce6_audio_enable(struct radeon_device *rdev,
 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
         struct radeon_crtc *crtc, unsigned int clock)
 {
-    /* Two dtos; generally use dto0 for HDMI */
+        /* Two dtos; generally use dto0 for HDMI */
         u32 value = 0;
 
-    if (crtc)
+        if (crtc)
                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
 
         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
 
-    /* Express [24MHz / target pixel clock] as an exact rational
-     * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
-     * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
-     */
-    WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
-    WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
+        /* Express [24MHz / target pixel clock] as an exact rational
+         * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
+         * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
+         */
+        WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
+        WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
 }
 
 void dce6_dp_audio_set_dto(struct radeon_device *rdev,
         struct radeon_crtc *crtc, unsigned int clock)
 {
-    /* Two dtos; generally use dto1 for DP */
+        /* Two dtos; generally use dto1 for DP */
         u32 value = 0;
         value |= DCCG_AUDIO_DTO_SEL;
 
-    if (crtc)
+        if (crtc)
                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
 
         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
 
-    /* Express [24MHz / target pixel clock] as an exact rational
-     * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
-     * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
-     */
-    WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
-    WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
+        /* Express [24MHz / target pixel clock] as an exact rational
+         * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
+         * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
+         */
+        if (ASIC_IS_DCE8(rdev)) {
+                WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
+                WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
+        } else {
+                WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
+                WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
+        }
 }
 
-void dce6_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable)
+void dce6_dp_enable(struct drm_encoder *encoder, bool enable)
 {
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-        uint32_t offset;
 
         if (!dig || !dig->afmt)
                 return;
 
-        offset = dig->afmt->offset;
-
         if (enable) {
-        if (dig->afmt->enabled)
-            return;
-
-                WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
-                WREG32(EVERGREEN_DP_SEC_CNTL + offset,
-                        EVERGREEN_DP_SEC_ASP_ENABLE |           /* Audio packet transmission */
-                        EVERGREEN_DP_SEC_ATP_ENABLE |           /* Audio timestamp packet transmission */
-                        EVERGREEN_DP_SEC_AIP_ENABLE |           /* Audio infoframe packet transmission */
-                        EVERGREEN_DP_SEC_STREAM_ENABLE);        /* Master enable for secondary stream engine */
-                radeon_audio_enable(rdev, dig->afmt->pin, true);
+                WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
+                       EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
+                WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
+                       EVERGREEN_DP_SEC_ASP_ENABLE |            /* Audio packet transmission */
+                       EVERGREEN_DP_SEC_ATP_ENABLE |            /* Audio timestamp packet transmission */
+                       EVERGREEN_DP_SEC_AIP_ENABLE |            /* Audio infoframe packet transmission */
+                       EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */
         } else {
-                if (!dig->afmt->enabled)
-                        return;
-
-                WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0);
-                radeon_audio_enable(rdev, dig->afmt->pin, false);
+                WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
         }
 
         dig->afmt->enabled = enable;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 78600f534c80..973df064c14f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
         WREG32(DMA_CNTL, tmp);
         WREG32(GRBM_INT_CNTL, 0);
+        WREG32(SRBM_INT_CNTL, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
         if (rdev->num_crtc >= 4) {
@@ -4590,6 +4593,9 @@ int evergreen_irq_set(struct radeon_device *rdev)
         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
 
+        /* posting read */
+        RREG32(SRBM_STATUS);
+
         return 0;
 }
 
@@ -5066,6 +5072,10 @@ restart_ih:
                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
                                 break;
                         }
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 1d9aebc79595..c18d4ecbd95d 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -272,7 +272,7 @@ void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
 }
 
 void dce4_dp_audio_set_dto(struct radeon_device *rdev,
-        struct radeon_crtc *crtc, unsigned int clock)
+                           struct radeon_crtc *crtc, unsigned int clock)
 {
         u32 value;
 
@@ -294,7 +294,7 @@ void dce4_dp_audio_set_dto(struct radeon_device *rdev,
          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
          */
         WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
-        WREG32(DCCG_AUDIO_DTO1_MODULE, rdev->clock.max_pixel_clock * 10);
+        WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
 }
 
 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
@@ -350,20 +350,9 @@ void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
 
-        WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
-                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
-                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
-
         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
                 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 
-        WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
-                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
-
-        WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
-                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
-                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
-
         WREG32(AFMT_60958_0 + offset,
                 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 
@@ -408,15 +397,19 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
         if (!dig || !dig->afmt)
                 return;
 
-        /* Silent, r600_hdmi_enable will raise WARN for us */
-        if (enable && dig->afmt->enabled)
-                return;
-        if (!enable && !dig->afmt->enabled)
-                return;
+        if (enable) {
+                WREG32(HDMI_INFOFRAME_CONTROL1 + dig->afmt->offset,
+                       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
+
+                WREG32(HDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset,
+                       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
+                       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 
-        if (!enable && dig->afmt->pin) {
-                radeon_audio_enable(rdev, dig->afmt->pin, 0);
-                dig->afmt->pin = NULL;
+                WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
+                       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
+                       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
+        } else {
+                WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
         }
 
         dig->afmt->enabled = enable;
@@ -425,33 +418,28 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 }
 
-void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable)
+void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
 {
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-        uint32_t offset;
 
         if (!dig || !dig->afmt)
                 return;
 
-        offset = dig->afmt->offset;
-
         if (enable) {
                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
                 struct radeon_connector_atom_dig *dig_connector;
                 uint32_t val;
 
-                if (dig->afmt->enabled)
-                        return;
-
-                WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
+                WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
+                       EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
 
                 if (radeon_connector->con_priv) {
                         dig_connector = radeon_connector->con_priv;
-                        val = RREG32(EVERGREEN_DP_SEC_AUD_N + offset);
+                        val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
                         val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
 
                         if (dig_connector->dp_clock == 162000)
@@ -459,21 +447,16 @@ void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable)
                         else
                                 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
 
-                        WREG32(EVERGREEN_DP_SEC_AUD_N + offset, val);
+                        WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
                 }
 
-                WREG32(EVERGREEN_DP_SEC_CNTL + offset,
+                WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
                         EVERGREEN_DP_SEC_ASP_ENABLE |           /* Audio packet transmission */
                         EVERGREEN_DP_SEC_ATP_ENABLE |           /* Audio timestamp packet transmission */
                         EVERGREEN_DP_SEC_AIP_ENABLE |           /* Audio infoframe packet transmission */
                         EVERGREEN_DP_SEC_STREAM_ENABLE);        /* Master enable for secondary stream engine */
-                radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
         } else {
-                if (!dig->afmt->enabled)
-                        return;
-
-                WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0);
-                radeon_audio_enable(rdev, dig->afmt->pin, 0);
+                WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
         }
 
         dig->afmt->enabled = enable;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index ee83d2a88750..a8d1d5240fcb 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1191,6 +1191,10 @@
 #define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 /* display watermarks */
 #define DC_LB_MEMORY_SPLIT                                0x6b0c
 #define PRIORITY_A_CNT                                    0x6b18
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 24242a7f0ac3..dab00812abaa 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -962,6 +962,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -1086,12 +1088,12 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
         if ((rdev->config.cayman.max_backends_per_se == 1) &&
             (rdev->flags & RADEON_IS_IGP)) {
-                if ((disabled_rb_mask & 3) == 1) {
-                        /* RB0 disabled, RB1 enabled */
-                        tmp = 0x11111111;
-                } else {
+                if ((disabled_rb_mask & 3) == 2) {
                         /* RB1 disabled, RB0 enabled */
                         tmp = 0x00000000;
+                } else {
+                        /* RB0 disabled, RB1 enabled */
+                        tmp = 0x11111111;
                 }
         } else {
                 tmp = gb_addr_config & NUM_PIPES_MASK;
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index ad7125486894..6b44580440d0 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -82,6 +82,10 @@
 #define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define SRBM_STATUS2                                    0x0EC4
 #define         DMA_BUSY                                (1 << 5)
 #define         DMA1_BUSY                               (1 << 6)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 279801ca5110..04f2514f7564 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -728,6 +728,10 @@ int r100_irq_set(struct radeon_device *rdev)
                 tmp |= RADEON_FP2_DETECT_MASK;
         }
         WREG32(RADEON_GEN_INT_CNTL, tmp);
+
+        /* read back to post the write */
+        RREG32(RADEON_GEN_INT_CNTL);
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 07a71a2488c9..2fcad344492f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3784,6 +3784,9 @@ int r600_irq_set(struct radeon_device *rdev)
                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
         }
 
+        /* posting read */
+        RREG32(R_000E50_SRBM_STATUS);
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 843b65f46ece..fa2154493cf1 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -188,7 +188,7 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                         radeon_crtc = to_radeon_crtc(crtc);
                         if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
-                                vrefresh = radeon_crtc->hw_mode.vrefresh;
+                                vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);
                                 break;
                         }
                 }
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 62c91ed669ce..dd6606b8e23c 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -476,17 +476,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
         if (!dig || !dig->afmt)
                 return;
 
-        /* Silent, r600_hdmi_enable will raise WARN for us */
-        if (enable && dig->afmt->enabled)
-                return;
-        if (!enable && !dig->afmt->enabled)
-                return;
-
-        if (!enable && dig->afmt->pin) {
-                radeon_audio_enable(rdev, dig->afmt->pin, 0);
-                dig->afmt->pin = NULL;
-        }
-
         /* Older chipsets require setting HDMI and routing manually */
         if (!ASIC_IS_DCE3(rdev)) {
                 if (enable)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5587603b4a89..33d5a4f4eebd 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1565,6 +1565,7 @@ struct radeon_dpm {
         int                     new_active_crtc_count;
         u32                     current_active_crtcs;
         int                     current_active_crtc_count;
+        bool single_display;
         struct radeon_dpm_dynamic_state dyn_state;
         struct radeon_dpm_fan fan;
         u32 tdp_limit;
diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c
index a3ceef6d9632..b21ef69a34ac 100644
--- a/drivers/gpu/drm/radeon/radeon_audio.c
+++ b/drivers/gpu/drm/radeon/radeon_audio.c
@@ -101,8 +101,8 @@ static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
         struct drm_display_mode *mode);
 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
-void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable);
-void dce6_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable);
+void evergreen_dp_enable(struct drm_encoder *encoder, bool enable);
+void dce6_dp_enable(struct drm_encoder *encoder, bool enable);
 
 static const u32 pin_offsets[7] =
 {
@@ -210,7 +210,7 @@ static struct radeon_audio_funcs dce4_dp_funcs = {
         .set_avi_packet = evergreen_set_avi_packet,
         .set_audio_packet = dce4_set_audio_packet,
         .mode_set = radeon_audio_dp_mode_set,
-        .dpms = evergreen_enable_dp_audio_packets,
+        .dpms = evergreen_dp_enable,
 };
 
 static struct radeon_audio_funcs dce6_hdmi_funcs = {
@@ -240,7 +240,7 @@ static struct radeon_audio_funcs dce6_dp_funcs = {
         .set_avi_packet = evergreen_set_avi_packet,
         .set_audio_packet = dce4_set_audio_packet,
         .mode_set = radeon_audio_dp_mode_set,
-        .dpms = dce6_enable_dp_audio_packets,
+        .dpms = dce6_dp_enable,
 };
 
 static void radeon_audio_interface_init(struct radeon_device *rdev)
@@ -452,7 +452,7 @@ void radeon_audio_enable(struct radeon_device *rdev,
 }
 
 void radeon_audio_detect(struct drm_connector *connector,
-        enum drm_connector_status status)
+                         enum drm_connector_status status)
 {
         struct radeon_device *rdev;
         struct radeon_encoder *radeon_encoder;
@@ -483,14 +483,11 @@ void radeon_audio_detect(struct drm_connector *connector,
                 else
                         radeon_encoder->audio = rdev->audio.hdmi_funcs;
 
-                radeon_audio_write_speaker_allocation(connector->encoder);
-                radeon_audio_write_sad_regs(connector->encoder);
-                if (connector->encoder->crtc)
-                        radeon_audio_write_latency_fields(connector->encoder,
-                                &connector->encoder->crtc->mode);
+                dig->afmt->pin = radeon_audio_get_pin(connector->encoder);
                 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
         } else {
                 radeon_audio_enable(rdev, dig->afmt->pin, 0);
+                dig->afmt->pin = NULL;
         }
 }
 
@@ -694,23 +691,22 @@ static void radeon_audio_set_mute(struct drm_encoder *encoder, bool mute)
  * update the info frames with the data from the current display mode
  */
 static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder,
-        struct drm_display_mode *mode)
+                                       struct drm_display_mode *mode)
 {
-        struct radeon_device *rdev = encoder->dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 
         if (!dig || !dig->afmt)
                 return;
 
-        /* disable audio prior to setting up hw */
-        dig->afmt->pin = radeon_audio_get_pin(encoder);
-        radeon_audio_enable(rdev, dig->afmt->pin, 0);
+        radeon_audio_set_mute(encoder, true);
 
+        radeon_audio_write_speaker_allocation(encoder);
+        radeon_audio_write_sad_regs(encoder);
+        radeon_audio_write_latency_fields(encoder, mode);
         radeon_audio_set_dto(encoder, mode->clock);
         radeon_audio_set_vbi_packet(encoder);
         radeon_hdmi_set_color_depth(encoder);
-        radeon_audio_set_mute(encoder, false);
         radeon_audio_update_acr(encoder, mode->clock);
         radeon_audio_set_audio_packet(encoder);
         radeon_audio_select_pin(encoder);
@@ -718,8 +714,7 @@ static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder,
         if (radeon_audio_set_avi_packet(encoder, mode) < 0)
                 return;
 
-        /* enable audio after to setting up hw */
-        radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
+        radeon_audio_set_mute(encoder, false);
 }
 
 static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
@@ -729,23 +724,26 @@ static void radeon_audio_dp_mode_set(struct drm_encoder *encoder,
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        struct radeon_connector_atom_dig *dig_connector =
+                radeon_connector->con_priv;
 
         if (!dig || !dig->afmt)
                 return;
 
-        /* disable audio prior to setting up hw */
-        dig->afmt->pin = radeon_audio_get_pin(encoder);
-        radeon_audio_enable(rdev, dig->afmt->pin, 0);
-
-        radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10);
+        radeon_audio_write_speaker_allocation(encoder);
+        radeon_audio_write_sad_regs(encoder);
+        radeon_audio_write_latency_fields(encoder, mode);
+        if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev))
+                radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10);
+        else
+                radeon_audio_set_dto(encoder, dig_connector->dp_clock);
         radeon_audio_set_audio_packet(encoder);
         radeon_audio_select_pin(encoder);
 
         if (radeon_audio_set_avi_packet(encoder, mode) < 0)
                 return;
-
-        /* enable audio after to setting up hw */
-        radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
 }
 
 void radeon_audio_mode_set(struct drm_encoder *encoder,
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 63ccb8fa799c..d27e4ccb848c 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -76,7 +76,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
 
 static bool radeon_read_bios(struct radeon_device *rdev)
 {
-        uint8_t __iomem *bios;
+        uint8_t __iomem *bios, val1, val2;
         size_t size;
 
         rdev->bios = NULL;
@@ -86,15 +86,19 @@ static bool radeon_read_bios(struct radeon_device *rdev)
                 return false;
         }
 
-        if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
+        val1 = readb(&bios[0]);
+        val2 = readb(&bios[1]);
+
+        if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
                 pci_unmap_rom(rdev->pdev, bios);
                 return false;
         }
-        rdev->bios = kmemdup(bios, size, GFP_KERNEL);
+        rdev->bios = kzalloc(size, GFP_KERNEL);
         if (rdev->bios == NULL) {
                 pci_unmap_rom(rdev->pdev, bios);
                 return false;
         }
+        memcpy_fromio(rdev->bios, bios, size);
         pci_unmap_rom(rdev->pdev, bios);
         return true;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index c830863bc98a..4d0f96cc3da4 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -256,11 +256,13 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
         u32 ring = RADEON_CS_RING_GFX;
         s32 priority = 0;
 
+        INIT_LIST_HEAD(&p->validated);
+
         if (!cs->num_chunks) {
                 return 0;
         }
+
         /* get chunks */
-        INIT_LIST_HEAD(&p->validated);
         p->idx = 0;
         p->ib.sa_bo = NULL;
         p->const_ib.sa_bo = NULL;
@@ -715,6 +717,7 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
         struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
         struct radeon_device *rdev = p->rdev;
         uint32_t header;
+        int ret = 0, i;
 
         if (idx >= ib_chunk->length_dw) {
                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
@@ -743,14 +746,25 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
                 break;
         default:
                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
-                return -EINVAL;
+                ret = -EINVAL;
+                goto dump_ib;
         }
         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
-                return -EINVAL;
+                ret = -EINVAL;
+                goto dump_ib;
         }
         return 0;
+
+dump_ib:
+        for (i = 0; i < ib_chunk->length_dw; i++) {
+                if (i == idx)
+                        printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
+                else
+                        printk("\t0x%08x\n", radeon_get_ib_value(p, i));
+        }
+        return ret;
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 6b670b0bc47b..3a297037cc17 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -179,9 +179,12 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
                     (rdev->pdev->subsystem_vendor == 0x1734) &&
                     (rdev->pdev->subsystem_device == 0x1107))
                         use_bl = false;
+/* Older PPC macs use on-GPU backlight controller */
+#ifndef CONFIG_PPC_PMAC
                 /* disable native backlight control on older asics */
                 else if (rdev->family < CHIP_R600)
                         use_bl = false;
+#endif
                 else
                         use_bl = true;
         }
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index d13d1b5a859f..df09ca7c4889 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -1030,37 +1030,59 @@ static inline bool radeon_test_signaled(struct radeon_fence *fence)
         return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
 }
 
+struct radeon_wait_cb {
+        struct fence_cb base;
+        struct task_struct *task;
+};
+
+static void
+radeon_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
+{
+        struct radeon_wait_cb *wait =
+                container_of(cb, struct radeon_wait_cb, base);
+
+        wake_up_process(wait->task);
+}
+
 static signed long radeon_fence_default_wait(struct fence *f, bool intr,
                                              signed long t)
 {
         struct radeon_fence *fence = to_radeon_fence(f);
         struct radeon_device *rdev = fence->rdev;
-        bool signaled;
+        struct radeon_wait_cb cb;
 
-        fence_enable_sw_signaling(&fence->base);
+        cb.task = current;
 
-        /*
-         * This function has to return -EDEADLK, but cannot hold
-         * exclusive_lock during the wait because some callers
-         * may already hold it. This means checking needs_reset without
-         * lock, and not fiddling with any gpu internals.
-         *
-         * The callback installed with fence_enable_sw_signaling will
-         * run before our wait_event_*timeout call, so we will see
-         * both the signaled fence and the changes to needs_reset.
-         */
+        if (fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
+                return t;
+
+        while (t > 0) {
+                if (intr)
+                        set_current_state(TASK_INTERRUPTIBLE);
+                else
+                        set_current_state(TASK_UNINTERRUPTIBLE);
+
+                /*
+                 * radeon_test_signaled must be called after
+                 * set_current_state to prevent a race with wake_up_process
+                 */
+                if (radeon_test_signaled(fence))
+                        break;
+
+                if (rdev->needs_reset) {
+                        t = -EDEADLK;
+                        break;
+                }
+
+                t = schedule_timeout(t);
+
+                if (t > 0 && intr && signal_pending(current))
+                        t = -ERESTARTSYS;
+        }
+
+        __set_current_state(TASK_RUNNING);
+        fence_remove_callback(f, &cb.base);
 
-        if (intr)
-                t = wait_event_interruptible_timeout(rdev->fence_queue,
-                        ((signaled = radeon_test_signaled(fence)) ||
-                         rdev->needs_reset), t);
-        else
-                t = wait_event_timeout(rdev->fence_queue,
-                        ((signaled = radeon_test_signaled(fence)) ||
-                         rdev->needs_reset), t);
-
-        if (t > 0 && !signaled)
-                return -EDEADLK;
         return t;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c
index 061eaa9c19c7..122eb5693ba1 100644
--- a/drivers/gpu/drm/radeon/radeon_kfd.c
+++ b/drivers/gpu/drm/radeon/radeon_kfd.c
@@ -153,7 +153,7 @@ void radeon_kfd_device_init(struct radeon_device *rdev)
                         .compute_vmid_bitmap = 0xFF00,
 
                         .first_compute_pipe = 1,
-                        .compute_pipe_count = 8 - 1,
+                        .compute_pipe_count = 4 - 1,
                 };
 
                 radeon_doorbell_get_kfd_info(rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_mn.c b/drivers/gpu/drm/radeon/radeon_mn.c
index a69bd441dd2d..572b4dbec186 100644
--- a/drivers/gpu/drm/radeon/radeon_mn.c
+++ b/drivers/gpu/drm/radeon/radeon_mn.c
@@ -122,7 +122,6 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn,
         it = interval_tree_iter_first(&rmn->objects, start, end);
         while (it) {
                 struct radeon_bo *bo;
-                struct fence *fence;
                 int r;
 
                 bo = container_of(it, struct radeon_bo, mn_it);
@@ -134,12 +133,10 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn,
                         continue;
                 }
 
-                fence = reservation_object_get_excl(bo->tbo.resv);
-                if (fence) {
-                        r = radeon_fence_wait((struct radeon_fence *)fence, false);
-                        if (r)
-                                DRM_ERROR("(%d) failed to wait for user bo\n", r);
-                }
+                r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true,
+                        false, MAX_SCHEDULE_TIMEOUT);
+                if (r)
+                        DRM_ERROR("(%d) failed to wait for user bo\n", r);
 
                 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU);
                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 43e09942823e..318165d4855c 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -173,17 +173,6 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
                 else
                         rbo->placements[i].lpfn = 0;
         }
-
-        /*
-         * Use two-ended allocation depending on the buffer size to
-         * improve fragmentation quality.
-         * 512kb was measured as the most optimal number.
-         */
-        if (rbo->tbo.mem.size > 512 * 1024) {
-                for (i = 0; i < c; i++) {
-                        rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
-                }
-        }
 }
 
 int radeon_bo_create(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 9f758d39420d..c1ba83a8dd8c 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -837,12 +837,8 @@ static void radeon_dpm_thermal_work_handler(struct work_struct *work)
         radeon_pm_compute_clocks(rdev);
 }
 
-static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
-                                                     enum radeon_pm_state_type dpm_state)
+static bool radeon_dpm_single_display(struct radeon_device *rdev)
 {
-        int i;
-        struct radeon_ps *ps;
-        u32 ui_class;
         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
                 true : false;
 
@@ -852,6 +848,23 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
                         single_display = false;
         }
 
+        /* 120hz tends to be problematic even if they are under the
+         * vblank limit.
+         */
+        if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
+                single_display = false;
+
+        return single_display;
+}
+
+static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
+                                                     enum radeon_pm_state_type dpm_state)
+{
+        int i;
+        struct radeon_ps *ps;
+        u32 ui_class;
+        bool single_display = radeon_dpm_single_display(rdev);
+
         /* certain older asics have a separare 3D performance state,
          * so try that first if the user selected performance
          */
@@ -977,6 +990,7 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
         struct radeon_ps *ps;
         enum radeon_pm_state_type dpm_state;
         int ret;
+        bool single_display = radeon_dpm_single_display(rdev);
 
         /* if dpm init failed */
         if (!rdev->pm.dpm_enabled)
@@ -1001,6 +1015,9 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
                 /* vce just modifies an existing state so force a change */
                 if (ps->vce_active != rdev->pm.dpm.vce_active)
                         goto force;
+                /* user has made a display change (such as timing) */
+                if (rdev->pm.dpm.single_display != single_display)
+                        goto force;
                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
                          * all we need to do is update the display configuration.
@@ -1063,6 +1080,7 @@ force:
 
         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
+        rdev->pm.dpm.single_display = single_display;
 
         /* wait for the rings to drain */
         for (i = 0; i < RADEON_NUM_RINGS; i++) {
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 2456f69efd23..8c7872339c2a 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -495,7 +495,7 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
         seq_printf(m, "%u dwords in ring\n", count);
 
-        if (!ring->ready)
+        if (!ring->ring)
                 return 0;
 
         /* print 8 dw before current rptr as often it's the last executed
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index d02aa1d0f588..b292aca0f342 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -598,6 +598,10 @@ static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
         enum dma_data_direction direction = write ?
                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 
+        /* double check that we don't free the table twice */
+        if (!ttm->sg->sgl)
+                return;
+
         /* free the sg table and pages again */
         dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index d81182ad53ec..97a904835759 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -694,6 +694,10 @@ int rs600_irq_set(struct radeon_device *rdev)
         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
         if (ASIC_IS_DCE2(rdev))
                 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
+
+        /* posting read */
+        RREG32(R_000040_GEN_INT_CNTL);
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 73107fe9e46f..a7fb2735d4a9 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 1);
+        WREG32(SRBM_INT_ACK, 1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -4699,12 +4701,6 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
                 switch (pkt.type) {
                 case RADEON_PACKET_TYPE0:
                         dev_err(rdev->dev, "Packet0 not allowed!\n");
-                        for (i = 0; i < ib->length_dw; i++) {
-                                if (i == idx)
-                                        printk("\t0x%08x <---\n", ib->ptr[i]);
-                                else
-                                        printk("\t0x%08x\n", ib->ptr[i]);
-                        }
                         ret = -EINVAL;
                         break;
                 case RADEON_PACKET_TYPE2:
@@ -4736,8 +4732,15 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
                         ret = -EINVAL;
                         break;
                 }
-                if (ret)
+                if (ret) {
+                        for (i = 0; i < ib->length_dw; i++) {
+                                if (i == idx)
+                                        printk("\t0x%08x <---\n", ib->ptr[i]);
+                                else
+                                        printk("\t0x%08x\n", ib->ptr[i]);
+                        }
                         break;
+                }
         } while (idx < ib->length_dw);
 
         return ret;
@@ -5910,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
         tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
         WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
         WREG32(GRBM_INT_CNTL, 0);
+        WREG32(SRBM_INT_CNTL, 0);
         if (rdev->num_crtc >= 2) {
                 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
                 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -6199,6 +6203,9 @@ int si_irq_set(struct radeon_device *rdev)
 
         WREG32(CG_THERMAL_INT, thermal_int);
 
+        /* posting read */
+        RREG32(SRBM_STATUS);
+
         return 0;
 }
 
@@ -6609,6 +6616,10 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
@@ -7119,8 +7130,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
 
         if (!vclk || !dclk) {
-                /* keep the Bypass mode, put PLL to sleep */
-                WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
+                /* keep the Bypass mode */
                 return 0;
         }
 
@@ -7136,8 +7146,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         /* set VCO_MODE to 1 */
         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
 
-        /* toggle UPLL_SLEEP to 1 then back to 0 */
-        WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
+        /* disable sleep mode */
         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
 
         /* deassert UPLL_RESET */
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index cbd91d226f3c..99a9835c9f61 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -358,6 +358,10 @@
 #define CC_SYS_RB_BACKEND_DISABLE                       0xe80
 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define SRBM_STATUS2                                    0x0EC4
 #define         DMA_BUSY                                (1 << 5)
 #define         DMA1_BUSY                               (1 << 6)
@@ -908,8 +912,8 @@
 
 #define DCCG_AUDIO_DTO0_PHASE                           0x05b0
 #define DCCG_AUDIO_DTO0_MODULE                          0x05b4
-#define DCCG_AUDIO_DTO1_PHASE                           0x05b8
-#define DCCG_AUDIO_DTO1_MODULE                          0x05bc
+#define DCCG_AUDIO_DTO1_PHASE                           0x05c0
+#define DCCG_AUDIO_DTO1_MODULE                          0x05c4
 
 #define AFMT_AUDIO_SRC_CONTROL                          0x713c
 #define         AFMT_AUDIO_SRC_SELECT(x)                (((x) & 7) << 0)
diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c
index 1ac7bb825a1b..fbbe78fbd087 100644
--- a/drivers/gpu/drm/radeon/vce_v2_0.c
+++ b/drivers/gpu/drm/radeon/vce_v2_0.c
@@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev)
         WREG32(VCE_LMI_SWAP_CNTL1, 0);
         WREG32(VCE_LMI_VM_CTRL, 0);
 
+        WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
+
+        addr &= 0xff;
         size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
         WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
         WREG32(VCE_VCPU_CACHE_SIZE0, size);