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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c49
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c75
-rw-r--r--drivers/gpu/drm/radeon/r100.c24
-rw-r--r--drivers/gpu/drm/radeon/r600.c16
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c25
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.h24
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c58
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c47
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c93
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c28
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h4
-rw-r--r--drivers/gpu/drm/radeon/rv770.c61
18 files changed, 369 insertions, 204 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 577239a24fd5..cd0290f946cf 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -332,6 +332,11 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
332 args.usV_SyncWidth = 332 args.usV_SyncWidth =
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
334 334
335 args.ucOverscanRight = radeon_crtc->h_border;
336 args.ucOverscanLeft = radeon_crtc->h_border;
337 args.ucOverscanBottom = radeon_crtc->v_border;
338 args.ucOverscanTop = radeon_crtc->v_border;
339
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 340 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY; 341 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 342 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
@@ -534,6 +539,21 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
534 pll->algo = PLL_ALGO_LEGACY; 539 pll->algo = PLL_ALGO_LEGACY;
535 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 540 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
536 } 541 }
542 /* There is some evidence (often anecdotal) that RV515/RV620 LVDS
543 * (on some boards at least) prefers the legacy algo. I'm not
544 * sure whether this should handled generically or on a
545 * case-by-case quirk basis. Both algos should work fine in the
546 * majority of cases.
547 */
548 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) &&
549 ((rdev->family == CHIP_RV515) ||
550 (rdev->family == CHIP_RV620))) {
551 /* allow the user to overrride just in case */
552 if (radeon_new_pll == 1)
553 pll->algo = PLL_ALGO_NEW;
554 else
555 pll->algo = PLL_ALGO_LEGACY;
556 }
537 } else { 557 } else {
538 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 558 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
539 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 559 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -1056,11 +1076,11 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1056 1076
1057 if (rdev->family >= CHIP_RV770) { 1077 if (rdev->family >= CHIP_RV770) {
1058 if (radeon_crtc->crtc_id) { 1078 if (radeon_crtc->crtc_id) {
1059 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 1079 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1060 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 1080 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1061 } else { 1081 } else {
1062 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 1082 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1063 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 1083 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1064 } 1084 }
1065 } 1085 }
1066 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1086 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
@@ -1197,8 +1217,18 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1197 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1198 struct drm_device *dev = crtc->dev; 1218 struct drm_device *dev = crtc->dev;
1199 struct radeon_device *rdev = dev->dev_private; 1219 struct radeon_device *rdev = dev->dev_private;
1220 struct drm_encoder *encoder;
1221 bool is_tvcv = false;
1200 1222
1201 /* TODO color tiling */ 1223 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1224 /* find tv std */
1225 if (encoder->crtc == crtc) {
1226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1227 if (radeon_encoder->active_device &
1228 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1229 is_tvcv = true;
1230 }
1231 }
1202 1232
1203 atombios_disable_ss(crtc); 1233 atombios_disable_ss(crtc);
1204 /* always set DCPLL */ 1234 /* always set DCPLL */
@@ -1207,9 +1237,14 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1207 atombios_crtc_set_pll(crtc, adjusted_mode); 1237 atombios_crtc_set_pll(crtc, adjusted_mode);
1208 atombios_enable_ss(crtc); 1238 atombios_enable_ss(crtc);
1209 1239
1210 if (ASIC_IS_AVIVO(rdev)) 1240 if (ASIC_IS_DCE4(rdev))
1211 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1241 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1212 else { 1242 else if (ASIC_IS_AVIVO(rdev)) {
1243 if (is_tvcv)
1244 atombios_crtc_set_timing(crtc, adjusted_mode);
1245 else
1246 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1247 } else {
1213 atombios_crtc_set_timing(crtc, adjusted_mode); 1248 atombios_crtc_set_timing(crtc, adjusted_mode);
1214 if (radeon_crtc->crtc_id == 0) 1249 if (radeon_crtc->crtc_id == 0)
1215 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1250 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 957d5067ad9c..79082d4398ae 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -675,6 +675,43 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
675 return 0; 675 return 0;
676} 676}
677 677
678static int evergreen_cp_start(struct radeon_device *rdev)
679{
680 int r;
681 uint32_t cp_me;
682
683 r = radeon_ring_lock(rdev, 7);
684 if (r) {
685 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
686 return r;
687 }
688 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
689 radeon_ring_write(rdev, 0x1);
690 radeon_ring_write(rdev, 0x0);
691 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
692 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
693 radeon_ring_write(rdev, 0);
694 radeon_ring_write(rdev, 0);
695 radeon_ring_unlock_commit(rdev);
696
697 cp_me = 0xff;
698 WREG32(CP_ME_CNTL, cp_me);
699
700 r = radeon_ring_lock(rdev, 4);
701 if (r) {
702 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
703 return r;
704 }
705 /* init some VGT regs */
706 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
707 radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2);
708 radeon_ring_write(rdev, 0xe);
709 radeon_ring_write(rdev, 0x10);
710 radeon_ring_unlock_commit(rdev);
711
712 return 0;
713}
714
678int evergreen_cp_resume(struct radeon_device *rdev) 715int evergreen_cp_resume(struct radeon_device *rdev)
679{ 716{
680 u32 tmp; 717 u32 tmp;
@@ -719,7 +756,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
719 rdev->cp.rptr = RREG32(CP_RB_RPTR); 756 rdev->cp.rptr = RREG32(CP_RB_RPTR);
720 rdev->cp.wptr = RREG32(CP_RB_WPTR); 757 rdev->cp.wptr = RREG32(CP_RB_WPTR);
721 758
722 r600_cp_start(rdev); 759 evergreen_cp_start(rdev);
723 rdev->cp.ready = true; 760 rdev->cp.ready = true;
724 r = radeon_ring_test(rdev); 761 r = radeon_ring_test(rdev);
725 if (r) { 762 if (r) {
@@ -1123,14 +1160,25 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1123 EVERGREEN_MAX_BACKENDS_MASK)); 1160 EVERGREEN_MAX_BACKENDS_MASK));
1124 break; 1161 break;
1125 } 1162 }
1126 } else 1163 } else {
1127 gb_backend_map = 1164 switch (rdev->family) {
1128 evergreen_get_tile_pipe_to_backend_map(rdev, 1165 case CHIP_CYPRESS:
1129 rdev->config.evergreen.max_tile_pipes, 1166 case CHIP_HEMLOCK:
1130 rdev->config.evergreen.max_backends, 1167 gb_backend_map = 0x66442200;
1131 ((EVERGREEN_MAX_BACKENDS_MASK << 1168 break;
1132 rdev->config.evergreen.max_backends) & 1169 case CHIP_JUNIPER:
1133 EVERGREEN_MAX_BACKENDS_MASK)); 1170 gb_backend_map = 0x00006420;
1171 break;
1172 default:
1173 gb_backend_map =
1174 evergreen_get_tile_pipe_to_backend_map(rdev,
1175 rdev->config.evergreen.max_tile_pipes,
1176 rdev->config.evergreen.max_backends,
1177 ((EVERGREEN_MAX_BACKENDS_MASK <<
1178 rdev->config.evergreen.max_backends) &
1179 EVERGREEN_MAX_BACKENDS_MASK));
1180 }
1181 }
1134 1182
1135 rdev->config.evergreen.tile_config = gb_addr_config; 1183 rdev->config.evergreen.tile_config = gb_addr_config;
1136 WREG32(GB_BACKEND_MAP, gb_backend_map); 1184 WREG32(GB_BACKEND_MAP, gb_backend_map);
@@ -2054,11 +2102,6 @@ int evergreen_resume(struct radeon_device *rdev)
2054 */ 2102 */
2055 /* post card */ 2103 /* post card */
2056 atom_asic_init(rdev->mode_info.atom_context); 2104 atom_asic_init(rdev->mode_info.atom_context);
2057 /* Initialize clocks */
2058 r = radeon_clocks_init(rdev);
2059 if (r) {
2060 return r;
2061 }
2062 2105
2063 r = evergreen_startup(rdev); 2106 r = evergreen_startup(rdev);
2064 if (r) { 2107 if (r) {
@@ -2164,9 +2207,6 @@ int evergreen_init(struct radeon_device *rdev)
2164 radeon_surface_init(rdev); 2207 radeon_surface_init(rdev);
2165 /* Initialize clocks */ 2208 /* Initialize clocks */
2166 radeon_get_clock_info(rdev->ddev); 2209 radeon_get_clock_info(rdev->ddev);
2167 r = radeon_clocks_init(rdev);
2168 if (r)
2169 return r;
2170 /* Fence driver */ 2210 /* Fence driver */
2171 r = radeon_fence_driver_init(rdev); 2211 r = radeon_fence_driver_init(rdev);
2172 if (r) 2212 if (r)
@@ -2236,7 +2276,6 @@ void evergreen_fini(struct radeon_device *rdev)
2236 evergreen_pcie_gart_fini(rdev); 2276 evergreen_pcie_gart_fini(rdev);
2237 radeon_gem_fini(rdev); 2277 radeon_gem_fini(rdev);
2238 radeon_fence_driver_fini(rdev); 2278 radeon_fence_driver_fini(rdev);
2239 radeon_clocks_fini(rdev);
2240 radeon_agp_fini(rdev); 2279 radeon_agp_fini(rdev);
2241 radeon_bo_fini(rdev); 2280 radeon_bo_fini(rdev);
2242 radeon_atombios_fini(rdev); 2281 radeon_atombios_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e817a0bb5eb4..e151f16a8f86 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2020,18 +2020,7 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *l
2020 return false; 2020 return false;
2021 } 2021 }
2022 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 2022 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2023 if (elapsed >= 3000) { 2023 if (elapsed >= 10000) {
2024 /* very likely the improbable case where current
2025 * rptr is equal to last recorded, a while ago, rptr
2026 * this is more likely a false positive update tracking
2027 * information which should force us to be recall at
2028 * latter point
2029 */
2030 lockup->last_cp_rptr = cp->rptr;
2031 lockup->last_jiffies = jiffies;
2032 return false;
2033 }
2034 if (elapsed >= 1000) {
2035 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 2024 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2036 return true; 2025 return true;
2037 } 2026 }
@@ -3308,13 +3297,14 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3308 unsigned long size; 3297 unsigned long size;
3309 unsigned prim_walk; 3298 unsigned prim_walk;
3310 unsigned nverts; 3299 unsigned nverts;
3300 unsigned num_cb = track->num_cb;
3311 3301
3312 for (i = 0; i < track->num_cb; i++) { 3302 if (!track->zb_cb_clear && !track->color_channel_mask &&
3303 !track->blend_read_enable)
3304 num_cb = 0;
3305
3306 for (i = 0; i < num_cb; i++) {
3313 if (track->cb[i].robj == NULL) { 3307 if (track->cb[i].robj == NULL) {
3314 if (!(track->zb_cb_clear || track->color_channel_mask ||
3315 track->blend_read_enable)) {
3316 continue;
3317 }
3318 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3308 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3319 return -EINVAL; 3309 return -EINVAL;
3320 } 3310 }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index d0ebae9dde25..afc18d87fdca 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2119,10 +2119,7 @@ int r600_cp_start(struct radeon_device *rdev)
2119 } 2119 }
2120 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2120 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2121 radeon_ring_write(rdev, 0x1); 2121 radeon_ring_write(rdev, 0x1);
2122 if (rdev->family >= CHIP_CEDAR) { 2122 if (rdev->family >= CHIP_RV770) {
2123 radeon_ring_write(rdev, 0x0);
2124 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2125 } else if (rdev->family >= CHIP_RV770) {
2126 radeon_ring_write(rdev, 0x0); 2123 radeon_ring_write(rdev, 0x0);
2127 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); 2124 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2128 } else { 2125 } else {
@@ -2489,11 +2486,6 @@ int r600_resume(struct radeon_device *rdev)
2489 */ 2486 */
2490 /* post card */ 2487 /* post card */
2491 atom_asic_init(rdev->mode_info.atom_context); 2488 atom_asic_init(rdev->mode_info.atom_context);
2492 /* Initialize clocks */
2493 r = radeon_clocks_init(rdev);
2494 if (r) {
2495 return r;
2496 }
2497 2489
2498 r = r600_startup(rdev); 2490 r = r600_startup(rdev);
2499 if (r) { 2491 if (r) {
@@ -2586,9 +2578,6 @@ int r600_init(struct radeon_device *rdev)
2586 radeon_surface_init(rdev); 2578 radeon_surface_init(rdev);
2587 /* Initialize clocks */ 2579 /* Initialize clocks */
2588 radeon_get_clock_info(rdev->ddev); 2580 radeon_get_clock_info(rdev->ddev);
2589 r = radeon_clocks_init(rdev);
2590 if (r)
2591 return r;
2592 /* Fence driver */ 2581 /* Fence driver */
2593 r = radeon_fence_driver_init(rdev); 2582 r = radeon_fence_driver_init(rdev);
2594 if (r) 2583 if (r)
@@ -2663,7 +2652,6 @@ void r600_fini(struct radeon_device *rdev)
2663 radeon_agp_fini(rdev); 2652 radeon_agp_fini(rdev);
2664 radeon_gem_fini(rdev); 2653 radeon_gem_fini(rdev);
2665 radeon_fence_driver_fini(rdev); 2654 radeon_fence_driver_fini(rdev);
2666 radeon_clocks_fini(rdev);
2667 radeon_bo_fini(rdev); 2655 radeon_bo_fini(rdev);
2668 radeon_atombios_fini(rdev); 2656 radeon_atombios_fini(rdev);
2669 kfree(rdev->bios); 2657 kfree(rdev->bios);
@@ -3541,7 +3529,7 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3541 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 3529 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3542 */ 3530 */
3543 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { 3531 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
3544 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 3532 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3545 u32 tmp; 3533 u32 tmp;
3546 3534
3547 WREG32(HDP_DEBUG1, 0); 3535 WREG32(HDP_DEBUG1, 0);
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index d13622ae74e9..9ceb2a1ce799 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -1,3 +1,28 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
1#include "drmP.h" 26#include "drmP.h"
2#include "drm.h" 27#include "drm.h"
3#include "radeon_drm.h" 28#include "radeon_drm.h"
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h
index fdc3b378cbb0..f437d36dd98c 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.h
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h
@@ -1,3 +1,27 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
1 25
2#ifndef R600_BLIT_SHADERS_H 26#ifndef R600_BLIT_SHADERS_H
3#define R600_BLIT_SHADERS_H 27#define R600_BLIT_SHADERS_H
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index d8864949e387..250a3a918193 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -1170,9 +1170,8 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1170 /* using get ib will give us the offset into the mipmap bo */ 1170 /* using get ib will give us the offset into the mipmap bo */
1171 word0 = radeon_get_ib_value(p, idx + 3) << 8; 1171 word0 = radeon_get_ib_value(p, idx + 3) << 8;
1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) { 1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1173 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1173 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture)); 1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
1175 return -EINVAL;
1176 } 1175 }
1177 return 0; 1176 return 0;
1178} 1177}
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3dfcfa3ca425..a168d644bf9e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1013,6 +1013,11 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1013int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1013int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *filp); 1014 struct drm_file *filp);
1015 1015
1016/* VRAM scratch page for HDP bug */
1017struct r700_vram_scratch {
1018 struct radeon_bo *robj;
1019 volatile uint32_t *ptr;
1020};
1016 1021
1017/* 1022/*
1018 * Core structure, functions and helpers. 1023 * Core structure, functions and helpers.
@@ -1079,6 +1084,7 @@ struct radeon_device {
1079 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1084 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1080 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1085 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1081 struct r600_blit r600_blit; 1086 struct r600_blit r600_blit;
1087 struct r700_vram_scratch vram_scratch;
1082 int msi_enabled; /* msi enabled */ 1088 int msi_enabled; /* msi enabled */
1083 struct r600_ih ih; /* r6/700 interrupt ring */ 1089 struct r600_ih ih; /* r6/700 interrupt ring */
1084 struct workqueue_struct *wq; 1090 struct workqueue_struct *wq;
@@ -1333,8 +1339,6 @@ extern bool radeon_card_posted(struct radeon_device *rdev);
1333extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1339extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1334extern void radeon_update_display_priority(struct radeon_device *rdev); 1340extern void radeon_update_display_priority(struct radeon_device *rdev);
1335extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1341extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1336extern int radeon_clocks_init(struct radeon_device *rdev);
1337extern void radeon_clocks_fini(struct radeon_device *rdev);
1338extern void radeon_scratch_init(struct radeon_device *rdev); 1342extern void radeon_scratch_init(struct radeon_device *rdev);
1339extern void radeon_surface_init(struct radeon_device *rdev); 1343extern void radeon_surface_init(struct radeon_device *rdev);
1340extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1344extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index a21bf88e8c2d..25e1dd197791 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -858,21 +858,3 @@ int radeon_asic_init(struct radeon_device *rdev)
858 return 0; 858 return 0;
859} 859}
860 860
861/*
862 * Wrapper around modesetting bits. Move to radeon_clocks.c?
863 */
864int radeon_clocks_init(struct radeon_device *rdev)
865{
866 int r;
867
868 r = radeon_static_clocks_init(rdev->ddev);
869 if (r) {
870 return r;
871 }
872 DRM_INFO("Clocks initialized !\n");
873 return 0;
874}
875
876void radeon_clocks_fini(struct radeon_device *rdev)
877{
878}
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 61141981880d..ebae14c4b768 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -85,6 +85,19 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
85 for (i = 0; i < num_indices; i++) { 85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i]; 86 gpio = &i2c_info->asGPIO_Info[i];
87 87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
88 if (gpio->sucI2cId.ucAccess == id) { 101 if (gpio->sucI2cId.ucAccess == id) {
89 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
90 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
@@ -147,6 +160,20 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev)
147 for (i = 0; i < num_indices; i++) { 160 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i]; 161 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false; 162 i2c.valid = false;
163
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev)) {
166 if ((i == 7) &&
167 (gpio->usClkMaskRegisterIndex == 0x1936) &&
168 (gpio->sucI2cId.ucAccess == 0)) {
169 gpio->sucI2cId.ucAccess = 0x97;
170 gpio->ucDataMaskShift = 8;
171 gpio->ucDataEnShift = 8;
172 gpio->ucDataY_Shift = 8;
173 gpio->ucDataA_Shift = 8;
174 }
175 }
176
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 14448a740ba6..5249af8931e6 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -327,6 +327,14 @@ void radeon_get_clock_info(struct drm_device *dev)
327 mpll->max_feedback_div = 0xff; 327 mpll->max_feedback_div = 0xff;
328 mpll->best_vco = 0; 328 mpll->best_vco = 0;
329 329
330 if (!rdev->clock.default_sclk)
331 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
332 if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)
333 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
334
335 rdev->pm.current_sclk = rdev->clock.default_sclk;
336 rdev->pm.current_mclk = rdev->clock.default_mclk;
337
330} 338}
331 339
332/* 10 khz */ 340/* 10 khz */
@@ -897,53 +905,3 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
897 } 905 }
898} 906}
899 907
900static void radeon_apply_clock_quirks(struct radeon_device *rdev)
901{
902 uint32_t tmp;
903
904 /* XXX make sure engine is idle */
905
906 if (rdev->family < CHIP_RS600) {
907 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
908 if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
909 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
910 if ((rdev->family == CHIP_RV250)
911 || (rdev->family == CHIP_RV280))
912 tmp |=
913 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
914 if ((rdev->family == CHIP_RV350)
915 || (rdev->family == CHIP_RV380))
916 tmp |= R300_SCLK_FORCE_VAP;
917 if (rdev->family == CHIP_R420)
918 tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
919 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
920 } else if (rdev->family < CHIP_R600) {
921 tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
922 tmp |= AVIVO_CP_FORCEON;
923 WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
924
925 tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
926 tmp |= AVIVO_E2_FORCEON;
927 WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
928
929 tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
930 tmp |= AVIVO_IDCT_FORCEON;
931 WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
932 }
933}
934
935int radeon_static_clocks_init(struct drm_device *dev)
936{
937 struct radeon_device *rdev = dev->dev_private;
938
939 /* XXX make sure engine is idle */
940
941 if (radeon_dynclks != -1) {
942 if (radeon_dynclks) {
943 if (rdev->asic->set_clock_gating)
944 radeon_set_clock_gating(rdev, 1);
945 }
946 }
947 radeon_apply_clock_quirks(rdev);
948 return 0;
949}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index bd74e428bd14..a04b7a6ad95f 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -1485,6 +1485,11 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1485 /* PowerMac8,1 ? */ 1485 /* PowerMac8,1 ? */
1486 /* imac g5 isight */ 1486 /* imac g5 isight */
1487 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1487 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1488 } else if ((rdev->pdev->device == 0x4a48) &&
1489 (rdev->pdev->subsystem_vendor == 0x1002) &&
1490 (rdev->pdev->subsystem_device == 0x4a48)) {
1491 /* Mac X800 */
1492 rdev->mode_info.connector_table = CT_MAC_X800;
1488 } else 1493 } else
1489#endif /* CONFIG_PPC_PMAC */ 1494#endif /* CONFIG_PPC_PMAC */
1490#ifdef CONFIG_PPC64 1495#ifdef CONFIG_PPC64
@@ -1961,6 +1966,48 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1961 CONNECTOR_OBJECT_ID_VGA, 1966 CONNECTOR_OBJECT_ID_VGA,
1962 &hpd); 1967 &hpd);
1963 break; 1968 break;
1969 case CT_MAC_X800:
1970 DRM_INFO("Connector Table: %d (mac x800)\n",
1971 rdev->mode_info.connector_table);
1972 /* DVI - primary dac, internal tmds */
1973 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1974 hpd.hpd = RADEON_HPD_1; /* ??? */
1975 radeon_add_legacy_encoder(dev,
1976 radeon_get_encoder_enum(dev,
1977 ATOM_DEVICE_DFP1_SUPPORT,
1978 0),
1979 ATOM_DEVICE_DFP1_SUPPORT);
1980 radeon_add_legacy_encoder(dev,
1981 radeon_get_encoder_enum(dev,
1982 ATOM_DEVICE_CRT1_SUPPORT,
1983 1),
1984 ATOM_DEVICE_CRT1_SUPPORT);
1985 radeon_add_legacy_connector(dev, 0,
1986 ATOM_DEVICE_DFP1_SUPPORT |
1987 ATOM_DEVICE_CRT1_SUPPORT,
1988 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1989 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1990 &hpd);
1991 /* DVI - tv dac, dvo */
1992 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1993 hpd.hpd = RADEON_HPD_2; /* ??? */
1994 radeon_add_legacy_encoder(dev,
1995 radeon_get_encoder_enum(dev,
1996 ATOM_DEVICE_DFP2_SUPPORT,
1997 0),
1998 ATOM_DEVICE_DFP2_SUPPORT);
1999 radeon_add_legacy_encoder(dev,
2000 radeon_get_encoder_enum(dev,
2001 ATOM_DEVICE_CRT2_SUPPORT,
2002 2),
2003 ATOM_DEVICE_CRT2_SUPPORT);
2004 radeon_add_legacy_connector(dev, 1,
2005 ATOM_DEVICE_DFP2_SUPPORT |
2006 ATOM_DEVICE_CRT2_SUPPORT,
2007 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2008 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2009 &hpd);
2010 break;
1964 default: 2011 default:
1965 DRM_INFO("Connector table: %d (invalid)\n", 2012 DRM_INFO("Connector table: %d (invalid)\n",
1966 rdev->mode_info.connector_table); 2013 rdev->mode_info.connector_table);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 1a5ee392e9c7..ecc1a8fafbfd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -481,7 +481,8 @@ static int radeon_lvds_mode_valid(struct drm_connector *connector,
481 return MODE_OK; 481 return MODE_OK;
482} 482}
483 483
484static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector) 484static enum drm_connector_status
485radeon_lvds_detect(struct drm_connector *connector, bool force)
485{ 486{
486 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 487 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
487 struct drm_encoder *encoder = radeon_best_single_encoder(connector); 488 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
@@ -594,7 +595,8 @@ static int radeon_vga_mode_valid(struct drm_connector *connector,
594 return MODE_OK; 595 return MODE_OK;
595} 596}
596 597
597static enum drm_connector_status radeon_vga_detect(struct drm_connector *connector) 598static enum drm_connector_status
599radeon_vga_detect(struct drm_connector *connector, bool force)
598{ 600{
599 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 601 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
600 struct drm_encoder *encoder; 602 struct drm_encoder *encoder;
@@ -691,7 +693,8 @@ static int radeon_tv_mode_valid(struct drm_connector *connector,
691 return MODE_OK; 693 return MODE_OK;
692} 694}
693 695
694static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector) 696static enum drm_connector_status
697radeon_tv_detect(struct drm_connector *connector, bool force)
695{ 698{
696 struct drm_encoder *encoder; 699 struct drm_encoder *encoder;
697 struct drm_encoder_helper_funcs *encoder_funcs; 700 struct drm_encoder_helper_funcs *encoder_funcs;
@@ -748,7 +751,8 @@ static int radeon_dvi_get_modes(struct drm_connector *connector)
748 * we have to check if this analog encoder is shared with anyone else (TV) 751 * we have to check if this analog encoder is shared with anyone else (TV)
749 * if its shared we have to set the other connector to disconnected. 752 * if its shared we have to set the other connector to disconnected.
750 */ 753 */
751static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector) 754static enum drm_connector_status
755radeon_dvi_detect(struct drm_connector *connector, bool force)
752{ 756{
753 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 757 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
754 struct drm_encoder *encoder = NULL; 758 struct drm_encoder *encoder = NULL;
@@ -972,7 +976,8 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
972 return ret; 976 return ret;
973} 977}
974 978
975static enum drm_connector_status radeon_dp_detect(struct drm_connector *connector) 979static enum drm_connector_status
980radeon_dp_detect(struct drm_connector *connector, bool force)
976{ 981{
977 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 982 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
978 enum drm_connector_status ret = connector_status_disconnected; 983 enum drm_connector_status ret = connector_status_disconnected;
@@ -1051,10 +1056,16 @@ radeon_add_atom_connector(struct drm_device *dev,
1051 uint32_t subpixel_order = SubPixelNone; 1056 uint32_t subpixel_order = SubPixelNone;
1052 bool shared_ddc = false; 1057 bool shared_ddc = false;
1053 1058
1054 /* fixme - tv/cv/din */
1055 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1059 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1056 return; 1060 return;
1057 1061
1062 /* if the user selected tv=0 don't try and add the connector */
1063 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1064 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1065 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1066 (radeon_tv == 0))
1067 return;
1068
1058 /* see if we already added it */ 1069 /* see if we already added it */
1059 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1060 radeon_connector = to_radeon_connector(connector); 1071 radeon_connector = to_radeon_connector(connector);
@@ -1209,19 +1220,17 @@ radeon_add_atom_connector(struct drm_device *dev,
1209 case DRM_MODE_CONNECTOR_SVIDEO: 1220 case DRM_MODE_CONNECTOR_SVIDEO:
1210 case DRM_MODE_CONNECTOR_Composite: 1221 case DRM_MODE_CONNECTOR_Composite:
1211 case DRM_MODE_CONNECTOR_9PinDIN: 1222 case DRM_MODE_CONNECTOR_9PinDIN:
1212 if (radeon_tv == 1) { 1223 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
1213 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); 1224 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
1214 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); 1225 radeon_connector->dac_load_detect = true;
1215 radeon_connector->dac_load_detect = true; 1226 drm_connector_attach_property(&radeon_connector->base,
1216 drm_connector_attach_property(&radeon_connector->base, 1227 rdev->mode_info.load_detect_property,
1217 rdev->mode_info.load_detect_property, 1228 1);
1218 1); 1229 drm_connector_attach_property(&radeon_connector->base,
1219 drm_connector_attach_property(&radeon_connector->base, 1230 rdev->mode_info.tv_std_property,
1220 rdev->mode_info.tv_std_property, 1231 radeon_atombios_get_tv_info(rdev));
1221 radeon_atombios_get_tv_info(rdev)); 1232 /* no HPD on analog connectors */
1222 /* no HPD on analog connectors */ 1233 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1223 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1224 }
1225 break; 1234 break;
1226 case DRM_MODE_CONNECTOR_LVDS: 1235 case DRM_MODE_CONNECTOR_LVDS:
1227 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1236 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -1272,10 +1281,16 @@ radeon_add_legacy_connector(struct drm_device *dev,
1272 struct radeon_connector *radeon_connector; 1281 struct radeon_connector *radeon_connector;
1273 uint32_t subpixel_order = SubPixelNone; 1282 uint32_t subpixel_order = SubPixelNone;
1274 1283
1275 /* fixme - tv/cv/din */
1276 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1284 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1277 return; 1285 return;
1278 1286
1287 /* if the user selected tv=0 don't try and add the connector */
1288 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1289 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1290 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1291 (radeon_tv == 0))
1292 return;
1293
1279 /* see if we already added it */ 1294 /* see if we already added it */
1280 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1295 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1281 radeon_connector = to_radeon_connector(connector); 1296 radeon_connector = to_radeon_connector(connector);
@@ -1347,26 +1362,24 @@ radeon_add_legacy_connector(struct drm_device *dev,
1347 case DRM_MODE_CONNECTOR_SVIDEO: 1362 case DRM_MODE_CONNECTOR_SVIDEO:
1348 case DRM_MODE_CONNECTOR_Composite: 1363 case DRM_MODE_CONNECTOR_Composite:
1349 case DRM_MODE_CONNECTOR_9PinDIN: 1364 case DRM_MODE_CONNECTOR_9PinDIN:
1350 if (radeon_tv == 1) { 1365 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
1351 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); 1366 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
1352 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); 1367 radeon_connector->dac_load_detect = true;
1353 radeon_connector->dac_load_detect = true; 1368 /* RS400,RC410,RS480 chipset seems to report a lot
1354 /* RS400,RC410,RS480 chipset seems to report a lot 1369 * of false positive on load detect, we haven't yet
1355 * of false positive on load detect, we haven't yet 1370 * found a way to make load detect reliable on those
1356 * found a way to make load detect reliable on those 1371 * chipset, thus just disable it for TV.
1357 * chipset, thus just disable it for TV. 1372 */
1358 */ 1373 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
1359 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) 1374 radeon_connector->dac_load_detect = false;
1360 radeon_connector->dac_load_detect = false; 1375 drm_connector_attach_property(&radeon_connector->base,
1361 drm_connector_attach_property(&radeon_connector->base, 1376 rdev->mode_info.load_detect_property,
1362 rdev->mode_info.load_detect_property, 1377 radeon_connector->dac_load_detect);
1363 radeon_connector->dac_load_detect); 1378 drm_connector_attach_property(&radeon_connector->base,
1364 drm_connector_attach_property(&radeon_connector->base, 1379 rdev->mode_info.tv_std_property,
1365 rdev->mode_info.tv_std_property, 1380 radeon_combios_get_tv_info(rdev));
1366 radeon_combios_get_tv_info(rdev)); 1381 /* no HPD on analog connectors */
1367 /* no HPD on analog connectors */ 1382 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1368 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1369 }
1370 break; 1383 break;
1371 case DRM_MODE_CONNECTOR_LVDS: 1384 case DRM_MODE_CONNECTOR_LVDS:
1372 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1385 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 69b3c2291e92..256d204a6d24 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -293,30 +293,20 @@ bool radeon_card_posted(struct radeon_device *rdev)
293void radeon_update_bandwidth_info(struct radeon_device *rdev) 293void radeon_update_bandwidth_info(struct radeon_device *rdev)
294{ 294{
295 fixed20_12 a; 295 fixed20_12 a;
296 u32 sclk, mclk; 296 u32 sclk = rdev->pm.current_sclk;
297 u32 mclk = rdev->pm.current_mclk;
297 298
298 if (rdev->flags & RADEON_IS_IGP) { 299 /* sclk/mclk in Mhz */
299 sclk = radeon_get_engine_clock(rdev); 300 a.full = dfixed_const(100);
300 mclk = rdev->clock.default_mclk; 301 rdev->pm.sclk.full = dfixed_const(sclk);
301 302 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
302 a.full = dfixed_const(100); 303 rdev->pm.mclk.full = dfixed_const(mclk);
303 rdev->pm.sclk.full = dfixed_const(sclk); 304 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
304 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
305 rdev->pm.mclk.full = dfixed_const(mclk);
306 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
307 305
306 if (rdev->flags & RADEON_IS_IGP) {
308 a.full = dfixed_const(16); 307 a.full = dfixed_const(16);
309 /* core_bandwidth = sclk(Mhz) * 16 */ 308 /* core_bandwidth = sclk(Mhz) * 16 */
310 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 309 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
311 } else {
312 sclk = radeon_get_engine_clock(rdev);
313 mclk = radeon_get_memory_clock(rdev);
314
315 a.full = dfixed_const(100);
316 rdev->pm.sclk.full = dfixed_const(sclk);
317 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
318 rdev->pm.mclk.full = dfixed_const(mclk);
319 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
320 } 310 }
321} 311}
322 312
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 6dd434ad2429..127a395f70fb 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1140,17 +1140,18 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1140 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1140 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1141 else 1141 else
1142 radeon_crtc->rmx_type = RMX_OFF; 1142 radeon_crtc->rmx_type = RMX_OFF;
1143 src_v = crtc->mode.vdisplay;
1144 dst_v = radeon_crtc->native_mode.vdisplay;
1145 src_h = crtc->mode.hdisplay;
1146 dst_h = radeon_crtc->native_mode.vdisplay;
1147 /* copy native mode */ 1143 /* copy native mode */
1148 memcpy(&radeon_crtc->native_mode, 1144 memcpy(&radeon_crtc->native_mode,
1149 &radeon_encoder->native_mode, 1145 &radeon_encoder->native_mode,
1150 sizeof(struct drm_display_mode)); 1146 sizeof(struct drm_display_mode));
1147 src_v = crtc->mode.vdisplay;
1148 dst_v = radeon_crtc->native_mode.vdisplay;
1149 src_h = crtc->mode.hdisplay;
1150 dst_h = radeon_crtc->native_mode.hdisplay;
1151 1151
1152 /* fix up for overscan on hdmi */ 1152 /* fix up for overscan on hdmi */
1153 if (ASIC_IS_AVIVO(rdev) && 1153 if (ASIC_IS_AVIVO(rdev) &&
1154 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1154 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1155 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1155 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1156 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1156 drm_detect_hdmi_monitor(radeon_connector->edid) && 1157 drm_detect_hdmi_monitor(radeon_connector->edid) &&
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 0416804d8f30..6a13ee38a5b9 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -213,7 +213,7 @@ static void post_xfer(struct i2c_adapter *i2c_adap)
213 213
214static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 214static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
215{ 215{
216 u32 sclk = radeon_get_engine_clock(rdev); 216 u32 sclk = rdev->pm.current_sclk;
217 u32 prescale = 0; 217 u32 prescale = 0;
218 u32 nm; 218 u32 nm;
219 u8 n, m, loop; 219 u8 n, m, loop;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 8f93e2b4b0c8..17a6602b5885 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -204,7 +204,7 @@ struct radeon_i2c_chan {
204 204
205/* mostly for macs, but really any system without connector tables */ 205/* mostly for macs, but really any system without connector tables */
206enum radeon_connector_table { 206enum radeon_connector_table {
207 CT_NONE, 207 CT_NONE = 0,
208 CT_GENERIC, 208 CT_GENERIC,
209 CT_IBOOK, 209 CT_IBOOK,
210 CT_POWERBOOK_EXTERNAL, 210 CT_POWERBOOK_EXTERNAL,
@@ -215,6 +215,7 @@ enum radeon_connector_table {
215 CT_IMAC_G5_ISIGHT, 215 CT_IMAC_G5_ISIGHT,
216 CT_EMAC, 216 CT_EMAC,
217 CT_RN50_POWER, 217 CT_RN50_POWER,
218 CT_MAC_X800,
218}; 219};
219 220
220enum radeon_dvo_chip { 221enum radeon_dvo_chip {
@@ -600,7 +601,6 @@ extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct d
600void radeon_enc_destroy(struct drm_encoder *encoder); 601void radeon_enc_destroy(struct drm_encoder *encoder);
601void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 602void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
602void radeon_combios_asic_init(struct drm_device *dev); 603void radeon_combios_asic_init(struct drm_device *dev);
603extern int radeon_static_clocks_init(struct drm_device *dev);
604bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 604bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
605 struct drm_display_mode *mode, 605 struct drm_display_mode *mode,
606 struct drm_display_mode *adjusted_mode); 606 struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index f1c796810117..bfa59db374d2 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -905,6 +905,54 @@ static void rv770_gpu_init(struct radeon_device *rdev)
905 905
906} 906}
907 907
908static int rv770_vram_scratch_init(struct radeon_device *rdev)
909{
910 int r;
911 u64 gpu_addr;
912
913 if (rdev->vram_scratch.robj == NULL) {
914 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
915 true, RADEON_GEM_DOMAIN_VRAM,
916 &rdev->vram_scratch.robj);
917 if (r) {
918 return r;
919 }
920 }
921
922 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
923 if (unlikely(r != 0))
924 return r;
925 r = radeon_bo_pin(rdev->vram_scratch.robj,
926 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
927 if (r) {
928 radeon_bo_unreserve(rdev->vram_scratch.robj);
929 return r;
930 }
931 r = radeon_bo_kmap(rdev->vram_scratch.robj,
932 (void **)&rdev->vram_scratch.ptr);
933 if (r)
934 radeon_bo_unpin(rdev->vram_scratch.robj);
935 radeon_bo_unreserve(rdev->vram_scratch.robj);
936
937 return r;
938}
939
940static void rv770_vram_scratch_fini(struct radeon_device *rdev)
941{
942 int r;
943
944 if (rdev->vram_scratch.robj == NULL) {
945 return;
946 }
947 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
948 if (likely(r == 0)) {
949 radeon_bo_kunmap(rdev->vram_scratch.robj);
950 radeon_bo_unpin(rdev->vram_scratch.robj);
951 radeon_bo_unreserve(rdev->vram_scratch.robj);
952 }
953 radeon_bo_unref(&rdev->vram_scratch.robj);
954}
955
908int rv770_mc_init(struct radeon_device *rdev) 956int rv770_mc_init(struct radeon_device *rdev)
909{ 957{
910 u32 tmp; 958 u32 tmp;
@@ -970,6 +1018,9 @@ static int rv770_startup(struct radeon_device *rdev)
970 if (r) 1018 if (r)
971 return r; 1019 return r;
972 } 1020 }
1021 r = rv770_vram_scratch_init(rdev);
1022 if (r)
1023 return r;
973 rv770_gpu_init(rdev); 1024 rv770_gpu_init(rdev);
974 r = r600_blit_init(rdev); 1025 r = r600_blit_init(rdev);
975 if (r) { 1026 if (r) {
@@ -1023,11 +1074,6 @@ int rv770_resume(struct radeon_device *rdev)
1023 */ 1074 */
1024 /* post card */ 1075 /* post card */
1025 atom_asic_init(rdev->mode_info.atom_context); 1076 atom_asic_init(rdev->mode_info.atom_context);
1026 /* Initialize clocks */
1027 r = radeon_clocks_init(rdev);
1028 if (r) {
1029 return r;
1030 }
1031 1077
1032 r = rv770_startup(rdev); 1078 r = rv770_startup(rdev);
1033 if (r) { 1079 if (r) {
@@ -1118,9 +1164,6 @@ int rv770_init(struct radeon_device *rdev)
1118 radeon_surface_init(rdev); 1164 radeon_surface_init(rdev);
1119 /* Initialize clocks */ 1165 /* Initialize clocks */
1120 radeon_get_clock_info(rdev->ddev); 1166 radeon_get_clock_info(rdev->ddev);
1121 r = radeon_clocks_init(rdev);
1122 if (r)
1123 return r;
1124 /* Fence driver */ 1167 /* Fence driver */
1125 r = radeon_fence_driver_init(rdev); 1168 r = radeon_fence_driver_init(rdev);
1126 if (r) 1169 if (r)
@@ -1195,9 +1238,9 @@ void rv770_fini(struct radeon_device *rdev)
1195 r600_irq_fini(rdev); 1238 r600_irq_fini(rdev);
1196 radeon_irq_kms_fini(rdev); 1239 radeon_irq_kms_fini(rdev);
1197 rv770_pcie_gart_fini(rdev); 1240 rv770_pcie_gart_fini(rdev);
1241 rv770_vram_scratch_fini(rdev);
1198 radeon_gem_fini(rdev); 1242 radeon_gem_fini(rdev);
1199 radeon_fence_driver_fini(rdev); 1243 radeon_fence_driver_fini(rdev);
1200 radeon_clocks_fini(rdev);
1201 radeon_agp_fini(rdev); 1244 radeon_agp_fini(rdev);
1202 radeon_bo_fini(rdev); 1245 radeon_bo_fini(rdev);
1203 radeon_atombios_fini(rdev); 1246 radeon_atombios_fini(rdev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 21:03:18 -0500