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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c81
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c29
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c140
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c71
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c13
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h2
-rw-r--r--drivers/gpu/drm/radeon/ni.c14
-rw-r--r--drivers/gpu/drm/radeon/r600.c20
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c196
-rw-r--r--drivers/gpu/drm/radeon/r600d.h28
-rw-r--r--drivers/gpu/drm/radeon/radeon.h27
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h10
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c51
-rw-r--r--drivers/gpu/drm/radeon/radeon_atpx_handler.c56
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c138
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c57
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c32
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c26
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c35
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c1
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r6009
-rw-r--r--drivers/gpu/drm/radeon/rv515.c13
-rw-r--r--drivers/gpu/drm/radeon/si.c35
-rw-r--r--drivers/gpu/drm/radeon/sid.h3
31 files changed, 728 insertions, 405 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 9e6f76fec527..2817101fb167 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -258,8 +258,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
258 radeon_crtc->enabled = true; 258 radeon_crtc->enabled = true;
259 /* adjust pm to dpms changes BEFORE enabling crtcs */ 259 /* adjust pm to dpms changes BEFORE enabling crtcs */
260 radeon_pm_compute_clocks(rdev); 260 radeon_pm_compute_clocks(rdev);
261 /* disable crtc pair power gating before programming */ 261 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
262 if (ASIC_IS_DCE6(rdev))
263 atombios_powergate_crtc(crtc, ATOM_DISABLE); 262 atombios_powergate_crtc(crtc, ATOM_DISABLE);
264 atombios_enable_crtc(crtc, ATOM_ENABLE); 263 atombios_enable_crtc(crtc, ATOM_ENABLE);
265 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 264 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
@@ -278,25 +277,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
278 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 277 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
279 atombios_enable_crtc(crtc, ATOM_DISABLE); 278 atombios_enable_crtc(crtc, ATOM_DISABLE);
280 radeon_crtc->enabled = false; 279 radeon_crtc->enabled = false;
281 /* power gating is per-pair */ 280 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
282 if (ASIC_IS_DCE6(rdev)) { 281 atombios_powergate_crtc(crtc, ATOM_ENABLE);
283 struct drm_crtc *other_crtc;
284 struct radeon_crtc *other_radeon_crtc;
285 list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
286 other_radeon_crtc = to_radeon_crtc(other_crtc);
287 if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
288 ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
289 ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
290 ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
291 ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
292 ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
293 /* if both crtcs in the pair are off, enable power gating */
294 if (other_radeon_crtc->enabled == false)
295 atombios_powergate_crtc(crtc, ATOM_ENABLE);
296 break;
297 }
298 }
299 }
300 /* adjust pm to dpms changes AFTER disabling crtcs */ 282 /* adjust pm to dpms changes AFTER disabling crtcs */
301 radeon_pm_compute_clocks(rdev); 283 radeon_pm_compute_clocks(rdev);
302 break; 284 break;
@@ -444,11 +426,28 @@ union atom_enable_ss {
444static void atombios_crtc_program_ss(struct radeon_device *rdev, 426static void atombios_crtc_program_ss(struct radeon_device *rdev,
445 int enable, 427 int enable,
446 int pll_id, 428 int pll_id,
429 int crtc_id,
447 struct radeon_atom_ss *ss) 430 struct radeon_atom_ss *ss)
448{ 431{
432 unsigned i;
449 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 433 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
450 union atom_enable_ss args; 434 union atom_enable_ss args;
451 435
436 if (!enable) {
437 for (i = 0; i < rdev->num_crtc; i++) {
438 if (rdev->mode_info.crtcs[i] &&
439 rdev->mode_info.crtcs[i]->enabled &&
440 i != crtc_id &&
441 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
442 /* one other crtc is using this pll don't turn
443 * off spread spectrum as it might turn off
444 * display on active crtc
445 */
446 return;
447 }
448 }
449 }
450
452 memset(&args, 0, sizeof(args)); 451 memset(&args, 0, sizeof(args));
453 452
454 if (ASIC_IS_DCE5(rdev)) { 453 if (ASIC_IS_DCE5(rdev)) {
@@ -1028,7 +1027,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1028 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 1027 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1029 &ref_div, &post_div); 1028 &ref_div, &post_div);
1030 1029
1031 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss); 1030 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1032 1031
1033 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1032 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1034 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1033 encoder_mode, radeon_encoder->encoder_id, mode->clock,
@@ -1051,7 +1050,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1051 ss.step = step_size; 1050 ss.step = step_size;
1052 } 1051 }
1053 1052
1054 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss); 1053 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1055 } 1054 }
1056} 1055}
1057 1056
@@ -1531,12 +1530,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1531 * crtc virtual pixel clock. 1530 * crtc virtual pixel clock.
1532 */ 1531 */
1533 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1532 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1534 if (ASIC_IS_DCE5(rdev)) 1533 if (rdev->clock.dp_extclk)
1535 return ATOM_DCPLL; 1534 return ATOM_PPLL_INVALID;
1536 else if (ASIC_IS_DCE6(rdev)) 1535 else if (ASIC_IS_DCE6(rdev))
1537 return ATOM_PPLL0; 1536 return ATOM_PPLL0;
1538 else if (rdev->clock.dp_extclk) 1537 else if (ASIC_IS_DCE5(rdev))
1539 return ATOM_PPLL_INVALID; 1538 return ATOM_DCPLL;
1540 } 1539 }
1541 } 1540 }
1542 } 1541 }
@@ -1572,11 +1571,11 @@ void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1572 ASIC_INTERNAL_SS_ON_DCPLL, 1571 ASIC_INTERNAL_SS_ON_DCPLL,
1573 rdev->clock.default_dispclk); 1572 rdev->clock.default_dispclk);
1574 if (ss_enabled) 1573 if (ss_enabled)
1575 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss); 1574 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1576 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1575 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1577 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1576 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1578 if (ss_enabled) 1577 if (ss_enabled)
1579 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss); 1578 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1580 } 1579 }
1581 1580
1582} 1581}
@@ -1635,18 +1634,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1635static void atombios_crtc_prepare(struct drm_crtc *crtc) 1634static void atombios_crtc_prepare(struct drm_crtc *crtc)
1636{ 1635{
1637 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1636 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1637 struct drm_device *dev = crtc->dev;
1638 struct radeon_device *rdev = dev->dev_private;
1638 1639
1640 radeon_crtc->in_mode_set = true;
1639 /* pick pll */ 1641 /* pick pll */
1640 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1642 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1641 1643
1644 /* disable crtc pair power gating before programming */
1645 if (ASIC_IS_DCE6(rdev))
1646 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1647
1642 atombios_lock_crtc(crtc, ATOM_ENABLE); 1648 atombios_lock_crtc(crtc, ATOM_ENABLE);
1643 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1649 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1644} 1650}
1645 1651
1646static void atombios_crtc_commit(struct drm_crtc *crtc) 1652static void atombios_crtc_commit(struct drm_crtc *crtc)
1647{ 1653{
1654 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1655
1648 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1656 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1649 atombios_lock_crtc(crtc, ATOM_DISABLE); 1657 atombios_lock_crtc(crtc, ATOM_DISABLE);
1658 radeon_crtc->in_mode_set = false;
1650} 1659}
1651 1660
1652static void atombios_crtc_disable(struct drm_crtc *crtc) 1661static void atombios_crtc_disable(struct drm_crtc *crtc)
@@ -1655,9 +1664,22 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1655 struct drm_device *dev = crtc->dev; 1664 struct drm_device *dev = crtc->dev;
1656 struct radeon_device *rdev = dev->dev_private; 1665 struct radeon_device *rdev = dev->dev_private;
1657 struct radeon_atom_ss ss; 1666 struct radeon_atom_ss ss;
1667 int i;
1658 1668
1659 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1669 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1660 1670
1671 for (i = 0; i < rdev->num_crtc; i++) {
1672 if (rdev->mode_info.crtcs[i] &&
1673 rdev->mode_info.crtcs[i]->enabled &&
1674 i != radeon_crtc->crtc_id &&
1675 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1676 /* one other crtc is using this pll don't turn
1677 * off the pll
1678 */
1679 goto done;
1680 }
1681 }
1682
1661 switch (radeon_crtc->pll_id) { 1683 switch (radeon_crtc->pll_id) {
1662 case ATOM_PPLL1: 1684 case ATOM_PPLL1:
1663 case ATOM_PPLL2: 1685 case ATOM_PPLL2:
@@ -1674,6 +1696,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1674 default: 1696 default:
1675 break; 1697 break;
1676 } 1698 }
1699done:
1677 radeon_crtc->pll_id = -1; 1700 radeon_crtc->pll_id = -1;
1678} 1701}
1679 1702
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 7712cf5ab33b..3623b98ed3fe 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -577,30 +577,25 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
577 struct radeon_device *rdev = dev->dev_private; 577 struct radeon_device *rdev = dev->dev_private;
578 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 578 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
579 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 579 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
580 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
581 u8 tmp;
580 582
581 if (!ASIC_IS_DCE4(rdev)) 583 if (!ASIC_IS_DCE4(rdev))
582 return panel_mode; 584 return panel_mode;
583 585
584 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 586 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
585 ENCODER_OBJECT_ID_NUTMEG) 587 /* DP bridge chips */
586 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 588 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
587 else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 589 if (tmp & 1)
588 ENCODER_OBJECT_ID_TRAVIS) { 590 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
589 u8 id[6]; 591 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
590 int i; 592 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
591 for (i = 0; i < 6; i++)
592 id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
593 if (id[0] == 0x73 &&
594 id[1] == 0x69 &&
595 id[2] == 0x76 &&
596 id[3] == 0x61 &&
597 id[4] == 0x72 &&
598 id[5] == 0x54)
599 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 593 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
600 else 594 else
601 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 595 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
602 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 596 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
603 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 597 /* eDP */
598 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
604 if (tmp & 1) 599 if (tmp & 1)
605 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 600 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
606 } 601 }
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index f9bc27fe269a..6e8803a1170c 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1379,6 +1379,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1379 struct drm_device *dev = encoder->dev; 1379 struct drm_device *dev = encoder->dev;
1380 struct radeon_device *rdev = dev->dev_private; 1380 struct radeon_device *rdev = dev->dev_private;
1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1382 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1383 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1382 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1384 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1383 struct radeon_connector *radeon_connector = NULL; 1385 struct radeon_connector *radeon_connector = NULL;
1384 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1386 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
@@ -1390,19 +1392,37 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1390 1392
1391 switch (mode) { 1393 switch (mode) {
1392 case DRM_MODE_DPMS_ON: 1394 case DRM_MODE_DPMS_ON:
1393 /* some early dce3.2 boards have a bug in their transmitter control table */ 1395 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1394 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) || 1396 if (!connector)
1395 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1397 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1396 if (ASIC_IS_DCE6(rdev)) { 1398 else
1397 /* It seems we need to call ATOM_ENCODER_CMD_SETUP again 1399 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1398 * before reenabling encoder on DPMS ON, otherwise we never 1400
1399 * get picture 1401 /* setup and enable the encoder */
1400 */ 1402 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1401 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1403 atombios_dig_encoder_setup(encoder,
1404 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1405 dig->panel_mode);
1406 if (ext_encoder) {
1407 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1408 atombios_external_encoder_setup(encoder, ext_encoder,
1409 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1402 } 1410 }
1403 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1411 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1404 } else { 1412 } else if (ASIC_IS_DCE4(rdev)) {
1413 /* setup and enable the encoder */
1414 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1415 /* enable the transmitter */
1416 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1405 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1417 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1418 } else {
1419 /* setup and enable the encoder and transmitter */
1420 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1421 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1422 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1423 /* some early dce3.2 boards have a bug in their transmitter control table */
1424 if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1425 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1406 } 1426 }
1407 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1427 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1428 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
@@ -1420,10 +1440,19 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1420 case DRM_MODE_DPMS_STANDBY: 1440 case DRM_MODE_DPMS_STANDBY:
1421 case DRM_MODE_DPMS_SUSPEND: 1441 case DRM_MODE_DPMS_SUSPEND:
1422 case DRM_MODE_DPMS_OFF: 1442 case DRM_MODE_DPMS_OFF:
1423 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) 1443 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1444 /* disable the transmitter */
1424 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1445 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1425 else 1446 } else if (ASIC_IS_DCE4(rdev)) {
1447 /* disable the transmitter */
1448 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1449 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1450 } else {
1451 /* disable the encoder and transmitter */
1426 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1452 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1453 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1454 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1455 }
1427 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1456 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1428 if (ASIC_IS_DCE4(rdev)) 1457 if (ASIC_IS_DCE4(rdev))
1429 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1458 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
@@ -1740,13 +1769,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1740 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1769 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1741 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1770 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1742 struct drm_encoder *test_encoder; 1771 struct drm_encoder *test_encoder;
1743 struct radeon_encoder_atom_dig *dig; 1772 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1744 uint32_t dig_enc_in_use = 0; 1773 uint32_t dig_enc_in_use = 0;
1745 1774
1746 /* DCE4/5 */ 1775 if (ASIC_IS_DCE6(rdev)) {
1747 if (ASIC_IS_DCE4(rdev)) { 1776 /* DCE6 */
1748 dig = radeon_encoder->enc_priv; 1777 switch (radeon_encoder->encoder_id) {
1749 if (ASIC_IS_DCE41(rdev)) { 1778 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1779 if (dig->linkb)
1780 return 1;
1781 else
1782 return 0;
1783 break;
1784 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1785 if (dig->linkb)
1786 return 3;
1787 else
1788 return 2;
1789 break;
1790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1791 if (dig->linkb)
1792 return 5;
1793 else
1794 return 4;
1795 break;
1796 }
1797 } else if (ASIC_IS_DCE4(rdev)) {
1798 /* DCE4/5 */
1799 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1750 /* ontario follows DCE4 */ 1800 /* ontario follows DCE4 */
1751 if (rdev->family == CHIP_PALM) { 1801 if (rdev->family == CHIP_PALM) {
1752 if (dig->linkb) 1802 if (dig->linkb)
@@ -1848,10 +1898,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1848 struct drm_device *dev = encoder->dev; 1898 struct drm_device *dev = encoder->dev;
1849 struct radeon_device *rdev = dev->dev_private; 1899 struct radeon_device *rdev = dev->dev_private;
1850 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1900 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1851 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1852 1901
1853 radeon_encoder->pixel_clock = adjusted_mode->clock; 1902 radeon_encoder->pixel_clock = adjusted_mode->clock;
1854 1903
1904 /* need to call this here rather than in prepare() since we need some crtc info */
1905 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1906
1855 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1907 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1856 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1908 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1857 atombios_yuv_setup(encoder, true); 1909 atombios_yuv_setup(encoder, true);
@@ -1870,38 +1922,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1870 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1922 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1871 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1923 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1872 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1924 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1873 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1925 /* handled in dpms */
1874 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1875 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1876
1877 if (!connector)
1878 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1879 else
1880 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1881
1882 /* setup and enable the encoder */
1883 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1884 atombios_dig_encoder_setup(encoder,
1885 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1886 dig->panel_mode);
1887 } else if (ASIC_IS_DCE4(rdev)) {
1888 /* disable the transmitter */
1889 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1890 /* setup and enable the encoder */
1891 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1892
1893 /* enable the transmitter */
1894 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1895 } else {
1896 /* disable the encoder and transmitter */
1897 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1898 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1899
1900 /* setup and enable the encoder and transmitter */
1901 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1902 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1903 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1904 }
1905 break; 1926 break;
1906 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1927 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1907 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1928 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1922,14 +1943,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1922 break; 1943 break;
1923 } 1944 }
1924 1945
1925 if (ext_encoder) {
1926 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1927 atombios_external_encoder_setup(encoder, ext_encoder,
1928 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1929 else
1930 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1931 }
1932
1933 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1946 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1934 1947
1935 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1948 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
@@ -2116,7 +2129,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2116 } 2129 }
2117 2130
2118 radeon_atom_output_lock(encoder, true); 2131 radeon_atom_output_lock(encoder, true);
2119 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2120 2132
2121 if (connector) { 2133 if (connector) {
2122 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2134 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -2137,6 +2149,7 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2137 2149
2138static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2150static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2139{ 2151{
2152 /* need to call this here as we need the crtc set up */
2140 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2153 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2141 radeon_atom_output_lock(encoder, false); 2154 radeon_atom_output_lock(encoder, false);
2142} 2155}
@@ -2177,14 +2190,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2179 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2192 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2180 if (ASIC_IS_DCE4(rdev)) 2193 /* handled in dpms */
2181 /* disable the transmitter */
2182 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2183 else {
2184 /* disable the encoder and transmitter */
2185 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2186 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2187 }
2188 break; 2194 break;
2189 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2195 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2190 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2196 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e585a3b947eb..e93b80a6d4e9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1229,24 +1229,8 @@ void evergreen_agp_enable(struct radeon_device *rdev)
1229 1229
1230void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 1230void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1231{ 1231{
1232 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1233 save->vga_control[1] = RREG32(D2VGA_CONTROL);
1234 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 1232 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1235 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 1233 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1236 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1237 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1238 if (rdev->num_crtc >= 4) {
1239 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1240 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1241 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1242 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1243 }
1244 if (rdev->num_crtc >= 6) {
1245 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1246 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1247 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1248 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1249 }
1250 1234
1251 /* Stop all video */ 1235 /* Stop all video */
1252 WREG32(VGA_RENDER_CONTROL, 0); 1236 WREG32(VGA_RENDER_CONTROL, 0);
@@ -1357,47 +1341,6 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1357 /* Unlock host access */ 1341 /* Unlock host access */
1358 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 1342 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1359 mdelay(1); 1343 mdelay(1);
1360 /* Restore video state */
1361 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1362 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1363 if (rdev->num_crtc >= 4) {
1364 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1365 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1366 }
1367 if (rdev->num_crtc >= 6) {
1368 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1369 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1370 }
1371 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1372 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1373 if (rdev->num_crtc >= 4) {
1374 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1375 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1376 }
1377 if (rdev->num_crtc >= 6) {
1378 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1379 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1380 }
1381 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1382 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1383 if (rdev->num_crtc >= 4) {
1384 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1385 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1386 }
1387 if (rdev->num_crtc >= 6) {
1388 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1389 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1390 }
1391 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1392 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1393 if (rdev->num_crtc >= 4) {
1394 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1395 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1396 }
1397 if (rdev->num_crtc >= 6) {
1398 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1399 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1400 }
1401 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1344 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1402} 1345}
1403 1346
@@ -1986,10 +1929,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1986 if (rdev->flags & RADEON_IS_IGP) 1929 if (rdev->flags & RADEON_IS_IGP)
1987 rdev->config.evergreen.tile_config |= 1 << 4; 1930 rdev->config.evergreen.tile_config |= 1 << 4;
1988 else { 1931 else {
1989 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1932 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1990 rdev->config.evergreen.tile_config |= 1 << 4; 1933 case 0: /* four banks */
1991 else
1992 rdev->config.evergreen.tile_config |= 0 << 4; 1934 rdev->config.evergreen.tile_config |= 0 << 4;
1935 break;
1936 case 1: /* eight banks */
1937 rdev->config.evergreen.tile_config |= 1 << 4;
1938 break;
1939 case 2: /* sixteen banks */
1940 default:
1941 rdev->config.evergreen.tile_config |= 2 << 4;
1942 break;
1943 }
1993 } 1944 }
1994 rdev->config.evergreen.tile_config |= 0 << 8; 1945 rdev->config.evergreen.tile_config |= 0 << 8;
1995 rdev->config.evergreen.tile_config |= 1946 rdev->config.evergreen.tile_config |=
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index c16554122ccd..e44a62a07fe3 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -788,6 +788,13 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
788 case V_030000_SQ_TEX_DIM_1D_ARRAY: 788 case V_030000_SQ_TEX_DIM_1D_ARRAY:
789 case V_030000_SQ_TEX_DIM_2D_ARRAY: 789 case V_030000_SQ_TEX_DIM_2D_ARRAY:
790 depth = 1; 790 depth = 1;
791 break;
792 case V_030000_SQ_TEX_DIM_2D_MSAA:
793 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
794 surf.nsamples = 1 << llevel;
795 llevel = 0;
796 depth = 1;
797 break;
791 case V_030000_SQ_TEX_DIM_3D: 798 case V_030000_SQ_TEX_DIM_3D:
792 break; 799 break;
793 default: 800 default:
@@ -961,13 +968,15 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
961 968
962 if (track->db_dirty) { 969 if (track->db_dirty) {
963 /* Check stencil buffer */ 970 /* Check stencil buffer */
964 if (G_028800_STENCIL_ENABLE(track->db_depth_control)) { 971 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
972 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
965 r = evergreen_cs_track_validate_stencil(p); 973 r = evergreen_cs_track_validate_stencil(p);
966 if (r) 974 if (r)
967 return r; 975 return r;
968 } 976 }
969 /* Check depth buffer */ 977 /* Check depth buffer */
970 if (G_028800_Z_ENABLE(track->db_depth_control)) { 978 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
979 G_028800_Z_ENABLE(track->db_depth_control)) {
971 r = evergreen_cs_track_validate_depth(p); 980 r = evergreen_cs_track_validate_depth(p);
972 if (r) 981 if (r)
973 return r; 982 return r;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index d3bd098e4e19..79347855d9bf 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1277,6 +1277,8 @@
1277#define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1277#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1278#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1278#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1279#define C_028044_FORMAT 0xFFFFFFFE 1279#define C_028044_FORMAT 0xFFFFFFFE
1280#define V_028044_STENCIL_INVALID 0
1281#define V_028044_STENCIL_8 1
1280#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1282#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1281#define DB_Z_READ_BASE 0x28048 1283#define DB_Z_READ_BASE 0x28048
1282#define DB_STENCIL_READ_BASE 0x2804c 1284#define DB_STENCIL_READ_BASE 0x2804c
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 9945d86d9001..853800e8582f 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -574,10 +574,18 @@ static void cayman_gpu_init(struct radeon_device *rdev)
574 if (rdev->flags & RADEON_IS_IGP) 574 if (rdev->flags & RADEON_IS_IGP)
575 rdev->config.cayman.tile_config |= 1 << 4; 575 rdev->config.cayman.tile_config |= 1 << 4;
576 else { 576 else {
577 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 577 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578 rdev->config.cayman.tile_config |= 1 << 4; 578 case 0: /* four banks */
579 else
580 rdev->config.cayman.tile_config |= 0 << 4; 579 rdev->config.cayman.tile_config |= 0 << 4;
580 break;
581 case 1: /* eight banks */
582 rdev->config.cayman.tile_config |= 1 << 4;
583 break;
584 case 2: /* sixteen banks */
585 default:
586 rdev->config.cayman.tile_config |= 2 << 4;
587 break;
588 }
581 } 589 }
582 rdev->config.cayman.tile_config |= 590 rdev->config.cayman.tile_config |=
583 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 591 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 637280f541a3..d79c639ae739 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3789,3 +3789,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3789 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3789 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3790 } 3790 }
3791} 3791}
3792
3793/**
3794 * r600_get_gpu_clock - return GPU clock counter snapshot
3795 *
3796 * @rdev: radeon_device pointer
3797 *
3798 * Fetches a GPU clock counter snapshot (R6xx-cayman).
3799 * Returns the 64 bit clock counter snapshot.
3800 */
3801uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
3802{
3803 uint64_t clock;
3804
3805 mutex_lock(&rdev->gpu_clock_mutex);
3806 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3807 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3808 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3809 mutex_unlock(&rdev->gpu_clock_mutex);
3810 return clock;
3811}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index ca87f7afaf23..f37676d7f217 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -47,18 +47,23 @@ struct r600_cs_track {
47 u32 npipes; 47 u32 npipes;
48 /* value we track */ 48 /* value we track */
49 u32 sq_config; 49 u32 sq_config;
50 u32 log_nsamples;
50 u32 nsamples; 51 u32 nsamples;
51 u32 cb_color_base_last[8]; 52 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8]; 53 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8]; 54 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8]; 55 u64 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8]; /* unused */ 56 struct radeon_bo *cb_color_frag_bo[8];
56 struct radeon_bo *cb_color_tile_bo[8]; /* unused */ 57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
57 u32 cb_color_info[8]; 61 u32 cb_color_info[8];
58 u32 cb_color_view[8]; 62 u32 cb_color_view[8];
59 u32 cb_color_size_idx[8]; /* unused */ 63 u32 cb_color_size_idx[8]; /* unused */
60 u32 cb_target_mask; 64 u32 cb_target_mask;
61 u32 cb_shader_mask; /* unused */ 65 u32 cb_shader_mask; /* unused */
66 bool is_resolve;
62 u32 cb_color_size[8]; 67 u32 cb_color_size[8];
63 u32 vgt_strmout_en; 68 u32 vgt_strmout_en;
64 u32 vgt_strmout_buffer_en; 69 u32 vgt_strmout_buffer_en;
@@ -311,7 +316,15 @@ static void r600_cs_track_init(struct r600_cs_track *track)
311 track->cb_color_bo[i] = NULL; 316 track->cb_color_bo[i] = NULL;
312 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 317 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
313 track->cb_color_bo_mc[i] = 0xFFFFFFFF; 318 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
314 } 319 track->cb_color_frag_bo[i] = NULL;
320 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
321 track->cb_color_tile_bo[i] = NULL;
322 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
323 track->cb_color_mask[i] = 0xFFFFFFFF;
324 }
325 track->is_resolve = false;
326 track->nsamples = 16;
327 track->log_nsamples = 4;
315 track->cb_target_mask = 0xFFFFFFFF; 328 track->cb_target_mask = 0xFFFFFFFF;
316 track->cb_shader_mask = 0xFFFFFFFF; 329 track->cb_shader_mask = 0xFFFFFFFF;
317 track->cb_dirty = true; 330 track->cb_dirty = true;
@@ -348,11 +361,9 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
348 volatile u32 *ib = p->ib.ptr; 361 volatile u32 *ib = p->ib.ptr;
349 unsigned array_mode; 362 unsigned array_mode;
350 u32 format; 363 u32 format;
364 /* When resolve is used, the second colorbuffer has always 1 sample. */
365 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
351 366
352 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
353 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
354 return -EINVAL;
355 }
356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; 367 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
357 format = G_0280A0_FORMAT(track->cb_color_info[i]); 368 format = G_0280A0_FORMAT(track->cb_color_info[i]);
358 if (!r600_fmt_is_valid_color(format)) { 369 if (!r600_fmt_is_valid_color(format)) {
@@ -375,7 +386,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
375 array_check.group_size = track->group_size; 386 array_check.group_size = track->group_size;
376 array_check.nbanks = track->nbanks; 387 array_check.nbanks = track->nbanks;
377 array_check.npipes = track->npipes; 388 array_check.npipes = track->npipes;
378 array_check.nsamples = track->nsamples; 389 array_check.nsamples = nsamples;
379 array_check.blocksize = r600_fmt_get_blocksize(format); 390 array_check.blocksize = r600_fmt_get_blocksize(format);
380 if (r600_get_array_mode_alignment(&array_check, 391 if (r600_get_array_mode_alignment(&array_check,
381 &pitch_align, &height_align, &depth_align, &base_align)) { 392 &pitch_align, &height_align, &depth_align, &base_align)) {
@@ -420,7 +431,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
420 } 431 }
421 432
422 /* check offset */ 433 /* check offset */
423 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format); 434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
435 r600_fmt_get_blocksize(format) * nsamples;
424 switch (array_mode) { 436 switch (array_mode) {
425 default: 437 default:
426 case V_0280A0_ARRAY_LINEAR_GENERAL: 438 case V_0280A0_ARRAY_LINEAR_GENERAL:
@@ -441,7 +453,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
441 * broken userspace. 453 * broken userspace.
442 */ 454 */
443 } else { 455 } else {
444 dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n", 456 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
445 __func__, i, array_mode, 457 __func__, i, array_mode,
446 track->cb_color_bo_offset[i], tmp, 458 track->cb_color_bo_offset[i], tmp,
447 radeon_bo_size(track->cb_color_bo[i]), 459 radeon_bo_size(track->cb_color_bo[i]),
@@ -458,6 +470,51 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
458 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | 470 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
459 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 471 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
460 ib[track->cb_color_size_idx[i]] = tmp; 472 ib[track->cb_color_size_idx[i]] = tmp;
473
474 /* FMASK/CMASK */
475 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
476 case V_0280A0_TILE_DISABLE:
477 break;
478 case V_0280A0_FRAG_ENABLE:
479 if (track->nsamples > 1) {
480 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
481 /* the tile size is 8x8, but the size is in units of bits.
482 * for bytes, do just * 8. */
483 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
484
485 if (bytes + track->cb_color_frag_offset[i] >
486 radeon_bo_size(track->cb_color_frag_bo[i])) {
487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
488 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
489 __func__, tile_max, bytes,
490 track->cb_color_frag_offset[i],
491 radeon_bo_size(track->cb_color_frag_bo[i]));
492 return -EINVAL;
493 }
494 }
495 /* fall through */
496 case V_0280A0_CLEAR_ENABLE:
497 {
498 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
499 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
500 * (128*128) / (8*8) / 2 = 128 bytes per block. */
501 uint32_t bytes = (block_max + 1) * 128;
502
503 if (bytes + track->cb_color_tile_offset[i] >
504 radeon_bo_size(track->cb_color_tile_bo[i])) {
505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
506 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
507 __func__, block_max, bytes,
508 track->cb_color_tile_offset[i],
509 radeon_bo_size(track->cb_color_tile_bo[i]));
510 return -EINVAL;
511 }
512 break;
513 }
514 default:
515 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
516 return -EINVAL;
517 }
461 return 0; 518 return 0;
462} 519}
463 520
@@ -566,7 +623,7 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
566 623
567 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 624 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
568 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 625 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
569 tmp = ntiles * bpe * 64 * nviews; 626 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
570 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 627 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
571 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 628 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
572 array_mode, 629 array_mode,
@@ -746,6 +803,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
746 */ 803 */
747 if (track->cb_dirty) { 804 if (track->cb_dirty) {
748 tmp = track->cb_target_mask; 805 tmp = track->cb_target_mask;
806
807 /* We must check both colorbuffers for RESOLVE. */
808 if (track->is_resolve) {
809 tmp |= 0xff;
810 }
811
749 for (i = 0; i < 8; i++) { 812 for (i = 0; i < 8; i++) {
750 if ((tmp >> (i * 4)) & 0xF) { 813 if ((tmp >> (i * 4)) & 0xF) {
751 /* at least one component is enabled */ 814 /* at least one component is enabled */
@@ -764,8 +827,10 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
764 } 827 }
765 828
766 /* Check depth buffer */ 829 /* Check depth buffer */
767 if (track->db_dirty && (G_028800_STENCIL_ENABLE(track->db_depth_control) || 830 if (track->db_dirty &&
768 G_028800_Z_ENABLE(track->db_depth_control))) { 831 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
832 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
833 G_028800_Z_ENABLE(track->db_depth_control))) {
769 r = r600_cs_track_validate_db(p); 834 r = r600_cs_track_validate_db(p);
770 if (r) 835 if (r)
771 return r; 836 return r;
@@ -1229,9 +1294,15 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1229 break; 1294 break;
1230 case R_028C04_PA_SC_AA_CONFIG: 1295 case R_028C04_PA_SC_AA_CONFIG:
1231 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1296 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1297 track->log_nsamples = tmp;
1232 track->nsamples = 1 << tmp; 1298 track->nsamples = 1 << tmp;
1233 track->cb_dirty = true; 1299 track->cb_dirty = true;
1234 break; 1300 break;
1301 case R_028808_CB_COLOR_CONTROL:
1302 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1303 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1304 track->cb_dirty = true;
1305 break;
1235 case R_0280A0_CB_COLOR0_INFO: 1306 case R_0280A0_CB_COLOR0_INFO:
1236 case R_0280A4_CB_COLOR1_INFO: 1307 case R_0280A4_CB_COLOR1_INFO:
1237 case R_0280A8_CB_COLOR2_INFO: 1308 case R_0280A8_CB_COLOR2_INFO:
@@ -1310,16 +1381,21 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1310 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1381 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1311 return -EINVAL; 1382 return -EINVAL;
1312 } 1383 }
1313 ib[idx] = track->cb_color_base_last[tmp];
1314 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 1384 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1385 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1386 ib[idx] = track->cb_color_base_last[tmp];
1315 } else { 1387 } else {
1316 r = r600_cs_packet_next_reloc(p, &reloc); 1388 r = r600_cs_packet_next_reloc(p, &reloc);
1317 if (r) { 1389 if (r) {
1318 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1390 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1319 return -EINVAL; 1391 return -EINVAL;
1320 } 1392 }
1321 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1322 track->cb_color_frag_bo[tmp] = reloc->robj; 1393 track->cb_color_frag_bo[tmp] = reloc->robj;
1394 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1395 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1396 }
1397 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1398 track->cb_dirty = true;
1323 } 1399 }
1324 break; 1400 break;
1325 case R_0280C0_CB_COLOR0_TILE: 1401 case R_0280C0_CB_COLOR0_TILE:
@@ -1336,16 +1412,35 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1336 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1412 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1337 return -EINVAL; 1413 return -EINVAL;
1338 } 1414 }
1339 ib[idx] = track->cb_color_base_last[tmp];
1340 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 1415 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1416 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1417 ib[idx] = track->cb_color_base_last[tmp];
1341 } else { 1418 } else {
1342 r = r600_cs_packet_next_reloc(p, &reloc); 1419 r = r600_cs_packet_next_reloc(p, &reloc);
1343 if (r) { 1420 if (r) {
1344 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1421 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1345 return -EINVAL; 1422 return -EINVAL;
1346 } 1423 }
1347 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1348 track->cb_color_tile_bo[tmp] = reloc->robj; 1424 track->cb_color_tile_bo[tmp] = reloc->robj;
1425 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1426 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1427 }
1428 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1429 track->cb_dirty = true;
1430 }
1431 break;
1432 case R_028100_CB_COLOR0_MASK:
1433 case R_028104_CB_COLOR1_MASK:
1434 case R_028108_CB_COLOR2_MASK:
1435 case R_02810C_CB_COLOR3_MASK:
1436 case R_028110_CB_COLOR4_MASK:
1437 case R_028114_CB_COLOR5_MASK:
1438 case R_028118_CB_COLOR6_MASK:
1439 case R_02811C_CB_COLOR7_MASK:
1440 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1441 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1442 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1443 track->cb_dirty = true;
1349 } 1444 }
1350 break; 1445 break;
1351 case CB_COLOR0_BASE: 1446 case CB_COLOR0_BASE:
@@ -1490,7 +1585,7 @@ unsigned r600_mip_minify(unsigned size, unsigned level)
1490} 1585}
1491 1586
1492static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, 1587static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1493 unsigned w0, unsigned h0, unsigned d0, unsigned format, 1588 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
1494 unsigned block_align, unsigned height_align, unsigned base_align, 1589 unsigned block_align, unsigned height_align, unsigned base_align,
1495 unsigned *l0_size, unsigned *mipmap_size) 1590 unsigned *l0_size, unsigned *mipmap_size)
1496{ 1591{
@@ -1518,7 +1613,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1518 1613
1519 depth = r600_mip_minify(d0, i); 1614 depth = r600_mip_minify(d0, i);
1520 1615
1521 size = nbx * nby * blocksize; 1616 size = nbx * nby * blocksize * nsamples;
1522 if (nfaces) 1617 if (nfaces)
1523 size *= nfaces; 1618 size *= nfaces;
1524 else 1619 else
@@ -1557,13 +1652,14 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1557 u32 tiling_flags) 1652 u32 tiling_flags)
1558{ 1653{
1559 struct r600_cs_track *track = p->track; 1654 struct r600_cs_track *track = p->track;
1560 u32 nfaces, llevel, blevel, w0, h0, d0; 1655 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1561 u32 word0, word1, l0_size, mipmap_size, word2, word3; 1656 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1562 u32 height_align, pitch, pitch_align, depth_align; 1657 u32 height_align, pitch, pitch_align, depth_align;
1563 u32 array, barray, larray; 1658 u32 barray, larray;
1564 u64 base_align; 1659 u64 base_align;
1565 struct array_mode_checker array_check; 1660 struct array_mode_checker array_check;
1566 u32 format; 1661 u32 format;
1662 bool is_array;
1567 1663
1568 /* on legacy kernel we don't perform advanced check */ 1664 /* on legacy kernel we don't perform advanced check */
1569 if (p->rdev == NULL) 1665 if (p->rdev == NULL)
@@ -1581,12 +1677,28 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1581 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1677 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1582 } 1678 }
1583 word1 = radeon_get_ib_value(p, idx + 1); 1679 word1 = radeon_get_ib_value(p, idx + 1);
1680 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1681 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1682 word4 = radeon_get_ib_value(p, idx + 4);
1683 word5 = radeon_get_ib_value(p, idx + 5);
1684 dim = G_038000_DIM(word0);
1584 w0 = G_038000_TEX_WIDTH(word0) + 1; 1685 w0 = G_038000_TEX_WIDTH(word0) + 1;
1686 pitch = (G_038000_PITCH(word0) + 1) * 8;
1585 h0 = G_038004_TEX_HEIGHT(word1) + 1; 1687 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1586 d0 = G_038004_TEX_DEPTH(word1); 1688 d0 = G_038004_TEX_DEPTH(word1);
1689 format = G_038004_DATA_FORMAT(word1);
1690 blevel = G_038010_BASE_LEVEL(word4);
1691 llevel = G_038014_LAST_LEVEL(word5);
1692 /* pitch in texels */
1693 array_check.array_mode = G_038000_TILE_MODE(word0);
1694 array_check.group_size = track->group_size;
1695 array_check.nbanks = track->nbanks;
1696 array_check.npipes = track->npipes;
1697 array_check.nsamples = 1;
1698 array_check.blocksize = r600_fmt_get_blocksize(format);
1587 nfaces = 1; 1699 nfaces = 1;
1588 array = 0; 1700 is_array = false;
1589 switch (G_038000_DIM(word0)) { 1701 switch (dim) {
1590 case V_038000_SQ_TEX_DIM_1D: 1702 case V_038000_SQ_TEX_DIM_1D:
1591 case V_038000_SQ_TEX_DIM_2D: 1703 case V_038000_SQ_TEX_DIM_2D:
1592 case V_038000_SQ_TEX_DIM_3D: 1704 case V_038000_SQ_TEX_DIM_3D:
@@ -1599,29 +1711,25 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1599 break; 1711 break;
1600 case V_038000_SQ_TEX_DIM_1D_ARRAY: 1712 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1601 case V_038000_SQ_TEX_DIM_2D_ARRAY: 1713 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1602 array = 1; 1714 is_array = true;
1603 break; 1715 break;
1604 case V_038000_SQ_TEX_DIM_2D_MSAA:
1605 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: 1716 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1717 is_array = true;
1718 /* fall through */
1719 case V_038000_SQ_TEX_DIM_2D_MSAA:
1720 array_check.nsamples = 1 << llevel;
1721 llevel = 0;
1722 break;
1606 default: 1723 default:
1607 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); 1724 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1608 return -EINVAL; 1725 return -EINVAL;
1609 } 1726 }
1610 format = G_038004_DATA_FORMAT(word1);
1611 if (!r600_fmt_is_valid_texture(format, p->family)) { 1727 if (!r600_fmt_is_valid_texture(format, p->family)) {
1612 dev_warn(p->dev, "%s:%d texture invalid format %d\n", 1728 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1613 __func__, __LINE__, format); 1729 __func__, __LINE__, format);
1614 return -EINVAL; 1730 return -EINVAL;
1615 } 1731 }
1616 1732
1617 /* pitch in texels */
1618 pitch = (G_038000_PITCH(word0) + 1) * 8;
1619 array_check.array_mode = G_038000_TILE_MODE(word0);
1620 array_check.group_size = track->group_size;
1621 array_check.nbanks = track->nbanks;
1622 array_check.npipes = track->npipes;
1623 array_check.nsamples = 1;
1624 array_check.blocksize = r600_fmt_get_blocksize(format);
1625 if (r600_get_array_mode_alignment(&array_check, 1733 if (r600_get_array_mode_alignment(&array_check,
1626 &pitch_align, &height_align, &depth_align, &base_align)) { 1734 &pitch_align, &height_align, &depth_align, &base_align)) {
1627 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", 1735 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
@@ -1647,24 +1755,17 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1647 return -EINVAL; 1755 return -EINVAL;
1648 } 1756 }
1649 1757
1650 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1651 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1652
1653 word0 = radeon_get_ib_value(p, idx + 4);
1654 word1 = radeon_get_ib_value(p, idx + 5);
1655 blevel = G_038010_BASE_LEVEL(word0);
1656 llevel = G_038014_LAST_LEVEL(word1);
1657 if (blevel > llevel) { 1758 if (blevel > llevel) {
1658 dev_warn(p->dev, "texture blevel %d > llevel %d\n", 1759 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1659 blevel, llevel); 1760 blevel, llevel);
1660 } 1761 }
1661 if (array == 1) { 1762 if (is_array) {
1662 barray = G_038014_BASE_ARRAY(word1); 1763 barray = G_038014_BASE_ARRAY(word5);
1663 larray = G_038014_LAST_ARRAY(word1); 1764 larray = G_038014_LAST_ARRAY(word5);
1664 1765
1665 nfaces = larray - barray + 1; 1766 nfaces = larray - barray + 1;
1666 } 1767 }
1667 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format, 1768 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
1668 pitch_align, height_align, base_align, 1769 pitch_align, height_align, base_align,
1669 &l0_size, &mipmap_size); 1770 &l0_size, &mipmap_size);
1670 /* using get ib will give us the offset into the texture bo */ 1771 /* using get ib will give us the offset into the texture bo */
@@ -1677,7 +1778,6 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1677 return -EINVAL; 1778 return -EINVAL;
1678 } 1779 }
1679 /* using get ib will give us the offset into the mipmap bo */ 1780 /* using get ib will give us the offset into the mipmap bo */
1680 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1681 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { 1781 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1682 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1782 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1683 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ 1783 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 4b116ae75fc2..fa6f37099ba9 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -66,6 +66,14 @@
66#define CC_RB_BACKEND_DISABLE 0x98F4 66#define CC_RB_BACKEND_DISABLE 0x98F4
67#define BACKEND_DISABLE(x) ((x) << 16) 67#define BACKEND_DISABLE(x) ((x) << 16)
68 68
69#define R_028808_CB_COLOR_CONTROL 0x28808
70#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
71#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
72#define C_028808_SPECIAL_OP 0xFFFFFF8F
73#define V_028808_SPECIAL_NORMAL 0x00
74#define V_028808_SPECIAL_DISABLE 0x01
75#define V_028808_SPECIAL_RESOLVE_BOX 0x07
76
69#define CB_COLOR0_BASE 0x28040 77#define CB_COLOR0_BASE 0x28040
70#define CB_COLOR1_BASE 0x28044 78#define CB_COLOR1_BASE 0x28044
71#define CB_COLOR2_BASE 0x28048 79#define CB_COLOR2_BASE 0x28048
@@ -92,6 +100,20 @@
92#define R_028094_CB_COLOR5_VIEW 0x028094 100#define R_028094_CB_COLOR5_VIEW 0x028094
93#define R_028098_CB_COLOR6_VIEW 0x028098 101#define R_028098_CB_COLOR6_VIEW 0x028098
94#define R_02809C_CB_COLOR7_VIEW 0x02809C 102#define R_02809C_CB_COLOR7_VIEW 0x02809C
103#define R_028100_CB_COLOR0_MASK 0x028100
104#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
105#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
106#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
107#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
108#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
109#define C_028100_FMASK_TILE_MAX 0x00000FFF
110#define R_028104_CB_COLOR1_MASK 0x028104
111#define R_028108_CB_COLOR2_MASK 0x028108
112#define R_02810C_CB_COLOR3_MASK 0x02810C
113#define R_028110_CB_COLOR4_MASK 0x028110
114#define R_028114_CB_COLOR5_MASK 0x028114
115#define R_028118_CB_COLOR6_MASK 0x028118
116#define R_02811C_CB_COLOR7_MASK 0x02811C
95#define CB_COLOR0_INFO 0x280a0 117#define CB_COLOR0_INFO 0x280a0
96# define CB_FORMAT(x) ((x) << 2) 118# define CB_FORMAT(x) ((x) << 2)
97# define CB_ARRAY_MODE(x) ((x) << 8) 119# define CB_ARRAY_MODE(x) ((x) << 8)
@@ -602,6 +624,9 @@
602#define RLC_HB_WPTR 0x3f1c 624#define RLC_HB_WPTR 0x3f1c
603#define RLC_HB_WPTR_LSB_ADDR 0x3f14 625#define RLC_HB_WPTR_LSB_ADDR 0x3f14
604#define RLC_HB_WPTR_MSB_ADDR 0x3f18 626#define RLC_HB_WPTR_MSB_ADDR 0x3f18
627#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
628#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
629#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
605#define RLC_MC_CNTL 0x3f44 630#define RLC_MC_CNTL 0x3f44
606#define RLC_UCODE_CNTL 0x3f48 631#define RLC_UCODE_CNTL 0x3f48
607#define RLC_UCODE_ADDR 0x3f2c 632#define RLC_UCODE_ADDR 0x3f2c
@@ -1397,6 +1422,9 @@
1397#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1422#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1398#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1423#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1399#define C_0280A0_TILE_MODE 0xFFF3FFFF 1424#define C_0280A0_TILE_MODE 0xFFF3FFFF
1425#define V_0280A0_TILE_DISABLE 0
1426#define V_0280A0_CLEAR_ENABLE 1
1427#define V_0280A0_FRAG_ENABLE 2
1400#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1428#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1401#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1429#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1402#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1430#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5431af292408..59a15315ae9f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -142,21 +142,6 @@ struct radeon_device;
142/* 142/*
143 * BIOS. 143 * BIOS.
144 */ 144 */
145#define ATRM_BIOS_PAGE 4096
146
147#if defined(CONFIG_VGA_SWITCHEROO)
148bool radeon_atrm_supported(struct pci_dev *pdev);
149int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
150#else
151static inline bool radeon_atrm_supported(struct pci_dev *pdev)
152{
153 return false;
154}
155
156static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
157 return -EINVAL;
158}
159#endif
160bool radeon_get_bios(struct radeon_device *rdev); 145bool radeon_get_bios(struct radeon_device *rdev);
161 146
162/* 147/*
@@ -300,6 +285,7 @@ struct radeon_bo_va {
300 uint64_t soffset; 285 uint64_t soffset;
301 uint64_t eoffset; 286 uint64_t eoffset;
302 uint32_t flags; 287 uint32_t flags;
288 struct radeon_fence *fence;
303 bool valid; 289 bool valid;
304}; 290};
305 291
@@ -1533,6 +1519,7 @@ struct radeon_device {
1533 unsigned debugfs_count; 1519 unsigned debugfs_count;
1534 /* virtual memory */ 1520 /* virtual memory */
1535 struct radeon_vm_manager vm_manager; 1521 struct radeon_vm_manager vm_manager;
1522 struct mutex gpu_clock_mutex;
1536}; 1523};
1537 1524
1538int radeon_device_init(struct radeon_device *rdev, 1525int radeon_device_init(struct radeon_device *rdev,
@@ -1733,11 +1720,11 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1733#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1720#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1734#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1721#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1735#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1722#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1736#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc)) 1723#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1737#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base)) 1724#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1738#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc)) 1725#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1739#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc)) 1726#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1740#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev)) 1727#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1741 1728
1742/* Common functions */ 1729/* Common functions */
1743/* AGP */ 1730/* AGP */
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index f4af24310438..18c38d14c8cd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -255,13 +255,10 @@ extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
255 * rv515 255 * rv515
256 */ 256 */
257struct rv515_mc_save { 257struct rv515_mc_save {
258 u32 d1vga_control;
259 u32 d2vga_control;
260 u32 vga_render_control; 258 u32 vga_render_control;
261 u32 vga_hdp_control; 259 u32 vga_hdp_control;
262 u32 d1crtc_control;
263 u32 d2crtc_control;
264}; 260};
261
265int rv515_init(struct radeon_device *rdev); 262int rv515_init(struct radeon_device *rdev);
266void rv515_fini(struct radeon_device *rdev); 263void rv515_fini(struct radeon_device *rdev);
267uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 264uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
@@ -371,6 +368,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
371 unsigned num_gpu_pages, 368 unsigned num_gpu_pages,
372 struct radeon_sa_bo *vb); 369 struct radeon_sa_bo *vb);
373int r600_mc_wait_for_idle(struct radeon_device *rdev); 370int r600_mc_wait_for_idle(struct radeon_device *rdev);
371uint64_t r600_get_gpu_clock(struct radeon_device *rdev);
374 372
375/* 373/*
376 * rv770,rv730,rv710,rv740 374 * rv770,rv730,rv710,rv740
@@ -389,11 +387,10 @@ void r700_cp_fini(struct radeon_device *rdev);
389 * evergreen 387 * evergreen
390 */ 388 */
391struct evergreen_mc_save { 389struct evergreen_mc_save {
392 u32 vga_control[6];
393 u32 vga_render_control; 390 u32 vga_render_control;
394 u32 vga_hdp_control; 391 u32 vga_hdp_control;
395 u32 crtc_control[6];
396}; 392};
393
397void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 394void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
398int evergreen_init(struct radeon_device *rdev); 395int evergreen_init(struct radeon_device *rdev);
399void evergreen_fini(struct radeon_device *rdev); 396void evergreen_fini(struct radeon_device *rdev);
@@ -472,5 +469,6 @@ int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
472void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); 469void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
473void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm); 470void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
474int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 471int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
472uint64_t si_get_gpu_clock(struct radeon_device *rdev);
475 473
476#endif 474#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index b1e3820df363..d67d4f3eb6f4 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -452,7 +452,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
452 } 452 }
453 453
454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
455 if ((dev->pdev->device == 0x9802) && 455 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
456 (dev->pdev->subsystem_vendor == 0x1734) && 456 (dev->pdev->subsystem_vendor == 0x1734) &&
457 (dev->pdev->subsystem_device == 0x11bd)) { 457 (dev->pdev->subsystem_device == 0x11bd)) {
458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
@@ -1263,6 +1263,8 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1263union igp_info { 1263union igp_info {
1264 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1264 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1265 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1266 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1267 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1266}; 1268};
1267 1269
1268bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1270bool radeon_atombios_sideport_present(struct radeon_device *rdev)
@@ -1390,27 +1392,50 @@ static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1390 struct radeon_mode_info *mode_info = &rdev->mode_info; 1392 struct radeon_mode_info *mode_info = &rdev->mode_info;
1391 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1393 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1392 u16 data_offset, size; 1394 u16 data_offset, size;
1393 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info; 1395 union igp_info *igp_info;
1394 u8 frev, crev; 1396 u8 frev, crev;
1395 u16 percentage = 0, rate = 0; 1397 u16 percentage = 0, rate = 0;
1396 1398
1397 /* get any igp specific overrides */ 1399 /* get any igp specific overrides */
1398 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1400 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1399 &frev, &crev, &data_offset)) { 1401 &frev, &crev, &data_offset)) {
1400 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *) 1402 igp_info = (union igp_info *)
1401 (mode_info->atom_context->bios + data_offset); 1403 (mode_info->atom_context->bios + data_offset);
1402 switch (id) { 1404 switch (crev) {
1403 case ASIC_INTERNAL_SS_ON_TMDS: 1405 case 6:
1404 percentage = le16_to_cpu(igp_info->usDVISSPercentage); 1406 switch (id) {
1405 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz); 1407 case ASIC_INTERNAL_SS_ON_TMDS:
1408 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1409 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1410 break;
1411 case ASIC_INTERNAL_SS_ON_HDMI:
1412 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1413 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1414 break;
1415 case ASIC_INTERNAL_SS_ON_LVDS:
1416 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1417 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1418 break;
1419 }
1406 break; 1420 break;
1407 case ASIC_INTERNAL_SS_ON_HDMI: 1421 case 7:
1408 percentage = le16_to_cpu(igp_info->usHDMISSPercentage); 1422 switch (id) {
1409 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz); 1423 case ASIC_INTERNAL_SS_ON_TMDS:
1424 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1425 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1426 break;
1427 case ASIC_INTERNAL_SS_ON_HDMI:
1428 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1429 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1430 break;
1431 case ASIC_INTERNAL_SS_ON_LVDS:
1432 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1433 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1434 break;
1435 }
1410 break; 1436 break;
1411 case ASIC_INTERNAL_SS_ON_LVDS: 1437 default:
1412 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage); 1438 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1413 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1414 break; 1439 break;
1415 } 1440 }
1416 if (percentage) 1441 if (percentage)
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 98724fcb0088..2a2cf0b88a28 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -30,57 +30,8 @@ static struct radeon_atpx_priv {
30 /* handle for device - and atpx */ 30 /* handle for device - and atpx */
31 acpi_handle dhandle; 31 acpi_handle dhandle;
32 acpi_handle atpx_handle; 32 acpi_handle atpx_handle;
33 acpi_handle atrm_handle;
34} radeon_atpx_priv; 33} radeon_atpx_priv;
35 34
36/* retrieve the ROM in 4k blocks */
37static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
38 int offset, int len)
39{
40 acpi_status status;
41 union acpi_object atrm_arg_elements[2], *obj;
42 struct acpi_object_list atrm_arg;
43 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
44
45 atrm_arg.count = 2;
46 atrm_arg.pointer = &atrm_arg_elements[0];
47
48 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
49 atrm_arg_elements[0].integer.value = offset;
50
51 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
52 atrm_arg_elements[1].integer.value = len;
53
54 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
55 if (ACPI_FAILURE(status)) {
56 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
57 return -ENODEV;
58 }
59
60 obj = (union acpi_object *)buffer.pointer;
61 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
62 len = obj->buffer.length;
63 kfree(buffer.pointer);
64 return len;
65}
66
67bool radeon_atrm_supported(struct pci_dev *pdev)
68{
69 /* get the discrete ROM only via ATRM */
70 if (!radeon_atpx_priv.atpx_detected)
71 return false;
72
73 if (radeon_atpx_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev))
74 return false;
75 return true;
76}
77
78
79int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len)
80{
81 return radeon_atrm_call(radeon_atpx_priv.atrm_handle, bios, offset, len);
82}
83
84static int radeon_atpx_get_version(acpi_handle handle) 35static int radeon_atpx_get_version(acpi_handle handle)
85{ 36{
86 acpi_status status; 37 acpi_status status;
@@ -198,7 +149,7 @@ static int radeon_atpx_power_state(enum vga_switcheroo_client_id id,
198 149
199static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev) 150static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
200{ 151{
201 acpi_handle dhandle, atpx_handle, atrm_handle; 152 acpi_handle dhandle, atpx_handle;
202 acpi_status status; 153 acpi_status status;
203 154
204 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev); 155 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
@@ -209,13 +160,8 @@ static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
209 if (ACPI_FAILURE(status)) 160 if (ACPI_FAILURE(status))
210 return false; 161 return false;
211 162
212 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
213 if (ACPI_FAILURE(status))
214 return false;
215
216 radeon_atpx_priv.dhandle = dhandle; 163 radeon_atpx_priv.dhandle = dhandle;
217 radeon_atpx_priv.atpx_handle = atpx_handle; 164 radeon_atpx_priv.atpx_handle = atpx_handle;
218 radeon_atpx_priv.atrm_handle = atrm_handle;
219 return true; 165 return true;
220} 166}
221 167
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 501f4881e5aa..d306cc8fdeaa 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -32,6 +32,7 @@
32 32
33#include <linux/vga_switcheroo.h> 33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h> 34#include <linux/slab.h>
35#include <linux/acpi.h>
35/* 36/*
36 * BIOS. 37 * BIOS.
37 */ 38 */
@@ -98,16 +99,81 @@ static bool radeon_read_bios(struct radeon_device *rdev)
98 return true; 99 return true;
99} 100}
100 101
102#ifdef CONFIG_ACPI
101/* ATRM is used to get the BIOS on the discrete cards in 103/* ATRM is used to get the BIOS on the discrete cards in
102 * dual-gpu systems. 104 * dual-gpu systems.
103 */ 105 */
106/* retrieve the ROM in 4k blocks */
107#define ATRM_BIOS_PAGE 4096
108/**
109 * radeon_atrm_call - fetch a chunk of the vbios
110 *
111 * @atrm_handle: acpi ATRM handle
112 * @bios: vbios image pointer
113 * @offset: offset of vbios image data to fetch
114 * @len: length of vbios image data to fetch
115 *
116 * Executes ATRM to fetch a chunk of the discrete
117 * vbios image on PX systems (all asics).
118 * Returns the length of the buffer fetched.
119 */
120static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
121 int offset, int len)
122{
123 acpi_status status;
124 union acpi_object atrm_arg_elements[2], *obj;
125 struct acpi_object_list atrm_arg;
126 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
127
128 atrm_arg.count = 2;
129 atrm_arg.pointer = &atrm_arg_elements[0];
130
131 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
132 atrm_arg_elements[0].integer.value = offset;
133
134 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
135 atrm_arg_elements[1].integer.value = len;
136
137 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
138 if (ACPI_FAILURE(status)) {
139 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
140 return -ENODEV;
141 }
142
143 obj = (union acpi_object *)buffer.pointer;
144 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
145 len = obj->buffer.length;
146 kfree(buffer.pointer);
147 return len;
148}
149
104static bool radeon_atrm_get_bios(struct radeon_device *rdev) 150static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{ 151{
106 int ret; 152 int ret;
107 int size = 256 * 1024; 153 int size = 256 * 1024;
108 int i; 154 int i;
155 struct pci_dev *pdev = NULL;
156 acpi_handle dhandle, atrm_handle;
157 acpi_status status;
158 bool found = false;
159
160 /* ATRM is for the discrete card only */
161 if (rdev->flags & RADEON_IS_IGP)
162 return false;
163
164 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
165 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
166 if (!dhandle)
167 continue;
168
169 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
170 if (!ACPI_FAILURE(status)) {
171 found = true;
172 break;
173 }
174 }
109 175
110 if (!radeon_atrm_supported(rdev->pdev)) 176 if (!found)
111 return false; 177 return false;
112 178
113 rdev->bios = kmalloc(size, GFP_KERNEL); 179 rdev->bios = kmalloc(size, GFP_KERNEL);
@@ -117,9 +183,10 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
117 } 183 }
118 184
119 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 185 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
120 ret = radeon_atrm_get_bios_chunk(rdev->bios, 186 ret = radeon_atrm_call(atrm_handle,
121 (i * ATRM_BIOS_PAGE), 187 rdev->bios,
122 ATRM_BIOS_PAGE); 188 (i * ATRM_BIOS_PAGE),
189 ATRM_BIOS_PAGE);
123 if (ret < ATRM_BIOS_PAGE) 190 if (ret < ATRM_BIOS_PAGE)
124 break; 191 break;
125 } 192 }
@@ -130,6 +197,12 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
130 } 197 }
131 return true; 198 return true;
132} 199}
200#else
201static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
202{
203 return false;
204}
205#endif
133 206
134static bool ni_read_disabled_bios(struct radeon_device *rdev) 207static bool ni_read_disabled_bios(struct radeon_device *rdev)
135{ 208{
@@ -476,6 +549,61 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
476 return legacy_read_disabled_bios(rdev); 549 return legacy_read_disabled_bios(rdev);
477} 550}
478 551
552#ifdef CONFIG_ACPI
553static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
554{
555 bool ret = false;
556 struct acpi_table_header *hdr;
557 acpi_size tbl_size;
558 UEFI_ACPI_VFCT *vfct;
559 GOP_VBIOS_CONTENT *vbios;
560 VFCT_IMAGE_HEADER *vhdr;
561
562 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
563 return false;
564 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
565 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
566 goto out_unmap;
567 }
568
569 vfct = (UEFI_ACPI_VFCT *)hdr;
570 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
571 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
572 goto out_unmap;
573 }
574
575 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
576 vhdr = &vbios->VbiosHeader;
577 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
578 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
579 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
580
581 if (vhdr->PCIBus != rdev->pdev->bus->number ||
582 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
583 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
584 vhdr->VendorID != rdev->pdev->vendor ||
585 vhdr->DeviceID != rdev->pdev->device) {
586 DRM_INFO("ACPI VFCT table is not for this card\n");
587 goto out_unmap;
588 };
589
590 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
591 DRM_ERROR("ACPI VFCT image truncated\n");
592 goto out_unmap;
593 }
594
595 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
596 ret = !!rdev->bios;
597
598out_unmap:
599 return ret;
600}
601#else
602static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
603{
604 return false;
605}
606#endif
479 607
480bool radeon_get_bios(struct radeon_device *rdev) 608bool radeon_get_bios(struct radeon_device *rdev)
481{ 609{
@@ -484,6 +612,8 @@ bool radeon_get_bios(struct radeon_device *rdev)
484 612
485 r = radeon_atrm_get_bios(rdev); 613 r = radeon_atrm_get_bios(rdev);
486 if (r == false) 614 if (r == false)
615 r = radeon_acpi_vfct_bios(rdev);
616 if (r == false)
487 r = igp_read_bios_from_vram(rdev); 617 r = igp_read_bios_from_vram(rdev);
488 if (r == false) 618 if (r == false)
489 r = radeon_read_bios(rdev); 619 r = radeon_read_bios(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 576f4f6919f2..f75247d42ffd 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -719,6 +719,34 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
719 return i2c; 719 return i2c;
720} 720}
721 721
722static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
723{
724 struct drm_device *dev = rdev->ddev;
725 struct radeon_i2c_bus_rec i2c;
726 u16 offset;
727 u8 id, blocks, clk, data;
728 int i;
729
730 i2c.valid = false;
731
732 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
733 if (offset) {
734 blocks = RBIOS8(offset + 2);
735 for (i = 0; i < blocks; i++) {
736 id = RBIOS8(offset + 3 + (i * 5) + 0);
737 if (id == 136) {
738 clk = RBIOS8(offset + 3 + (i * 5) + 3);
739 data = RBIOS8(offset + 3 + (i * 5) + 4);
740 /* gpiopad */
741 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
742 (1 << clk), (1 << data));
743 break;
744 }
745 }
746 }
747 return i2c;
748}
749
722void radeon_combios_i2c_init(struct radeon_device *rdev) 750void radeon_combios_i2c_init(struct radeon_device *rdev)
723{ 751{
724 struct drm_device *dev = rdev->ddev; 752 struct drm_device *dev = rdev->ddev;
@@ -755,30 +783,14 @@ void radeon_combios_i2c_init(struct radeon_device *rdev)
755 } else if (rdev->family == CHIP_RS300 || 783 } else if (rdev->family == CHIP_RS300 ||
756 rdev->family == CHIP_RS400 || 784 rdev->family == CHIP_RS400 ||
757 rdev->family == CHIP_RS480) { 785 rdev->family == CHIP_RS480) {
758 u16 offset;
759 u8 id, blocks, clk, data;
760 int i;
761
762 /* 0x68 */ 786 /* 0x68 */
763 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 787 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
764 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 788 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
765 789
766 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 790 /* gpiopad */
767 if (offset) { 791 i2c = radeon_combios_get_i2c_info_from_table(rdev);
768 blocks = RBIOS8(offset + 2); 792 if (i2c.valid)
769 for (i = 0; i < blocks; i++) { 793 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
770 id = RBIOS8(offset + 3 + (i * 5) + 0);
771 if (id == 136) {
772 clk = RBIOS8(offset + 3 + (i * 5) + 3);
773 data = RBIOS8(offset + 3 + (i * 5) + 4);
774 /* gpiopad */
775 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
776 (1 << clk), (1 << data));
777 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
778 break;
779 }
780 }
781 }
782 } else if ((rdev->family == CHIP_R200) || 794 } else if ((rdev->family == CHIP_R200) ||
783 (rdev->family >= CHIP_R300)) { 795 (rdev->family >= CHIP_R300)) {
784 /* 0x68 */ 796 /* 0x68 */
@@ -2321,7 +2333,10 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2321 connector = (tmp >> 12) & 0xf; 2333 connector = (tmp >> 12) & 0xf;
2322 2334
2323 ddc_type = (tmp >> 8) & 0xf; 2335 ddc_type = (tmp >> 8) & 0xf;
2324 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2336 if (ddc_type == 5)
2337 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2338 else
2339 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2325 2340
2326 switch (connector) { 2341 switch (connector) {
2327 case CONNECTOR_PROPRIETARY_LEGACY: 2342 case CONNECTOR_PROPRIETARY_LEGACY:
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 8a4c49ef0cc4..b4a0db24f4dd 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -278,6 +278,30 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
278 return 0; 278 return 0;
279} 279}
280 280
281static void radeon_bo_vm_fence_va(struct radeon_cs_parser *parser,
282 struct radeon_fence *fence)
283{
284 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
285 struct radeon_vm *vm = &fpriv->vm;
286 struct radeon_bo_list *lobj;
287
288 if (parser->chunk_ib_idx == -1) {
289 return;
290 }
291 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) {
292 return;
293 }
294
295 list_for_each_entry(lobj, &parser->validated, tv.head) {
296 struct radeon_bo_va *bo_va;
297 struct radeon_bo *rbo = lobj->bo;
298
299 bo_va = radeon_bo_va(rbo, vm);
300 radeon_fence_unref(&bo_va->fence);
301 bo_va->fence = radeon_fence_ref(fence);
302 }
303}
304
281/** 305/**
282 * cs_parser_fini() - clean parser states 306 * cs_parser_fini() - clean parser states
283 * @parser: parser structure holding parsing context. 307 * @parser: parser structure holding parsing context.
@@ -290,11 +314,14 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
290{ 314{
291 unsigned i; 315 unsigned i;
292 316
293 if (!error) 317 if (!error) {
318 /* fence all bo va before ttm_eu_fence_buffer_objects so bo are still reserved */
319 radeon_bo_vm_fence_va(parser, parser->ib.fence);
294 ttm_eu_fence_buffer_objects(&parser->validated, 320 ttm_eu_fence_buffer_objects(&parser->validated,
295 parser->ib.fence); 321 parser->ib.fence);
296 else 322 } else {
297 ttm_eu_backoff_reservation(&parser->validated); 323 ttm_eu_backoff_reservation(&parser->validated);
324 }
298 325
299 if (parser->relocs != NULL) { 326 if (parser->relocs != NULL) {
300 for (i = 0; i < parser->nrelocs; i++) { 327 for (i = 0; i < parser->nrelocs; i++) {
@@ -388,7 +415,6 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
388 415
389 if (parser->chunk_ib_idx == -1) 416 if (parser->chunk_ib_idx == -1)
390 return 0; 417 return 0;
391
392 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 418 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
393 return 0; 419 return 0;
394 420
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 711e95ad39bf..8794744cdf1a 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -67,7 +67,8 @@ static void radeon_hide_cursor(struct drm_crtc *crtc)
67 67
68 if (ASIC_IS_DCE4(rdev)) { 68 if (ASIC_IS_DCE4(rdev)) {
69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
70 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); 70 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
71 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
71 } else if (ASIC_IS_AVIVO(rdev)) { 72 } else if (ASIC_IS_AVIVO(rdev)) {
72 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 73 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
73 WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 74 WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
@@ -94,7 +95,8 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
94 if (ASIC_IS_DCE4(rdev)) { 95 if (ASIC_IS_DCE4(rdev)) {
95 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 96 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
96 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 97 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
97 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); 98 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
99 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
98 } else if (ASIC_IS_AVIVO(rdev)) { 100 } else if (ASIC_IS_AVIVO(rdev)) {
99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 101 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
100 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 102 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 742af8244e89..7a3daebd732d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1009,6 +1009,7 @@ int radeon_device_init(struct radeon_device *rdev,
1009 atomic_set(&rdev->ih.lock, 0); 1009 atomic_set(&rdev->ih.lock, 0);
1010 mutex_init(&rdev->gem.mutex); 1010 mutex_init(&rdev->gem.mutex);
1011 mutex_init(&rdev->pm.mutex); 1011 mutex_init(&rdev->pm.mutex);
1012 mutex_init(&rdev->gpu_clock_mutex);
1012 init_rwsem(&rdev->pm.mclk_lock); 1013 init_rwsem(&rdev->pm.mclk_lock);
1013 init_rwsem(&rdev->exclusive_lock); 1014 init_rwsem(&rdev->exclusive_lock);
1014 init_waitqueue_head(&rdev->irq.vblank_queue); 1015 init_waitqueue_head(&rdev->irq.vblank_queue);
@@ -1050,7 +1051,7 @@ int radeon_device_init(struct radeon_device *rdev,
1050 if (rdev->flags & RADEON_IS_AGP) 1051 if (rdev->flags & RADEON_IS_AGP)
1051 rdev->need_dma32 = true; 1052 rdev->need_dma32 = true;
1052 if ((rdev->flags & RADEON_IS_PCI) && 1053 if ((rdev->flags & RADEON_IS_PCI) &&
1053 (rdev->family < CHIP_RS400)) 1054 (rdev->family <= CHIP_RS740))
1054 rdev->need_dma32 = true; 1055 rdev->need_dma32 = true;
1055 1056
1056 dma_bits = rdev->need_dma32 ? 32 : 40; 1057 dma_bits = rdev->need_dma32 ? 32 : 40;
@@ -1345,12 +1346,15 @@ retry:
1345 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1346 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1346 radeon_ring_restore(rdev, &rdev->ring[i], 1347 radeon_ring_restore(rdev, &rdev->ring[i],
1347 ring_sizes[i], ring_data[i]); 1348 ring_sizes[i], ring_data[i]);
1349 ring_sizes[i] = 0;
1350 ring_data[i] = NULL;
1348 } 1351 }
1349 1352
1350 r = radeon_ib_ring_tests(rdev); 1353 r = radeon_ib_ring_tests(rdev);
1351 if (r) { 1354 if (r) {
1352 dev_err(rdev->dev, "ib ring test failed (%d).\n", r); 1355 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1353 if (saved) { 1356 if (saved) {
1357 saved = false;
1354 radeon_suspend(rdev); 1358 radeon_suspend(rdev);
1355 goto retry; 1359 goto retry;
1356 } 1360 }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index dcea6f01ae4e..8c593ea82c41 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -59,9 +59,14 @@
59 * 2.15.0 - add max_pipes query 59 * 2.15.0 - add max_pipes query
60 * 2.16.0 - fix evergreen 2D tiled surface calculation 60 * 2.16.0 - fix evergreen 2D tiled surface calculation
61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
62 * 2.18.0 - r600-eg: allow "invalid" DB formats
63 * 2.19.0 - r600-eg: MSAA textures
64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
65 * 2.21.0 - r600-r700: FMASK and CMASK
66 * 2.22.0 - r600 only: RESOLVE_BOX allowed
62 */ 67 */
63#define KMS_DRIVER_MAJOR 2 68#define KMS_DRIVER_MAJOR 2
64#define KMS_DRIVER_MINOR 17 69#define KMS_DRIVER_MINOR 22
65#define KMS_DRIVER_PATCHLEVEL 0 70#define KMS_DRIVER_PATCHLEVEL 0
66int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 71int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
67int radeon_driver_unload_kms(struct drm_device *dev); 72int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index b3720054614d..bb3b7fe05ccd 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -814,7 +814,7 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
814 return -EINVAL; 814 return -EINVAL;
815 } 815 }
816 816
817 if (bo_va->valid) 817 if (bo_va->valid && mem)
818 return 0; 818 return 0;
819 819
820 ngpu_pages = radeon_bo_ngpu_pages(bo); 820 ngpu_pages = radeon_bo_ngpu_pages(bo);
@@ -859,11 +859,27 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
859 struct radeon_bo *bo) 859 struct radeon_bo *bo)
860{ 860{
861 struct radeon_bo_va *bo_va; 861 struct radeon_bo_va *bo_va;
862 int r;
862 863
863 bo_va = radeon_bo_va(bo, vm); 864 bo_va = radeon_bo_va(bo, vm);
864 if (bo_va == NULL) 865 if (bo_va == NULL)
865 return 0; 866 return 0;
866 867
868 /* wait for va use to end */
869 while (bo_va->fence) {
870 r = radeon_fence_wait(bo_va->fence, false);
871 if (r) {
872 DRM_ERROR("error while waiting for fence: %d\n", r);
873 }
874 if (r == -EDEADLK) {
875 r = radeon_gpu_reset(rdev);
876 if (!r)
877 continue;
878 }
879 break;
880 }
881 radeon_fence_unref(&bo_va->fence);
882
867 mutex_lock(&rdev->vm_manager.lock); 883 mutex_lock(&rdev->vm_manager.lock);
868 mutex_lock(&vm->mutex); 884 mutex_lock(&vm->mutex);
869 radeon_vm_bo_update_pte(rdev, vm, bo, NULL); 885 radeon_vm_bo_update_pte(rdev, vm, bo, NULL);
@@ -934,7 +950,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
934} 950}
935 951
936/** 952/**
937 * radeon_vm_init - tear down a vm instance 953 * radeon_vm_fini - tear down a vm instance
938 * 954 *
939 * @rdev: radeon_device pointer 955 * @rdev: radeon_device pointer
940 * @vm: requested vm 956 * @vm: requested vm
@@ -952,12 +968,15 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
952 radeon_vm_unbind_locked(rdev, vm); 968 radeon_vm_unbind_locked(rdev, vm);
953 mutex_unlock(&rdev->vm_manager.lock); 969 mutex_unlock(&rdev->vm_manager.lock);
954 970
955 /* remove all bo */ 971 /* remove all bo at this point non are busy any more because unbind
972 * waited for the last vm fence to signal
973 */
956 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 974 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
957 if (!r) { 975 if (!r) {
958 bo_va = radeon_bo_va(rdev->ring_tmp_bo.bo, vm); 976 bo_va = radeon_bo_va(rdev->ring_tmp_bo.bo, vm);
959 list_del_init(&bo_va->bo_list); 977 list_del_init(&bo_va->bo_list);
960 list_del_init(&bo_va->vm_list); 978 list_del_init(&bo_va->vm_list);
979 radeon_fence_unref(&bo_va->fence);
961 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 980 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
962 kfree(bo_va); 981 kfree(bo_va);
963 } 982 }
@@ -969,6 +988,7 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
969 r = radeon_bo_reserve(bo_va->bo, false); 988 r = radeon_bo_reserve(bo_va->bo, false);
970 if (!r) { 989 if (!r) {
971 list_del_init(&bo_va->bo_list); 990 list_del_init(&bo_va->bo_list);
991 radeon_fence_unref(&bo_va->fence);
972 radeon_bo_unreserve(bo_va->bo); 992 radeon_bo_unreserve(bo_va->bo);
973 kfree(bo_va); 993 kfree(bo_va);
974 } 994 }
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 84d045245739..1b57b0058ad6 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -134,25 +134,16 @@ void radeon_gem_object_close(struct drm_gem_object *obj,
134 struct radeon_device *rdev = rbo->rdev; 134 struct radeon_device *rdev = rbo->rdev;
135 struct radeon_fpriv *fpriv = file_priv->driver_priv; 135 struct radeon_fpriv *fpriv = file_priv->driver_priv;
136 struct radeon_vm *vm = &fpriv->vm; 136 struct radeon_vm *vm = &fpriv->vm;
137 struct radeon_bo_va *bo_va, *tmp;
138 137
139 if (rdev->family < CHIP_CAYMAN) { 138 if (rdev->family < CHIP_CAYMAN) {
140 return; 139 return;
141 } 140 }
142 141
143 if (radeon_bo_reserve(rbo, false)) { 142 if (radeon_bo_reserve(rbo, false)) {
143 dev_err(rdev->dev, "leaking bo va because we fail to reserve bo\n");
144 return; 144 return;
145 } 145 }
146 list_for_each_entry_safe(bo_va, tmp, &rbo->va, bo_list) { 146 radeon_vm_bo_rmv(rdev, vm, rbo);
147 if (bo_va->vm == vm) {
148 /* remove from this vm address space */
149 mutex_lock(&vm->mutex);
150 list_del(&bo_va->vm_list);
151 mutex_unlock(&vm->mutex);
152 list_del(&bo_va->bo_list);
153 kfree(bo_va);
154 }
155 }
156 radeon_bo_unreserve(rbo); 147 radeon_bo_unreserve(rbo);
157} 148}
158 149
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 1d73f16b5d97..414b4acf6947 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -29,6 +29,7 @@
29#include "drm_sarea.h" 29#include "drm_sarea.h"
30#include "radeon.h" 30#include "radeon.h"
31#include "radeon_drm.h" 31#include "radeon_drm.h"
32#include "radeon_asic.h"
32 33
33#include <linux/vga_switcheroo.h> 34#include <linux/vga_switcheroo.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
@@ -167,17 +168,39 @@ static void radeon_set_filp_rights(struct drm_device *dev,
167int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 168int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
168{ 169{
169 struct radeon_device *rdev = dev->dev_private; 170 struct radeon_device *rdev = dev->dev_private;
170 struct drm_radeon_info *info; 171 struct drm_radeon_info *info = data;
171 struct radeon_mode_info *minfo = &rdev->mode_info; 172 struct radeon_mode_info *minfo = &rdev->mode_info;
172 uint32_t *value_ptr; 173 uint32_t value, *value_ptr;
173 uint32_t value; 174 uint64_t value64, *value_ptr64;
174 struct drm_crtc *crtc; 175 struct drm_crtc *crtc;
175 int i, found; 176 int i, found;
176 177
177 info = data; 178 /* TIMESTAMP is a 64-bit value, needs special handling. */
179 if (info->request == RADEON_INFO_TIMESTAMP) {
180 if (rdev->family >= CHIP_R600) {
181 value_ptr64 = (uint64_t*)((unsigned long)info->value);
182 if (rdev->family >= CHIP_TAHITI) {
183 value64 = si_get_gpu_clock(rdev);
184 } else {
185 value64 = r600_get_gpu_clock(rdev);
186 }
187
188 if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
189 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
190 return -EFAULT;
191 }
192 return 0;
193 } else {
194 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
195 return -EINVAL;
196 }
197 }
198
178 value_ptr = (uint32_t *)((unsigned long)info->value); 199 value_ptr = (uint32_t *)((unsigned long)info->value);
179 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) 200 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) {
201 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
180 return -EFAULT; 202 return -EFAULT;
203 }
181 204
182 switch (info->request) { 205 switch (info->request) {
183 case RADEON_INFO_DEVICE_ID: 206 case RADEON_INFO_DEVICE_ID:
@@ -337,7 +360,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
337 return -EINVAL; 360 return -EINVAL;
338 } 361 }
339 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { 362 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
340 DRM_ERROR("copy_to_user\n"); 363 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
341 return -EFAULT; 364 return -EFAULT;
342 } 365 }
343 return 0; 366 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index d5fd615897ec..94b4a1c12893 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -1025,9 +1025,11 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1025 1025
1026static void radeon_crtc_prepare(struct drm_crtc *crtc) 1026static void radeon_crtc_prepare(struct drm_crtc *crtc)
1027{ 1027{
1028 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1028 struct drm_device *dev = crtc->dev; 1029 struct drm_device *dev = crtc->dev;
1029 struct drm_crtc *crtci; 1030 struct drm_crtc *crtci;
1030 1031
1032 radeon_crtc->in_mode_set = true;
1031 /* 1033 /*
1032 * The hardware wedges sometimes if you reconfigure one CRTC 1034 * The hardware wedges sometimes if you reconfigure one CRTC
1033 * whilst another is running (see fdo bug #24611). 1035 * whilst another is running (see fdo bug #24611).
@@ -1038,6 +1040,7 @@ static void radeon_crtc_prepare(struct drm_crtc *crtc)
1038 1040
1039static void radeon_crtc_commit(struct drm_crtc *crtc) 1041static void radeon_crtc_commit(struct drm_crtc *crtc)
1040{ 1042{
1043 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1041 struct drm_device *dev = crtc->dev; 1044 struct drm_device *dev = crtc->dev;
1042 struct drm_crtc *crtci; 1045 struct drm_crtc *crtci;
1043 1046
@@ -1048,6 +1051,7 @@ static void radeon_crtc_commit(struct drm_crtc *crtc)
1048 if (crtci->enabled) 1051 if (crtci->enabled)
1049 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1052 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1050 } 1053 }
1054 radeon_crtc->in_mode_set = false;
1051} 1055}
1052 1056
1053static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1057static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index f380d59c5763..d56978949f34 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -275,6 +275,7 @@ struct radeon_crtc {
275 u16 lut_r[256], lut_g[256], lut_b[256]; 275 u16 lut_r[256], lut_g[256], lut_b[256];
276 bool enabled; 276 bool enabled;
277 bool can_tile; 277 bool can_tile;
278 bool in_mode_set;
278 uint32_t crtc_offset; 279 uint32_t crtc_offset;
279 struct drm_gem_object *cursor_bo; 280 struct drm_gem_object *cursor_bo;
280 uint64_t cursor_addr; 281 uint64_t cursor_addr;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 1f1a4c803c1d..9024e7222839 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -52,11 +52,7 @@ void radeon_bo_clear_va(struct radeon_bo *bo)
52 52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */ 54 /* remove from all vm address space */
55 mutex_lock(&bo_va->vm->mutex); 55 radeon_vm_bo_rmv(bo->rdev, bo_va->vm, bo);
56 list_del(&bo_va->vm_list);
57 mutex_unlock(&bo_va->vm->mutex);
58 list_del(&bo_va->bo_list);
59 kfree(bo_va);
60 } 56 }
61} 57}
62 58
@@ -136,6 +132,7 @@ int radeon_bo_create(struct radeon_device *rdev,
136 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 132 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
137 sizeof(struct radeon_bo)); 133 sizeof(struct radeon_bo));
138 134
135retry:
139 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
140 if (bo == NULL) 137 if (bo == NULL)
141 return -ENOMEM; 138 return -ENOMEM;
@@ -149,8 +146,6 @@ int radeon_bo_create(struct radeon_device *rdev,
149 bo->surface_reg = -1; 146 bo->surface_reg = -1;
150 INIT_LIST_HEAD(&bo->list); 147 INIT_LIST_HEAD(&bo->list);
151 INIT_LIST_HEAD(&bo->va); 148 INIT_LIST_HEAD(&bo->va);
152
153retry:
154 radeon_ttm_placement_from_domain(bo, domain); 149 radeon_ttm_placement_from_domain(bo, domain);
155 /* Kernel allocation are uninterruptible */ 150 /* Kernel allocation are uninterruptible */
156 down_read(&rdev->pm.mclk_lock); 151 down_read(&rdev->pm.mclk_lock);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index ec79b3750430..43c431a2686d 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -706,6 +706,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig
706 if (radeon_debugfs_ring_init(rdev, ring)) { 706 if (radeon_debugfs_ring_init(rdev, ring)) {
707 DRM_ERROR("Failed to register debugfs file for rings !\n"); 707 DRM_ERROR("Failed to register debugfs file for rings !\n");
708 } 708 }
709 radeon_ring_lockup_update(ring);
709 return 0; 710 return 0;
710} 711}
711 712
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 5e659b034d9a..20bfbda7b3f1 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -744,15 +744,6 @@ r600 0x9400
7440x00028C38 CB_CLRCMP_DST 7440x00028C38 CB_CLRCMP_DST
7450x00028C3C CB_CLRCMP_MSK 7450x00028C3C CB_CLRCMP_MSK
7460x00028C34 CB_CLRCMP_SRC 7460x00028C34 CB_CLRCMP_SRC
7470x00028100 CB_COLOR0_MASK
7480x00028104 CB_COLOR1_MASK
7490x00028108 CB_COLOR2_MASK
7500x0002810C CB_COLOR3_MASK
7510x00028110 CB_COLOR4_MASK
7520x00028114 CB_COLOR5_MASK
7530x00028118 CB_COLOR6_MASK
7540x0002811C CB_COLOR7_MASK
7550x00028808 CB_COLOR_CONTROL
7560x0002842C CB_FOG_BLUE 7470x0002842C CB_FOG_BLUE
7570x00028428 CB_FOG_GREEN 7480x00028428 CB_FOG_GREEN
7580x00028424 CB_FOG_RED 7490x00028424 CB_FOG_RED
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index a12fbcc8ccb6..aa8ef491ef3c 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -281,12 +281,8 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
281 281
282void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 282void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
283{ 283{
284 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
285 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
286 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 284 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
287 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 285 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
288 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
289 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
290 286
291 /* Stop all video */ 287 /* Stop all video */
292 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 288 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
@@ -311,15 +307,6 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
311 /* Unlock host access */ 307 /* Unlock host access */
312 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 308 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
313 mdelay(1); 309 mdelay(1);
314 /* Restore video state */
315 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
316 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
317 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
318 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
319 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
320 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
321 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
322 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
323 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 310 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
324} 311}
325 312
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c053f8193771..0139e227e3c7 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev)
1639 /* XXX what about 12? */ 1639 /* XXX what about 12? */
1640 rdev->config.si.tile_config |= (3 << 0); 1640 rdev->config.si.tile_config |= (3 << 0);
1641 break; 1641 break;
1642 } 1642 }
1643 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1643 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1644 rdev->config.si.tile_config |= 1 << 4; 1644 case 0: /* four banks */
1645 else
1646 rdev->config.si.tile_config |= 0 << 4; 1645 rdev->config.si.tile_config |= 0 << 4;
1646 break;
1647 case 1: /* eight banks */
1648 rdev->config.si.tile_config |= 1 << 4;
1649 break;
1650 case 2: /* sixteen banks */
1651 default:
1652 rdev->config.si.tile_config |= 2 << 4;
1653 break;
1654 }
1647 rdev->config.si.tile_config |= 1655 rdev->config.si.tile_config |=
1648 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1656 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1649 rdev->config.si.tile_config |= 1657 rdev->config.si.tile_config |=
@@ -3960,3 +3968,22 @@ void si_fini(struct radeon_device *rdev)
3960 rdev->bios = NULL; 3968 rdev->bios = NULL;
3961} 3969}
3962 3970
3971/**
3972 * si_get_gpu_clock - return GPU clock counter snapshot
3973 *
3974 * @rdev: radeon_device pointer
3975 *
3976 * Fetches a GPU clock counter snapshot (SI).
3977 * Returns the 64 bit clock counter snapshot.
3978 */
3979uint64_t si_get_gpu_clock(struct radeon_device *rdev)
3980{
3981 uint64_t clock;
3982
3983 mutex_lock(&rdev->gpu_clock_mutex);
3984 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3985 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3986 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3987 mutex_unlock(&rdev->gpu_clock_mutex);
3988 return clock;
3989}
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 7869089e8761..ef4815c27b1c 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -698,6 +698,9 @@
698#define RLC_UCODE_ADDR 0xC32C 698#define RLC_UCODE_ADDR 0xC32C
699#define RLC_UCODE_DATA 0xC330 699#define RLC_UCODE_DATA 0xC330
700 700
701#define RLC_GPU_CLOCK_COUNT_LSB 0xC338
702#define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
703#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
701#define RLC_MC_CNTL 0xC344 704#define RLC_MC_CNTL 0xC344
702#define RLC_UCODE_CNTL 0xC348 705#define RLC_UCODE_CNTL 0xC348
703 706
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 14:39:24 -0500