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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c54
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c175
-rw-r--r--drivers/gpu/drm/radeon/ci_dpm.c33
-rw-r--r--drivers/gpu/drm/radeon/cik.c176
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c3
-rw-r--r--drivers/gpu/drm/radeon/cikd.h9
-rw-r--r--drivers/gpu/drm/radeon/dce6_afmt.c14
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c28
-rw-r--r--drivers/gpu/drm/radeon/evergreen_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/kv_dpm.c135
-rw-r--r--drivers/gpu/drm/radeon/r600.c14
-rw-r--r--drivers/gpu/drm/radeon/r600_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c35
-rw-r--r--drivers/gpu/drm/radeon/radeon.h12
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atpx_handler.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c44
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c111
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c26
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c60
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h12
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c52
-rw-r--r--drivers/gpu/drm/radeon/radeon_ucode.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_vce.c3
-rw-r--r--drivers/gpu/drm/radeon/rv770_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/si.c65
-rw-r--r--drivers/gpu/drm/radeon/si_dma.c1
-rw-r--r--drivers/gpu/drm/radeon/uvd_v1_0.c10
32 files changed, 717 insertions, 424 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index fb187c78978f..c31c12b4e666 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1177,27 +1177,43 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1177 1177
1178 /* Set NUM_BANKS. */ 1178 /* Set NUM_BANKS. */
1179 if (rdev->family >= CHIP_TAHITI) { 1179 if (rdev->family >= CHIP_TAHITI) {
1180 unsigned tileb, index, num_banks, tile_split_bytes; 1180 unsigned index, num_banks;
1181 1181
1182 /* Calculate the macrotile mode index. */ 1182 if (rdev->family >= CHIP_BONAIRE) {
1183 tile_split_bytes = 64 << tile_split; 1183 unsigned tileb, tile_split_bytes;
1184 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1185 tileb = min(tile_split_bytes, tileb);
1186 1184
1187 for (index = 0; tileb > 64; index++) { 1185 /* Calculate the macrotile mode index. */
1188 tileb >>= 1; 1186 tile_split_bytes = 64 << tile_split;
1189 } 1187 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1188 tileb = min(tile_split_bytes, tileb);
1190 1189
1191 if (index >= 16) { 1190 for (index = 0; tileb > 64; index++)
1192 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1191 tileb >>= 1;
1193 target_fb->bits_per_pixel, tile_split); 1192
1194 return -EINVAL; 1193 if (index >= 16) {
1195 } 1194 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1195 target_fb->bits_per_pixel, tile_split);
1196 return -EINVAL;
1197 }
1196 1198
1197 if (rdev->family >= CHIP_BONAIRE)
1198 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1199 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1199 else 1200 } else {
1201 switch (target_fb->bits_per_pixel) {
1202 case 8:
1203 index = 10;
1204 break;
1205 case 16:
1206 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1207 break;
1208 default:
1209 case 32:
1210 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1211 break;
1212 }
1213
1200 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1214 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1215 }
1216
1201 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1217 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1202 } else { 1218 } else {
1203 /* NI and older. */ 1219 /* NI and older. */
@@ -1720,8 +1736,9 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1720 } 1736 }
1721 /* otherwise, pick one of the plls */ 1737 /* otherwise, pick one of the plls */
1722 if ((rdev->family == CHIP_KAVERI) || 1738 if ((rdev->family == CHIP_KAVERI) ||
1723 (rdev->family == CHIP_KABINI)) { 1739 (rdev->family == CHIP_KABINI) ||
1724 /* KB/KV has PPLL1 and PPLL2 */ 1740 (rdev->family == CHIP_MULLINS)) {
1741 /* KB/KV/ML has PPLL1 and PPLL2 */
1725 pll_in_use = radeon_get_pll_use_mask(crtc); 1742 pll_in_use = radeon_get_pll_use_mask(crtc);
1726 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1743 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1727 return ATOM_PPLL2; 1744 return ATOM_PPLL2;
@@ -1885,6 +1902,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1885 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1902 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1886 is_tvcv = true; 1903 is_tvcv = true;
1887 1904
1905 if (!radeon_crtc->adjusted_clock)
1906 return -EINVAL;
1907
1888 atombios_crtc_set_pll(crtc, adjusted_mode); 1908 atombios_crtc_set_pll(crtc, adjusted_mode);
1889 1909
1890 if (ASIC_IS_DCE4(rdev)) 1910 if (ASIC_IS_DCE4(rdev))
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 8b0ab170cef9..54e4f52549af 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -142,7 +142,8 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
142 return recv_bytes; 142 return recv_bytes;
143} 143}
144 144
145#define HEADER_SIZE 4 145#define BARE_ADDRESS_SIZE 3
146#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
146 147
147static ssize_t 148static ssize_t
148radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 149radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
@@ -160,13 +161,19 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
160 tx_buf[0] = msg->address & 0xff; 161 tx_buf[0] = msg->address & 0xff;
161 tx_buf[1] = msg->address >> 8; 162 tx_buf[1] = msg->address >> 8;
162 tx_buf[2] = msg->request << 4; 163 tx_buf[2] = msg->request << 4;
163 tx_buf[3] = msg->size - 1; 164 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
164 165
165 switch (msg->request & ~DP_AUX_I2C_MOT) { 166 switch (msg->request & ~DP_AUX_I2C_MOT) {
166 case DP_AUX_NATIVE_WRITE: 167 case DP_AUX_NATIVE_WRITE:
167 case DP_AUX_I2C_WRITE: 168 case DP_AUX_I2C_WRITE:
169 /* tx_size needs to be 4 even for bare address packets since the atom
170 * table needs the info in tx_buf[3].
171 */
168 tx_size = HEADER_SIZE + msg->size; 172 tx_size = HEADER_SIZE + msg->size;
169 tx_buf[3] |= tx_size << 4; 173 if (msg->size == 0)
174 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
175 else
176 tx_buf[3] |= tx_size << 4;
170 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 177 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
171 ret = radeon_process_aux_ch(chan, 178 ret = radeon_process_aux_ch(chan,
172 tx_buf, tx_size, NULL, 0, delay, &ack); 179 tx_buf, tx_size, NULL, 0, delay, &ack);
@@ -176,8 +183,14 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
176 break; 183 break;
177 case DP_AUX_NATIVE_READ: 184 case DP_AUX_NATIVE_READ:
178 case DP_AUX_I2C_READ: 185 case DP_AUX_I2C_READ:
186 /* tx_size needs to be 4 even for bare address packets since the atom
187 * table needs the info in tx_buf[3].
188 */
179 tx_size = HEADER_SIZE; 189 tx_size = HEADER_SIZE;
180 tx_buf[3] |= tx_size << 4; 190 if (msg->size == 0)
191 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
192 else
193 tx_buf[3] |= tx_size << 4;
181 ret = radeon_process_aux_ch(chan, 194 ret = radeon_process_aux_ch(chan,
182 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 195 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
183 break; 196 break;
@@ -186,7 +199,7 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
186 break; 199 break;
187 } 200 }
188 201
189 if (ret > 0) 202 if (ret >= 0)
190 msg->reply = ack >> 4; 203 msg->reply = ack >> 4;
191 204
192 return ret; 205 return ret;
@@ -194,98 +207,16 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
194 207
195void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 208void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
196{ 209{
197 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
198
199 dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;
200 dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;
201}
202
203int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
204 u8 write_byte, u8 *read_byte)
205{
206 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
207 struct radeon_i2c_chan *auxch = i2c_get_adapdata(adapter);
208 u16 address = algo_data->address;
209 u8 msg[5];
210 u8 reply[2];
211 unsigned retry;
212 int msg_bytes;
213 int reply_bytes = 1;
214 int ret; 210 int ret;
215 u8 ack;
216 211
217 /* Set up the address */ 212 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
218 msg[0] = address; 213 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
219 msg[1] = address >> 8; 214 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
215 ret = drm_dp_aux_register_i2c_bus(&radeon_connector->ddc_bus->aux);
216 if (!ret)
217 radeon_connector->ddc_bus->has_aux = true;
220 218
221 /* Set up the command byte */ 219 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
222 if (mode & MODE_I2C_READ) {
223 msg[2] = DP_AUX_I2C_READ << 4;
224 msg_bytes = 4;
225 msg[3] = msg_bytes << 4;
226 } else {
227 msg[2] = DP_AUX_I2C_WRITE << 4;
228 msg_bytes = 5;
229 msg[3] = msg_bytes << 4;
230 msg[4] = write_byte;
231 }
232
233 /* special handling for start/stop */
234 if (mode & (MODE_I2C_START | MODE_I2C_STOP))
235 msg[3] = 3 << 4;
236
237 /* Set MOT bit for all but stop */
238 if ((mode & MODE_I2C_STOP) == 0)
239 msg[2] |= DP_AUX_I2C_MOT << 4;
240
241 for (retry = 0; retry < 7; retry++) {
242 ret = radeon_process_aux_ch(auxch,
243 msg, msg_bytes, reply, reply_bytes, 0, &ack);
244 if (ret == -EBUSY)
245 continue;
246 else if (ret < 0) {
247 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
248 return ret;
249 }
250
251 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
252 case DP_AUX_NATIVE_REPLY_ACK:
253 /* I2C-over-AUX Reply field is only valid
254 * when paired with AUX ACK.
255 */
256 break;
257 case DP_AUX_NATIVE_REPLY_NACK:
258 DRM_DEBUG_KMS("aux_ch native nack\n");
259 return -EREMOTEIO;
260 case DP_AUX_NATIVE_REPLY_DEFER:
261 DRM_DEBUG_KMS("aux_ch native defer\n");
262 usleep_range(500, 600);
263 continue;
264 default:
265 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
266 return -EREMOTEIO;
267 }
268
269 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
270 case DP_AUX_I2C_REPLY_ACK:
271 if (mode == MODE_I2C_READ)
272 *read_byte = reply[0];
273 return ret;
274 case DP_AUX_I2C_REPLY_NACK:
275 DRM_DEBUG_KMS("aux_i2c nack\n");
276 return -EREMOTEIO;
277 case DP_AUX_I2C_REPLY_DEFER:
278 DRM_DEBUG_KMS("aux_i2c defer\n");
279 usleep_range(400, 500);
280 break;
281 default:
282 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
283 return -EREMOTEIO;
284 }
285 }
286
287 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
288 return -EREMOTEIO;
289} 220}
290 221
291/***** general DP utility functions *****/ 222/***** general DP utility functions *****/
@@ -420,12 +351,11 @@ static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
420 351
421u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 352u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
422{ 353{
423 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
424 struct drm_device *dev = radeon_connector->base.dev; 354 struct drm_device *dev = radeon_connector->base.dev;
425 struct radeon_device *rdev = dev->dev_private; 355 struct radeon_device *rdev = dev->dev_private;
426 356
427 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 357 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
428 dig_connector->dp_i2c_bus->rec.i2c_id, 0); 358 radeon_connector->ddc_bus->rec.i2c_id, 0);
429} 359}
430 360
431static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 361static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
@@ -436,11 +366,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
436 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 366 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
437 return; 367 return;
438 368
439 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3)) 369 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
440 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 370 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
441 buf[0], buf[1], buf[2]); 371 buf[0], buf[1], buf[2]);
442 372
443 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3)) 373 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
444 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 374 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
445 buf[0], buf[1], buf[2]); 375 buf[0], buf[1], buf[2]);
446} 376}
@@ -451,7 +381,7 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
451 u8 msg[DP_DPCD_SIZE]; 381 u8 msg[DP_DPCD_SIZE];
452 int ret, i; 382 int ret, i;
453 383
454 ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg, 384 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
455 DP_DPCD_SIZE); 385 DP_DPCD_SIZE);
456 if (ret > 0) { 386 if (ret > 0) {
457 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 387 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
@@ -489,21 +419,23 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
489 419
490 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 420 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
491 /* DP bridge chips */ 421 /* DP bridge chips */
492 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, 422 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
493 DP_EDP_CONFIGURATION_CAP, &tmp); 423 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
494 if (tmp & 1) 424 if (tmp & 1)
495 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 425 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
496 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 426 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
497 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 427 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
498 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 428 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
499 else 429 else
500 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 430 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
431 }
501 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 432 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
502 /* eDP */ 433 /* eDP */
503 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, 434 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
504 DP_EDP_CONFIGURATION_CAP, &tmp); 435 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
505 if (tmp & 1) 436 if (tmp & 1)
506 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 437 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
438 }
507 } 439 }
508 440
509 return panel_mode; 441 return panel_mode;
@@ -554,7 +486,8 @@ bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
554 u8 link_status[DP_LINK_STATUS_SIZE]; 486 u8 link_status[DP_LINK_STATUS_SIZE];
555 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 487 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
556 488
557 if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0) 489 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
490 <= 0)
558 return false; 491 return false;
559 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 492 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
560 return false; 493 return false;
@@ -574,7 +507,7 @@ void radeon_dp_set_rx_power_state(struct drm_connector *connector,
574 507
575 /* power up/down the sink */ 508 /* power up/down the sink */
576 if (dig_connector->dpcd[0] >= 0x11) { 509 if (dig_connector->dpcd[0] >= 0x11) {
577 drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux, 510 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
578 DP_SET_POWER, power_state); 511 DP_SET_POWER, power_state);
579 usleep_range(1000, 2000); 512 usleep_range(1000, 2000);
580 } 513 }
@@ -878,11 +811,15 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
878 else 811 else
879 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 812 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
880 813
881 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp); 814 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
882 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 815 == 1) {
883 dp_info.tp3_supported = true; 816 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
884 else 817 dp_info.tp3_supported = true;
818 else
819 dp_info.tp3_supported = false;
820 } else {
885 dp_info.tp3_supported = false; 821 dp_info.tp3_supported = false;
822 }
886 823
887 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 824 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
888 dp_info.rdev = rdev; 825 dp_info.rdev = rdev;
@@ -890,7 +827,7 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
890 dp_info.connector = connector; 827 dp_info.connector = connector;
891 dp_info.dp_lane_count = dig_connector->dp_lane_count; 828 dp_info.dp_lane_count = dig_connector->dp_lane_count;
892 dp_info.dp_clock = dig_connector->dp_clock; 829 dp_info.dp_clock = dig_connector->dp_clock;
893 dp_info.aux = &dig_connector->dp_i2c_bus->aux; 830 dp_info.aux = &radeon_connector->ddc_bus->aux;
894 831
895 if (radeon_dp_link_train_init(&dp_info)) 832 if (radeon_dp_link_train_init(&dp_info))
896 goto done; 833 goto done;
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index cad89a977527..10dae4106c08 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -21,8 +21,10 @@
21 * 21 *
22 */ 22 */
23 23
24#include <linux/firmware.h>
24#include "drmP.h" 25#include "drmP.h"
25#include "radeon.h" 26#include "radeon.h"
27#include "radeon_ucode.h"
26#include "cikd.h" 28#include "cikd.h"
27#include "r600_dpm.h" 29#include "r600_dpm.h"
28#include "ci_dpm.h" 30#include "ci_dpm.h"
@@ -202,24 +204,29 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
202 struct ci_power_info *pi = ci_get_pi(rdev); 204 struct ci_power_info *pi = ci_get_pi(rdev);
203 205
204 switch (rdev->pdev->device) { 206 switch (rdev->pdev->device) {
207 case 0x6649:
205 case 0x6650: 208 case 0x6650:
209 case 0x6651:
206 case 0x6658: 210 case 0x6658:
207 case 0x665C: 211 case 0x665C:
212 case 0x665D:
208 default: 213 default:
209 pi->powertune_defaults = &defaults_bonaire_xt; 214 pi->powertune_defaults = &defaults_bonaire_xt;
210 break; 215 break;
211 case 0x6651:
212 case 0x665D:
213 pi->powertune_defaults = &defaults_bonaire_pro;
214 break;
215 case 0x6640: 216 case 0x6640:
216 pi->powertune_defaults = &defaults_saturn_xt;
217 break;
218 case 0x6641: 217 case 0x6641:
219 pi->powertune_defaults = &defaults_saturn_pro; 218 case 0x6646:
219 case 0x6647:
220 pi->powertune_defaults = &defaults_saturn_xt;
220 break; 221 break;
221 case 0x67B8: 222 case 0x67B8:
222 case 0x67B0: 223 case 0x67B0:
224 pi->powertune_defaults = &defaults_hawaii_xt;
225 break;
226 case 0x67BA:
227 case 0x67B1:
228 pi->powertune_defaults = &defaults_hawaii_pro;
229 break;
223 case 0x67A0: 230 case 0x67A0:
224 case 0x67A1: 231 case 0x67A1:
225 case 0x67A2: 232 case 0x67A2:
@@ -228,11 +235,7 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
228 case 0x67AA: 235 case 0x67AA:
229 case 0x67B9: 236 case 0x67B9:
230 case 0x67BE: 237 case 0x67BE:
231 pi->powertune_defaults = &defaults_hawaii_xt; 238 pi->powertune_defaults = &defaults_bonaire_xt;
232 break;
233 case 0x67BA:
234 case 0x67B1:
235 pi->powertune_defaults = &defaults_hawaii_pro;
236 break; 239 break;
237 } 240 }
238 241
@@ -5146,6 +5149,12 @@ int ci_dpm_init(struct radeon_device *rdev)
5146 pi->mclk_dpm_key_disabled = 0; 5149 pi->mclk_dpm_key_disabled = 0;
5147 pi->pcie_dpm_key_disabled = 0; 5150 pi->pcie_dpm_key_disabled = 0;
5148 5151
5152 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5153 if ((rdev->pdev->device == 0x6658) &&
5154 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5155 pi->mclk_dpm_key_disabled = 1;
5156 }
5157
5149 pi->caps_sclk_ds = true; 5158 pi->caps_sclk_ds = true;
5150 5159
5151 pi->mclk_strobe_mode_threshold = 40000; 5160 pi->mclk_strobe_mode_threshold = 40000;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 745143c2358f..d2fd98968085 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -38,6 +38,7 @@ MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
38MODULE_FIRMWARE("radeon/BONAIRE_ce.bin"); 38MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
39MODULE_FIRMWARE("radeon/BONAIRE_mec.bin"); 39MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
40MODULE_FIRMWARE("radeon/BONAIRE_mc.bin"); 40MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
41MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
41MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); 42MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
42MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin"); 43MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
43MODULE_FIRMWARE("radeon/BONAIRE_smc.bin"); 44MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
@@ -46,6 +47,7 @@ MODULE_FIRMWARE("radeon/HAWAII_me.bin");
46MODULE_FIRMWARE("radeon/HAWAII_ce.bin"); 47MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
47MODULE_FIRMWARE("radeon/HAWAII_mec.bin"); 48MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
48MODULE_FIRMWARE("radeon/HAWAII_mc.bin"); 49MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
50MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
49MODULE_FIRMWARE("radeon/HAWAII_rlc.bin"); 51MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
50MODULE_FIRMWARE("radeon/HAWAII_sdma.bin"); 52MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
51MODULE_FIRMWARE("radeon/HAWAII_smc.bin"); 53MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
@@ -61,6 +63,12 @@ MODULE_FIRMWARE("radeon/KABINI_ce.bin");
61MODULE_FIRMWARE("radeon/KABINI_mec.bin"); 63MODULE_FIRMWARE("radeon/KABINI_mec.bin");
62MODULE_FIRMWARE("radeon/KABINI_rlc.bin"); 64MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
63MODULE_FIRMWARE("radeon/KABINI_sdma.bin"); 65MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
66MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
67MODULE_FIRMWARE("radeon/MULLINS_me.bin");
68MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
69MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
70MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
71MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
64 72
65extern int r600_ih_ring_alloc(struct radeon_device *rdev); 73extern int r600_ih_ring_alloc(struct radeon_device *rdev);
66extern void r600_ih_ring_fini(struct radeon_device *rdev); 74extern void r600_ih_ring_fini(struct radeon_device *rdev);
@@ -1471,6 +1479,43 @@ static const u32 hawaii_mgcg_cgcg_init[] =
1471 0xd80c, 0xff000ff0, 0x00000100 1479 0xd80c, 0xff000ff0, 0x00000100
1472}; 1480};
1473 1481
1482static const u32 godavari_golden_registers[] =
1483{
1484 0x55e4, 0xff607fff, 0xfc000100,
1485 0x6ed8, 0x00010101, 0x00010000,
1486 0x9830, 0xffffffff, 0x00000000,
1487 0x98302, 0xf00fffff, 0x00000400,
1488 0x6130, 0xffffffff, 0x00010000,
1489 0x5bb0, 0x000000f0, 0x00000070,
1490 0x5bc0, 0xf0311fff, 0x80300000,
1491 0x98f8, 0x73773777, 0x12010001,
1492 0x98fc, 0xffffffff, 0x00000010,
1493 0x8030, 0x00001f0f, 0x0000100a,
1494 0x2f48, 0x73773777, 0x12010001,
1495 0x2408, 0x000fffff, 0x000c007f,
1496 0x8a14, 0xf000003f, 0x00000007,
1497 0x8b24, 0xffffffff, 0x00ff0fff,
1498 0x30a04, 0x0000ff0f, 0x00000000,
1499 0x28a4c, 0x07ffffff, 0x06000000,
1500 0x4d8, 0x00000fff, 0x00000100,
1501 0xd014, 0x00010000, 0x00810001,
1502 0xd814, 0x00010000, 0x00810001,
1503 0x3e78, 0x00000001, 0x00000002,
1504 0xc768, 0x00000008, 0x00000008,
1505 0xc770, 0x00000f00, 0x00000800,
1506 0xc774, 0x00000f00, 0x00000800,
1507 0xc798, 0x00ffffff, 0x00ff7fbf,
1508 0xc79c, 0x00ffffff, 0x00ff7faf,
1509 0x8c00, 0x000000ff, 0x00000001,
1510 0x214f8, 0x01ff01ff, 0x00000002,
1511 0x21498, 0x007ff800, 0x00200000,
1512 0x2015c, 0xffffffff, 0x00000f40,
1513 0x88c4, 0x001f3ae3, 0x00000082,
1514 0x88d4, 0x0000001f, 0x00000010,
1515 0x30934, 0xffffffff, 0x00000000
1516};
1517
1518
1474static void cik_init_golden_registers(struct radeon_device *rdev) 1519static void cik_init_golden_registers(struct radeon_device *rdev)
1475{ 1520{
1476 switch (rdev->family) { 1521 switch (rdev->family) {
@@ -1502,6 +1547,20 @@ static void cik_init_golden_registers(struct radeon_device *rdev)
1502 kalindi_golden_spm_registers, 1547 kalindi_golden_spm_registers,
1503 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 1548 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1504 break; 1549 break;
1550 case CHIP_MULLINS:
1551 radeon_program_register_sequence(rdev,
1552 kalindi_mgcg_cgcg_init,
1553 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1554 radeon_program_register_sequence(rdev,
1555 godavari_golden_registers,
1556 (const u32)ARRAY_SIZE(godavari_golden_registers));
1557 radeon_program_register_sequence(rdev,
1558 kalindi_golden_common_registers,
1559 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1560 radeon_program_register_sequence(rdev,
1561 kalindi_golden_spm_registers,
1562 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1563 break;
1505 case CHIP_KAVERI: 1564 case CHIP_KAVERI:
1506 radeon_program_register_sequence(rdev, 1565 radeon_program_register_sequence(rdev,
1507 spectre_mgcg_cgcg_init, 1566 spectre_mgcg_cgcg_init,
@@ -1703,20 +1762,20 @@ int ci_mc_load_microcode(struct radeon_device *rdev)
1703 const __be32 *fw_data; 1762 const __be32 *fw_data;
1704 u32 running, blackout = 0; 1763 u32 running, blackout = 0;
1705 u32 *io_mc_regs; 1764 u32 *io_mc_regs;
1706 int i, ucode_size, regs_size; 1765 int i, regs_size, ucode_size;
1707 1766
1708 if (!rdev->mc_fw) 1767 if (!rdev->mc_fw)
1709 return -EINVAL; 1768 return -EINVAL;
1710 1769
1770 ucode_size = rdev->mc_fw->size / 4;
1771
1711 switch (rdev->family) { 1772 switch (rdev->family) {
1712 case CHIP_BONAIRE: 1773 case CHIP_BONAIRE:
1713 io_mc_regs = (u32 *)&bonaire_io_mc_regs; 1774 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1714 ucode_size = CIK_MC_UCODE_SIZE;
1715 regs_size = BONAIRE_IO_MC_REGS_SIZE; 1775 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1716 break; 1776 break;
1717 case CHIP_HAWAII: 1777 case CHIP_HAWAII:
1718 io_mc_regs = (u32 *)&hawaii_io_mc_regs; 1778 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1719 ucode_size = HAWAII_MC_UCODE_SIZE;
1720 regs_size = HAWAII_IO_MC_REGS_SIZE; 1779 regs_size = HAWAII_IO_MC_REGS_SIZE;
1721 break; 1780 break;
1722 default: 1781 default:
@@ -1783,7 +1842,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
1783 const char *chip_name; 1842 const char *chip_name;
1784 size_t pfp_req_size, me_req_size, ce_req_size, 1843 size_t pfp_req_size, me_req_size, ce_req_size,
1785 mec_req_size, rlc_req_size, mc_req_size = 0, 1844 mec_req_size, rlc_req_size, mc_req_size = 0,
1786 sdma_req_size, smc_req_size = 0; 1845 sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
1787 char fw_name[30]; 1846 char fw_name[30];
1788 int err; 1847 int err;
1789 1848
@@ -1797,7 +1856,8 @@ static int cik_init_microcode(struct radeon_device *rdev)
1797 ce_req_size = CIK_CE_UCODE_SIZE * 4; 1856 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1798 mec_req_size = CIK_MEC_UCODE_SIZE * 4; 1857 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1799 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4; 1858 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1800 mc_req_size = CIK_MC_UCODE_SIZE * 4; 1859 mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
1860 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
1801 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1861 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1802 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4); 1862 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
1803 break; 1863 break;
@@ -1809,6 +1869,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
1809 mec_req_size = CIK_MEC_UCODE_SIZE * 4; 1869 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1810 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4; 1870 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1811 mc_req_size = HAWAII_MC_UCODE_SIZE * 4; 1871 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
1872 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
1812 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1873 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1813 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4); 1874 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
1814 break; 1875 break;
@@ -1830,6 +1891,15 @@ static int cik_init_microcode(struct radeon_device *rdev)
1830 rlc_req_size = KB_RLC_UCODE_SIZE * 4; 1891 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
1831 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; 1892 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1832 break; 1893 break;
1894 case CHIP_MULLINS:
1895 chip_name = "MULLINS";
1896 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1897 me_req_size = CIK_ME_UCODE_SIZE * 4;
1898 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1899 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1900 rlc_req_size = ML_RLC_UCODE_SIZE * 4;
1901 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1902 break;
1833 default: BUG(); 1903 default: BUG();
1834 } 1904 }
1835 1905
@@ -1904,16 +1974,22 @@ static int cik_init_microcode(struct radeon_device *rdev)
1904 1974
1905 /* No SMC, MC ucode on APUs */ 1975 /* No SMC, MC ucode on APUs */
1906 if (!(rdev->flags & RADEON_IS_IGP)) { 1976 if (!(rdev->flags & RADEON_IS_IGP)) {
1907 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 1977 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1908 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 1978 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1909 if (err) 1979 if (err) {
1910 goto out; 1980 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1911 if (rdev->mc_fw->size != mc_req_size) { 1981 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1982 if (err)
1983 goto out;
1984 }
1985 if ((rdev->mc_fw->size != mc_req_size) &&
1986 (rdev->mc_fw->size != mc2_req_size)){
1912 printk(KERN_ERR 1987 printk(KERN_ERR
1913 "cik_mc: Bogus length %zu in firmware \"%s\"\n", 1988 "cik_mc: Bogus length %zu in firmware \"%s\"\n",
1914 rdev->mc_fw->size, fw_name); 1989 rdev->mc_fw->size, fw_name);
1915 err = -EINVAL; 1990 err = -EINVAL;
1916 } 1991 }
1992 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1917 1993
1918 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 1994 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1919 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 1995 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
@@ -3262,6 +3338,7 @@ static void cik_gpu_init(struct radeon_device *rdev)
3262 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 3338 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3263 break; 3339 break;
3264 case CHIP_KABINI: 3340 case CHIP_KABINI:
3341 case CHIP_MULLINS:
3265 default: 3342 default:
3266 rdev->config.cik.max_shader_engines = 1; 3343 rdev->config.cik.max_shader_engines = 1;
3267 rdev->config.cik.max_tile_pipes = 2; 3344 rdev->config.cik.max_tile_pipes = 2;
@@ -3692,6 +3769,7 @@ int cik_copy_cpdma(struct radeon_device *rdev,
3692 r = radeon_fence_emit(rdev, fence, ring->idx); 3769 r = radeon_fence_emit(rdev, fence, ring->idx);
3693 if (r) { 3770 if (r) {
3694 radeon_ring_unlock_undo(rdev, ring); 3771 radeon_ring_unlock_undo(rdev, ring);
3772 radeon_semaphore_free(rdev, &sem, NULL);
3695 return r; 3773 return r;
3696 } 3774 }
3697 3775
@@ -5790,6 +5868,9 @@ static int cik_rlc_resume(struct radeon_device *rdev)
5790 case CHIP_KABINI: 5868 case CHIP_KABINI:
5791 size = KB_RLC_UCODE_SIZE; 5869 size = KB_RLC_UCODE_SIZE;
5792 break; 5870 break;
5871 case CHIP_MULLINS:
5872 size = ML_RLC_UCODE_SIZE;
5873 break;
5793 } 5874 }
5794 5875
5795 cik_rlc_stop(rdev); 5876 cik_rlc_stop(rdev);
@@ -6538,6 +6619,7 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
6538 buffer[count++] = cpu_to_le32(0x00000000); 6619 buffer[count++] = cpu_to_le32(0x00000000);
6539 break; 6620 break;
6540 case CHIP_KABINI: 6621 case CHIP_KABINI:
6622 case CHIP_MULLINS:
6541 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 6623 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6542 buffer[count++] = cpu_to_le32(0x00000000); 6624 buffer[count++] = cpu_to_le32(0x00000000);
6543 break; 6625 break;
@@ -6683,6 +6765,19 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
6683 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 6765 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6684 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 6766 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6685 } 6767 }
6768 /* pflip */
6769 if (rdev->num_crtc >= 2) {
6770 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6771 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6772 }
6773 if (rdev->num_crtc >= 4) {
6774 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6775 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6776 }
6777 if (rdev->num_crtc >= 6) {
6778 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6779 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6780 }
6686 6781
6687 /* dac hotplug */ 6782 /* dac hotplug */
6688 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); 6783 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
@@ -7039,6 +7134,25 @@ int cik_irq_set(struct radeon_device *rdev)
7039 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 7134 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
7040 } 7135 }
7041 7136
7137 if (rdev->num_crtc >= 2) {
7138 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
7139 GRPH_PFLIP_INT_MASK);
7140 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
7141 GRPH_PFLIP_INT_MASK);
7142 }
7143 if (rdev->num_crtc >= 4) {
7144 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
7145 GRPH_PFLIP_INT_MASK);
7146 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
7147 GRPH_PFLIP_INT_MASK);
7148 }
7149 if (rdev->num_crtc >= 6) {
7150 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
7151 GRPH_PFLIP_INT_MASK);
7152 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
7153 GRPH_PFLIP_INT_MASK);
7154 }
7155
7042 WREG32(DC_HPD1_INT_CONTROL, hpd1); 7156 WREG32(DC_HPD1_INT_CONTROL, hpd1);
7043 WREG32(DC_HPD2_INT_CONTROL, hpd2); 7157 WREG32(DC_HPD2_INT_CONTROL, hpd2);
7044 WREG32(DC_HPD3_INT_CONTROL, hpd3); 7158 WREG32(DC_HPD3_INT_CONTROL, hpd3);
@@ -7075,6 +7189,29 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
7075 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 7189 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7076 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); 7190 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7077 7191
7192 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
7193 EVERGREEN_CRTC0_REGISTER_OFFSET);
7194 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
7195 EVERGREEN_CRTC1_REGISTER_OFFSET);
7196 if (rdev->num_crtc >= 4) {
7197 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
7198 EVERGREEN_CRTC2_REGISTER_OFFSET);
7199 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
7200 EVERGREEN_CRTC3_REGISTER_OFFSET);
7201 }
7202 if (rdev->num_crtc >= 6) {
7203 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
7204 EVERGREEN_CRTC4_REGISTER_OFFSET);
7205 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
7206 EVERGREEN_CRTC5_REGISTER_OFFSET);
7207 }
7208
7209 if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
7210 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
7211 GRPH_PFLIP_INT_CLEAR);
7212 if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
7213 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
7214 GRPH_PFLIP_INT_CLEAR);
7078 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) 7215 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7079 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 7216 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
7080 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) 7217 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
@@ -7085,6 +7222,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
7085 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 7222 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
7086 7223
7087 if (rdev->num_crtc >= 4) { 7224 if (rdev->num_crtc >= 4) {
7225 if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
7226 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
7227 GRPH_PFLIP_INT_CLEAR);
7228 if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
7229 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
7230 GRPH_PFLIP_INT_CLEAR);
7088 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 7231 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7089 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 7232 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
7090 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 7233 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
@@ -7096,6 +7239,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
7096 } 7239 }
7097 7240
7098 if (rdev->num_crtc >= 6) { 7241 if (rdev->num_crtc >= 6) {
7242 if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
7243 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
7244 GRPH_PFLIP_INT_CLEAR);
7245 if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
7246 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
7247 GRPH_PFLIP_INT_CLEAR);
7099 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 7248 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7100 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 7249 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
7101 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 7250 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
@@ -7447,6 +7596,15 @@ restart_ih:
7447 break; 7596 break;
7448 } 7597 }
7449 break; 7598 break;
7599 case 8: /* D1 page flip */
7600 case 10: /* D2 page flip */
7601 case 12: /* D3 page flip */
7602 case 14: /* D4 page flip */
7603 case 16: /* D5 page flip */
7604 case 18: /* D6 page flip */
7605 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
7606 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
7607 break;
7450 case 42: /* HPD hotplug */ 7608 case 42: /* HPD hotplug */
7451 switch (src_data) { 7609 switch (src_data) {
7452 case 0: 7610 case 0:
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 89b4afa5041c..72e464c79a88 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -562,6 +562,7 @@ int cik_copy_dma(struct radeon_device *rdev,
562 r = radeon_fence_emit(rdev, fence, ring->idx); 562 r = radeon_fence_emit(rdev, fence, ring->idx);
563 if (r) { 563 if (r) {
564 radeon_ring_unlock_undo(rdev, ring); 564 radeon_ring_unlock_undo(rdev, ring);
565 radeon_semaphore_free(rdev, &sem, NULL);
565 return r; 566 return r;
566 } 567 }
567 568
@@ -597,7 +598,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
597 tmp = 0xCAFEDEAD; 598 tmp = 0xCAFEDEAD;
598 writel(tmp, ptr); 599 writel(tmp, ptr);
599 600
600 r = radeon_ring_lock(rdev, ring, 4); 601 r = radeon_ring_lock(rdev, ring, 5);
601 if (r) { 602 if (r) {
602 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 603 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
603 return r; 604 return r;
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 213873270d5f..dd7926394a8f 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -888,6 +888,15 @@
888# define DC_HPD6_RX_INTERRUPT (1 << 18) 888# define DC_HPD6_RX_INTERRUPT (1 << 18)
889#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 889#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
890 890
891/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
892#define GRPH_INT_STATUS 0x6858
893# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
894# define GRPH_PFLIP_INT_CLEAR (1 << 8)
895/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
896#define GRPH_INT_CONTROL 0x685c
897# define GRPH_PFLIP_INT_MASK (1 << 0)
898# define GRPH_PFLIP_INT_TYPE (1 << 8)
899
891#define DAC_AUTODETECT_INT_CONTROL 0x67c8 900#define DAC_AUTODETECT_INT_CONTROL 0x67c8
892 901
893#define DC_HPD1_INT_STATUS 0x601c 902#define DC_HPD1_INT_STATUS 0x601c
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 94e858751994..0a65dc7e93e7 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -309,11 +309,17 @@ int dce6_audio_init(struct radeon_device *rdev)
309 309
310 rdev->audio.enabled = true; 310 rdev->audio.enabled = true;
311 311
312 if (ASIC_IS_DCE8(rdev)) 312 if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */
313 rdev->audio.num_pins = 7;
314 else if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
315 rdev->audio.num_pins = 3;
316 else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */
317 rdev->audio.num_pins = 7;
318 else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */
313 rdev->audio.num_pins = 6; 319 rdev->audio.num_pins = 6;
314 else if (ASIC_IS_DCE61(rdev)) 320 else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */
315 rdev->audio.num_pins = 4; 321 rdev->audio.num_pins = 2;
316 else 322 else /* SI: 6 streams, 6 endpoints */
317 rdev->audio.num_pins = 6; 323 rdev->audio.num_pins = 6;
318 324
319 for (i = 0; i < rdev->audio.num_pins; i++) { 325 for (i = 0; i < rdev->audio.num_pins; i++) {
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index b406546440da..0f7a51a3694f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4371,7 +4371,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
4371 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 4371 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
4372 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 4372 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
4373 u32 grbm_int_cntl = 0; 4373 u32 grbm_int_cntl = 0;
4374 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
4375 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; 4374 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
4376 u32 dma_cntl, dma_cntl1 = 0; 4375 u32 dma_cntl, dma_cntl1 = 0;
4377 u32 thermal_int = 0; 4376 u32 thermal_int = 0;
@@ -4554,15 +4553,21 @@ int evergreen_irq_set(struct radeon_device *rdev)
4554 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 4553 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
4555 } 4554 }
4556 4555
4557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 4556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
4558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 4557 GRPH_PFLIP_INT_MASK);
4558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
4559 GRPH_PFLIP_INT_MASK);
4559 if (rdev->num_crtc >= 4) { 4560 if (rdev->num_crtc >= 4) {
4560 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 4561 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
4561 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 4562 GRPH_PFLIP_INT_MASK);
4563 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
4564 GRPH_PFLIP_INT_MASK);
4562 } 4565 }
4563 if (rdev->num_crtc >= 6) { 4566 if (rdev->num_crtc >= 6) {
4564 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 4567 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
4565 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 4568 GRPH_PFLIP_INT_MASK);
4569 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
4570 GRPH_PFLIP_INT_MASK);
4566 } 4571 }
4567 4572
4568 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4573 WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -4951,6 +4956,15 @@ restart_ih:
4951 break; 4956 break;
4952 } 4957 }
4953 break; 4958 break;
4959 case 8: /* D1 page flip */
4960 case 10: /* D2 page flip */
4961 case 12: /* D3 page flip */
4962 case 14: /* D4 page flip */
4963 case 16: /* D5 page flip */
4964 case 18: /* D6 page flip */
4965 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
4966 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
4967 break;
4954 case 42: /* HPD hotplug */ 4968 case 42: /* HPD hotplug */
4955 switch (src_data) { 4969 switch (src_data) {
4956 case 0: 4970 case 0:
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c
index 287fe966d7de..478caefe0fef 100644
--- a/drivers/gpu/drm/radeon/evergreen_dma.c
+++ b/drivers/gpu/drm/radeon/evergreen_dma.c
@@ -151,6 +151,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
151 r = radeon_fence_emit(rdev, fence, ring->idx); 151 r = radeon_fence_emit(rdev, fence, ring->idx);
152 if (r) { 152 if (r) {
153 radeon_ring_unlock_undo(rdev, ring); 153 radeon_ring_unlock_undo(rdev, ring);
154 radeon_semaphore_free(rdev, &sem, NULL);
154 return r; 155 return r;
155 } 156 }
156 157
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index 16ec9d56a234..3f6e817d97ee 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -546,6 +546,52 @@ static int kv_set_divider_value(struct radeon_device *rdev,
546 return 0; 546 return 0;
547} 547}
548 548
549static u32 kv_convert_vid2_to_vid7(struct radeon_device *rdev,
550 struct sumo_vid_mapping_table *vid_mapping_table,
551 u32 vid_2bit)
552{
553 struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
554 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
555 u32 i;
556
557 if (vddc_sclk_table && vddc_sclk_table->count) {
558 if (vid_2bit < vddc_sclk_table->count)
559 return vddc_sclk_table->entries[vid_2bit].v;
560 else
561 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
562 } else {
563 for (i = 0; i < vid_mapping_table->num_entries; i++) {
564 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
565 return vid_mapping_table->entries[i].vid_7bit;
566 }
567 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
568 }
569}
570
571static u32 kv_convert_vid7_to_vid2(struct radeon_device *rdev,
572 struct sumo_vid_mapping_table *vid_mapping_table,
573 u32 vid_7bit)
574{
575 struct radeon_clock_voltage_dependency_table *vddc_sclk_table =
576 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
577 u32 i;
578
579 if (vddc_sclk_table && vddc_sclk_table->count) {
580 for (i = 0; i < vddc_sclk_table->count; i++) {
581 if (vddc_sclk_table->entries[i].v == vid_7bit)
582 return i;
583 }
584 return vddc_sclk_table->count - 1;
585 } else {
586 for (i = 0; i < vid_mapping_table->num_entries; i++) {
587 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
588 return vid_mapping_table->entries[i].vid_2bit;
589 }
590
591 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
592 }
593}
594
549static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev, 595static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
550 u16 voltage) 596 u16 voltage)
551{ 597{
@@ -556,9 +602,9 @@ static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
556 u32 vid_2bit) 602 u32 vid_2bit)
557{ 603{
558 struct kv_power_info *pi = kv_get_pi(rdev); 604 struct kv_power_info *pi = kv_get_pi(rdev);
559 u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev, 605 u32 vid_8bit = kv_convert_vid2_to_vid7(rdev,
560 &pi->sys_info.vid_mapping_table, 606 &pi->sys_info.vid_mapping_table,
561 vid_2bit); 607 vid_2bit);
562 608
563 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit); 609 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
564} 610}
@@ -639,7 +685,7 @@ static int kv_force_lowest_valid(struct radeon_device *rdev)
639 685
640static int kv_unforce_levels(struct radeon_device *rdev) 686static int kv_unforce_levels(struct radeon_device *rdev)
641{ 687{
642 if (rdev->family == CHIP_KABINI) 688 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
643 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel); 689 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
644 else 690 else
645 return kv_set_enabled_levels(rdev); 691 return kv_set_enabled_levels(rdev);
@@ -1362,13 +1408,20 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1362 struct radeon_uvd_clock_voltage_dependency_table *table = 1408 struct radeon_uvd_clock_voltage_dependency_table *table =
1363 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1409 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1364 int ret; 1410 int ret;
1411 u32 mask;
1365 1412
1366 if (!gate) { 1413 if (!gate) {
1367 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state) 1414 if (table->count)
1368 pi->uvd_boot_level = table->count - 1; 1415 pi->uvd_boot_level = table->count - 1;
1369 else 1416 else
1370 pi->uvd_boot_level = 0; 1417 pi->uvd_boot_level = 0;
1371 1418
1419 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1420 mask = 1 << pi->uvd_boot_level;
1421 } else {
1422 mask = 0x1f;
1423 }
1424
1372 ret = kv_copy_bytes_to_smc(rdev, 1425 ret = kv_copy_bytes_to_smc(rdev,
1373 pi->dpm_table_start + 1426 pi->dpm_table_start +
1374 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), 1427 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
@@ -1377,11 +1430,9 @@ static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1377 if (ret) 1430 if (ret)
1378 return ret; 1431 return ret;
1379 1432
1380 if (!pi->caps_uvd_dpm || 1433 kv_send_msg_to_smc_with_parameter(rdev,
1381 pi->caps_stable_p_state) 1434 PPSMC_MSG_UVDDPM_SetEnabledMask,
1382 kv_send_msg_to_smc_with_parameter(rdev, 1435 mask);
1383 PPSMC_MSG_UVDDPM_SetEnabledMask,
1384 (1 << pi->uvd_boot_level));
1385 } 1436 }
1386 1437
1387 return kv_enable_uvd_dpm(rdev, !gate); 1438 return kv_enable_uvd_dpm(rdev, !gate);
@@ -1617,7 +1668,7 @@ static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1617 if (pi->acp_power_gated == gate) 1668 if (pi->acp_power_gated == gate)
1618 return; 1669 return;
1619 1670
1620 if (rdev->family == CHIP_KABINI) 1671 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1621 return; 1672 return;
1622 1673
1623 pi->acp_power_gated = gate; 1674 pi->acp_power_gated = gate;
@@ -1786,7 +1837,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
1786 } 1837 }
1787 } 1838 }
1788 1839
1789 if (rdev->family == CHIP_KABINI) { 1840 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1790 if (pi->enable_dpm) { 1841 if (pi->enable_dpm) {
1791 kv_set_valid_clock_range(rdev, new_ps); 1842 kv_set_valid_clock_range(rdev, new_ps);
1792 kv_update_dfs_bypass_settings(rdev, new_ps); 1843 kv_update_dfs_bypass_settings(rdev, new_ps);
@@ -1812,6 +1863,8 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
1812 return ret; 1863 return ret;
1813 } 1864 }
1814 kv_update_sclk_t(rdev); 1865 kv_update_sclk_t(rdev);
1866 if (rdev->family == CHIP_MULLINS)
1867 kv_enable_nb_dpm(rdev);
1815 } 1868 }
1816 } else { 1869 } else {
1817 if (pi->enable_dpm) { 1870 if (pi->enable_dpm) {
@@ -1862,7 +1915,7 @@ void kv_dpm_reset_asic(struct radeon_device *rdev)
1862{ 1915{
1863 struct kv_power_info *pi = kv_get_pi(rdev); 1916 struct kv_power_info *pi = kv_get_pi(rdev);
1864 1917
1865 if (rdev->family == CHIP_KABINI) { 1918 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
1866 kv_force_lowest_valid(rdev); 1919 kv_force_lowest_valid(rdev);
1867 kv_init_graphics_levels(rdev); 1920 kv_init_graphics_levels(rdev);
1868 kv_program_bootup_state(rdev); 1921 kv_program_bootup_state(rdev);
@@ -1901,14 +1954,41 @@ static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1901static void kv_patch_voltage_values(struct radeon_device *rdev) 1954static void kv_patch_voltage_values(struct radeon_device *rdev)
1902{ 1955{
1903 int i; 1956 int i;
1904 struct radeon_uvd_clock_voltage_dependency_table *table = 1957 struct radeon_uvd_clock_voltage_dependency_table *uvd_table =
1905 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1958 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1959 struct radeon_vce_clock_voltage_dependency_table *vce_table =
1960 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1961 struct radeon_clock_voltage_dependency_table *samu_table =
1962 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1963 struct radeon_clock_voltage_dependency_table *acp_table =
1964 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1906 1965
1907 if (table->count) { 1966 if (uvd_table->count) {
1908 for (i = 0; i < table->count; i++) 1967 for (i = 0; i < uvd_table->count; i++)
1909 table->entries[i].v = 1968 uvd_table->entries[i].v =
1910 kv_convert_8bit_index_to_voltage(rdev, 1969 kv_convert_8bit_index_to_voltage(rdev,
1911 table->entries[i].v); 1970 uvd_table->entries[i].v);
1971 }
1972
1973 if (vce_table->count) {
1974 for (i = 0; i < vce_table->count; i++)
1975 vce_table->entries[i].v =
1976 kv_convert_8bit_index_to_voltage(rdev,
1977 vce_table->entries[i].v);
1978 }
1979
1980 if (samu_table->count) {
1981 for (i = 0; i < samu_table->count; i++)
1982 samu_table->entries[i].v =
1983 kv_convert_8bit_index_to_voltage(rdev,
1984 samu_table->entries[i].v);
1985 }
1986
1987 if (acp_table->count) {
1988 for (i = 0; i < acp_table->count; i++)
1989 acp_table->entries[i].v =
1990 kv_convert_8bit_index_to_voltage(rdev,
1991 acp_table->entries[i].v);
1912 } 1992 }
1913 1993
1914} 1994}
@@ -1941,7 +2021,7 @@ static int kv_force_dpm_highest(struct radeon_device *rdev)
1941 break; 2021 break;
1942 } 2022 }
1943 2023
1944 if (rdev->family == CHIP_KABINI) 2024 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1945 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2025 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1946 else 2026 else
1947 return kv_set_enabled_level(rdev, i); 2027 return kv_set_enabled_level(rdev, i);
@@ -1961,7 +2041,7 @@ static int kv_force_dpm_lowest(struct radeon_device *rdev)
1961 break; 2041 break;
1962 } 2042 }
1963 2043
1964 if (rdev->family == CHIP_KABINI) 2044 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
1965 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); 2045 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1966 else 2046 else
1967 return kv_set_enabled_level(rdev, i); 2047 return kv_set_enabled_level(rdev, i);
@@ -2118,7 +2198,7 @@ static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2118 else 2198 else
2119 pi->battery_state = false; 2199 pi->battery_state = false;
2120 2200
2121 if (rdev->family == CHIP_KABINI) { 2201 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2122 ps->dpm0_pg_nb_ps_lo = 0x1; 2202 ps->dpm0_pg_nb_ps_lo = 0x1;
2123 ps->dpm0_pg_nb_ps_hi = 0x0; 2203 ps->dpm0_pg_nb_ps_hi = 0x0;
2124 ps->dpmx_nb_ps_lo = 0x1; 2204 ps->dpmx_nb_ps_lo = 0x1;
@@ -2179,7 +2259,7 @@ static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2179 if (pi->lowest_valid > pi->highest_valid) 2259 if (pi->lowest_valid > pi->highest_valid)
2180 return -EINVAL; 2260 return -EINVAL;
2181 2261
2182 if (rdev->family == CHIP_KABINI) { 2262 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) {
2183 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2263 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2184 pi->graphics_level[i].GnbSlow = 1; 2264 pi->graphics_level[i].GnbSlow = 1;
2185 pi->graphics_level[i].ForceNbPs1 = 0; 2265 pi->graphics_level[i].ForceNbPs1 = 0;
@@ -2253,9 +2333,9 @@ static void kv_init_graphics_levels(struct radeon_device *rdev)
2253 break; 2333 break;
2254 2334
2255 kv_set_divider_value(rdev, i, table->entries[i].clk); 2335 kv_set_divider_value(rdev, i, table->entries[i].clk);
2256 vid_2bit = sumo_convert_vid7_to_vid2(rdev, 2336 vid_2bit = kv_convert_vid7_to_vid2(rdev,
2257 &pi->sys_info.vid_mapping_table, 2337 &pi->sys_info.vid_mapping_table,
2258 table->entries[i].v); 2338 table->entries[i].v);
2259 kv_set_vid(rdev, i, vid_2bit); 2339 kv_set_vid(rdev, i, vid_2bit);
2260 kv_set_at(rdev, i, pi->at[i]); 2340 kv_set_at(rdev, i, pi->at[i]);
2261 kv_dpm_power_level_enabled_for_throttle(rdev, i, true); 2341 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
@@ -2324,7 +2404,7 @@ static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2324 struct kv_power_info *pi = kv_get_pi(rdev); 2404 struct kv_power_info *pi = kv_get_pi(rdev);
2325 u32 nbdpmconfig1; 2405 u32 nbdpmconfig1;
2326 2406
2327 if (rdev->family == CHIP_KABINI) 2407 if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2328 return; 2408 return;
2329 2409
2330 if (pi->sys_info.nb_dpm_enable) { 2410 if (pi->sys_info.nb_dpm_enable) {
@@ -2631,9 +2711,6 @@ int kv_dpm_init(struct radeon_device *rdev)
2631 2711
2632 pi->sram_end = SMC_RAM_END; 2712 pi->sram_end = SMC_RAM_END;
2633 2713
2634 if (rdev->family == CHIP_KABINI)
2635 pi->high_voltage_t = 4001;
2636
2637 pi->enable_nb_dpm = true; 2714 pi->enable_nb_dpm = true;
2638 2715
2639 pi->caps_power_containment = true; 2716 pi->caps_power_containment = true;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6e887d004eba..bbc189fd3ddc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2839,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
2839 r = radeon_fence_emit(rdev, fence, ring->idx); 2839 r = radeon_fence_emit(rdev, fence, ring->idx);
2840 if (r) { 2840 if (r) {
2841 radeon_ring_unlock_undo(rdev, ring); 2841 radeon_ring_unlock_undo(rdev, ring);
2842 radeon_semaphore_free(rdev, &sem, NULL);
2842 return r; 2843 return r;
2843 } 2844 }
2844 2845
@@ -3505,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev)
3505 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3506 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3506 u32 grbm_int_cntl = 0; 3507 u32 grbm_int_cntl = 0;
3507 u32 hdmi0, hdmi1; 3508 u32 hdmi0, hdmi1;
3508 u32 d1grph = 0, d2grph = 0;
3509 u32 dma_cntl; 3509 u32 dma_cntl;
3510 u32 thermal_int = 0; 3510 u32 thermal_int = 0;
3511 3511
@@ -3614,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev)
3614 WREG32(CP_INT_CNTL, cp_int_cntl); 3614 WREG32(CP_INT_CNTL, cp_int_cntl);
3615 WREG32(DMA_CNTL, dma_cntl); 3615 WREG32(DMA_CNTL, dma_cntl);
3616 WREG32(DxMODE_INT_MASK, mode_int); 3616 WREG32(DxMODE_INT_MASK, mode_int);
3617 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3617 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3618 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3618 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3619 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3619 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3620 if (ASIC_IS_DCE3(rdev)) { 3620 if (ASIC_IS_DCE3(rdev)) {
3621 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3621 WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -3918,6 +3918,14 @@ restart_ih:
3918 break; 3918 break;
3919 } 3919 }
3920 break; 3920 break;
3921 case 9: /* D1 pflip */
3922 DRM_DEBUG("IH: D1 flip\n");
3923 radeon_crtc_handle_flip(rdev, 0);
3924 break;
3925 case 11: /* D2 pflip */
3926 DRM_DEBUG("IH: D2 flip\n");
3927 radeon_crtc_handle_flip(rdev, 1);
3928 break;
3921 case 19: /* HPD/DAC hotplug */ 3929 case 19: /* HPD/DAC hotplug */
3922 switch (src_data) { 3930 switch (src_data) {
3923 case 0: 3931 case 0:
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index 53fcb28f5578..4969cef44a19 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -489,6 +489,7 @@ int r600_copy_dma(struct radeon_device *rdev,
489 r = radeon_fence_emit(rdev, fence, ring->idx); 489 r = radeon_fence_emit(rdev, fence, ring->idx);
490 if (r) { 490 if (r) {
491 radeon_ring_unlock_undo(rdev, ring); 491 radeon_ring_unlock_undo(rdev, ring);
492 radeon_semaphore_free(rdev, &sem, NULL);
492 return r; 493 return r;
493 } 494 }
494 495
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index cbf7e3269f84..9c61b74ef441 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -158,16 +158,18 @@ u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
158 u32 line_time_us, vblank_lines; 158 u32 line_time_us, vblank_lines;
159 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */ 159 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
160 160
161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 161 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
162 radeon_crtc = to_radeon_crtc(crtc); 162 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
163 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 163 radeon_crtc = to_radeon_crtc(crtc);
164 line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) / 164 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
165 radeon_crtc->hw_mode.clock; 165 line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
166 vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end - 166 radeon_crtc->hw_mode.clock;
167 radeon_crtc->hw_mode.crtc_vdisplay + 167 vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
168 (radeon_crtc->v_border * 2); 168 radeon_crtc->hw_mode.crtc_vdisplay +
169 vblank_time_us = vblank_lines * line_time_us; 169 (radeon_crtc->v_border * 2);
170 break; 170 vblank_time_us = vblank_lines * line_time_us;
171 break;
172 }
171 } 173 }
172 } 174 }
173 175
@@ -181,14 +183,15 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
181 struct radeon_crtc *radeon_crtc; 183 struct radeon_crtc *radeon_crtc;
182 u32 vrefresh = 0; 184 u32 vrefresh = 0;
183 185
184 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 186 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
185 radeon_crtc = to_radeon_crtc(crtc); 187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
186 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 188 radeon_crtc = to_radeon_crtc(crtc);
187 vrefresh = radeon_crtc->hw_mode.vrefresh; 189 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
188 break; 190 vrefresh = radeon_crtc->hw_mode.vrefresh;
191 break;
192 }
189 } 193 }
190 } 194 }
191
192 return vrefresh; 195 return vrefresh;
193} 196}
194 197
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f21db7a0b34d..68528619834a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -730,6 +730,12 @@ struct cik_irq_stat_regs {
730 u32 disp_int_cont4; 730 u32 disp_int_cont4;
731 u32 disp_int_cont5; 731 u32 disp_int_cont5;
732 u32 disp_int_cont6; 732 u32 disp_int_cont6;
733 u32 d1grph_int;
734 u32 d2grph_int;
735 u32 d3grph_int;
736 u32 d4grph_int;
737 u32 d5grph_int;
738 u32 d6grph_int;
733}; 739};
734 740
735union radeon_irq_stat_regs { 741union radeon_irq_stat_regs {
@@ -739,7 +745,7 @@ union radeon_irq_stat_regs {
739 struct cik_irq_stat_regs cik; 745 struct cik_irq_stat_regs cik;
740}; 746};
741 747
742#define RADEON_MAX_HPD_PINS 6 748#define RADEON_MAX_HPD_PINS 7
743#define RADEON_MAX_CRTCS 6 749#define RADEON_MAX_CRTCS 6
744#define RADEON_MAX_AFMT_BLOCKS 7 750#define RADEON_MAX_AFMT_BLOCKS 7
745 751
@@ -2321,6 +2327,7 @@ struct radeon_device {
2321 bool have_disp_power_ref; 2327 bool have_disp_power_ref;
2322}; 2328};
2323 2329
2330bool radeon_is_px(struct drm_device *dev);
2324int radeon_device_init(struct radeon_device *rdev, 2331int radeon_device_init(struct radeon_device *rdev,
2325 struct drm_device *ddev, 2332 struct drm_device *ddev,
2326 struct pci_dev *pdev, 2333 struct pci_dev *pdev,
@@ -2631,6 +2638,9 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
2631#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2638#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2632#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2639#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2633#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2640#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2641#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2642#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2643#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI))
2634 2644
2635#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2645#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2636 (rdev->ddev->pdev->device == 0x6850) || \ 2646 (rdev->ddev->pdev->device == 0x6850) || \
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index b8a24a75d4ff..be20e62dac83 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2516,6 +2516,7 @@ int radeon_asic_init(struct radeon_device *rdev)
2516 break; 2516 break;
2517 case CHIP_KAVERI: 2517 case CHIP_KAVERI:
2518 case CHIP_KABINI: 2518 case CHIP_KABINI:
2519 case CHIP_MULLINS:
2519 rdev->asic = &kv_asic; 2520 rdev->asic = &kv_asic;
2520 /* set num crtcs */ 2521 /* set num crtcs */
2521 if (rdev->family == CHIP_KAVERI) { 2522 if (rdev->family == CHIP_KAVERI) {
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index fa9a9c02751e..a9fb0d016d38 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -59,7 +59,7 @@ struct atpx_mux {
59 u16 mux; 59 u16 mux;
60} __packed; 60} __packed;
61 61
62bool radeon_is_px(void) { 62bool radeon_has_atpx(void) {
63 return radeon_atpx_priv.atpx_detected; 63 return radeon_atpx_priv.atpx_detected;
64} 64}
65 65
@@ -528,6 +528,13 @@ static bool radeon_atpx_detect(void)
528 has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true); 528 has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
529 } 529 }
530 530
531 /* some newer PX laptops mark the dGPU as a non-VGA display device */
532 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
533 vga_count++;
534
535 has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
536 }
537
531 if (has_atpx && vga_count == 2) { 538 if (has_atpx && vga_count == 2) {
532 acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer); 539 acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
533 printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n", 540 printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n",
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index c566b486ca08..ea50e0ae7bf7 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1261,21 +1261,6 @@ static const struct drm_connector_funcs radeon_dvi_connector_funcs = {
1261 .force = radeon_dvi_force, 1261 .force = radeon_dvi_force,
1262}; 1262};
1263 1263
1264static void radeon_dp_connector_destroy(struct drm_connector *connector)
1265{
1266 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1267 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1268
1269 if (radeon_connector->edid)
1270 kfree(radeon_connector->edid);
1271 if (radeon_dig_connector->dp_i2c_bus)
1272 radeon_i2c_destroy(radeon_dig_connector->dp_i2c_bus);
1273 kfree(radeon_connector->con_priv);
1274 drm_sysfs_connector_remove(connector);
1275 drm_connector_cleanup(connector);
1276 kfree(connector);
1277}
1278
1279static int radeon_dp_get_modes(struct drm_connector *connector) 1264static int radeon_dp_get_modes(struct drm_connector *connector)
1280{ 1265{
1281 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1266 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1553,7 +1538,7 @@ static const struct drm_connector_funcs radeon_dp_connector_funcs = {
1553 .detect = radeon_dp_detect, 1538 .detect = radeon_dp_detect,
1554 .fill_modes = drm_helper_probe_single_connector_modes, 1539 .fill_modes = drm_helper_probe_single_connector_modes,
1555 .set_property = radeon_connector_set_property, 1540 .set_property = radeon_connector_set_property,
1556 .destroy = radeon_dp_connector_destroy, 1541 .destroy = radeon_connector_destroy,
1557 .force = radeon_dvi_force, 1542 .force = radeon_dvi_force,
1558}; 1543};
1559 1544
@@ -1562,7 +1547,7 @@ static const struct drm_connector_funcs radeon_edp_connector_funcs = {
1562 .detect = radeon_dp_detect, 1547 .detect = radeon_dp_detect,
1563 .fill_modes = drm_helper_probe_single_connector_modes, 1548 .fill_modes = drm_helper_probe_single_connector_modes,
1564 .set_property = radeon_lvds_set_property, 1549 .set_property = radeon_lvds_set_property,
1565 .destroy = radeon_dp_connector_destroy, 1550 .destroy = radeon_connector_destroy,
1566 .force = radeon_dvi_force, 1551 .force = radeon_dvi_force,
1567}; 1552};
1568 1553
@@ -1571,7 +1556,7 @@ static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
1571 .detect = radeon_dp_detect, 1556 .detect = radeon_dp_detect,
1572 .fill_modes = drm_helper_probe_single_connector_modes, 1557 .fill_modes = drm_helper_probe_single_connector_modes,
1573 .set_property = radeon_lvds_set_property, 1558 .set_property = radeon_lvds_set_property,
1574 .destroy = radeon_dp_connector_destroy, 1559 .destroy = radeon_connector_destroy,
1575 .force = radeon_dvi_force, 1560 .force = radeon_dvi_force,
1576}; 1561};
1577 1562
@@ -1668,17 +1653,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1668 radeon_dig_connector->igp_lane_info = igp_lane_info; 1653 radeon_dig_connector->igp_lane_info = igp_lane_info;
1669 radeon_connector->con_priv = radeon_dig_connector; 1654 radeon_connector->con_priv = radeon_dig_connector;
1670 if (i2c_bus->valid) { 1655 if (i2c_bus->valid) {
1671 /* add DP i2c bus */ 1656 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1672 if (connector_type == DRM_MODE_CONNECTOR_eDP) 1657 if (radeon_connector->ddc_bus)
1673 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1674 else
1675 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1676 if (radeon_dig_connector->dp_i2c_bus)
1677 has_aux = true; 1658 has_aux = true;
1678 else 1659 else
1679 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1680 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1681 if (!radeon_connector->ddc_bus)
1682 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1660 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1683 } 1661 }
1684 switch (connector_type) { 1662 switch (connector_type) {
@@ -1893,10 +1871,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1893 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type); 1871 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
1894 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); 1872 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1895 if (i2c_bus->valid) { 1873 if (i2c_bus->valid) {
1896 /* add DP i2c bus */
1897 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1898 if (!radeon_dig_connector->dp_i2c_bus)
1899 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1900 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); 1874 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1901 if (radeon_connector->ddc_bus) 1875 if (radeon_connector->ddc_bus)
1902 has_aux = true; 1876 has_aux = true;
@@ -1942,14 +1916,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1942 drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type); 1916 drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type);
1943 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); 1917 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
1944 if (i2c_bus->valid) { 1918 if (i2c_bus->valid) {
1945 /* add DP i2c bus */ 1919 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1946 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch"); 1920 if (radeon_connector->ddc_bus)
1947 if (radeon_dig_connector->dp_i2c_bus)
1948 has_aux = true; 1921 has_aux = true;
1949 else 1922 else
1950 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1951 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1952 if (!radeon_connector->ddc_bus)
1953 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1923 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1954 } 1924 }
1955 drm_object_attach_property(&radeon_connector->base.base, 1925 drm_object_attach_property(&radeon_connector->base.base,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 835516d2d257..0e770bbf7e29 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -99,14 +99,18 @@ static const char radeon_family_name[][16] = {
99 "KAVERI", 99 "KAVERI",
100 "KABINI", 100 "KABINI",
101 "HAWAII", 101 "HAWAII",
102 "MULLINS",
102 "LAST", 103 "LAST",
103}; 104};
104 105
105#if defined(CONFIG_VGA_SWITCHEROO) 106bool radeon_is_px(struct drm_device *dev)
106bool radeon_is_px(void); 107{
107#else 108 struct radeon_device *rdev = dev->dev_private;
108static inline bool radeon_is_px(void) { return false; } 109
109#endif 110 if (rdev->flags & RADEON_IS_PX)
111 return true;
112 return false;
113}
110 114
111/** 115/**
112 * radeon_program_register_sequence - program an array of registers. 116 * radeon_program_register_sequence - program an array of registers.
@@ -1082,7 +1086,7 @@ static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
1082{ 1086{
1083 struct drm_device *dev = pci_get_drvdata(pdev); 1087 struct drm_device *dev = pci_get_drvdata(pdev);
1084 1088
1085 if (radeon_is_px() && state == VGA_SWITCHEROO_OFF) 1089 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1086 return; 1090 return;
1087 1091
1088 if (state == VGA_SWITCHEROO_ON) { 1092 if (state == VGA_SWITCHEROO_ON) {
@@ -1301,9 +1305,7 @@ int radeon_device_init(struct radeon_device *rdev,
1301 * ignore it */ 1305 * ignore it */
1302 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1306 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1303 1307
1304 if (radeon_runtime_pm == 1) 1308 if (rdev->flags & RADEON_IS_PX)
1305 runtime = true;
1306 if ((radeon_runtime_pm == -1) && radeon_is_px())
1307 runtime = true; 1309 runtime = true;
1308 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1310 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1309 if (runtime) 1311 if (runtime)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 386cfa4c194d..408b6ac53f0b 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -284,6 +284,10 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
284 u32 update_pending; 284 u32 update_pending;
285 int vpos, hpos; 285 int vpos, hpos;
286 286
287 /* can happen during initialization */
288 if (radeon_crtc == NULL)
289 return;
290
287 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 291 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
288 work = radeon_crtc->unpin_work; 292 work = radeon_crtc->unpin_work;
289 if (work == NULL || 293 if (work == NULL ||
@@ -759,19 +763,18 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
759 763
760 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != 764 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
761 ENCODER_OBJECT_ID_NONE) { 765 ENCODER_OBJECT_ID_NONE) {
762 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 766 if (radeon_connector->ddc_bus->has_aux)
763
764 if (dig->dp_i2c_bus)
765 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 767 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
766 &dig->dp_i2c_bus->adapter); 768 &radeon_connector->ddc_bus->aux.ddc);
767 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 769 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
768 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 770 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
769 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 771 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
770 772
771 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 773 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
772 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 774 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
775 radeon_connector->ddc_bus->has_aux)
773 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 776 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
774 &dig->dp_i2c_bus->adapter); 777 &radeon_connector->ddc_bus->aux.ddc);
775 else if (radeon_connector->ddc_bus && !radeon_connector->edid) 778 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
776 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 779 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
777 &radeon_connector->ddc_bus->adapter); 780 &radeon_connector->ddc_bus->adapter);
@@ -827,20 +830,52 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
827 830
828 /* make sure nominator is large enough */ 831 /* make sure nominator is large enough */
829 if (*nom < nom_min) { 832 if (*nom < nom_min) {
830 tmp = (nom_min + *nom - 1) / *nom; 833 tmp = DIV_ROUND_UP(nom_min, *nom);
831 *nom *= tmp; 834 *nom *= tmp;
832 *den *= tmp; 835 *den *= tmp;
833 } 836 }
834 837
835 /* make sure the denominator is large enough */ 838 /* make sure the denominator is large enough */
836 if (*den < den_min) { 839 if (*den < den_min) {
837 tmp = (den_min + *den - 1) / *den; 840 tmp = DIV_ROUND_UP(den_min, *den);
838 *nom *= tmp; 841 *nom *= tmp;
839 *den *= tmp; 842 *den *= tmp;
840 } 843 }
841} 844}
842 845
843/** 846/**
847 * avivo_get_fb_ref_div - feedback and ref divider calculation
848 *
849 * @nom: nominator
850 * @den: denominator
851 * @post_div: post divider
852 * @fb_div_max: feedback divider maximum
853 * @ref_div_max: reference divider maximum
854 * @fb_div: resulting feedback divider
855 * @ref_div: resulting reference divider
856 *
857 * Calculate feedback and reference divider for a given post divider. Makes
858 * sure we stay within the limits.
859 */
860static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
861 unsigned fb_div_max, unsigned ref_div_max,
862 unsigned *fb_div, unsigned *ref_div)
863{
864 /* limit reference * post divider to a maximum */
865 ref_div_max = min(128 / post_div, ref_div_max);
866
867 /* get matching reference and feedback divider */
868 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
869 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
870
871 /* limit fb divider to its maximum */
872 if (*fb_div > fb_div_max) {
873 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
874 *fb_div = fb_div_max;
875 }
876}
877
878/**
844 * radeon_compute_pll_avivo - compute PLL paramaters 879 * radeon_compute_pll_avivo - compute PLL paramaters
845 * 880 *
846 * @pll: information about the PLL 881 * @pll: information about the PLL
@@ -861,11 +896,14 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
861 u32 *ref_div_p, 896 u32 *ref_div_p,
862 u32 *post_div_p) 897 u32 *post_div_p)
863{ 898{
899 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
900 freq : freq / 10;
901
864 unsigned fb_div_min, fb_div_max, fb_div; 902 unsigned fb_div_min, fb_div_max, fb_div;
865 unsigned post_div_min, post_div_max, post_div; 903 unsigned post_div_min, post_div_max, post_div;
866 unsigned ref_div_min, ref_div_max, ref_div; 904 unsigned ref_div_min, ref_div_max, ref_div;
867 unsigned post_div_best, diff_best; 905 unsigned post_div_best, diff_best;
868 unsigned nom, den, tmp; 906 unsigned nom, den;
869 907
870 /* determine allowed feedback divider range */ 908 /* determine allowed feedback divider range */
871 fb_div_min = pll->min_feedback_div; 909 fb_div_min = pll->min_feedback_div;
@@ -881,14 +919,18 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
881 ref_div_min = pll->reference_div; 919 ref_div_min = pll->reference_div;
882 else 920 else
883 ref_div_min = pll->min_ref_div; 921 ref_div_min = pll->min_ref_div;
884 ref_div_max = pll->max_ref_div; 922
923 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
924 pll->flags & RADEON_PLL_USE_REF_DIV)
925 ref_div_max = pll->reference_div;
926 else
927 ref_div_max = pll->max_ref_div;
885 928
886 /* determine allowed post divider range */ 929 /* determine allowed post divider range */
887 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 930 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
888 post_div_min = pll->post_div; 931 post_div_min = pll->post_div;
889 post_div_max = pll->post_div; 932 post_div_max = pll->post_div;
890 } else { 933 } else {
891 unsigned target_clock = freq / 10;
892 unsigned vco_min, vco_max; 934 unsigned vco_min, vco_max;
893 935
894 if (pll->flags & RADEON_PLL_IS_LCD) { 936 if (pll->flags & RADEON_PLL_IS_LCD) {
@@ -899,6 +941,11 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
899 vco_max = pll->pll_out_max; 941 vco_max = pll->pll_out_max;
900 } 942 }
901 943
944 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
945 vco_min *= 10;
946 vco_max *= 10;
947 }
948
902 post_div_min = vco_min / target_clock; 949 post_div_min = vco_min / target_clock;
903 if ((target_clock * post_div_min) < vco_min) 950 if ((target_clock * post_div_min) < vco_min)
904 ++post_div_min; 951 ++post_div_min;
@@ -913,7 +960,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
913 } 960 }
914 961
915 /* represent the searched ratio as fractional number */ 962 /* represent the searched ratio as fractional number */
916 nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10; 963 nom = target_clock;
917 den = pll->reference_freq; 964 den = pll->reference_freq;
918 965
919 /* reduce the numbers to a simpler ratio */ 966 /* reduce the numbers to a simpler ratio */
@@ -927,7 +974,12 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
927 diff_best = ~0; 974 diff_best = ~0;
928 975
929 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 976 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
930 unsigned diff = abs(den - den / post_div * post_div); 977 unsigned diff;
978 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
979 ref_div_max, &fb_div, &ref_div);
980 diff = abs(target_clock - (pll->reference_freq * fb_div) /
981 (ref_div * post_div));
982
931 if (diff < diff_best || (diff == diff_best && 983 if (diff < diff_best || (diff == diff_best &&
932 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 984 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
933 985
@@ -937,29 +989,24 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
937 } 989 }
938 post_div = post_div_best; 990 post_div = post_div_best;
939 991
940 /* get matching reference and feedback divider */ 992 /* get the feedback and reference divider for the optimal value */
941 ref_div = max(den / post_div, 1u); 993 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
942 fb_div = nom; 994 &fb_div, &ref_div);
943
944 /* we're almost done, but reference and feedback
945 divider might be to large now */
946
947 tmp = ref_div;
948
949 if (fb_div > fb_div_max) {
950 ref_div = ref_div * fb_div_max / fb_div;
951 fb_div = fb_div_max;
952 }
953
954 if (ref_div > ref_div_max) {
955 ref_div = ref_div_max;
956 fb_div = nom * ref_div_max / tmp;
957 }
958 995
959 /* reduce the numbers to a simpler ratio once more */ 996 /* reduce the numbers to a simpler ratio once more */
960 /* this also makes sure that the reference divider is large enough */ 997 /* this also makes sure that the reference divider is large enough */
961 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 998 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
962 999
1000 /* avoid high jitter with small fractional dividers */
1001 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1002 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
1003 if (fb_div < fb_div_min) {
1004 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1005 fb_div *= tmp;
1006 ref_div *= tmp;
1007 }
1008 }
1009
963 /* and finally save the result */ 1010 /* and finally save the result */
964 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1011 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
965 *fb_div_p = fb_div / 10; 1012 *fb_div_p = fb_div / 10;
@@ -976,7 +1023,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
976 *post_div_p = post_div; 1023 *post_div_p = post_div;
977 1024
978 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1025 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
979 freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p, 1026 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
980 ref_div, post_div); 1027 ref_div, post_div);
981} 1028}
982 1029
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index d0eba48dd74e..c00a2f585185 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -115,6 +115,7 @@ extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
115 unsigned int flags, 115 unsigned int flags,
116 int *vpos, int *hpos, ktime_t *stime, 116 int *vpos, int *hpos, ktime_t *stime,
117 ktime_t *etime); 117 ktime_t *etime);
118extern bool radeon_is_px(struct drm_device *dev);
118extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 119extern const struct drm_ioctl_desc radeon_ioctls_kms[];
119extern int radeon_max_kms_ioctl; 120extern int radeon_max_kms_ioctl;
120int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 121int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
@@ -144,11 +145,9 @@ void radeon_debugfs_cleanup(struct drm_minor *minor);
144#if defined(CONFIG_VGA_SWITCHEROO) 145#if defined(CONFIG_VGA_SWITCHEROO)
145void radeon_register_atpx_handler(void); 146void radeon_register_atpx_handler(void);
146void radeon_unregister_atpx_handler(void); 147void radeon_unregister_atpx_handler(void);
147bool radeon_is_px(void);
148#else 148#else
149static inline void radeon_register_atpx_handler(void) {} 149static inline void radeon_register_atpx_handler(void) {}
150static inline void radeon_unregister_atpx_handler(void) {} 150static inline void radeon_unregister_atpx_handler(void) {}
151static inline bool radeon_is_px(void) { return false; }
152#endif 151#endif
153 152
154int radeon_no_wb; 153int radeon_no_wb;
@@ -186,7 +185,7 @@ module_param_named(dynclks, radeon_dynclks, int, 0444);
186MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 185MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
187module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 186module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
188 187
189MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); 188MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
190module_param_named(vramlimit, radeon_vram_limit, int, 0600); 189module_param_named(vramlimit, radeon_vram_limit, int, 0600);
191 190
192MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 191MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
@@ -405,12 +404,7 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
405 struct drm_device *drm_dev = pci_get_drvdata(pdev); 404 struct drm_device *drm_dev = pci_get_drvdata(pdev);
406 int ret; 405 int ret;
407 406
408 if (radeon_runtime_pm == 0) { 407 if (!radeon_is_px(drm_dev)) {
409 pm_runtime_forbid(dev);
410 return -EBUSY;
411 }
412
413 if (radeon_runtime_pm == -1 && !radeon_is_px()) {
414 pm_runtime_forbid(dev); 408 pm_runtime_forbid(dev);
415 return -EBUSY; 409 return -EBUSY;
416 } 410 }
@@ -434,10 +428,7 @@ static int radeon_pmops_runtime_resume(struct device *dev)
434 struct drm_device *drm_dev = pci_get_drvdata(pdev); 428 struct drm_device *drm_dev = pci_get_drvdata(pdev);
435 int ret; 429 int ret;
436 430
437 if (radeon_runtime_pm == 0) 431 if (!radeon_is_px(drm_dev))
438 return -EINVAL;
439
440 if (radeon_runtime_pm == -1 && !radeon_is_px())
441 return -EINVAL; 432 return -EINVAL;
442 433
443 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 434 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
@@ -462,14 +453,7 @@ static int radeon_pmops_runtime_idle(struct device *dev)
462 struct drm_device *drm_dev = pci_get_drvdata(pdev); 453 struct drm_device *drm_dev = pci_get_drvdata(pdev);
463 struct drm_crtc *crtc; 454 struct drm_crtc *crtc;
464 455
465 if (radeon_runtime_pm == 0) { 456 if (!radeon_is_px(drm_dev)) {
466 pm_runtime_forbid(dev);
467 return -EBUSY;
468 }
469
470 /* are we PX enabled? */
471 if (radeon_runtime_pm == -1 && !radeon_is_px()) {
472 DRM_DEBUG_DRIVER("failing to power off - not px\n");
473 pm_runtime_forbid(dev); 457 pm_runtime_forbid(dev);
474 return -EBUSY; 458 return -EBUSY;
475 } 459 }
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 614ad549297f..4b7b87f71a63 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -97,6 +97,7 @@ enum radeon_family {
97 CHIP_KAVERI, 97 CHIP_KAVERI,
98 CHIP_KABINI, 98 CHIP_KABINI,
99 CHIP_HAWAII, 99 CHIP_HAWAII,
100 CHIP_MULLINS,
100 CHIP_LAST, 101 CHIP_LAST,
101}; 102};
102 103
@@ -115,6 +116,7 @@ enum radeon_chip_flags {
115 RADEON_NEW_MEMMAP = 0x00400000UL, 116 RADEON_NEW_MEMMAP = 0x00400000UL,
116 RADEON_IS_PCI = 0x00800000UL, 117 RADEON_IS_PCI = 0x00800000UL,
117 RADEON_IS_IGPGART = 0x01000000UL, 118 RADEON_IS_IGPGART = 0x01000000UL,
119 RADEON_IS_PX = 0x02000000UL,
118}; 120};
119 121
120#endif 122#endif
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index e24ca6ab96de..7b944142a9fd 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -64,8 +64,7 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
64 radeon_router_select_ddc_port(radeon_connector); 64 radeon_router_select_ddc_port(radeon_connector);
65 65
66 if (use_aux) { 66 if (use_aux) {
67 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 67 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
68 ret = i2c_transfer(&dig->dp_i2c_bus->adapter, msgs, 2);
69 } else { 68 } else {
70 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 69 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
71 } 70 }
@@ -950,16 +949,16 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
950 /* set the radeon bit adapter */ 949 /* set the radeon bit adapter */
951 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 950 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
952 "Radeon i2c bit bus %s", name); 951 "Radeon i2c bit bus %s", name);
953 i2c->adapter.algo_data = &i2c->algo.bit; 952 i2c->adapter.algo_data = &i2c->bit;
954 i2c->algo.bit.pre_xfer = pre_xfer; 953 i2c->bit.pre_xfer = pre_xfer;
955 i2c->algo.bit.post_xfer = post_xfer; 954 i2c->bit.post_xfer = post_xfer;
956 i2c->algo.bit.setsda = set_data; 955 i2c->bit.setsda = set_data;
957 i2c->algo.bit.setscl = set_clock; 956 i2c->bit.setscl = set_clock;
958 i2c->algo.bit.getsda = get_data; 957 i2c->bit.getsda = get_data;
959 i2c->algo.bit.getscl = get_clock; 958 i2c->bit.getscl = get_clock;
960 i2c->algo.bit.udelay = 10; 959 i2c->bit.udelay = 10;
961 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 960 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
962 i2c->algo.bit.data = i2c; 961 i2c->bit.data = i2c;
963 ret = i2c_bit_add_bus(&i2c->adapter); 962 ret = i2c_bit_add_bus(&i2c->adapter);
964 if (ret) { 963 if (ret) {
965 DRM_ERROR("Failed to register bit i2c %s\n", name); 964 DRM_ERROR("Failed to register bit i2c %s\n", name);
@@ -974,46 +973,13 @@ out_free:
974 973
975} 974}
976 975
977struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
978 struct radeon_i2c_bus_rec *rec,
979 const char *name)
980{
981 struct radeon_i2c_chan *i2c;
982 int ret;
983
984 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
985 if (i2c == NULL)
986 return NULL;
987
988 i2c->rec = *rec;
989 i2c->adapter.owner = THIS_MODULE;
990 i2c->adapter.class = I2C_CLASS_DDC;
991 i2c->adapter.dev.parent = &dev->pdev->dev;
992 i2c->dev = dev;
993 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
994 "Radeon aux bus %s", name);
995 i2c_set_adapdata(&i2c->adapter, i2c);
996 i2c->adapter.algo_data = &i2c->algo.dp;
997 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
998 i2c->algo.dp.address = 0;
999 ret = i2c_dp_aux_add_bus(&i2c->adapter);
1000 if (ret) {
1001 DRM_INFO("Failed to register i2c %s\n", name);
1002 goto out_free;
1003 }
1004
1005 return i2c;
1006out_free:
1007 kfree(i2c);
1008 return NULL;
1009
1010}
1011
1012void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 976void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1013{ 977{
1014 if (!i2c) 978 if (!i2c)
1015 return; 979 return;
1016 i2c_del_adapter(&i2c->adapter); 980 i2c_del_adapter(&i2c->adapter);
981 if (i2c->has_aux)
982 drm_dp_aux_unregister_i2c_bus(&i2c->aux);
1017 kfree(i2c); 983 kfree(i2c);
1018} 984}
1019 985
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 3e49342a20e6..0cc47f12d995 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -35,9 +35,9 @@
35#include <linux/pm_runtime.h> 35#include <linux/pm_runtime.h>
36 36
37#if defined(CONFIG_VGA_SWITCHEROO) 37#if defined(CONFIG_VGA_SWITCHEROO)
38bool radeon_is_px(void); 38bool radeon_has_atpx(void);
39#else 39#else
40static inline bool radeon_is_px(void) { return false; } 40static inline bool radeon_has_atpx(void) { return false; }
41#endif 41#endif
42 42
43/** 43/**
@@ -107,6 +107,11 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
107 flags |= RADEON_IS_PCI; 107 flags |= RADEON_IS_PCI;
108 } 108 }
109 109
110 if ((radeon_runtime_pm != 0) &&
111 radeon_has_atpx() &&
112 ((flags & RADEON_IS_IGP) == 0))
113 flags |= RADEON_IS_PX;
114
110 /* radeon_device_init should report only fatal error 115 /* radeon_device_init should report only fatal error
111 * like memory allocation failure or iomapping failure, 116 * like memory allocation failure or iomapping failure,
112 * or memory manager initialization failure, it must 117 * or memory manager initialization failure, it must
@@ -137,8 +142,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
137 "Error during ACPI methods call\n"); 142 "Error during ACPI methods call\n");
138 } 143 }
139 144
140 if ((radeon_runtime_pm == 1) || 145 if (radeon_is_px(dev)) {
141 ((radeon_runtime_pm == -1) && radeon_is_px())) {
142 pm_runtime_use_autosuspend(dev->dev); 146 pm_runtime_use_autosuspend(dev->dev);
143 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 147 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
144 pm_runtime_set_active(dev->dev); 148 pm_runtime_set_active(dev->dev);
@@ -568,12 +572,17 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
568 } 572 }
569 573
570 r = radeon_vm_init(rdev, &fpriv->vm); 574 r = radeon_vm_init(rdev, &fpriv->vm);
571 if (r) 575 if (r) {
576 kfree(fpriv);
572 return r; 577 return r;
578 }
573 579
574 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 580 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
575 if (r) 581 if (r) {
582 radeon_vm_fini(rdev, &fpriv->vm);
583 kfree(fpriv);
576 return r; 584 return r;
585 }
577 586
578 /* map the ib pool buffer read only into 587 /* map the ib pool buffer read only into
579 * virtual address space */ 588 * virtual address space */
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 832d9fa1a4c4..6ddf31a2d34e 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -187,12 +187,10 @@ struct radeon_pll {
187struct radeon_i2c_chan { 187struct radeon_i2c_chan {
188 struct i2c_adapter adapter; 188 struct i2c_adapter adapter;
189 struct drm_device *dev; 189 struct drm_device *dev;
190 union { 190 struct i2c_algo_bit_data bit;
191 struct i2c_algo_bit_data bit;
192 struct i2c_algo_dp_aux_data dp;
193 } algo;
194 struct radeon_i2c_bus_rec rec; 191 struct radeon_i2c_bus_rec rec;
195 struct drm_dp_aux aux; 192 struct drm_dp_aux aux;
193 bool has_aux;
196}; 194};
197 195
198/* mostly for macs, but really any system without connector tables */ 196/* mostly for macs, but really any system without connector tables */
@@ -440,7 +438,6 @@ struct radeon_encoder {
440struct radeon_connector_atom_dig { 438struct radeon_connector_atom_dig {
441 uint32_t igp_lane_info; 439 uint32_t igp_lane_info;
442 /* displayport */ 440 /* displayport */
443 struct radeon_i2c_chan *dp_i2c_bus;
444 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 441 u8 dpcd[DP_RECEIVER_CAP_SIZE];
445 u8 dp_sink_type; 442 u8 dp_sink_type;
446 int dp_clock; 443 int dp_clock;
@@ -702,8 +699,6 @@ extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
702 uint8_t lane_set); 699 uint8_t lane_set);
703extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 700extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
704extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 701extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
705extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
706 u8 write_byte, u8 *read_byte);
707void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 702void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
708 703
709extern void radeon_i2c_init(struct radeon_device *rdev); 704extern void radeon_i2c_init(struct radeon_device *rdev);
@@ -715,9 +710,6 @@ extern void radeon_i2c_add(struct radeon_device *rdev,
715 const char *name); 710 const char *name);
716extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 711extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
717 struct radeon_i2c_bus_rec *i2c_bus); 712 struct radeon_i2c_bus_rec *i2c_bus);
718extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
719 struct radeon_i2c_bus_rec *rec,
720 const char *name);
721extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 713extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
722 struct radeon_i2c_bus_rec *rec, 714 struct radeon_i2c_bus_rec *rec,
723 const char *name); 715 const char *name);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index ee738a524639..f30b8426eee2 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -603,7 +603,6 @@ static const struct attribute_group *hwmon_groups[] = {
603static int radeon_hwmon_init(struct radeon_device *rdev) 603static int radeon_hwmon_init(struct radeon_device *rdev)
604{ 604{
605 int err = 0; 605 int err = 0;
606 struct device *hwmon_dev;
607 606
608 switch (rdev->pm.int_thermal_type) { 607 switch (rdev->pm.int_thermal_type) {
609 case THERMAL_TYPE_RV6XX: 608 case THERMAL_TYPE_RV6XX:
@@ -616,11 +615,11 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
616 case THERMAL_TYPE_KV: 615 case THERMAL_TYPE_KV:
617 if (rdev->asic->pm.get_temperature == NULL) 616 if (rdev->asic->pm.get_temperature == NULL)
618 return err; 617 return err;
619 hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 618 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
620 "radeon", rdev, 619 "radeon", rdev,
621 hwmon_groups); 620 hwmon_groups);
622 if (IS_ERR(hwmon_dev)) { 621 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
623 err = PTR_ERR(hwmon_dev); 622 err = PTR_ERR(rdev->pm.int_hwmon_dev);
624 dev_err(rdev->dev, 623 dev_err(rdev->dev,
625 "Unable to register hwmon device: %d\n", err); 624 "Unable to register hwmon device: %d\n", err);
626 } 625 }
@@ -632,6 +631,12 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
632 return err; 631 return err;
633} 632}
634 633
634static void radeon_hwmon_fini(struct radeon_device *rdev)
635{
636 if (rdev->pm.int_hwmon_dev)
637 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
638}
639
635static void radeon_dpm_thermal_work_handler(struct work_struct *work) 640static void radeon_dpm_thermal_work_handler(struct work_struct *work)
636{ 641{
637 struct radeon_device *rdev = 642 struct radeon_device *rdev =
@@ -1257,6 +1262,7 @@ int radeon_pm_init(struct radeon_device *rdev)
1257 case CHIP_RV670: 1262 case CHIP_RV670:
1258 case CHIP_RS780: 1263 case CHIP_RS780:
1259 case CHIP_RS880: 1264 case CHIP_RS880:
1265 case CHIP_RV770:
1260 case CHIP_BARTS: 1266 case CHIP_BARTS:
1261 case CHIP_TURKS: 1267 case CHIP_TURKS:
1262 case CHIP_CAICOS: 1268 case CHIP_CAICOS:
@@ -1273,7 +1279,6 @@ int radeon_pm_init(struct radeon_device *rdev)
1273 else 1279 else
1274 rdev->pm.pm_method = PM_METHOD_PROFILE; 1280 rdev->pm.pm_method = PM_METHOD_PROFILE;
1275 break; 1281 break;
1276 case CHIP_RV770:
1277 case CHIP_RV730: 1282 case CHIP_RV730:
1278 case CHIP_RV710: 1283 case CHIP_RV710:
1279 case CHIP_RV740: 1284 case CHIP_RV740:
@@ -1295,6 +1300,7 @@ int radeon_pm_init(struct radeon_device *rdev)
1295 case CHIP_KABINI: 1300 case CHIP_KABINI:
1296 case CHIP_KAVERI: 1301 case CHIP_KAVERI:
1297 case CHIP_HAWAII: 1302 case CHIP_HAWAII:
1303 case CHIP_MULLINS:
1298 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1304 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1299 if (!rdev->rlc_fw) 1305 if (!rdev->rlc_fw)
1300 rdev->pm.pm_method = PM_METHOD_PROFILE; 1306 rdev->pm.pm_method = PM_METHOD_PROFILE;
@@ -1353,6 +1359,8 @@ static void radeon_pm_fini_old(struct radeon_device *rdev)
1353 device_remove_file(rdev->dev, &dev_attr_power_method); 1359 device_remove_file(rdev->dev, &dev_attr_power_method);
1354 } 1360 }
1355 1361
1362 radeon_hwmon_fini(rdev);
1363
1356 if (rdev->pm.power_state) 1364 if (rdev->pm.power_state)
1357 kfree(rdev->pm.power_state); 1365 kfree(rdev->pm.power_state);
1358} 1366}
@@ -1372,6 +1380,8 @@ static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1372 } 1380 }
1373 radeon_dpm_fini(rdev); 1381 radeon_dpm_fini(rdev);
1374 1382
1383 radeon_hwmon_fini(rdev);
1384
1375 if (rdev->pm.power_state) 1385 if (rdev->pm.power_state)
1376 kfree(rdev->pm.power_state); 1386 kfree(rdev->pm.power_state);
1377} 1387}
@@ -1397,12 +1407,14 @@ static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1397 1407
1398 rdev->pm.active_crtcs = 0; 1408 rdev->pm.active_crtcs = 0;
1399 rdev->pm.active_crtc_count = 0; 1409 rdev->pm.active_crtc_count = 0;
1400 list_for_each_entry(crtc, 1410 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1401 &ddev->mode_config.crtc_list, head) { 1411 list_for_each_entry(crtc,
1402 radeon_crtc = to_radeon_crtc(crtc); 1412 &ddev->mode_config.crtc_list, head) {
1403 if (radeon_crtc->enabled) { 1413 radeon_crtc = to_radeon_crtc(crtc);
1404 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1414 if (radeon_crtc->enabled) {
1405 rdev->pm.active_crtc_count++; 1415 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1416 rdev->pm.active_crtc_count++;
1417 }
1406 } 1418 }
1407 } 1419 }
1408 1420
@@ -1469,12 +1481,14 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1469 /* update active crtc counts */ 1481 /* update active crtc counts */
1470 rdev->pm.dpm.new_active_crtcs = 0; 1482 rdev->pm.dpm.new_active_crtcs = 0;
1471 rdev->pm.dpm.new_active_crtc_count = 0; 1483 rdev->pm.dpm.new_active_crtc_count = 0;
1472 list_for_each_entry(crtc, 1484 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1473 &ddev->mode_config.crtc_list, head) { 1485 list_for_each_entry(crtc,
1474 radeon_crtc = to_radeon_crtc(crtc); 1486 &ddev->mode_config.crtc_list, head) {
1475 if (crtc->enabled) { 1487 radeon_crtc = to_radeon_crtc(crtc);
1476 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1488 if (crtc->enabled) {
1477 rdev->pm.dpm.new_active_crtc_count++; 1489 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1490 rdev->pm.dpm.new_active_crtc_count++;
1491 }
1478 } 1492 }
1479 } 1493 }
1480 1494
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
index a77cd274dfc3..4e7c3269b183 100644
--- a/drivers/gpu/drm/radeon/radeon_ucode.h
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -52,14 +52,20 @@
52#define BONAIRE_RLC_UCODE_SIZE 2048 52#define BONAIRE_RLC_UCODE_SIZE 2048
53#define KB_RLC_UCODE_SIZE 2560 53#define KB_RLC_UCODE_SIZE 2560
54#define KV_RLC_UCODE_SIZE 2560 54#define KV_RLC_UCODE_SIZE 2560
55#define ML_RLC_UCODE_SIZE 2560
55 56
56/* MC */ 57/* MC */
57#define BTC_MC_UCODE_SIZE 6024 58#define BTC_MC_UCODE_SIZE 6024
58#define CAYMAN_MC_UCODE_SIZE 6037 59#define CAYMAN_MC_UCODE_SIZE 6037
59#define SI_MC_UCODE_SIZE 7769 60#define SI_MC_UCODE_SIZE 7769
61#define TAHITI_MC_UCODE_SIZE 7808
62#define PITCAIRN_MC_UCODE_SIZE 7775
63#define VERDE_MC_UCODE_SIZE 7875
60#define OLAND_MC_UCODE_SIZE 7863 64#define OLAND_MC_UCODE_SIZE 7863
61#define CIK_MC_UCODE_SIZE 7866 65#define BONAIRE_MC_UCODE_SIZE 7866
66#define BONAIRE_MC2_UCODE_SIZE 7948
62#define HAWAII_MC_UCODE_SIZE 7933 67#define HAWAII_MC_UCODE_SIZE 7933
68#define HAWAII_MC2_UCODE_SIZE 8091
63 69
64/* SDMA */ 70/* SDMA */
65#define CIK_SDMA_UCODE_SIZE 1050 71#define CIK_SDMA_UCODE_SIZE 1050
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 5748bdaeacce..1b65ae2433cd 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -99,6 +99,7 @@ int radeon_uvd_init(struct radeon_device *rdev)
99 case CHIP_KABINI: 99 case CHIP_KABINI:
100 case CHIP_KAVERI: 100 case CHIP_KAVERI:
101 case CHIP_HAWAII: 101 case CHIP_HAWAII:
102 case CHIP_MULLINS:
102 fw_name = FIRMWARE_BONAIRE; 103 fw_name = FIRMWARE_BONAIRE;
103 break; 104 break;
104 105
@@ -465,6 +466,10 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
465 cmd = radeon_get_ib_value(p, p->idx) >> 1; 466 cmd = radeon_get_ib_value(p, p->idx) >> 1;
466 467
467 if (cmd < 0x4) { 468 if (cmd < 0x4) {
469 if (end <= start) {
470 DRM_ERROR("invalid reloc offset %X!\n", offset);
471 return -EINVAL;
472 }
468 if ((end - start) < buf_sizes[cmd]) { 473 if ((end - start) < buf_sizes[cmd]) {
469 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 474 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
470 (unsigned)(end - start), buf_sizes[cmd]); 475 (unsigned)(end - start), buf_sizes[cmd]);
diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c
index 76e9904bc537..f73324c81491 100644
--- a/drivers/gpu/drm/radeon/radeon_vce.c
+++ b/drivers/gpu/drm/radeon/radeon_vce.c
@@ -66,6 +66,7 @@ int radeon_vce_init(struct radeon_device *rdev)
66 case CHIP_BONAIRE: 66 case CHIP_BONAIRE:
67 case CHIP_KAVERI: 67 case CHIP_KAVERI:
68 case CHIP_KABINI: 68 case CHIP_KABINI:
69 case CHIP_MULLINS:
69 fw_name = FIRMWARE_BONAIRE; 70 fw_name = FIRMWARE_BONAIRE;
70 break; 71 break;
71 72
@@ -613,7 +614,7 @@ void radeon_vce_fence_emit(struct radeon_device *rdev,
613 struct radeon_fence *fence) 614 struct radeon_fence *fence)
614{ 615{
615 struct radeon_ring *ring = &rdev->ring[fence->ring]; 616 struct radeon_ring *ring = &rdev->ring[fence->ring];
616 uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr; 617 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
617 618
618 radeon_ring_write(ring, VCE_CMD_FENCE); 619 radeon_ring_write(ring, VCE_CMD_FENCE);
619 radeon_ring_write(ring, addr); 620 radeon_ring_write(ring, addr);
diff --git a/drivers/gpu/drm/radeon/rv770_dma.c b/drivers/gpu/drm/radeon/rv770_dma.c
index aca8cbe8a335..bbf2e076ee45 100644
--- a/drivers/gpu/drm/radeon/rv770_dma.c
+++ b/drivers/gpu/drm/radeon/rv770_dma.c
@@ -86,6 +86,7 @@ int rv770_copy_dma(struct radeon_device *rdev,
86 r = radeon_fence_emit(rdev, fence, ring->idx); 86 r = radeon_fence_emit(rdev, fence, ring->idx);
87 if (r) { 87 if (r) {
88 radeon_ring_unlock_undo(rdev, ring); 88 radeon_ring_unlock_undo(rdev, ring);
89 radeon_semaphore_free(rdev, &sem, NULL);
89 return r; 90 return r;
90 } 91 }
91 92
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index d589475fe9e6..22a63c98ba14 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -39,30 +39,35 @@ MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
39MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 39MODULE_FIRMWARE("radeon/TAHITI_me.bin");
40MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 40MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
41MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 41MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
42MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
42MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 43MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
43MODULE_FIRMWARE("radeon/TAHITI_smc.bin"); 44MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
44MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 45MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
45MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 46MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
46MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 47MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 48MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 50MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin"); 51MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
50MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 52MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
51MODULE_FIRMWARE("radeon/VERDE_me.bin"); 53MODULE_FIRMWARE("radeon/VERDE_me.bin");
52MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 54MODULE_FIRMWARE("radeon/VERDE_ce.bin");
53MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 55MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
54MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 57MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
55MODULE_FIRMWARE("radeon/VERDE_smc.bin"); 58MODULE_FIRMWARE("radeon/VERDE_smc.bin");
56MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 59MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
57MODULE_FIRMWARE("radeon/OLAND_me.bin"); 60MODULE_FIRMWARE("radeon/OLAND_me.bin");
58MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 61MODULE_FIRMWARE("radeon/OLAND_ce.bin");
59MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 62MODULE_FIRMWARE("radeon/OLAND_mc.bin");
63MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
60MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 64MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
61MODULE_FIRMWARE("radeon/OLAND_smc.bin"); 65MODULE_FIRMWARE("radeon/OLAND_smc.bin");
62MODULE_FIRMWARE("radeon/HAINAN_pfp.bin"); 66MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
63MODULE_FIRMWARE("radeon/HAINAN_me.bin"); 67MODULE_FIRMWARE("radeon/HAINAN_me.bin");
64MODULE_FIRMWARE("radeon/HAINAN_ce.bin"); 68MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
65MODULE_FIRMWARE("radeon/HAINAN_mc.bin"); 69MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
70MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
66MODULE_FIRMWARE("radeon/HAINAN_rlc.bin"); 71MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
67MODULE_FIRMWARE("radeon/HAINAN_smc.bin"); 72MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
68 73
@@ -1467,36 +1472,33 @@ int si_mc_load_microcode(struct radeon_device *rdev)
1467 const __be32 *fw_data; 1472 const __be32 *fw_data;
1468 u32 running, blackout = 0; 1473 u32 running, blackout = 0;
1469 u32 *io_mc_regs; 1474 u32 *io_mc_regs;
1470 int i, ucode_size, regs_size; 1475 int i, regs_size, ucode_size;
1471 1476
1472 if (!rdev->mc_fw) 1477 if (!rdev->mc_fw)
1473 return -EINVAL; 1478 return -EINVAL;
1474 1479
1480 ucode_size = rdev->mc_fw->size / 4;
1481
1475 switch (rdev->family) { 1482 switch (rdev->family) {
1476 case CHIP_TAHITI: 1483 case CHIP_TAHITI:
1477 io_mc_regs = (u32 *)&tahiti_io_mc_regs; 1484 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1478 ucode_size = SI_MC_UCODE_SIZE;
1479 regs_size = TAHITI_IO_MC_REGS_SIZE; 1485 regs_size = TAHITI_IO_MC_REGS_SIZE;
1480 break; 1486 break;
1481 case CHIP_PITCAIRN: 1487 case CHIP_PITCAIRN:
1482 io_mc_regs = (u32 *)&pitcairn_io_mc_regs; 1488 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1483 ucode_size = SI_MC_UCODE_SIZE;
1484 regs_size = TAHITI_IO_MC_REGS_SIZE; 1489 regs_size = TAHITI_IO_MC_REGS_SIZE;
1485 break; 1490 break;
1486 case CHIP_VERDE: 1491 case CHIP_VERDE:
1487 default: 1492 default:
1488 io_mc_regs = (u32 *)&verde_io_mc_regs; 1493 io_mc_regs = (u32 *)&verde_io_mc_regs;
1489 ucode_size = SI_MC_UCODE_SIZE;
1490 regs_size = TAHITI_IO_MC_REGS_SIZE; 1494 regs_size = TAHITI_IO_MC_REGS_SIZE;
1491 break; 1495 break;
1492 case CHIP_OLAND: 1496 case CHIP_OLAND:
1493 io_mc_regs = (u32 *)&oland_io_mc_regs; 1497 io_mc_regs = (u32 *)&oland_io_mc_regs;
1494 ucode_size = OLAND_MC_UCODE_SIZE;
1495 regs_size = TAHITI_IO_MC_REGS_SIZE; 1498 regs_size = TAHITI_IO_MC_REGS_SIZE;
1496 break; 1499 break;
1497 case CHIP_HAINAN: 1500 case CHIP_HAINAN:
1498 io_mc_regs = (u32 *)&hainan_io_mc_regs; 1501 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1499 ucode_size = OLAND_MC_UCODE_SIZE;
1500 regs_size = TAHITI_IO_MC_REGS_SIZE; 1502 regs_size = TAHITI_IO_MC_REGS_SIZE;
1501 break; 1503 break;
1502 } 1504 }
@@ -1552,7 +1554,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1552 const char *chip_name; 1554 const char *chip_name;
1553 const char *rlc_chip_name; 1555 const char *rlc_chip_name;
1554 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 1556 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1555 size_t smc_req_size; 1557 size_t smc_req_size, mc2_req_size;
1556 char fw_name[30]; 1558 char fw_name[30];
1557 int err; 1559 int err;
1558 1560
@@ -1567,6 +1569,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1567 ce_req_size = SI_CE_UCODE_SIZE * 4; 1569 ce_req_size = SI_CE_UCODE_SIZE * 4;
1568 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1570 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1569 mc_req_size = SI_MC_UCODE_SIZE * 4; 1571 mc_req_size = SI_MC_UCODE_SIZE * 4;
1572 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1570 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4); 1573 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1571 break; 1574 break;
1572 case CHIP_PITCAIRN: 1575 case CHIP_PITCAIRN:
@@ -1577,6 +1580,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1577 ce_req_size = SI_CE_UCODE_SIZE * 4; 1580 ce_req_size = SI_CE_UCODE_SIZE * 4;
1578 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1581 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1579 mc_req_size = SI_MC_UCODE_SIZE * 4; 1582 mc_req_size = SI_MC_UCODE_SIZE * 4;
1583 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1580 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4); 1584 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1581 break; 1585 break;
1582 case CHIP_VERDE: 1586 case CHIP_VERDE:
@@ -1587,6 +1591,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1587 ce_req_size = SI_CE_UCODE_SIZE * 4; 1591 ce_req_size = SI_CE_UCODE_SIZE * 4;
1588 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1592 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1589 mc_req_size = SI_MC_UCODE_SIZE * 4; 1593 mc_req_size = SI_MC_UCODE_SIZE * 4;
1594 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1590 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4); 1595 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1591 break; 1596 break;
1592 case CHIP_OLAND: 1597 case CHIP_OLAND:
@@ -1596,7 +1601,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1596 me_req_size = SI_PM4_UCODE_SIZE * 4; 1601 me_req_size = SI_PM4_UCODE_SIZE * 4;
1597 ce_req_size = SI_CE_UCODE_SIZE * 4; 1602 ce_req_size = SI_CE_UCODE_SIZE * 4;
1598 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1603 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1599 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1604 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1600 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4); 1605 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1601 break; 1606 break;
1602 case CHIP_HAINAN: 1607 case CHIP_HAINAN:
@@ -1606,7 +1611,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1606 me_req_size = SI_PM4_UCODE_SIZE * 4; 1611 me_req_size = SI_PM4_UCODE_SIZE * 4;
1607 ce_req_size = SI_CE_UCODE_SIZE * 4; 1612 ce_req_size = SI_CE_UCODE_SIZE * 4;
1608 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1613 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1609 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1614 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1610 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4); 1615 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1611 break; 1616 break;
1612 default: BUG(); 1617 default: BUG();
@@ -1659,16 +1664,22 @@ static int si_init_microcode(struct radeon_device *rdev)
1659 err = -EINVAL; 1664 err = -EINVAL;
1660 } 1665 }
1661 1666
1662 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 1667 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1663 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 1668 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1664 if (err) 1669 if (err) {
1665 goto out; 1670 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1666 if (rdev->mc_fw->size != mc_req_size) { 1671 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1672 if (err)
1673 goto out;
1674 }
1675 if ((rdev->mc_fw->size != mc_req_size) &&
1676 (rdev->mc_fw->size != mc2_req_size)) {
1667 printk(KERN_ERR 1677 printk(KERN_ERR
1668 "si_mc: Bogus length %zu in firmware \"%s\"\n", 1678 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1669 rdev->mc_fw->size, fw_name); 1679 rdev->mc_fw->size, fw_name);
1670 err = -EINVAL; 1680 err = -EINVAL;
1671 } 1681 }
1682 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1672 1683
1673 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 1684 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1674 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 1685 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
@@ -5769,7 +5780,6 @@ int si_irq_set(struct radeon_device *rdev)
5769 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 5780 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
5770 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; 5781 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
5771 u32 grbm_int_cntl = 0; 5782 u32 grbm_int_cntl = 0;
5772 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
5773 u32 dma_cntl, dma_cntl1; 5783 u32 dma_cntl, dma_cntl1;
5774 u32 thermal_int = 0; 5784 u32 thermal_int = 0;
5775 5785
@@ -5908,16 +5918,22 @@ int si_irq_set(struct radeon_device *rdev)
5908 } 5918 }
5909 5919
5910 if (rdev->num_crtc >= 2) { 5920 if (rdev->num_crtc >= 2) {
5911 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 5921 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
5912 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 5922 GRPH_PFLIP_INT_MASK);
5923 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
5924 GRPH_PFLIP_INT_MASK);
5913 } 5925 }
5914 if (rdev->num_crtc >= 4) { 5926 if (rdev->num_crtc >= 4) {
5915 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 5927 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
5916 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 5928 GRPH_PFLIP_INT_MASK);
5929 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
5930 GRPH_PFLIP_INT_MASK);
5917 } 5931 }
5918 if (rdev->num_crtc >= 6) { 5932 if (rdev->num_crtc >= 6) {
5919 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 5933 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
5920 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 5934 GRPH_PFLIP_INT_MASK);
5935 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
5936 GRPH_PFLIP_INT_MASK);
5921 } 5937 }
5922 5938
5923 if (!ASIC_IS_NODCE(rdev)) { 5939 if (!ASIC_IS_NODCE(rdev)) {
@@ -6281,6 +6297,15 @@ restart_ih:
6281 break; 6297 break;
6282 } 6298 }
6283 break; 6299 break;
6300 case 8: /* D1 page flip */
6301 case 10: /* D2 page flip */
6302 case 12: /* D3 page flip */
6303 case 14: /* D4 page flip */
6304 case 16: /* D5 page flip */
6305 case 18: /* D6 page flip */
6306 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6307 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6308 break;
6284 case 42: /* HPD hotplug */ 6309 case 42: /* HPD hotplug */
6285 switch (src_data) { 6310 switch (src_data) {
6286 case 0: 6311 case 0:
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index cf0fdad8c278..de0ca070122f 100644
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -213,6 +213,7 @@ int si_copy_dma(struct radeon_device *rdev,
213 r = radeon_fence_emit(rdev, fence, ring->idx); 213 r = radeon_fence_emit(rdev, fence, ring->idx);
214 if (r) { 214 if (r) {
215 radeon_ring_unlock_undo(rdev, ring); 215 radeon_ring_unlock_undo(rdev, ring);
216 radeon_semaphore_free(rdev, &sem, NULL);
216 return r; 217 return r;
217 } 218 }
218 219
diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 0a243f0e5d68..be42c8125203 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -83,7 +83,10 @@ int uvd_v1_0_init(struct radeon_device *rdev)
83 int r; 83 int r;
84 84
85 /* raise clocks while booting up the VCPU */ 85 /* raise clocks while booting up the VCPU */
86 radeon_set_uvd_clocks(rdev, 53300, 40000); 86 if (rdev->family < CHIP_RV740)
87 radeon_set_uvd_clocks(rdev, 10000, 10000);
88 else
89 radeon_set_uvd_clocks(rdev, 53300, 40000);
87 90
88 r = uvd_v1_0_start(rdev); 91 r = uvd_v1_0_start(rdev);
89 if (r) 92 if (r)
@@ -407,7 +410,10 @@ int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
407 struct radeon_fence *fence = NULL; 410 struct radeon_fence *fence = NULL;
408 int r; 411 int r;
409 412
410 r = radeon_set_uvd_clocks(rdev, 53300, 40000); 413 if (rdev->family < CHIP_RV740)
414 r = radeon_set_uvd_clocks(rdev, 10000, 10000);
415 else
416 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
411 if (r) { 417 if (r) {
412 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); 418 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
413 return r; 419 return r;
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-20 10:19:59 -0400