55 files changed, 2584 insertions, 1110 deletions

diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 5982321be4d5..1c02d23f6fcc 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,10 +1,14 @@
 config DRM_RADEON_KMS
-        bool "Enable modesetting on radeon by default"
+        bool "Enable modesetting on radeon by default - NEW DRIVER"
         depends on DRM_RADEON
         help
-          Choose this option if you want kernel modesetting enabled by default,
-          and you have a new enough userspace to support this. Running old
-          userspaces with this enabled will cause pain.
+          Choose this option if you want kernel modesetting enabled by default.
+
+          This is a completely new driver. It's only part of the existing drm
+          for compatibility reasons. It requires an entirely different graphics
+          stack above it and works very differently from the old drm stack.
+          i.e. don't enable this unless you know what you are doing it may
+          cause issues or bugs compared to the previous userspace driver stack.
 
           When kernel modesetting is enabled the IOCTL of radeon/drm
           driver are considered as invalid and an error message is printed
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index b5f5fe75e6af..1cc7b937b1ea 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -24,6 +24,9 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
 $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
         $(call if_changed,mkregtable)
 
+$(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable
+        $(call if_changed,mkregtable)
+
 $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
         $(call if_changed,mkregtable)
 
@@ -35,6 +38,8 @@ $(obj)/rv515.o: $(obj)/rv515_reg_safe.h
 
 $(obj)/r300.o: $(obj)/r300_reg_safe.h
 
+$(obj)/r420.o: $(obj)/r420_reg_safe.h
+
 $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
 
 radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h
index 6d0183c61d3b..c714179d1bfa 100644
--- a/drivers/gpu/drm/radeon/ObjectID.h
+++ b/drivers/gpu/drm/radeon/ObjectID.h
@@ -1,5 +1,5 @@
 /*
-* Copyright 2006-2007 Advanced Micro Devices, Inc.
+* Copyright 2006-2007 Advanced Micro Devices, Inc.  
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -41,14 +41,14 @@
 /****************************************************/
 /* Encoder Object ID Definition                     */
 /****************************************************/
-#define ENCODER_OBJECT_ID_NONE                    0x00
+#define ENCODER_OBJECT_ID_NONE                    0x00 
 
 /* Radeon Class Display Hardware */
 #define ENCODER_OBJECT_ID_INTERNAL_LVDS           0x01
 #define ENCODER_OBJECT_ID_INTERNAL_TMDS1          0x02
 #define ENCODER_OBJECT_ID_INTERNAL_TMDS2          0x03
 #define ENCODER_OBJECT_ID_INTERNAL_DAC1           0x04
-#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05  /* TV/CV DAC */
+#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05     /* TV/CV DAC */
 #define ENCODER_OBJECT_ID_INTERNAL_SDVOA          0x06
 #define ENCODER_OBJECT_ID_INTERNAL_SDVOB          0x07
 
@@ -56,11 +56,11 @@
 #define ENCODER_OBJECT_ID_SI170B                  0x08
 #define ENCODER_OBJECT_ID_CH7303                  0x09
 #define ENCODER_OBJECT_ID_CH7301                  0x0A
-#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B  /* This belongs to Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B    /* This belongs to Radeon Class Display Hardware */
 #define ENCODER_OBJECT_ID_EXTERNAL_SDVOA          0x0C
 #define ENCODER_OBJECT_ID_EXTERNAL_SDVOB          0x0D
 #define ENCODER_OBJECT_ID_TITFP513                0x0E
-#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F  /* not used for Radeon */
+#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F    /* not used for Radeon */
 #define ENCODER_OBJECT_ID_VT1623                  0x10
 #define ENCODER_OBJECT_ID_HDMI_SI1930             0x11
 #define ENCODER_OBJECT_ID_HDMI_INTERNAL           0x12
@@ -68,9 +68,9 @@
 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13
 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1    0x15
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
-#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
-#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
+#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
+#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
 #define ENCODER_OBJECT_ID_INTERNAL_DDI            0x19
 #define ENCODER_OBJECT_ID_VT1625                  0x1A
 #define ENCODER_OBJECT_ID_HDMI_SI1932             0x1B
@@ -86,7 +86,7 @@
 /****************************************************/
 /* Connector Object ID Definition                   */
 /****************************************************/
-#define CONNECTOR_OBJECT_ID_NONE                  0x00
+#define CONNECTOR_OBJECT_ID_NONE                  0x00 
 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I     0x01
 #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I       0x02
 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D     0x03
@@ -96,7 +96,7 @@
 #define CONNECTOR_OBJECT_ID_SVIDEO                0x07
 #define CONNECTOR_OBJECT_ID_YPbPr                 0x08
 #define CONNECTOR_OBJECT_ID_D_CONNECTOR           0x09
-#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
+#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
 #define CONNECTOR_OBJECT_ID_SCART                 0x0B
 #define CONNECTOR_OBJECT_ID_HDMI_TYPE_A           0x0C
 #define CONNECTOR_OBJECT_ID_HDMI_TYPE_B           0x0D
@@ -106,6 +106,8 @@
 #define CONNECTOR_OBJECT_ID_CROSSFIRE             0x11
 #define CONNECTOR_OBJECT_ID_HARDCODE_DVI          0x12
 #define CONNECTOR_OBJECT_ID_DISPLAYPORT           0x13
+#define CONNECTOR_OBJECT_ID_eDP                   0x14
+#define CONNECTOR_OBJECT_ID_MXM                   0x15
 
 /* deleted */
 
@@ -116,6 +118,14 @@
 #define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL                              0x01
 
 /****************************************************/
+/* Generic Object ID Definition                     */
+/****************************************************/
+#define GENERIC_OBJECT_ID_NONE                    0x00
+#define GENERIC_OBJECT_ID_GLSYNC                  0x01
+#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE        0x02
+#define GENERIC_OBJECT_ID_MXM_OPM                 0x03
+
+/****************************************************/
 /* Graphics Object ENUM ID Definition               */
 /****************************************************/
 #define GRAPH_OBJECT_ENUM_ID1                     0x01
@@ -124,6 +134,7 @@
 #define GRAPH_OBJECT_ENUM_ID4                     0x04
 #define GRAPH_OBJECT_ENUM_ID5                     0x05
 #define GRAPH_OBJECT_ENUM_ID6                     0x06
+#define GRAPH_OBJECT_ENUM_ID7                     0x07
 
 /****************************************************/
 /* Graphics Object ID Bit definition                */
@@ -133,35 +144,35 @@
 #define RESERVED1_ID_MASK                         0x0800
 #define OBJECT_TYPE_MASK                          0x7000
 #define RESERVED2_ID_MASK                         0x8000
-
+                                                  
 #define OBJECT_ID_SHIFT                           0x00
 #define ENUM_ID_SHIFT                             0x08
 #define OBJECT_TYPE_SHIFT                         0x0C
 
+
 /****************************************************/
 /* Graphics Object family definition                */
 /****************************************************/
-#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) \
-        (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
-         GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
+#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
+                                                                           GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
 /****************************************************/
 /* GPU Object ID definition - Shared with BIOS      */
 /****************************************************/
-#define GPU_ENUM_ID1    (GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
-                         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
+#define GPU_ENUM_ID1                            ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
 
 /****************************************************/
 /* Encoder Object ID definition - Shared with BIOS  */
 /****************************************************/
 /*
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101      
 #define ENCODER_INTERNAL_TMDS1_ENUM_ID1       0x2102
 #define ENCODER_INTERNAL_TMDS2_ENUM_ID1       0x2103
 #define ENCODER_INTERNAL_DAC1_ENUM_ID1        0x2104
 #define ENCODER_INTERNAL_DAC2_ENUM_ID1        0x2105
 #define ENCODER_INTERNAL_SDVOA_ENUM_ID1       0x2106
 #define ENCODER_INTERNAL_SDVOB_ENUM_ID1       0x2107
-#define ENCODER_SIL170B_ENUM_ID1              0x2108
+#define ENCODER_SIL170B_ENUM_ID1              0x2108  
 #define ENCODER_CH7303_ENUM_ID1               0x2109
 #define ENCODER_CH7301_ENUM_ID1               0x210A
 #define ENCODER_INTERNAL_DVO1_ENUM_ID1        0x210B
@@ -175,8 +186,8 @@
 #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   0x2113
 #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    0x2114
 #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    0x2115
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116
-#define ENCODER_SI178_ENUM_ID1                   0x2117
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116  
+#define ENCODER_SI178_ENUM_ID1                   0x2117 
 #define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
 #define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
 #define ENCODER_VT1625_ENUM_ID1                  0x211A
@@ -185,205 +196,169 @@
 #define ENCODER_DP_DP501_ENUM_ID1                0x211D
 #define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         0x211E
 */
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-#define ENCODER_SIL170B_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7303_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7301_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-#define ENCODER_TITFP513_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1623_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1930_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) /* Shared with CV/TV and CRT */
-
-#define ENCODER_SI178_ENUM_ID1  \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
-
-#define ENCODER_MVPU_FPGA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DDI_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1625_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1932_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_DP501_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_AN9801_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+#define ENCODER_SIL170B_ENUM_ID1           ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7303_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7301_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_TITFP513_ENUM_ID1          ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1623_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1930_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT)  // Shared with CV/TV and CRT
+
+#define ENCODER_SI178_ENUM_ID1                    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)  
+
+#define ENCODER_MVPU_FPGA_ENUM_ID1                ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DDI_ENUM_ID1     (  GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) 
+
+#define ENCODER_VT1625_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1932_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_DP501_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_AN9801_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)  
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
 
 /****************************************************/
 /* Connector Object ID definition - Shared with BIOS */
@@ -406,167 +381,253 @@
 #define CONNECTOR_7PIN_DIN_ENUM_ID1                 0x310F
 #define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1           0x3110
 */
-#define CONNECTOR_LVDS_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_COMPOSITE_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SVIDEO_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_YPbPr_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_D_CONNECTOR_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_9PIN_DIN_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SCART_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_7PIN_DIN_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID2 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID3 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID4 \
-        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
-         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+#define CONNECTOR_LVDS_ENUM_ID1                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_LVDS_ENUM_ID2                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID1              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID2              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_7PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+#define CONNECTOR_7PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID1        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID2        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID5         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID6         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_MXM_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_A
+
+#define CONNECTOR_MXM_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_B
+
+#define CONNECTOR_MXM_ENUM_ID3                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_C
+
+#define CONNECTOR_MXM_ENUM_ID4                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_D
+
+#define CONNECTOR_MXM_ENUM_ID5                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_TXxx
+
+#define CONNECTOR_MXM_ENUM_ID6                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_UXxx
+
+#define CONNECTOR_MXM_ENUM_ID7                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DAC
 
 /****************************************************/
 /* Router Object ID definition - Shared with BIOS   */
 /****************************************************/
-#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 \
-        (GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
-         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
-         ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
+#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1      ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
+                                                GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
 
 /* deleted */
 
 /****************************************************/
+/* Generic Object ID definition - Shared with BIOS  */
+/****************************************************/
+#define GENERICOBJECT_GLSYNC_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_MXM_OPM_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
+
+/****************************************************/
 /* Object Cap definition - Shared with BIOS         */
 /****************************************************/
 #define GRAPHICS_OBJECT_CAP_I2C                 0x00000001L
 #define GRAPHICS_OBJECT_CAP_TABLE_ID            0x00000002L
 
+
 #define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID                   0x01
 #define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID     0x02
 #define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID    0x03
@@ -575,4 +636,8 @@
 #pragma pack()
 #endif
 
-#endif /*GRAPHICTYPE */
+#endif  /*GRAPHICTYPE */
+
+
+
+
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 388140a7e651..7f152f66f196 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -24,6 +24,7 @@
 
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <asm/unaligned.h>
 
 #define ATOM_DEBUG
 
@@ -212,7 +213,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
         case ATOM_ARG_PS:
                 idx = U8(*ptr);
                 (*ptr)++;
-                val = le32_to_cpu(ctx->ps[idx]);
+                /* get_unaligned_le32 avoids unaligned accesses from atombios
+                 * tables, noticed on a DEC Alpha. */
+                val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
                 if (print)
                         DEBUG("PS[0x%02X,0x%04X]", idx, val);
                 break;
@@ -246,6 +249,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
                 case ATOM_WS_ATTRIBUTES:
                         val = gctx->io_attr;
                         break;
+                case ATOM_WS_REGPTR:
+                        val = gctx->reg_block;
+                        break;
                 default:
                         val = ctx->ws[idx];
                 }
@@ -385,6 +391,32 @@ static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
         return atom_get_src_int(ctx, attr, ptr, NULL, 1);
 }
 
+static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
+{
+        uint32_t val = 0xCDCDCDCD;
+
+        switch (align) {
+        case ATOM_SRC_DWORD:
+                val = U32(*ptr);
+                (*ptr) += 4;
+                break;
+        case ATOM_SRC_WORD0:
+        case ATOM_SRC_WORD8:
+        case ATOM_SRC_WORD16:
+                val = U16(*ptr);
+                (*ptr) += 2;
+                break;
+        case ATOM_SRC_BYTE0:
+        case ATOM_SRC_BYTE8:
+        case ATOM_SRC_BYTE16:
+        case ATOM_SRC_BYTE24:
+                val = U8(*ptr);
+                (*ptr)++;
+                break;
+        }
+        return val;
+}
+
 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
                              int *ptr, uint32_t *saved, int print)
 {
@@ -482,6 +514,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
                 case ATOM_WS_ATTRIBUTES:
                         gctx->io_attr = val;
                         break;
+                case ATOM_WS_REGPTR:
+                        gctx->reg_block = val;
+                        break;
                 default:
                         ctx->ws[idx] = val;
                 }
@@ -608,7 +643,7 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
         uint8_t count = U8((*ptr)++);
         SDEBUG("   count: %d\n", count);
         if (arg == ATOM_UNIT_MICROSEC)
-                schedule_timeout_uninterruptible(usecs_to_jiffies(count));
+                udelay(count);
         else
                 schedule_timeout_uninterruptible(msecs_to_jiffies(count));
 }
@@ -677,7 +712,7 @@ static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
         SDEBUG("   dst: ");
         dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
         SDEBUG("   src1: ");
-        src1 = atom_get_src(ctx, attr, ptr);
+        src1 = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
         SDEBUG("   src2: ");
         src2 = atom_get_src(ctx, attr, ptr);
         dst &= src1;
@@ -809,6 +844,38 @@ static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
         SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
 }
 
+static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++), shift;
+        uint32_t saved, dst;
+        int dptr = *ptr;
+        attr &= 0x38;
+        attr |= atom_def_dst[attr >> 3] << 6;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
+        SDEBUG("   shift: %d\n", shift);
+        dst <<= shift;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++), shift;
+        uint32_t saved, dst;
+        int dptr = *ptr;
+        attr &= 0x38;
+        attr |= atom_def_dst[attr >> 3] << 6;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
+        SDEBUG("   shift: %d\n", shift);
+        dst >>= shift;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
 {
         uint8_t attr = U8((*ptr)++), shift;
@@ -818,7 +885,7 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
         attr |= atom_def_dst[attr >> 3] << 6;
         SDEBUG("   dst: ");
         dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
-        shift = U8((*ptr)++);
+        shift = atom_get_src(ctx, attr, ptr);
         SDEBUG("   shift: %d\n", shift);
         dst <<= shift;
         SDEBUG("   dst: ");
@@ -834,7 +901,7 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
         attr |= atom_def_dst[attr >> 3] << 6;
         SDEBUG("   dst: ");
         dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
-        shift = U8((*ptr)++);
+        shift = atom_get_src(ctx, attr, ptr);
         SDEBUG("   shift: %d\n", shift);
         dst >>= shift;
         SDEBUG("   dst: ");
@@ -937,18 +1004,18 @@ static struct {
         atom_op_or, ATOM_ARG_FB}, {
         atom_op_or, ATOM_ARG_PLL}, {
         atom_op_or, ATOM_ARG_MC}, {
-        atom_op_shl, ATOM_ARG_REG}, {
-        atom_op_shl, ATOM_ARG_PS}, {
-        atom_op_shl, ATOM_ARG_WS}, {
-        atom_op_shl, ATOM_ARG_FB}, {
-        atom_op_shl, ATOM_ARG_PLL}, {
-        atom_op_shl, ATOM_ARG_MC}, {
-        atom_op_shr, ATOM_ARG_REG}, {
-        atom_op_shr, ATOM_ARG_PS}, {
-        atom_op_shr, ATOM_ARG_WS}, {
-        atom_op_shr, ATOM_ARG_FB}, {
-        atom_op_shr, ATOM_ARG_PLL}, {
-        atom_op_shr, ATOM_ARG_MC}, {
+        atom_op_shift_left, ATOM_ARG_REG}, {
+        atom_op_shift_left, ATOM_ARG_PS}, {
+        atom_op_shift_left, ATOM_ARG_WS}, {
+        atom_op_shift_left, ATOM_ARG_FB}, {
+        atom_op_shift_left, ATOM_ARG_PLL}, {
+        atom_op_shift_left, ATOM_ARG_MC}, {
+        atom_op_shift_right, ATOM_ARG_REG}, {
+        atom_op_shift_right, ATOM_ARG_PS}, {
+        atom_op_shift_right, ATOM_ARG_WS}, {
+        atom_op_shift_right, ATOM_ARG_FB}, {
+        atom_op_shift_right, ATOM_ARG_PLL}, {
+        atom_op_shift_right, ATOM_ARG_MC}, {
         atom_op_mul, ATOM_ARG_REG}, {
         atom_op_mul, ATOM_ARG_PS}, {
         atom_op_mul, ATOM_ARG_WS}, {
@@ -1058,8 +1125,6 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
 
         SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
 
-        /* reset reg block */
-        ctx->reg_block = 0;
         ectx.ctx = ctx;
         ectx.ps_shift = ps / 4;
         ectx.start = base;
@@ -1096,6 +1161,12 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
 void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
 {
         mutex_lock(&ctx->mutex);
+        /* reset reg block */
+        ctx->reg_block = 0;
+        /* reset fb window */
+        ctx->fb_base = 0;
+        /* reset io mode */
+        ctx->io_mode = ATOM_IO_MM;
         atom_execute_table_locked(ctx, index, params);
         mutex_unlock(&ctx->mutex);
 }
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 47fd943f6d14..bc73781423a1 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -91,6 +91,7 @@
 #define ATOM_WS_AND_MASK        0x45
 #define ATOM_WS_FB_WINDOW       0x46
 #define ATOM_WS_ATTRIBUTES      0x47
+#define ATOM_WS_REGPTR          0x48
 
 #define ATOM_IIO_NOP            0
 #define ATOM_IIO_START          1
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 260fcf59f00c..af464e351fbd 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -307,7 +307,6 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
         args.ucCRTC = radeon_crtc->crtc_id;
 
-        printk("executing set crtc dtd timing\n");
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
@@ -347,7 +346,6 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
         args.ucCRTC = radeon_crtc->crtc_id;
 
-        printk("executing set crtc timing\n");
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
@@ -409,59 +407,57 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
         }
 }
 
-void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+union adjust_pixel_clock {
+        ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
+};
+
+static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+                               struct drm_display_mode *mode,
+                               struct radeon_pll *pll)
 {
-        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
         struct drm_device *dev = crtc->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct drm_encoder *encoder = NULL;
         struct radeon_encoder *radeon_encoder = NULL;
-        uint8_t frev, crev;
-        int index;
-        SET_PIXEL_CLOCK_PS_ALLOCATION args;
-        PIXEL_CLOCK_PARAMETERS *spc1_ptr;
-        PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
-        PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
-        uint32_t pll_clock = mode->clock;
-        uint32_t adjusted_clock;
-        uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
-        struct radeon_pll *pll;
-        int pll_flags = 0;
+        u32 adjusted_clock = mode->clock;
 
-        memset(&args, 0, sizeof(args));
+        /* reset the pll flags */
+        pll->flags = 0;
 
         if (ASIC_IS_AVIVO(rdev)) {
                 if ((rdev->family == CHIP_RS600) ||
                     (rdev->family == CHIP_RS690) ||
                     (rdev->family == CHIP_RS740))
-                        pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
-                                      RADEON_PLL_PREFER_CLOSEST_LOWER);
+                        pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
+                                       RADEON_PLL_PREFER_CLOSEST_LOWER);
 
                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
-                        pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                        pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
                 else
-                        pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+                        pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
         } else {
-                pll_flags |= RADEON_PLL_LEGACY;
+                pll->flags |= RADEON_PLL_LEGACY;
 
                 if (mode->clock > 200000)       /* range limits??? */
-                        pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                        pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
                 else
-                        pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+                        pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
         }
 
         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                 if (encoder->crtc == crtc) {
-                        if (!ASIC_IS_AVIVO(rdev)) {
-                                if (encoder->encoder_type !=
-                                    DRM_MODE_ENCODER_DAC)
-                                        pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
-                                if (encoder->encoder_type ==
-                                        DRM_MODE_ENCODER_LVDS)
-                                        pll_flags |= RADEON_PLL_USE_REF_DIV;
-                        }
                         radeon_encoder = to_radeon_encoder(encoder);
+                        if (ASIC_IS_AVIVO(rdev)) {
+                                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
+                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
+                                        adjusted_clock = mode->clock * 2;
+                        } else {
+                                if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
+                                        pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
+                                if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
+                                        pll->flags |= RADEON_PLL_USE_REF_DIV;
+                        }
                         break;
                 }
         }
@@ -471,46 +467,101 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
          * special hw requirements.
          */
         if (ASIC_IS_DCE3(rdev)) {
-                ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
+                union adjust_pixel_clock args;
+                struct radeon_encoder_atom_dig *dig;
+                u8 frev, crev;
+                int index;
 
-                if (!encoder)
-                        return;
-
-                memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
-                adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
-                adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
-                adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
+                if (!radeon_encoder->enc_priv)
+                        return adjusted_clock;
+                dig = radeon_encoder->enc_priv;
 
                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
-                atom_execute_table(rdev->mode_info.atom_context,
-                                   index, (uint32_t *)&adjust_pll_args);
-                adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
-        } else {
-                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
-                if (ASIC_IS_AVIVO(rdev) &&
-                    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
-                        adjusted_clock = mode->clock * 2;
-                else
-                        adjusted_clock = mode->clock;
+                atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                                      &crev);
+
+                memset(&args, 0, sizeof(args));
+
+                switch (frev) {
+                case 1:
+                        switch (crev) {
+                        case 1:
+                        case 2:
+                                args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
+                                args.v1.ucTransmitterID = radeon_encoder->encoder_id;
+                                args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
+
+                                atom_execute_table(rdev->mode_info.atom_context,
+                                                   index, (uint32_t *)&args);
+                                adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
+                                break;
+                        default:
+                                DRM_ERROR("Unknown table version %d %d\n", frev, crev);
+                                return adjusted_clock;
+                        }
+                        break;
+                default:
+                        DRM_ERROR("Unknown table version %d %d\n", frev, crev);
+                        return adjusted_clock;
+                }
         }
+        return adjusted_clock;
+}
+
+union set_pixel_clock {
+        SET_PIXEL_CLOCK_PS_ALLOCATION base;
+        PIXEL_CLOCK_PARAMETERS v1;
+        PIXEL_CLOCK_PARAMETERS_V2 v2;
+        PIXEL_CLOCK_PARAMETERS_V3 v3;
+};
+
+void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *encoder = NULL;
+        struct radeon_encoder *radeon_encoder = NULL;
+        u8 frev, crev;
+        int index;
+        union set_pixel_clock args;
+        u32 pll_clock = mode->clock;
+        u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
+        struct radeon_pll *pll;
+        u32 adjusted_clock;
+
+        memset(&args, 0, sizeof(args));
+
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                if (encoder->crtc == crtc) {
+                        radeon_encoder = to_radeon_encoder(encoder);
+                        break;
+                }
+        }
+
+        if (!radeon_encoder)
+                return;
 
         if (radeon_crtc->crtc_id == 0)
                 pll = &rdev->clock.p1pll;
         else
                 pll = &rdev->clock.p2pll;
 
+        /* adjust pixel clock as needed */
+        adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
+
         if (ASIC_IS_AVIVO(rdev)) {
                 if (radeon_new_pll)
                         radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
                                                  &fb_div, &frac_fb_div,
-                                                 &ref_div, &post_div, pll_flags);
+                                                 &ref_div, &post_div);
                 else
                         radeon_compute_pll(pll, adjusted_clock, &pll_clock,
                                            &fb_div, &frac_fb_div,
-                                           &ref_div, &post_div, pll_flags);
+                                           &ref_div, &post_div);
         } else
                 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
-                                   &ref_div, &post_div, pll_flags);
+                                   &ref_div, &post_div);
 
         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
@@ -520,45 +571,38 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
         case 1:
                 switch (crev) {
                 case 1:
-                        spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
-                        spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
-                        spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
-                        spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
-                        spc1_ptr->ucFracFbDiv = frac_fb_div;
-                        spc1_ptr->ucPostDiv = post_div;
-                        spc1_ptr->ucPpll =
+                        args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
+                        args.v1.usRefDiv = cpu_to_le16(ref_div);
+                        args.v1.usFbDiv = cpu_to_le16(fb_div);
+                        args.v1.ucFracFbDiv = frac_fb_div;
+                        args.v1.ucPostDiv = post_div;
+                        args.v1.ucPpll =
                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
-                        spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
-                        spc1_ptr->ucRefDivSrc = 1;
+                        args.v1.ucCRTC = radeon_crtc->crtc_id;
+                        args.v1.ucRefDivSrc = 1;
                         break;
                 case 2:
-                        spc2_ptr =
-                            (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
-                        spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
-                        spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
-                        spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
-                        spc2_ptr->ucFracFbDiv = frac_fb_div;
-                        spc2_ptr->ucPostDiv = post_div;
-                        spc2_ptr->ucPpll =
+                        args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
+                        args.v2.usRefDiv = cpu_to_le16(ref_div);
+                        args.v2.usFbDiv = cpu_to_le16(fb_div);
+                        args.v2.ucFracFbDiv = frac_fb_div;
+                        args.v2.ucPostDiv = post_div;
+                        args.v2.ucPpll =
                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
-                        spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
-                        spc2_ptr->ucRefDivSrc = 1;
+                        args.v2.ucCRTC = radeon_crtc->crtc_id;
+                        args.v2.ucRefDivSrc = 1;
                         break;
                 case 3:
-                        if (!encoder)
-                                return;
-                        spc3_ptr =
-                            (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
-                        spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
-                        spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
-                        spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
-                        spc3_ptr->ucFracFbDiv = frac_fb_div;
-                        spc3_ptr->ucPostDiv = post_div;
-                        spc3_ptr->ucPpll =
+                        args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
+                        args.v3.usRefDiv = cpu_to_le16(ref_div);
+                        args.v3.usFbDiv = cpu_to_le16(fb_div);
+                        args.v3.ucFracFbDiv = frac_fb_div;
+                        args.v3.ucPostDiv = post_div;
+                        args.v3.ucPpll =
                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
-                        spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
-                        spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
-                        spc3_ptr->ucEncoderMode =
+                        args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
+                        args.v3.ucTransmitterId = radeon_encoder->encoder_id;
+                        args.v3.ucEncoderMode =
                             atombios_get_encoder_mode(encoder);
                         break;
                 default:
@@ -571,12 +615,11 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                 return;
         }
 
-        printk("executing set pll\n");
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
-int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
-                           struct drm_framebuffer *old_fb)
+static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                               struct drm_framebuffer *old_fb)
 {
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
         struct drm_device *dev = crtc->dev;
@@ -706,6 +749,42 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
         return 0;
 }
 
+int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                           struct drm_framebuffer *old_fb)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+
+        if (ASIC_IS_AVIVO(rdev))
+                return avivo_crtc_set_base(crtc, x, y, old_fb);
+        else
+                return radeon_crtc_set_base(crtc, x, y, old_fb);
+}
+
+/* properly set additional regs when using atombios */
+static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        u32 disp_merge_cntl;
+
+        switch (radeon_crtc->crtc_id) {
+        case 0:
+                disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
+                disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
+                WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
+                break;
+        case 1:
+                disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
+                disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
+                WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
+                WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
+                WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
+                break;
+        }
+}
+
 int atombios_crtc_mode_set(struct drm_crtc *crtc,
                            struct drm_display_mode *mode,
                            struct drm_display_mode *adjusted_mode,
@@ -727,8 +806,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
         else {
                 if (radeon_crtc->crtc_id == 0)
                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
-                radeon_crtc_set_base(crtc, x, y, old_fb);
-                radeon_legacy_atom_set_surface(crtc);
+                atombios_crtc_set_base(crtc, x, y, old_fb);
+                radeon_legacy_atom_fixup(crtc);
         }
         atombios_overscan_setup(crtc, mode, adjusted_mode);
         atombios_scaler_setup(crtc);
@@ -746,8 +825,8 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 
 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 {
-        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
         atombios_lock_crtc(crtc, 1);
+        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 }
 
 static void atombios_crtc_commit(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 0d63c4436e7c..99915a682d59 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -332,11 +332,13 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
         unsigned char *base;
+        int retry_count = 0;
 
         memset(&args, 0, sizeof(args));
 
         base = (unsigned char *)rdev->mode_info.atom_context->scratch;
 
+retry:
         memcpy(base, req_bytes, num_bytes);
 
         args.lpAuxRequest = 0;
@@ -347,10 +349,12 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
 
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 
-        if (args.ucReplyStatus) {
-                DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
+        if (args.ucReplyStatus && !args.ucDataOutLen) {
+                if (args.ucReplyStatus == 0x20 && retry_count++ < 10)
+                        goto retry;
+                DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
                           req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
-                          chan->rec.i2c_id, args.ucReplyStatus);
+                          chan->rec.i2c_id, args.ucReplyStatus, retry_count);
                 return false;
         }
 
@@ -468,7 +472,8 @@ void radeon_dp_set_link_config(struct drm_connector *connector,
         struct radeon_connector *radeon_connector;
         struct radeon_connector_atom_dig *dig_connector;
 
-        if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+        if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
+            (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
                 return;
 
         radeon_connector = to_radeon_connector(connector);
@@ -582,7 +587,8 @@ void dp_link_train(struct drm_encoder *encoder,
         u8 train_set[4];
         int i;
 
-        if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+        if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
+            (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
                 return;
 
         if (!radeon_encoder->enc_priv)
@@ -594,21 +600,14 @@ void dp_link_train(struct drm_encoder *encoder,
                 return;
         dig_connector = radeon_connector->con_priv;
 
-        if (ASIC_IS_DCE32(rdev)) {
-                if (dig->dig_block)
-                        enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
-                else
-                        enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
-                if (dig_connector->linkb)
-                        enc_id |= ATOM_DP_CONFIG_LINK_B;
-                else
-                        enc_id |= ATOM_DP_CONFIG_LINK_A;
-        } else {
-                if (dig_connector->linkb)
-                        enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B;
-                else
-                        enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A;
-        }
+        if (dig->dig_encoder)
+                enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
+        else
+                enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
+        if (dig_connector->linkb)
+                enc_id |= ATOM_DP_CONFIG_LINK_B;
+        else
+                enc_id |= ATOM_DP_CONFIG_LINK_A;
 
         memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
         if (dig_connector->dp_clock == 270000)
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index 0d79577c1576..607241c6a8a9 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -661,8 +661,10 @@ static int parser_auth(struct table *t, const char *filename)
         fseek(file, 0, SEEK_SET);
 
         /* get header */
-        if (fgets(buf, 1024, file) == NULL)
+        if (fgets(buf, 1024, file) == NULL) {
+                fclose(file);
                 return -1;
+        }
 
         /* first line will contain the last register
          * and gpu name */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 71727460968f..c0d4650cdb79 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -131,7 +131,8 @@ void r100_hpd_init(struct radeon_device *rdev)
                         break;
                 }
         }
-        r100_irq_set(rdev);
+        if (rdev->irq.installed)
+                r100_irq_set(rdev);
 }
 
 void r100_hpd_fini(struct radeon_device *rdev)
@@ -243,6 +244,11 @@ int r100_irq_set(struct radeon_device *rdev)
 {
         uint32_t tmp = 0;
 
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WREG32(R_000040_GEN_INT_CNTL, 0);
+                return -EINVAL;
+        }
         if (rdev->irq.sw_int) {
                 tmp |= RADEON_SW_INT_ENABLE;
         }
@@ -348,14 +354,25 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 }
 
+/* Who ever call radeon_fence_emit should call ring_lock and ask
+ * for enough space (today caller are ib schedule and buffer move) */
 void r100_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
-        /* Who ever call radeon_fence_emit should call ring_lock and ask
-         * for enough space (today caller are ib schedule and buffer move) */
+        /* We have to make sure that caches are flushed before
+         * CPU might read something from VRAM. */
+        radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
+        radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
         /* Wait until IDLE & CLEAN */
         radeon_ring_write(rdev, PACKET0(0x1720, 0));
         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
+                                RADEON_HDP_READ_BUFFER_INVALIDATE);
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
         /* Emit fence sequence & fire IRQ */
         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
         radeon_ring_write(rdev, fence->seq);
@@ -1493,6 +1510,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
                         return -EINVAL;
                 }
+                track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
                 track->immd_dwords = pkt->count - 1;
                 r = r100_cs_track_check(p->rdev, track);
@@ -1713,14 +1731,6 @@ void r100_gpu_init(struct radeon_device *rdev)
         r100_hdp_reset(rdev);
 }
 
-void r100_hdp_flush(struct radeon_device *rdev)
-{
-        u32 tmp;
-        tmp = RREG32(RADEON_HOST_PATH_CNTL);
-        tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
-        WREG32(RADEON_HOST_PATH_CNTL, tmp);
-}
-
 void r100_hdp_reset(struct radeon_device *rdev)
 {
         uint32_t tmp;
@@ -3313,6 +3323,7 @@ static int r100_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -3364,13 +3375,13 @@ int r100_suspend(struct radeon_device *rdev)
 
 void r100_fini(struct radeon_device *rdev)
 {
-        r100_suspend(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         if (rdev->flags & RADEON_IS_PCI)
                 r100_pci_gart_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_irq_kms_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_bo_fini(rdev);
@@ -3394,9 +3405,7 @@ int r100_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_AGP) {
                 r = radeon_agp_init(rdev);
                 if (r) {
-                        printk(KERN_WARNING "[drm] Disabling AGP\n");
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                        radeon_agp_disable(rdev);
                 } else {
                         rdev->mc.gtt_location = rdev->mc.agp_base;
                 }
@@ -3477,13 +3486,12 @@ int r100_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                r100_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCI)
                         r100_pci_gart_fini(rdev);
-                radeon_irq_kms_fini(rdev);
                 rdev->accel_working = false;
         }
         return 0;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 20942127c46b..ff1e0cd608bf 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -371,13 +371,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                 case 5:
                 case 6:
                 case 7:
+                        /* 1D/2D */
                         track->textures[i].tex_coord_type = 0;
                         break;
                 case 1:
-                        track->textures[i].tex_coord_type = 1;
+                        /* CUBE */
+                        track->textures[i].tex_coord_type = 2;
                         break;
                 case 2:
-                        track->textures[i].tex_coord_type = 2;
+                        /* 3D */
+                        track->textures[i].tex_coord_type = 1;
                         break;
                 }
                 break;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 3f2cc9e2e8d9..43b55a030b4d 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -36,7 +36,15 @@
 #include "rv350d.h"
 #include "r300_reg_safe.h"
 
-/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
+/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
+ *
+ * GPU Errata:
+ * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
+ *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
+ *   However, scheduling such write to the ring seems harmless, i suspect
+ *   the CP read collide with the flush somehow, or maybe the MC, hard to
+ *   tell. (Jerome Glisse)
+ */
 
 /*
  * rv370,rv380 PCIE GART
@@ -178,6 +186,11 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
         /* Wait until IDLE & CLEAN */
         radeon_ring_write(rdev, PACKET0(0x1720, 0));
         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
+                                RADEON_HDP_READ_BUFFER_INVALIDATE);
+        radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+        radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
         /* Emit fence sequence & fire IRQ */
         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
         radeon_ring_write(rdev, fence->seq);
@@ -493,11 +506,14 @@ void r300_vram_info(struct radeon_device *rdev)
 
         /* DDR for all card after R300 & IGP */
         rdev->mc.vram_is_ddr = true;
+
         tmp = RREG32(RADEON_MEM_CNTL);
-        if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
-                rdev->mc.vram_width = 128;
-        } else {
-                rdev->mc.vram_width = 64;
+        tmp &= R300_MEM_NUM_CHANNELS_MASK;
+        switch (tmp) {
+        case 0: rdev->mc.vram_width = 64; break;
+        case 1: rdev->mc.vram_width = 128; break;
+        case 2: rdev->mc.vram_width = 256; break;
+        default:  rdev->mc.vram_width = 128; break;
         }
 
         r100_vram_init_sizes(rdev);
@@ -1258,6 +1274,7 @@ static int r300_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -1313,7 +1330,6 @@ int r300_suspend(struct radeon_device *rdev)
 
 void r300_fini(struct radeon_device *rdev)
 {
-        r300_suspend(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
@@ -1322,6 +1338,7 @@ void r300_fini(struct radeon_device *rdev)
                 rv370_pcie_gart_fini(rdev);
         if (rdev->flags & RADEON_IS_PCI)
                 r100_pci_gart_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_irq_kms_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_bo_fini(rdev);
@@ -1403,15 +1420,15 @@ int r300_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                r300_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCIE)
                         rv370_pcie_gart_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCI)
                         r100_pci_gart_fini(rdev);
-                radeon_irq_kms_fini(rdev);
+                radeon_agp_fini(rdev);
                 rdev->accel_working = false;
         }
         return 0;
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index c05a7270cf0c..d9373246c97f 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -30,7 +30,15 @@
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "atom.h"
+#include "r100d.h"
 #include "r420d.h"
+#include "r420_reg_safe.h"
+
+static void r420_set_reg_safe(struct radeon_device *rdev)
+{
+        rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
+        rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
+}
 
 int r420_mc_init(struct radeon_device *rdev)
 {
@@ -42,9 +50,7 @@ int r420_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_AGP) {
                 r = radeon_agp_init(rdev);
                 if (r) {
-                        printk(KERN_WARNING "[drm] Disabling AGP\n");
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                        radeon_agp_disable(rdev);
                 } else {
                         rdev->mc.gtt_location = rdev->mc.agp_base;
                 }
@@ -165,6 +171,34 @@ static void r420_clock_resume(struct radeon_device *rdev)
         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 }
 
+static void r420_cp_errata_init(struct radeon_device *rdev)
+{
+        /* RV410 and R420 can lock up if CP DMA to host memory happens
+         * while the 2D engine is busy.
+         *
+         * The proper workaround is to queue a RESYNC at the beginning
+         * of the CP init, apparently.
+         */
+        radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
+        radeon_ring_lock(rdev, 8);
+        radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
+        radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
+        radeon_ring_write(rdev, 0xDEADBEEF);
+        radeon_ring_unlock_commit(rdev);
+}
+
+static void r420_cp_errata_fini(struct radeon_device *rdev)
+{
+        /* Catch the RESYNC we dispatched all the way back,
+         * at the very beginning of the CP init.
+         */
+        radeon_ring_lock(rdev, 8);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
+        radeon_ring_unlock_commit(rdev);
+        radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
+}
+
 static int r420_startup(struct radeon_device *rdev)
 {
         int r;
@@ -190,12 +224,14 @@ static int r420_startup(struct radeon_device *rdev)
         r420_pipes_init(rdev);
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
+        r420_cp_errata_init(rdev);
         r = r100_wb_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
@@ -238,6 +274,7 @@ int r420_resume(struct radeon_device *rdev)
 
 int r420_suspend(struct radeon_device *rdev)
 {
+        r420_cp_errata_fini(rdev);
         r100_cp_disable(rdev);
         r100_wb_disable(rdev);
         r100_irq_disable(rdev);
@@ -346,22 +383,21 @@ int r420_init(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
-        r300_set_reg_safe(rdev);
+        r420_set_reg_safe(rdev);
         rdev->accel_working = true;
         r = r420_startup(rdev);
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                r420_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCIE)
                         rv370_pcie_gart_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCI)
                         r100_pci_gart_fini(rdev);
                 radeon_agp_fini(rdev);
-                radeon_irq_kms_fini(rdev);
                 rdev->accel_working = false;
         }
         return 0;
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0f3843b6dac7..ddf5731eba0d 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -186,6 +186,7 @@ static int r520_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -293,13 +294,12 @@ int r520_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rv515_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 rv370_pcie_gart_fini(rdev);
                 radeon_agp_fini(rdev);
-                radeon_irq_kms_fini(rdev);
                 rdev->accel_working = false;
         }
         return 0;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index a0ac3c134b1b..2ffcf5a03551 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -285,7 +285,8 @@ void r600_hpd_init(struct radeon_device *rdev)
                         }
                 }
         }
-        r600_irq_set(rdev);
+        if (rdev->irq.installed)
+                r600_irq_set(rdev);
 }
 
 void r600_hpd_fini(struct radeon_device *rdev)
@@ -623,7 +624,6 @@ int r600_mc_init(struct radeon_device *rdev)
         fixed20_12 a;
         u32 tmp;
         int chansize, numchan;
-        int r;
 
         /* Get VRAM informations */
         rdev->mc.vram_is_ddr = true;
@@ -666,9 +666,6 @@ int r600_mc_init(struct radeon_device *rdev)
                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 
         if (rdev->flags & RADEON_IS_AGP) {
-                r = radeon_agp_init(rdev);
-                if (r)
-                        return r;
                 /* gtt_size is setup by radeon_agp_init */
                 rdev->mc.gtt_location = rdev->mc.agp_base;
                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
@@ -726,6 +723,10 @@ int r600_mc_init(struct radeon_device *rdev)
         a.full = rfixed_const(100);
         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+
+        if (rdev->flags & RADEON_IS_IGP)
+                rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+
         return 0;
 }
 
@@ -1384,11 +1385,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
         (void)RREG32(PCIE_PORT_DATA);
 }
 
-void r600_hdp_flush(struct radeon_device *rdev)
-{
-        WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
-}
-
 /*
  * CP & Ring
  */
@@ -1658,6 +1654,12 @@ void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
         rdev->cp.align_mask = 16 - 1;
 }
 
+void r600_cp_fini(struct radeon_device *rdev)
+{
+        r600_cp_stop(rdev);
+        radeon_ring_fini(rdev);
+}
+
 
 /*
  * GPU scratch registers helpers function.
@@ -1785,28 +1787,31 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
         radeon_ring_write(rdev, fence->seq);
+        radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
+        radeon_ring_write(rdev, 1);
         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
         radeon_ring_write(rdev, RB_INT_STAT);
 }
 
-int r600_copy_dma(struct radeon_device *rdev,
-                  uint64_t src_offset,
-                  uint64_t dst_offset,
-                  unsigned num_pages,
-                  struct radeon_fence *fence)
-{
-        /* FIXME: implement */
-        return 0;
-}
-
 int r600_copy_blit(struct radeon_device *rdev,
                    uint64_t src_offset, uint64_t dst_offset,
                    unsigned num_pages, struct radeon_fence *fence)
 {
-        r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
+        int r;
+
+        mutex_lock(&rdev->r600_blit.mutex);
+        rdev->r600_blit.vb_ib = NULL;
+        r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
+        if (r) {
+                if (rdev->r600_blit.vb_ib)
+                        radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
+                mutex_unlock(&rdev->r600_blit.mutex);
+                return r;
+        }
         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
         r600_blit_done_copy(rdev, fence);
+        mutex_unlock(&rdev->r600_blit.mutex);
         return 0;
 }
 
@@ -1862,26 +1867,25 @@ int r600_startup(struct radeon_device *rdev)
                         return r;
         }
         r600_gpu_init(rdev);
-
-        if (!rdev->r600_blit.shader_obj) {
-                r = r600_blit_init(rdev);
+        r = r600_blit_init(rdev);
+        if (r) {
+                r600_blit_fini(rdev);
+                rdev->asic->copy = NULL;
+                dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
+        }
+        /* pin copy shader into vram */
+        if (rdev->r600_blit.shader_obj) {
+                r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+                if (unlikely(r != 0))
+                        return r;
+                r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+                                &rdev->r600_blit.shader_gpu_addr);
+                radeon_bo_unreserve(rdev->r600_blit.shader_obj);
                 if (r) {
-                        DRM_ERROR("radeon: failed blitter (%d).\n", r);
+                        dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
                         return r;
                 }
         }
-
-        r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
-        if (unlikely(r != 0))
-                return r;
-        r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
-                        &rdev->r600_blit.shader_gpu_addr);
-        radeon_bo_unreserve(rdev->r600_blit.shader_obj);
-        if (r) {
-                dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
-                return r;
-        }
-
         /* Enable IRQ */
         r = r600_irq_init(rdev);
         if (r) {
@@ -1946,6 +1950,13 @@ int r600_resume(struct radeon_device *rdev)
                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                 return r;
         }
+
+        r = r600_audio_init(rdev);
+        if (r) {
+                DRM_ERROR("radeon: audio resume failed\n");
+                return r;
+        }
+
         return r;
 }
 
@@ -1953,17 +1964,21 @@ int r600_suspend(struct radeon_device *rdev)
 {
         int r;
 
+        r600_audio_fini(rdev);
         /* FIXME: we should wait for ring to be empty */
         r600_cp_stop(rdev);
         rdev->cp.ready = false;
+        r600_irq_suspend(rdev);
         r600_wb_disable(rdev);
         r600_pcie_gart_disable(rdev);
         /* unpin shaders bo */
-        r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
-        if (unlikely(r != 0))
-                return r;
-        radeon_bo_unpin(rdev->r600_blit.shader_obj);
-        radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+        if (rdev->r600_blit.shader_obj) {
+                r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+                if (!r) {
+                        radeon_bo_unpin(rdev->r600_blit.shader_obj);
+                        radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+                }
+        }
         return 0;
 }
 
@@ -2024,6 +2039,11 @@ int r600_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r)
+                        radeon_agp_disable(rdev);
+        }
         r = r600_mc_init(rdev);
         if (r)
                 return r;
@@ -2049,22 +2069,25 @@ int r600_init(struct radeon_device *rdev)
         rdev->accel_working = true;
         r = r600_startup(rdev);
         if (r) {
-                r600_suspend(rdev);
+                dev_err(rdev->dev, "disabling GPU acceleration\n");
+                r600_cp_fini(rdev);
                 r600_wb_fini(rdev);
-                radeon_ring_fini(rdev);
+                r600_irq_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 r600_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
         }
         if (rdev->accel_working) {
                 r = radeon_ib_pool_init(rdev);
                 if (r) {
-                        DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
-                        rdev->accel_working = false;
-                }
-                r = r600_ib_test(rdev);
-                if (r) {
-                        DRM_ERROR("radeon: failed testing IB (%d).\n", r);
+                        dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
                         rdev->accel_working = false;
+                } else {
+                        r = r600_ib_test(rdev);
+                        if (r) {
+                                dev_err(rdev->dev, "IB test failed (%d).\n", r);
+                                rdev->accel_working = false;
+                        }
                 }
         }
 
@@ -2076,21 +2099,17 @@ int r600_init(struct radeon_device *rdev)
 
 void r600_fini(struct radeon_device *rdev)
 {
-        /* Suspend operations */
-        r600_suspend(rdev);
-
         r600_audio_fini(rdev);
         r600_blit_fini(rdev);
+        r600_cp_fini(rdev);
+        r600_wb_fini(rdev);
         r600_irq_fini(rdev);
         radeon_irq_kms_fini(rdev);
-        radeon_ring_fini(rdev);
-        r600_wb_fini(rdev);
         r600_pcie_gart_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_clocks_fini(rdev);
-        if (rdev->flags & RADEON_IS_AGP)
-                radeon_agp_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);
@@ -2196,14 +2215,14 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
         rb_bufsz = drm_order(ring_size / 4);
         ring_size = (1 << rb_bufsz) * 4;
         rdev->ih.ring_size = ring_size;
-        rdev->ih.align_mask = 4 - 1;
+        rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
+        rdev->ih.rptr = 0;
 }
 
-static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
+static int r600_ih_ring_alloc(struct radeon_device *rdev)
 {
         int r;
 
-        rdev->ih.ring_size = ring_size;
         /* Allocate ring buffer */
         if (rdev->ih.ring_obj == NULL) {
                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
@@ -2233,9 +2252,6 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
                         return r;
                 }
         }
-        rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
-        rdev->ih.rptr = 0;
-
         return 0;
 }
 
@@ -2385,7 +2401,7 @@ int r600_irq_init(struct radeon_device *rdev)
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
 
         /* allocate ring */
-        ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size);
+        ret = r600_ih_ring_alloc(rdev);
         if (ret)
                 return ret;
 
@@ -2448,10 +2464,15 @@ int r600_irq_init(struct radeon_device *rdev)
         return ret;
 }
 
-void r600_irq_fini(struct radeon_device *rdev)
+void r600_irq_suspend(struct radeon_device *rdev)
 {
         r600_disable_interrupts(rdev);
         r600_rlc_stop(rdev);
+}
+
+void r600_irq_fini(struct radeon_device *rdev)
+{
+        r600_irq_suspend(rdev);
         r600_ih_ring_fini(rdev);
 }
 
@@ -2461,9 +2482,17 @@ int r600_irq_set(struct radeon_device *rdev)
         u32 mode_int = 0;
         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
 
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                return -EINVAL;
+        }
         /* don't enable anything if the ih is disabled */
-        if (!rdev->ih.enabled)
+        if (!rdev->ih.enabled) {
+                r600_disable_interrupts(rdev);
+                /* force the active interrupt state to all disabled */
+                r600_disable_interrupt_state(rdev);
                 return 0;
+        }
 
         if (ASIC_IS_DCE3(rdev)) {
                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
@@ -2633,16 +2662,18 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
         wptr = RREG32(IH_RB_WPTR);
 
         if (wptr & RB_OVERFLOW) {
-                WARN_ON(1);
-                /* XXX deal with overflow */
-                DRM_ERROR("IH RB overflow\n");
+                /* When a ring buffer overflow happen start parsing interrupt
+                 * from the last not overwritten vector (wptr + 16). Hopefully
+                 * this should allow us to catchup.
+                 */
+                dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
+                        wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
+                rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
                 tmp = RREG32(IH_RB_CNTL);
                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
                 WREG32(IH_RB_CNTL, tmp);
         }
-        wptr = wptr & WPTR_OFFSET_MASK;
-
-        return wptr;
+        return (wptr & rdev->ih.ptr_mask);
 }
 
 /*        r600 IV Ring
@@ -2678,12 +2709,13 @@ int r600_irq_process(struct radeon_device *rdev)
         u32 wptr = r600_get_ih_wptr(rdev);
         u32 rptr = rdev->ih.rptr;
         u32 src_id, src_data;
-        u32 last_entry = rdev->ih.ring_size - 16;
         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
         unsigned long flags;
         bool queue_hotplug = false;
 
         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
+        if (!rdev->ih.enabled)
+                return IRQ_NONE;
 
         spin_lock_irqsave(&rdev->ih.lock, flags);
 
@@ -2724,7 +2756,7 @@ restart_ih:
                                 }
                                 break;
                         default:
-                                DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+                                DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
                                 break;
                         }
                         break;
@@ -2744,7 +2776,7 @@ restart_ih:
                                 }
                                 break;
                         default:
-                                DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+                                DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
                                 break;
                         }
                         break;
@@ -2793,7 +2825,7 @@ restart_ih:
                                 }
                                 break;
                         default:
-                                DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+                                DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
                                 break;
                         }
                         break;
@@ -2807,15 +2839,13 @@ restart_ih:
                         DRM_DEBUG("IH: CP EOP\n");
                         break;
                 default:
-                        DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+                        DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
                         break;
                 }
 
                 /* wptr/rptr are in bytes! */
-                if (rptr == last_entry)
-                        rptr = 0;
-                else
-                        rptr += 16;
+                rptr += 16;
+                rptr &= rdev->ih.ptr_mask;
         }
         /* make sure wptr hasn't changed while processing */
         wptr = r600_get_ih_wptr(rdev);
@@ -2883,3 +2913,18 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
         return 0;
 #endif
 }
+
+/**
+ * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
+ * rdev: radeon device structure
+ * bo: buffer object struct which userspace is waiting for idle
+ *
+ * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
+ * through ring buffer, this leads to corruption in rendering, see
+ * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
+ * directly perform HDP flush by writing register through MMIO.
+ */
+void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
+{
+        WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+}
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 99e2c3891a7d..0dcb6904c4ff 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -35,7 +35,7 @@
  */
 static int r600_audio_chipset_supported(struct radeon_device *rdev)
 {
-        return rdev->family >= CHIP_R600
+        return (rdev->family >= CHIP_R600 && rdev->family < CHIP_RV710)
                 || rdev->family == CHIP_RS600
                 || rdev->family == CHIP_RS690
                 || rdev->family == CHIP_RS740;
@@ -261,7 +261,6 @@ void r600_audio_fini(struct radeon_device *rdev)
         if (!r600_audio_chipset_supported(rdev))
                 return;
 
-        WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000);
-
         del_timer(&rdev->audio_timer);
+        WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000);
 }
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 9aecafb51b66..446b765ac72a 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -449,6 +449,7 @@ int r600_blit_init(struct radeon_device *rdev)
         u32 packet2s[16];
         int num_packet2s = 0;
 
+        mutex_init(&rdev->r600_blit.mutex);
         rdev->r600_blit.state_offset = 0;
 
         if (rdev->family >= CHIP_RV770)
@@ -512,14 +513,16 @@ void r600_blit_fini(struct radeon_device *rdev)
 {
         int r;
 
+        if (rdev->r600_blit.shader_obj == NULL)
+                return;
+        /* If we can't reserve the bo, unref should be enough to destroy
+         * it when it becomes idle.
+         */
         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
-        if (unlikely(r != 0)) {
-                dev_err(rdev->dev, "(%d) can't finish r600 blit\n", r);
-                goto out_unref;
+        if (!r) {
+                radeon_bo_unpin(rdev->r600_blit.shader_obj);
+                radeon_bo_unreserve(rdev->r600_blit.shader_obj);
         }
-        radeon_bo_unpin(rdev->r600_blit.shader_obj);
-        radeon_bo_unreserve(rdev->r600_blit.shader_obj);
-out_unref:
         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 }
 
@@ -540,9 +543,6 @@ int r600_vb_ib_get(struct radeon_device *rdev)
 void r600_vb_ib_put(struct radeon_device *rdev)
 {
         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
-        mutex_lock(&rdev->ib_pool.mutex);
-        list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs);
-        mutex_unlock(&rdev->ib_pool.mutex);
         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 }
 
@@ -555,7 +555,8 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
         int dwords_per_loop = 76, num_loops;
 
         r = r600_vb_ib_get(rdev);
-        WARN_ON(r);
+        if (r)
+                return r;
 
         /* set_render_target emits 2 extra dwords on rv6xx */
         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
@@ -577,11 +578,12 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
         ring_size = num_loops * dwords_per_loop;
         /* set default  + shaders */
         ring_size += 40; /* shaders + def state */
-        ring_size += 5; /* fence emit for VB IB */
+        ring_size += 7; /* fence emit for VB IB */
         ring_size += 5; /* done copy */
-        ring_size += 5; /* fence emit for done copy */
+        ring_size += 7; /* fence emit for done copy */
         r = radeon_ring_lock(rdev, ring_size);
-        WARN_ON(r);
+        if (r)
+                return r;
 
         set_default_state(rdev); /* 14 */
         set_shaders(rdev); /* 26 */
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 6d5a711c2e91..75bcf35a0931 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -1428,9 +1428,12 @@ static void r700_gfx_init(struct drm_device *dev,
 
         gb_tiling_config |= R600_BANK_SWAPS(1);
 
-        backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
-                                                        dev_priv->r600_max_backends,
-                                                        (0xff << dev_priv->r600_max_backends) & 0xff);
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
+                backend_map = 0x28;
+        else
+                backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
+                                                                dev_priv->r600_max_backends,
+                                                                (0xff << dev_priv->r600_max_backends) & 0xff);
         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 
         cc_gc_shader_pipe_config =
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 44060b92d9e6..e4c45ec16507 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -36,6 +36,10 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
 
+struct r600_cs_track {
+        u32     cb_color0_base_last;
+};
+
 /**
  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
  * @parser:     parser structure holding parsing context.
@@ -177,6 +181,28 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 }
 
 /**
+ * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
+ * @parser:             parser structure holding parsing context.
+ *
+ * Check next packet is relocation packet3, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
+{
+        struct radeon_cs_packet p3reloc;
+        int r;
+
+        r = r600_cs_packet_parse(p, &p3reloc, p->idx);
+        if (r) {
+                return 0;
+        }
+        if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+                return 0;
+        }
+        return 1;
+}
+
+/**
  * r600_cs_packet_next_vline() - parse userspace VLINE packet
  * @parser:             parser structure holding parsing context.
  *
@@ -337,6 +363,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                 struct radeon_cs_packet *pkt)
 {
         struct radeon_cs_reloc *reloc;
+        struct r600_cs_track *track;
         volatile u32 *ib;
         unsigned idx;
         unsigned i;
@@ -344,6 +371,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
         int r;
         u32 idx_value;
 
+        track = (struct r600_cs_track *)p->track;
         ib = p->ib->ptr;
         idx = pkt->idx + 1;
         idx_value = radeon_get_ib_value(p, idx);
@@ -503,9 +531,60 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                 for (i = 0; i < pkt->count; i++) {
                         reg = start_reg + (4 * i);
                         switch (reg) {
+                        /* This register were added late, there is userspace
+                         * which does provide relocation for those but set
+                         * 0 offset. In order to avoid breaking old userspace
+                         * we detect this and set address to point to last
+                         * CB_COLOR0_BASE, note that if userspace doesn't set
+                         * CB_COLOR0_BASE before this register we will report
+                         * error. Old userspace always set CB_COLOR0_BASE
+                         * before any of this.
+                         */
+                        case R_0280E0_CB_COLOR0_FRAG:
+                        case R_0280E4_CB_COLOR1_FRAG:
+                        case R_0280E8_CB_COLOR2_FRAG:
+                        case R_0280EC_CB_COLOR3_FRAG:
+                        case R_0280F0_CB_COLOR4_FRAG:
+                        case R_0280F4_CB_COLOR5_FRAG:
+                        case R_0280F8_CB_COLOR6_FRAG:
+                        case R_0280FC_CB_COLOR7_FRAG:
+                        case R_0280C0_CB_COLOR0_TILE:
+                        case R_0280C4_CB_COLOR1_TILE:
+                        case R_0280C8_CB_COLOR2_TILE:
+                        case R_0280CC_CB_COLOR3_TILE:
+                        case R_0280D0_CB_COLOR4_TILE:
+                        case R_0280D4_CB_COLOR5_TILE:
+                        case R_0280D8_CB_COLOR6_TILE:
+                        case R_0280DC_CB_COLOR7_TILE:
+                                if (!r600_cs_packet_next_is_pkt3_nop(p)) {
+                                        if (!track->cb_color0_base_last) {
+                                                dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
+                                                return -EINVAL;
+                                        }
+                                        ib[idx+1+i] = track->cb_color0_base_last;
+                                        printk_once(KERN_WARNING "radeon: You have old & broken userspace "
+                                                "please consider updating mesa & xf86-video-ati\n");
+                                } else {
+                                        r = r600_cs_packet_next_reloc(p, &reloc);
+                                        if (r) {
+                                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
+                                                return -EINVAL;
+                                        }
+                                        ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                }
+                                break;
                         case DB_DEPTH_BASE:
                         case DB_HTILE_DATA_BASE:
                         case CB_COLOR0_BASE:
+                                r = r600_cs_packet_next_reloc(p, &reloc);
+                                if (r) {
+                                        DRM_ERROR("bad SET_CONTEXT_REG "
+                                                        "0x%04X\n", reg);
+                                        return -EINVAL;
+                                }
+                                ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                track->cb_color0_base_last = ib[idx+1+i];
+                                break;
                         case CB_COLOR1_BASE:
                         case CB_COLOR2_BASE:
                         case CB_COLOR3_BASE:
@@ -678,8 +757,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
 int r600_cs_parse(struct radeon_cs_parser *p)
 {
         struct radeon_cs_packet pkt;
+        struct r600_cs_track *track;
         int r;
 
+        track = kzalloc(sizeof(*track), GFP_KERNEL);
+        p->track = track;
         do {
                 r = r600_cs_packet_parse(p, &pkt, p->idx);
                 if (r) {
@@ -757,6 +839,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
         /* initialize parser */
         memset(&parser, 0, sizeof(struct radeon_cs_parser));
         parser.filp = filp;
+        parser.dev = &dev->pdev->dev;
         parser.rdev = NULL;
         parser.family = family;
         parser.ib = &fake_ib;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 05894edadab4..30480881aed1 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -882,4 +882,29 @@
 #define         S_000E60_SOFT_RESET_VMC(x)              (((x) & 1) << 17)
 
 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL           0x5480
+
+#define R_0280E0_CB_COLOR0_FRAG                      0x0280E0
+#define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280E0_BASE_256B                           0x00000000
+#define R_0280E4_CB_COLOR1_FRAG                      0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG                      0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG                      0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG                      0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG                      0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG                      0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG                      0x0280FC
+#define R_0280C0_CB_COLOR0_TILE                      0x0280C0
+#define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280C0_BASE_256B                           0x00000000
+#define R_0280C4_CB_COLOR1_TILE                      0x0280C4
+#define R_0280C8_CB_COLOR2_TILE                      0x0280C8
+#define R_0280CC_CB_COLOR3_TILE                      0x0280CC
+#define R_0280D0_CB_COLOR4_TILE                      0x0280D0
+#define R_0280D4_CB_COLOR5_TILE                      0x0280D4
+#define R_0280D8_CB_COLOR6_TILE                      0x0280D8
+#define R_0280DC_CB_COLOR7_TILE                      0x0280DC
+
+
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 53b55608102b..c0356bb193e5 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -96,6 +96,7 @@ extern int radeon_audio;
  * symbol;
  */
 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
+/* RADEON_IB_POOL_SIZE must be a power of 2 */
 #define RADEON_IB_POOL_SIZE             16
 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 #define RADEONFB_CONN_LIMIT             4
@@ -319,10 +320,12 @@ struct radeon_mc {
         u64                     real_vram_size;
         int                     vram_mtrr;
         bool                    vram_is_ddr;
+        bool                    igp_sideport_enabled;
 };
 
 int radeon_mc_setup(struct radeon_device *rdev);
-
+bool radeon_combios_sideport_present(struct radeon_device *rdev);
+bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 
 /*
  * GPU scratch registers structures, functions & helpers
@@ -361,11 +364,12 @@ void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  */
 struct radeon_ib {
         struct list_head        list;
-        unsigned long           idx;
+        unsigned                idx;
         uint64_t                gpu_addr;
         struct radeon_fence     *fence;
-        uint32_t        *ptr;
+        uint32_t                *ptr;
         uint32_t                length_dw;
+        bool                    free;
 };
 
 /*
@@ -375,10 +379,9 @@ struct radeon_ib {
 struct radeon_ib_pool {
         struct mutex            mutex;
         struct radeon_bo        *robj;
-        struct list_head        scheduled_ibs;
         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
         bool                    ready;
-        DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
+        unsigned                head_id;
 };
 
 struct radeon_cp {
@@ -408,13 +411,13 @@ struct r600_ih {
         unsigned                wptr_old;
         unsigned                ring_size;
         uint64_t                gpu_addr;
-        uint32_t                align_mask;
         uint32_t                ptr_mask;
         spinlock_t              lock;
         bool                    enabled;
 };
 
 struct r600_blit {
+        struct mutex            mutex;
         struct radeon_bo        *shader_obj;
         u64 shader_gpu_addr;
         u32 vs_offset, ps_offset;
@@ -463,6 +466,7 @@ struct radeon_cs_chunk {
 };
 
 struct radeon_cs_parser {
+        struct device           *dev;
         struct radeon_device    *rdev;
         struct drm_file         *filp;
         /* chunks */
@@ -654,11 +658,17 @@ struct radeon_asic {
                                uint32_t offset, uint32_t obj_size);
         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
         void (*bandwidth_update)(struct radeon_device *rdev);
-        void (*hdp_flush)(struct radeon_device *rdev);
         void (*hpd_init)(struct radeon_device *rdev);
         void (*hpd_fini)(struct radeon_device *rdev);
         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+        /* ioctl hw specific callback. Some hw might want to perform special
+         * operation on specific ioctl. For instance on wait idle some hw
+         * might want to perform and HDP flush through MMIO as it seems that
+         * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
+         * through ring.
+         */
+        void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 };
 
 /*
@@ -667,11 +677,14 @@ struct radeon_asic {
 struct r100_asic {
         const unsigned  *reg_safe_bm;
         unsigned        reg_safe_bm_size;
+        u32             hdp_cntl;
 };
 
 struct r300_asic {
         const unsigned  *reg_safe_bm;
         unsigned        reg_safe_bm_size;
+        u32             resync_scratch;
+        u32             hdp_cntl;
 };
 
 struct r600_asic {
@@ -843,7 +856,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
 
 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 {
-        if (reg < 0x10000)
+        if (reg < rdev->rmmio_size)
                 return readl(((void __iomem *)rdev->rmmio) + reg);
         else {
                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -853,7 +866,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 
 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
-        if (reg < 0x10000)
+        if (reg < rdev->rmmio_size)
                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
         else {
                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -1007,13 +1020,14 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
-#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
 
 /* Common functions */
+/* AGP */
+extern void radeon_agp_disable(struct radeon_device *rdev);
 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
@@ -1137,6 +1151,7 @@ extern bool r600_card_posted(struct radeon_device *rdev);
 extern void r600_cp_stop(struct radeon_device *rdev);
 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
 extern int r600_cp_resume(struct radeon_device *rdev);
+extern void r600_cp_fini(struct radeon_device *rdev);
 extern int r600_count_pipe_bits(uint32_t val);
 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
@@ -1157,7 +1172,8 @@ extern int r600_irq_init(struct radeon_device *rdev);
 extern void r600_irq_fini(struct radeon_device *rdev);
 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
 extern int r600_irq_set(struct radeon_device *rdev);
-
+extern void r600_irq_suspend(struct radeon_device *rdev);
+/* r600 audio */
 extern int r600_audio_init(struct radeon_device *rdev);
 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 54bf49a6d676..c0681a5556dc 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -144,9 +144,19 @@ int radeon_agp_init(struct radeon_device *rdev)
 
         ret = drm_agp_info(rdev->ddev, &info);
         if (ret) {
+                drm_agp_release(rdev->ddev);
                 DRM_ERROR("Unable to get AGP info: %d\n", ret);
                 return ret;
         }
+
+        if (rdev->ddev->agp->agp_info.aper_size < 32) {
+                drm_agp_release(rdev->ddev);
+                dev_warn(rdev->dev, "AGP aperture too small (%zuM) "
+                        "need at least 32M, disabling AGP\n",
+                        rdev->ddev->agp->agp_info.aper_size);
+                return -EINVAL;
+        }
+
         mode.mode = info.mode;
         agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
         is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
@@ -221,6 +231,7 @@ int radeon_agp_init(struct radeon_device *rdev)
         ret = drm_agp_enable(rdev->ddev, mode);
         if (ret) {
                 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
+                drm_agp_release(rdev->ddev);
                 return ret;
         }
 
@@ -252,10 +263,8 @@ void radeon_agp_resume(struct radeon_device *rdev)
 void radeon_agp_fini(struct radeon_device *rdev)
 {
 #if __OS_HAS_AGP
-        if (rdev->flags & RADEON_IS_AGP) {
-                if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
-                        drm_agp_release(rdev->ddev);
-                }
+        if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
+                drm_agp_release(rdev->ddev);
         }
 #endif
 }
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index eb29217bbf1d..05ee1aeac3fd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -77,7 +77,6 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 int r100_ring_test(struct radeon_device *rdev);
-void r100_hdp_flush(struct radeon_device *rdev);
 void r100_hpd_init(struct radeon_device *rdev);
 void r100_hpd_fini(struct radeon_device *rdev);
 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -114,11 +113,11 @@ static struct radeon_asic r100_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
         .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 
@@ -174,11 +173,11 @@ static struct radeon_asic r300_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
         .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 /*
@@ -218,11 +217,11 @@ static struct radeon_asic r420_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
         .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 
@@ -267,11 +266,11 @@ static struct radeon_asic rs400_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &r100_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &r100_hpd_init,
         .hpd_fini = &r100_hpd_fini,
         .hpd_sense = &r100_hpd_sense,
         .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 
@@ -324,11 +323,11 @@ static struct radeon_asic rs600_asic = {
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .bandwidth_update = &rs600_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
         .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 
@@ -372,11 +371,11 @@ static struct radeon_asic rs690_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rs690_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
         .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 
@@ -424,11 +423,11 @@ static struct radeon_asic rv515_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
         .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 
@@ -467,11 +466,11 @@ static struct radeon_asic r520_asic = {
         .set_surface_reg = r100_set_surface_reg,
         .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r100_hdp_flush,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
         .hpd_sense = &rs600_hpd_sense,
         .hpd_set_polarity = &rs600_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
 };
 
 /*
@@ -508,12 +507,12 @@ int r600_ring_test(struct radeon_device *rdev);
 int r600_copy_blit(struct radeon_device *rdev,
                    uint64_t src_offset, uint64_t dst_offset,
                    unsigned num_pages, struct radeon_fence *fence);
-void r600_hdp_flush(struct radeon_device *rdev);
 void r600_hpd_init(struct radeon_device *rdev);
 void r600_hpd_fini(struct radeon_device *rdev);
 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 void r600_hpd_set_polarity(struct radeon_device *rdev,
                            enum radeon_hpd_id hpd);
+extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 
 static struct radeon_asic r600_asic = {
         .init = &r600_init,
@@ -544,11 +543,11 @@ static struct radeon_asic r600_asic = {
         .set_surface_reg = r600_set_surface_reg,
         .clear_surface_reg = r600_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r600_hdp_flush,
         .hpd_init = &r600_hpd_init,
         .hpd_fini = &r600_hpd_fini,
         .hpd_sense = &r600_hpd_sense,
         .hpd_set_polarity = &r600_hpd_set_polarity,
+        .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
 /*
@@ -589,11 +588,11 @@ static struct radeon_asic rv770_asic = {
         .set_surface_reg = r600_set_surface_reg,
         .clear_surface_reg = r600_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
-        .hdp_flush = &r600_hdp_flush,
         .hpd_init = &r600_hpd_init,
         .hpd_fini = &r600_hpd_fini,
         .hpd_sense = &r600_hpd_sense,
         .hpd_set_polarity = &r600_hpd_set_polarity,
+        .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 321044bef71c..4d8831548a5f 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -114,6 +114,7 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 
                         i2c.valid = true;
+                        break;
                 }
         }
 
@@ -205,6 +206,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                         *connector_type = DRM_MODE_CONNECTOR_DVID;
         }
 
+        /* Asrock RS600 board lists the DVI port as HDMI */
+        if ((dev->pdev->device == 0x7941) &&
+            (dev->pdev->subsystem_vendor == 0x1849) &&
+            (dev->pdev->subsystem_device == 0x7941)) {
+                if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
+                    (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
+                        *connector_type = DRM_MODE_CONNECTOR_DVID;
+        }
+
         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
         if ((dev->pdev->device == 0x7941) &&
             (dev->pdev->subsystem_vendor == 0x147b) &&
@@ -286,6 +296,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                         *connector_type = DRM_MODE_CONNECTOR_DVID;
         }
 
+        /* XFX Pine Group device rv730 reports no VGA DDC lines
+         * even though they are wired up to record 0x93
+         */
+        if ((dev->pdev->device == 0x9498) &&
+            (dev->pdev->subsystem_vendor == 0x1682) &&
+            (dev->pdev->subsystem_device == 0x2452)) {
+                struct radeon_device *rdev = dev->dev_private;
+                *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
+        }
         return true;
 }
 
@@ -345,7 +364,9 @@ const int object_connector_convert[] = {
         DRM_MODE_CONNECTOR_Unknown,
         DRM_MODE_CONNECTOR_Unknown,
         DRM_MODE_CONNECTOR_Unknown,
-        DRM_MODE_CONNECTOR_DisplayPort
+        DRM_MODE_CONNECTOR_DisplayPort,
+        DRM_MODE_CONNECTOR_eDP,
+        DRM_MODE_CONNECTOR_Unknown
 };
 
 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
@@ -935,6 +956,43 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
         return false;
 }
 
+union igp_info {
+        struct _ATOM_INTEGRATED_SYSTEM_INFO info;
+        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
+};
+
+bool radeon_atombios_sideport_present(struct radeon_device *rdev)
+{
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
+        union igp_info *igp_info;
+        u8 frev, crev;
+        u16 data_offset;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+                               &crev, &data_offset);
+
+        igp_info = (union igp_info *)(mode_info->atom_context->bios +
+                                      data_offset);
+
+        if (igp_info) {
+                switch (crev) {
+                case 1:
+                        if (igp_info->info.ucMemoryType & 0xf0)
+                                return true;
+                        break;
+                case 2:
+                        if (igp_info->info_2.ucMemoryType & 0x0f)
+                                return true;
+                        break;
+                default:
+                        DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
+                        break;
+                }
+        }
+        return false;
+}
+
 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
                                    struct radeon_encoder_int_tmds *tmds)
 {
@@ -1026,6 +1084,7 @@ static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
+                                break;
                         }
                 }
         }
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 4ddfd4b5bc51..7932dc4d6b90 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -65,31 +65,42 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
         if (r) {
                 goto out_cleanup;
         }
-        start_jiffies = jiffies;
-        for (i = 0; i < n; i++) {
-                r = radeon_fence_create(rdev, &fence);
-                if (r) {
-                        goto out_cleanup;
+
+        /* r100 doesn't have dma engine so skip the test */
+        if (rdev->asic->copy_dma) {
+
+                start_jiffies = jiffies;
+                for (i = 0; i < n; i++) {
+                        r = radeon_fence_create(rdev, &fence);
+                        if (r) {
+                                goto out_cleanup;
+                        }
+
+                        r = radeon_copy_dma(rdev, saddr, daddr,
+                                        size / RADEON_GPU_PAGE_SIZE, fence);
+
+                        if (r) {
+                                goto out_cleanup;
+                        }
+                        r = radeon_fence_wait(fence, false);
+                        if (r) {
+                                goto out_cleanup;
+                        }
+                        radeon_fence_unref(&fence);
                 }
-                r = radeon_copy_dma(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence);
-                if (r) {
-                        goto out_cleanup;
+                end_jiffies = jiffies;
+                time = end_jiffies - start_jiffies;
+                time = jiffies_to_msecs(time);
+                if (time > 0) {
+                        i = ((n * size) >> 10) / time;
+                        printk(KERN_INFO "radeon: dma %u bo moves of %ukb from"
+                                        " %d to %d in %lums (%ukb/ms %ukb/s %uM/s)\n",
+                                        n, size >> 10,
+                                        sdomain, ddomain, time,
+                                        i, i * 1000, (i * 1000) / 1024);
                 }
-                r = radeon_fence_wait(fence, false);
-                if (r) {
-                        goto out_cleanup;
-                }
-                radeon_fence_unref(&fence);
-        }
-        end_jiffies = jiffies;
-        time = end_jiffies - start_jiffies;
-        time = jiffies_to_msecs(time);
-        if (time > 0) {
-                i = ((n * size) >> 10) / time;
-                printk(KERN_INFO "radeon: dma %u bo moves of %ukb from %d to %d"
-                       " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10,
-                       sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024);
         }
+
         start_jiffies = jiffies;
         for (i = 0; i < n; i++) {
                 r = radeon_fence_create(rdev, &fence);
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 812f24dbc2a8..73c4405bf42f 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -56,7 +56,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
         else if (post_div == 3)
                 sclk >>= 2;
         else if (post_div == 4)
-                sclk >>= 4;
+                sclk >>= 3;
 
         return sclk;
 }
@@ -86,7 +86,7 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
         else if (post_div == 3)
                 mclk >>= 2;
         else if (post_div == 4)
-                mclk >>= 4;
+                mclk >>= 3;
 
         return mclk;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index fd94dbca33ac..e7b19440102e 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -595,6 +595,48 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
         return false;
 }
 
+bool radeon_combios_sideport_present(struct radeon_device *rdev)
+{
+        struct drm_device *dev = rdev->ddev;
+        u16 igp_info;
+
+        igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
+
+        if (igp_info) {
+                if (RBIOS16(igp_info + 0x4))
+                        return true;
+        }
+        return false;
+}
+
+static const uint32_t default_primarydac_adj[CHIP_LAST] = {
+        0x00000808,             /* r100  */
+        0x00000808,             /* rv100 */
+        0x00000808,             /* rs100 */
+        0x00000808,             /* rv200 */
+        0x00000808,             /* rs200 */
+        0x00000808,             /* r200  */
+        0x00000808,             /* rv250 */
+        0x00000000,             /* rs300 */
+        0x00000808,             /* rv280 */
+        0x00000808,             /* r300  */
+        0x00000808,             /* r350  */
+        0x00000808,             /* rv350 */
+        0x00000808,             /* rv380 */
+        0x00000808,             /* r420  */
+        0x00000808,             /* r423  */
+        0x00000808,             /* rv410 */
+        0x00000000,             /* rs400 */
+        0x00000000,             /* rs480 */
+};
+
+static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
+                                                          struct radeon_encoder_primary_dac *p_dac)
+{
+        p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
+        return;
+}
+
 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
                                                                        radeon_encoder
                                                                        *encoder)
@@ -604,20 +646,20 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
         uint16_t dac_info;
         uint8_t rev, bg, dac;
         struct radeon_encoder_primary_dac *p_dac = NULL;
+        int found = 0;
 
-        if (rdev->bios == NULL)
+        p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
+                        GFP_KERNEL);
+
+        if (!p_dac)
                 return NULL;
 
+        if (rdev->bios == NULL)
+                goto out;
+
         /* check CRT table */
         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
         if (dac_info) {
-                p_dac =
-                    kzalloc(sizeof(struct radeon_encoder_primary_dac),
-                            GFP_KERNEL);
-
-                if (!p_dac)
-                        return NULL;
-
                 rev = RBIOS8(dac_info) & 0x3;
                 if (rev < 2) {
                         bg = RBIOS8(dac_info + 0x2) & 0xf;
@@ -628,9 +670,13 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
                         dac = RBIOS8(dac_info + 0x3) & 0xf;
                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
                 }
-
+                found = 1;
         }
 
+out:
+        if (!found) /* fallback to defaults */
+                radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
+
         return p_dac;
 }
 
@@ -641,6 +687,9 @@ radeon_combios_get_tv_info(struct radeon_device *rdev)
         uint16_t tv_info;
         enum radeon_tv_std tv_std = TV_STD_NTSC;
 
+        if (rdev->bios == NULL)
+                return tv_std;
+
         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
         if (tv_info) {
                 if (RBIOS8(tv_info + 6) == 'T') {
@@ -922,8 +971,7 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
                          lvds->native_mode.vdisplay);
 
                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
-                if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
-                        lvds->panel_vcc_delay = 2000;
+                lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
 
                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 20161567dbff..65f81942f399 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -49,8 +49,10 @@ void radeon_connector_hotplug(struct drm_connector *connector)
         if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 
-        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
-                if (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
+        if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+            (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
+                if ((radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+                    (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_eDP)) {
                         if (radeon_dp_needs_link_train(radeon_connector)) {
                                 if (connector->encoder)
                                         dp_link_train(connector->encoder, connector);
@@ -578,16 +580,18 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         struct drm_encoder *encoder;
         struct drm_encoder_helper_funcs *encoder_funcs;
-        bool dret;
+        bool dret = false;
         enum drm_connector_status ret = connector_status_disconnected;
 
         encoder = radeon_best_single_encoder(connector);
         if (!encoder)
                 ret = connector_status_disconnected;
 
-        radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
-        dret = radeon_ddc_probe(radeon_connector);
-        radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
+        if (radeon_connector->ddc_bus) {
+                radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
+                dret = radeon_ddc_probe(radeon_connector);
+                radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
+        }
         if (dret) {
                 if (radeon_connector->edid) {
                         kfree(radeon_connector->edid);
@@ -615,7 +619,7 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
                                 ret = connector_status_connected;
                 }
         } else {
-                if (radeon_connector->dac_load_detect) {
+                if (radeon_connector->dac_load_detect && encoder) {
                         encoder_funcs = encoder->helper_private;
                         ret = encoder_funcs->detect(encoder, connector);
                 }
@@ -738,11 +742,13 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
         struct drm_mode_object *obj;
         int i;
         enum drm_connector_status ret = connector_status_disconnected;
-        bool dret;
+        bool dret = false;
 
-        radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
-        dret = radeon_ddc_probe(radeon_connector);
-        radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
+        if (radeon_connector->ddc_bus) {
+                radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
+                dret = radeon_ddc_probe(radeon_connector);
+                radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
+        }
         if (dret) {
                 if (radeon_connector->edid) {
                         kfree(radeon_connector->edid);
@@ -774,7 +780,7 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
                          * connected and the DVI port disconnected.  If the edid doesn't
                          * say HDMI, vice versa.
                          */
-                        if (radeon_connector->shared_ddc && connector_status_connected) {
+                        if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
                                 struct drm_device *dev = connector->dev;
                                 struct drm_connector *list_connector;
                                 struct radeon_connector *list_radeon_connector;
@@ -898,10 +904,18 @@ static void radeon_dvi_force(struct drm_connector *connector)
 static int radeon_dvi_mode_valid(struct drm_connector *connector,
                                   struct drm_display_mode *mode)
 {
+        struct drm_device *dev = connector->dev;
+        struct radeon_device *rdev = dev->dev_private;
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 
         /* XXX check mode bandwidth */
 
+        /* clocks over 135 MHz have heat issues with DVI on RV100 */
+        if (radeon_connector->use_digital &&
+            (rdev->family == CHIP_RV100) &&
+            (mode->clock > 135000))
+                return MODE_CLOCK_HIGH;
+
         if (radeon_connector->use_digital && (mode->clock > 165000)) {
                 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
                     (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
@@ -967,7 +981,8 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
         }
 
         sink_type = radeon_dp_getsinktype(radeon_connector);
-        if (sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
+        if ((sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+            (sink_type == CONNECTOR_OBJECT_ID_eDP)) {
                 if (radeon_dp_getdpcd(radeon_connector)) {
                         radeon_dig_connector->dp_sink_type = sink_type;
                         ret = connector_status_connected;
@@ -992,7 +1007,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
 
         /* XXX check mode bandwidth */
 
-        if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
+        if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+            (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                 return radeon_dp_mode_valid_helper(radeon_connector, mode);
         else
                 return MODE_OK;
@@ -1044,8 +1060,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                         return;
                 }
                 if (radeon_connector->ddc_bus && i2c_bus->valid) {
-                        if (memcmp(&radeon_connector->ddc_bus->rec, i2c_bus,
-                                    sizeof(struct radeon_i2c_bus_rec)) == 0) {
+                        if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
                                 radeon_connector->shared_ddc = true;
                                 shared_ddc = true;
                         }
@@ -1145,6 +1160,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                 subpixel_order = SubPixelHorizontalRGB;
                 break;
         case DRM_MODE_CONNECTOR_DisplayPort:
+        case DRM_MODE_CONNECTOR_eDP:
                 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                 if (!radeon_dig_connector)
                         goto failed;
@@ -1157,10 +1173,16 @@ radeon_add_atom_connector(struct drm_device *dev,
                         goto failed;
                 if (i2c_bus->valid) {
                         /* add DP i2c bus */
-                        radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
+                        if (connector_type == DRM_MODE_CONNECTOR_eDP)
+                                radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
+                        else
+                                radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
                         if (!radeon_dig_connector->dp_i2c_bus)
                                 goto failed;
-                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
+                        if (connector_type == DRM_MODE_CONNECTOR_eDP)
+                                radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "eDP");
+                        else
+                                radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
                         if (!radeon_connector->ddc_bus)
                                 goto failed;
                 }
@@ -1324,7 +1346,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
                                 radeon_connector->dac_load_detect = false;
                         drm_connector_attach_property(&radeon_connector->base,
                                                       rdev->mode_info.load_detect_property,
-                                                      1);
+                                                      radeon_connector->dac_load_detect);
                         drm_connector_attach_property(&radeon_connector->base,
                                                       rdev->mode_info.tv_std_property,
                                                       radeon_combios_get_tv_info(rdev));
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 0b2f9c2ad2c1..06123ba31d31 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -2145,6 +2145,7 @@ int radeon_master_create(struct drm_device *dev, struct drm_master *master)
                          &master_priv->sarea);
         if (ret) {
                 DRM_ERROR("SAREA setup failed\n");
+                kfree(master_priv);
                 return ret;
         }
         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 65590a0f1d93..e9d085021c1f 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -86,7 +86,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
                                                 &p->validated);
                 }
         }
-        return radeon_bo_list_validate(&p->validated, p->ib->fence);
+        return radeon_bo_list_validate(&p->validated);
 }
 
 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
@@ -189,12 +189,10 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
 {
         unsigned i;
 
-        if (error) {
-                radeon_bo_list_unvalidate(&parser->validated,
-                                                parser->ib->fence);
-        } else {
-                radeon_bo_list_unreserve(&parser->validated);
+        if (!error && parser->ib) {
+                radeon_bo_list_fence(&parser->validated, parser->ib->fence);
         }
+        radeon_bo_list_unreserve(&parser->validated);
         for (i = 0; i < parser->nrelocs; i++) {
                 if (parser->relocs[i].gobj) {
                         mutex_lock(&parser->rdev->ddev->struct_mutex);
@@ -231,6 +229,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
         memset(&parser, 0, sizeof(struct radeon_cs_parser));
         parser.filp = filp;
         parser.rdev = rdev;
+        parser.dev = rdev->dev;
         r = radeon_cs_parser_init(&parser, data);
         if (r) {
                 DRM_ERROR("Failed to initialize parser !\n");
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7c6848096bcd..768b1509fa03 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -544,6 +544,7 @@ void radeon_agp_disable(struct radeon_device *rdev)
                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
         }
+        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 }
 
 void radeon_check_arguments(struct radeon_device *rdev)
@@ -733,16 +734,18 @@ void radeon_device_fini(struct radeon_device *rdev)
  */
 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 {
-        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_device *rdev;
         struct drm_crtc *crtc;
         int r;
 
-        if (dev == NULL || rdev == NULL) {
+        if (dev == NULL || dev->dev_private == NULL) {
                 return -ENODEV;
         }
         if (state.event == PM_EVENT_PRETHAW) {
                 return 0;
         }
+        rdev = dev->dev_private;
+
         /* unpin the front buffers */
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 91d72b70abc9..7e17a362b54b 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -234,7 +234,7 @@ static const char *encoder_names[34] = {
         "INTERNAL_UNIPHY2",
 };
 
-static const char *connector_names[13] = {
+static const char *connector_names[15] = {
         "Unknown",
         "VGA",
         "DVI-I",
@@ -248,6 +248,8 @@ static const char *connector_names[13] = {
         "DisplayPort",
         "HDMI-A",
         "HDMI-B",
+        "TV",
+        "eDP",
 };
 
 static const char *hpd_names[7] = {
@@ -276,7 +278,7 @@ static void radeon_print_display_setup(struct drm_device *dev)
                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
-                if (radeon_connector->ddc_bus)
+                if (radeon_connector->ddc_bus) {
                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
                                  radeon_connector->ddc_bus->rec.mask_data_reg,
@@ -286,6 +288,15 @@ static void radeon_print_display_setup(struct drm_device *dev)
                                  radeon_connector->ddc_bus->rec.en_data_reg,
                                  radeon_connector->ddc_bus->rec.y_clk_reg,
                                  radeon_connector->ddc_bus->rec.y_data_reg);
+                } else {
+                        if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
+                                DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
+                }
                 DRM_INFO("  Encoders:\n");
                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                         radeon_encoder = to_radeon_encoder(encoder);
@@ -329,8 +340,11 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
                         else
                                 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
-                } else
+                } else {
                         ret = radeon_get_legacy_connector_info_from_bios(dev);
+                        if (ret == false)
+                                ret = radeon_get_legacy_connector_info_from_table(dev);
+                }
         } else {
                 if (!ASIC_IS_AVIVO(rdev))
                         ret = radeon_get_legacy_connector_info_from_table(dev);
@@ -349,9 +363,11 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 {
         int ret = 0;
 
-        if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+        if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+            (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
-                if (dig->dp_i2c_bus)
+                if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
+                     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
         }
         if (!radeon_connector->ddc_bus)
@@ -404,11 +420,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
                         uint32_t *fb_div_p,
                         uint32_t *frac_fb_div_p,
                         uint32_t *ref_div_p,
-                        uint32_t *post_div_p,
-                        int flags)
+                        uint32_t *post_div_p)
 {
         uint32_t min_ref_div = pll->min_ref_div;
         uint32_t max_ref_div = pll->max_ref_div;
+        uint32_t min_post_div = pll->min_post_div;
+        uint32_t max_post_div = pll->max_post_div;
         uint32_t min_fractional_feed_div = 0;
         uint32_t max_fractional_feed_div = 0;
         uint32_t best_vco = pll->best_vco;
@@ -424,7 +441,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
         DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
         freq = freq * 1000;
 
-        if (flags & RADEON_PLL_USE_REF_DIV)
+        if (pll->flags & RADEON_PLL_USE_REF_DIV)
                 min_ref_div = max_ref_div = pll->reference_div;
         else {
                 while (min_ref_div < max_ref_div-1) {
@@ -439,19 +456,22 @@ void radeon_compute_pll(struct radeon_pll *pll,
                 }
         }
 
-        if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+        if (pll->flags & RADEON_PLL_USE_POST_DIV)
+                min_post_div = max_post_div = pll->post_div;
+
+        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
                 min_fractional_feed_div = pll->min_frac_feedback_div;
                 max_fractional_feed_div = pll->max_frac_feedback_div;
         }
 
-        for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
+        for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
                 uint32_t ref_div;
 
-                if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+                if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
                         continue;
 
                 /* legacy radeons only have a few post_divs */
-                if (flags & RADEON_PLL_LEGACY) {
+                if (pll->flags & RADEON_PLL_LEGACY) {
                         if ((post_div == 5) ||
                             (post_div == 7) ||
                             (post_div == 9) ||
@@ -498,7 +518,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
                                         current_freq = radeon_div(tmp, ref_div * post_div);
 
-                                        if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
+                                        if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
                                                 error = freq - current_freq;
                                                 error = error < 0 ? 0xffffffff : error;
                                         } else
@@ -525,12 +545,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                                         best_freq = current_freq;
                                                         best_error = error;
                                                         best_vco_diff = vco_diff;
-                                                } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
+                                                } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
                                                         best_post_div = post_div;
                                                         best_ref_div = ref_div;
                                                         best_feedback_div = feedback_div;
@@ -566,8 +586,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
                               uint32_t *fb_div_p,
                               uint32_t *frac_fb_div_p,
                               uint32_t *ref_div_p,
-                              uint32_t *post_div_p,
-                              int flags)
+                              uint32_t *post_div_p)
 {
         fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
         fixed20_12 pll_out_max, pll_out_min;
@@ -661,7 +680,6 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
                 radeonfb_remove(dev, fb);
 
         if (radeon_fb->obj) {
-                radeon_gem_object_unpin(radeon_fb->obj);
                 mutex_lock(&dev->struct_mutex);
                 drm_gem_object_unreference(radeon_fb->obj);
                 mutex_unlock(&dev->struct_mutex);
@@ -709,7 +727,11 @@ radeon_user_framebuffer_create(struct drm_device *dev,
         struct drm_gem_object *obj;
 
         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
-
+        if (obj ==  NULL) {
+                dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
+                        "can't create framebuffer\n", mode_cmd->handle);
+                return NULL;
+        }
         return radeon_framebuffer_create(dev, mode_cmd, obj);
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index e13785282a82..c57ad606504d 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -106,9 +106,10 @@
  * 1.29- R500 3D cmd buffer support
  * 1.30- Add support for occlusion queries
  * 1.31- Add support for num Z pipes from GET_PARAM
+ * 1.32- fixes for rv740 setup
  */
 #define DRIVER_MAJOR            1
-#define DRIVER_MINOR            31
+#define DRIVER_MINOR            32
 #define DRIVER_PATCHLEVEL       0
 
 enum radeon_cp_microcode_version {
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index ccba95f83d11..3c91724457ca 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -156,6 +156,26 @@ radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t
         return ret;
 }
 
+static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
+{
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+        case ENCODER_OBJECT_ID_INTERNAL_DDI:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                return true;
+        default:
+                return false;
+        }
+}
 void
 radeon_link_encoder_connector(struct drm_device *dev)
 {
@@ -202,7 +222,7 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 radeon_connector = to_radeon_connector(connector);
-                if (radeon_encoder->devices & radeon_connector->devices)
+                if (radeon_encoder->active_device & radeon_connector->devices)
                         return connector;
         }
         return NULL;
@@ -596,21 +616,23 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                 return ATOM_ENCODER_MODE_LVDS;
                 break;
         case DRM_MODE_CONNECTOR_DisplayPort:
+        case DRM_MODE_CONNECTOR_eDP:
                 radeon_dig_connector = radeon_connector->con_priv;
-                if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
+                if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+                    (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                         return ATOM_ENCODER_MODE_DP;
                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
                         return ATOM_ENCODER_MODE_HDMI;
                 else
                         return ATOM_ENCODER_MODE_DVI;
                 break;
-        case CONNECTOR_DVI_A:
-        case CONNECTOR_VGA:
+        case DRM_MODE_CONNECTOR_DVIA:
+        case DRM_MODE_CONNECTOR_VGA:
                 return ATOM_ENCODER_MODE_CRT;
                 break;
-        case CONNECTOR_STV:
-        case CONNECTOR_CTV:
-        case CONNECTOR_DIN:
+        case DRM_MODE_CONNECTOR_Composite:
+        case DRM_MODE_CONNECTOR_SVIDEO:
+        case DRM_MODE_CONNECTOR_9PinDIN:
                 /* fix me */
                 return ATOM_ENCODER_MODE_TV;
                 /*return ATOM_ENCODER_MODE_CV;*/
@@ -674,31 +696,11 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 
         memset(&args, 0, sizeof(args));
 
-        if (ASIC_IS_DCE32(rdev)) {
-                if (dig->dig_block)
-                        index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
-                else
-                        index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
-                num = dig->dig_block + 1;
-        } else {
-                switch (radeon_encoder->encoder_id) {
-                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-                        /* XXX doesn't really matter which dig encoder we pick as long as it's
-                         * not already in use
-                         */
-                        if (dig_connector->linkb)
-                                index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
-                        else
-                                index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
-                        num = 1;
-                        break;
-                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                        /* Only dig2 encoder can drive LVTMA */
-                        index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
-                        num = 2;
-                        break;
-                }
-        }
+        if (dig->dig_encoder)
+                index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
+        else
+                index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
+        num = dig->dig_encoder + 1;
 
         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 
@@ -820,7 +822,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
         }
         if (ASIC_IS_DCE32(rdev)) {
-                if (dig->dig_block)
+                if (dig->dig_encoder == 1)
                         args.v2.acConfig.ucEncoderSel = 1;
                 if (dig_connector->linkb)
                         args.v2.acConfig.ucLinkSel = 1;
@@ -847,17 +849,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                                 args.v2.acConfig.fCoherentMode = 1;
                 }
         } else {
+
                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 
+                if (dig->dig_encoder)
+                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
+                else
+                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
+
                 switch (radeon_encoder->encoder_id) {
                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-                        /* XXX doesn't really matter which dig encoder we pick as long as it's
-                         * not already in use
-                         */
-                        if (dig_connector->linkb)
-                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
-                        else
-                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
                         if (rdev->flags & RADEON_IS_IGP) {
                                 if (radeon_encoder->pixel_clock > 165000) {
                                         if (dig_connector->igp_lane_info & 0x3)
@@ -876,10 +877,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                                 }
                         }
                         break;
-                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                        /* Only dig2 encoder can drive LVTMA */
-                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
-                        break;
                 }
 
                 if (radeon_encoder->pixel_clock > 165000)
@@ -1044,6 +1041,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
         union crtc_sourc_param args;
         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
         uint8_t frev, crev;
+        struct radeon_encoder_atom_dig *dig;
 
         memset(&args, 0, sizeof(args));
 
@@ -1107,40 +1105,16 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-                                if (ASIC_IS_DCE32(rdev)) {
-                                        if (radeon_crtc->crtc_id)
-                                                args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
-                                        else
-                                                args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
-                                } else {
-                                        struct drm_connector *connector;
-                                        struct radeon_connector *radeon_connector;
-                                        struct radeon_connector_atom_dig *dig_connector;
-
-                                        connector = radeon_get_connector_for_encoder(encoder);
-                                        if (!connector)
-                                                return;
-                                        radeon_connector = to_radeon_connector(connector);
-                                        if (!radeon_connector->con_priv)
-                                                return;
-                                        dig_connector = radeon_connector->con_priv;
-
-                                        /* XXX doesn't really matter which dig encoder we pick as long as it's
-                                         * not already in use
-                                         */
-                                        if (dig_connector->linkb)
-                                                args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
-                                        else
-                                                args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
-                                }
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                                dig = radeon_encoder->enc_priv;
+                                if (dig->dig_encoder)
+                                        args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
+                                else
+                                        args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
                                 break;
                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
                                 break;
-                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                                /* Only dig2 encoder can drive LVTMA */
-                                args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
-                                break;
                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
@@ -1200,6 +1174,47 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
         }
 }
 
+static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_encoder *test_encoder;
+        struct radeon_encoder_atom_dig *dig;
+        uint32_t dig_enc_in_use = 0;
+        /* on DCE32 and encoder can driver any block so just crtc id */
+        if (ASIC_IS_DCE32(rdev)) {
+                return radeon_crtc->crtc_id;
+        }
+
+        /* on DCE3 - LVTMA can only be driven by DIGB */
+        list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
+                struct radeon_encoder *radeon_test_encoder;
+
+                if (encoder == test_encoder)
+                        continue;
+
+                if (!radeon_encoder_is_digital(test_encoder))
+                        continue;
+
+                radeon_test_encoder = to_radeon_encoder(test_encoder);
+                dig = radeon_test_encoder->enc_priv;
+
+                if (dig->dig_encoder >= 0)
+                        dig_enc_in_use |= (1 << dig->dig_encoder);
+        }
+
+        if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
+                if (dig_enc_in_use & 0x2)
+                        DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
+                return 1;
+        }
+        if (!(dig_enc_in_use & 1))
+                return 0;
+        return 1;
+}
+
 static void
 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
                              struct drm_display_mode *mode,
@@ -1212,12 +1227,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 
         if (radeon_encoder->active_device &
             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
-                if (radeon_encoder->enc_priv) {
-                        struct radeon_encoder_atom_dig *dig;
-
-                        dig = radeon_encoder->enc_priv;
-                        dig->dig_block = radeon_crtc->crtc_id;
-                }
+                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+                if (dig)
+                        dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
         }
         radeon_encoder->pixel_clock = adjusted_mode->clock;
 
@@ -1377,7 +1389,13 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
 {
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_encoder_atom_dig *dig;
         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+
+        if (radeon_encoder_is_digital(encoder)) {
+                dig = radeon_encoder->enc_priv;
+                dig->dig_encoder = -1;
+        }
         radeon_encoder->active_device = 0;
 }
 
@@ -1434,6 +1452,7 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
 
         /* coherent mode by default */
         dig->coherent_mode = true;
+        dig->dig_encoder = -1;
 
         return dig;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 3ba213d1b06c..d71e346e9ab5 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -248,7 +248,7 @@ int radeonfb_create(struct drm_device *dev,
         if (ret)
                 goto out_unref;
 
-        memset_io(fbptr, 0xff, aligned_size);
+        memset_io(fbptr, 0x0, aligned_size);
 
         strcpy(info->fix.id, "radeondrmfb");
 
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 4cdd8b4f7549..8495d4e32e18 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -140,16 +140,15 @@ int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
 
 bool radeon_fence_signaled(struct radeon_fence *fence)
 {
-        struct radeon_device *rdev = fence->rdev;
         unsigned long irq_flags;
         bool signaled = false;
 
-        if (rdev->gpu_lockup) {
+        if (!fence)
                 return true;
-        }
-        if (fence == NULL) {
+
+        if (fence->rdev->gpu_lockup)
                 return true;
-        }
+
         write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
         signaled = fence->signaled;
         /* if we are shuting down report all fence as signaled */
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 60df2d7e7e4c..db8e9a355a01 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -131,7 +131,6 @@ int radeon_gem_set_domain(struct drm_gem_object *gobj,
                         printk(KERN_ERR "Failed to wait for object !\n");
                         return r;
                 }
-                radeon_hdp_flush(robj->rdev);
         }
         return 0;
 }
@@ -309,10 +308,12 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
         }
         robj = gobj->driver_private;
         r = radeon_bo_wait(robj, NULL, false);
+        /* callback hw specific functions if any */
+        if (robj->rdev->asic->ioctl_wait_idle)
+                robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
         mutex_lock(&dev->struct_mutex);
         drm_gem_object_unreference(gobj);
         mutex_unlock(&dev->struct_mutex);
-        radeon_hdp_flush(robj->rdev);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index b79ecc4a7cc4..2f349a300195 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -289,16 +289,16 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr
         drm_radeon_irq_emit_t *emit = data;
         int result;
 
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
-                return -EINVAL;
-
-        LOCK_TEST_WITH_RETURN(dev, file_priv);
-
         if (!dev_priv) {
                 DRM_ERROR("called with no initialization\n");
                 return -EINVAL;
         }
 
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+                return -EINVAL;
+
+        LOCK_TEST_WITH_RETURN(dev, file_priv);
+
         result = radeon_emit_irq(dev);
 
         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9223296fe37b..3cfd60fd0083 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -97,6 +97,7 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
         rdev->irq.sw_int = false;
         for (i = 0; i < 2; i++) {
                 rdev->irq.crtc_vblank_int[i] = false;
+                rdev->irq.hpd[i] = false;
         }
         radeon_irq_set(rdev);
 }
@@ -128,17 +129,22 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
                         DRM_INFO("radeon: using MSI.\n");
                 }
         }
-        drm_irq_install(rdev->ddev);
         rdev->irq.installed = true;
+        r = drm_irq_install(rdev->ddev);
+        if (r) {
+                rdev->irq.installed = false;
+                return r;
+        }
         DRM_INFO("radeon: irq initialized.\n");
         return 0;
 }
 
 void radeon_irq_kms_fini(struct radeon_device *rdev)
 {
+        drm_vblank_cleanup(rdev->ddev);
         if (rdev->irq.installed) {
-                rdev->irq.installed = false;
                 drm_irq_uninstall(rdev->ddev);
+                rdev->irq.installed = false;
                 if (rdev->msi_enabled)
                         pci_disable_msi(rdev->pdev);
         }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index cc27485a07ad..b6d8081e1246 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -339,69 +339,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
         }
 }
 
-/* properly set crtc bpp when using atombios */
-void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
-{
-        struct drm_device *dev = crtc->dev;
-        struct radeon_device *rdev = dev->dev_private;
-        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-        int format;
-        uint32_t crtc_gen_cntl;
-        uint32_t disp_merge_cntl;
-        uint32_t crtc_pitch;
-
-        switch (crtc->fb->bits_per_pixel) {
-        case 8:
-                format = 2;
-                break;
-        case 15:      /*  555 */
-                format = 3;
-                break;
-        case 16:      /*  565 */
-                format = 4;
-                break;
-        case 24:      /*  RGB */
-                format = 5;
-                break;
-        case 32:      /* xRGB */
-                format = 6;
-                break;
-        default:
-                return;
-        }
-
-        crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
-                        ((crtc->fb->bits_per_pixel * 8) - 1)) /
-                       (crtc->fb->bits_per_pixel * 8));
-        crtc_pitch |= crtc_pitch << 16;
-
-        WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
-
-        switch (radeon_crtc->crtc_id) {
-        case 0:
-                disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
-                disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
-                WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
-
-                crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
-                crtc_gen_cntl |= (format << 8);
-                crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
-                WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
-                break;
-        case 1:
-                disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
-                disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
-                WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
-
-                crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
-                crtc_gen_cntl |= (format << 8);
-                WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
-                WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
-                WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
-                break;
-        }
-}
-
 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                          struct drm_framebuffer *old_fb)
 {
@@ -755,7 +692,6 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
         uint32_t post_divider = 0;
         uint32_t freq = 0;
         uint8_t pll_gain;
-        int pll_flags = RADEON_PLL_LEGACY;
         bool use_bios_divs = false;
         /* PLL registers */
         uint32_t pll_ref_div = 0;
@@ -789,10 +725,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
         else
                 pll = &rdev->clock.p1pll;
 
+        pll->flags = RADEON_PLL_LEGACY;
+
         if (mode->clock > 200000) /* range limits??? */
-                pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
         else
-                pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+                pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                 if (encoder->crtc == crtc) {
@@ -804,7 +742,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                         }
 
                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
-                                pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
+                                pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
                                 if (!rdev->is_atom_bios) {
                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -819,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                                                 }
                                         }
                                 }
-                                pll_flags |= RADEON_PLL_USE_REF_DIV;
+                                pll->flags |= RADEON_PLL_USE_REF_DIV;
                         }
                 }
         }
@@ -829,8 +767,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
         if (!use_bios_divs) {
                 radeon_compute_pll(pll, mode->clock,
                                    &freq, &feedback_div, &frac_fb_div,
-                                   &reference_div, &post_divider,
-                                   pll_flags);
+                                   &reference_div, &post_divider);
 
                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
                         if (post_div->divider == post_divider)
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 981508ff7037..38e45e231ef5 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -46,6 +46,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
         int panel_pwr_delay = 2000;
+        bool is_mac = false;
         DRM_DEBUG("\n");
 
         if (radeon_encoder->enc_priv) {
@@ -58,6 +59,15 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
                 }
         }
 
+        /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
+         * Taken from radeonfb.
+         */
+        if ((rdev->mode_info.connector_table == CT_IBOOK) ||
+            (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
+            (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
+            (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
+                is_mac = true;
+
         switch (mode) {
         case DRM_MODE_DPMS_ON:
                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
@@ -74,6 +84,8 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 
                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
+                if (is_mac)
+                        lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
                 udelay(panel_pwr_delay * 1000);
                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
@@ -85,7 +97,14 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
-                lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
+                if (is_mac) {
+                        lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
+                        WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+                        lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
+                } else {
+                        WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+                        lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
+                }
                 udelay(panel_pwr_delay * 1000);
                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 3a12bb0c0563..417684daef4c 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -77,7 +77,7 @@ struct radeon_tv_mode_constants {
         unsigned pix_to_tv;
 };
 
-static const uint16_t hor_timing_NTSC[] = {
+static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
         0x0007,
         0x003f,
         0x0263,
@@ -98,7 +98,7 @@ static const uint16_t hor_timing_NTSC[] = {
         0
 };
 
-static const uint16_t vert_timing_NTSC[] = {
+static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
         0x2001,
         0x200d,
         0x1006,
@@ -115,7 +115,7 @@ static const uint16_t vert_timing_NTSC[] = {
         0
 };
 
-static const uint16_t hor_timing_PAL[] = {
+static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
         0x0007,
         0x0058,
         0x027c,
@@ -136,7 +136,7 @@ static const uint16_t hor_timing_PAL[] = {
         0
 };
 
-static const uint16_t vert_timing_PAL[] =       {
+static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
         0x2001,
         0x200c,
         0x1005,
@@ -623,9 +623,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
         }
         flicker_removal = (tmp + 500) / 1000;
 
-        if (flicker_removal < 3)
-                flicker_removal = 3;
-        for (i = 0; i < 6; ++i) {
+        if (flicker_removal < 2)
+                flicker_removal = 2;
+        for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
                 if (flicker_removal == SLOPE_limit[i])
                         break;
         }
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 402369db5ba0..e81b2aeb6a8f 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -46,32 +46,6 @@ struct radeon_device;
 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
 
-enum radeon_connector_type {
-        CONNECTOR_NONE,
-        CONNECTOR_VGA,
-        CONNECTOR_DVI_I,
-        CONNECTOR_DVI_D,
-        CONNECTOR_DVI_A,
-        CONNECTOR_STV,
-        CONNECTOR_CTV,
-        CONNECTOR_LVDS,
-        CONNECTOR_DIGITAL,
-        CONNECTOR_SCART,
-        CONNECTOR_HDMI_TYPE_A,
-        CONNECTOR_HDMI_TYPE_B,
-        CONNECTOR_0XC,
-        CONNECTOR_0XD,
-        CONNECTOR_DIN,
-        CONNECTOR_DISPLAY_PORT,
-        CONNECTOR_UNSUPPORTED
-};
-
-enum radeon_dvi_type {
-        DVI_AUTO,
-        DVI_DIGITAL,
-        DVI_ANALOG
-};
-
 enum radeon_rmx_type {
         RMX_OFF,
         RMX_FULL,
@@ -151,16 +125,24 @@ struct radeon_tmds_pll {
 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
+#define RADEON_PLL_USE_POST_DIV         (1 << 12)
 
 struct radeon_pll {
-        uint16_t reference_freq;
-        uint16_t reference_div;
+        /* reference frequency */
+        uint32_t reference_freq;
+
+        /* fixed dividers */
+        uint32_t reference_div;
+        uint32_t post_div;
+
+        /* pll in/out limits */
         uint32_t pll_in_min;
         uint32_t pll_in_max;
         uint32_t pll_out_min;
         uint32_t pll_out_max;
-        uint16_t xclk;
+        uint32_t best_vco;
 
+        /* divider limits */
         uint32_t min_ref_div;
         uint32_t max_ref_div;
         uint32_t min_post_div;
@@ -169,7 +151,12 @@ struct radeon_pll {
         uint32_t max_feedback_div;
         uint32_t min_frac_feedback_div;
         uint32_t max_frac_feedback_div;
-        uint32_t best_vco;
+
+        /* flags for the current clock */
+        uint32_t flags;
+
+        /* pll id */
+        uint32_t id;
 };
 
 struct radeon_i2c_chan {
@@ -312,7 +299,7 @@ struct radeon_atom_ss {
 struct radeon_encoder_atom_dig {
         /* atom dig */
         bool coherent_mode;
-        int dig_block;
+        int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
         /* atom lvds */
         uint32_t lvds_misc;
         uint16_t panel_pwr_delay;
@@ -443,8 +430,7 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
                                uint32_t *fb_div_p,
                                uint32_t *frac_fb_div_p,
                                uint32_t *ref_div_p,
-                               uint32_t *post_div_p,
-                               int flags);
+                               uint32_t *post_div_p);
 
 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
                                      uint64_t freq,
@@ -452,8 +438,7 @@ extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
                                      uint32_t *fb_div_p,
                                      uint32_t *frac_fb_div_p,
                                      uint32_t *ref_div_p,
-                                     uint32_t *post_div_p,
-                                     int flags);
+                                     uint32_t *post_div_p);
 
 extern void radeon_setup_encoder_clones(struct drm_device *dev);
 
@@ -479,7 +464,6 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
 
 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                                  struct drm_framebuffer *old_fb);
-extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
 
 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
                                   struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d9ffe1f56e8f..f1da370928eb 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -220,9 +220,11 @@ int radeon_bo_unpin(struct radeon_bo *bo)
 
 int radeon_bo_evict_vram(struct radeon_device *rdev)
 {
-        if (rdev->flags & RADEON_IS_IGP) {
-                /* Useless to evict on IGP chips */
-                return 0;
+        /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
+        if (0 && (rdev->flags & RADEON_IS_IGP)) {
+                if (rdev->mc.igp_sideport_enabled == false)
+                        /* Useless to evict on IGP chips */
+                        return 0;
         }
         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 }
@@ -304,11 +306,10 @@ void radeon_bo_list_unreserve(struct list_head *head)
         }
 }
 
-int radeon_bo_list_validate(struct list_head *head, void *fence)
+int radeon_bo_list_validate(struct list_head *head)
 {
         struct radeon_bo_list *lobj;
         struct radeon_bo *bo;
-        struct radeon_fence *old_fence = NULL;
         int r;
 
         r = radeon_bo_list_reserve(head);
@@ -332,32 +333,27 @@ int radeon_bo_list_validate(struct list_head *head, void *fence)
                 }
                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
                 lobj->tiling_flags = bo->tiling_flags;
-                if (fence) {
-                        old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
-                        bo->tbo.sync_obj = radeon_fence_ref(fence);
-                        bo->tbo.sync_obj_arg = NULL;
-                }
-                if (old_fence) {
-                        radeon_fence_unref(&old_fence);
-                }
         }
         return 0;
 }
 
-void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
+void radeon_bo_list_fence(struct list_head *head, void *fence)
 {
         struct radeon_bo_list *lobj;
-        struct radeon_fence *old_fence;
-
-        if (fence)
-                list_for_each_entry(lobj, head, list) {
-                        old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
-                        if (old_fence == fence) {
-                                lobj->bo->tbo.sync_obj = NULL;
-                                radeon_fence_unref(&old_fence);
-                        }
+        struct radeon_bo *bo;
+        struct radeon_fence *old_fence = NULL;
+
+        list_for_each_entry(lobj, head, list) {
+                bo = lobj->bo;
+                spin_lock(&bo->tbo.lock);
+                old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
+                bo->tbo.sync_obj = radeon_fence_ref(fence);
+                bo->tbo.sync_obj_arg = NULL;
+                spin_unlock(&bo->tbo.lock);
+                if (old_fence) {
+                        radeon_fence_unref(&old_fence);
                 }
-        radeon_bo_list_unreserve(head);
+        }
 }
 
 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index a02f18011ad1..7ab43de1e244 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -156,8 +156,8 @@ extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
                                 struct list_head *head);
 extern int radeon_bo_list_reserve(struct list_head *head);
 extern void radeon_bo_list_unreserve(struct list_head *head);
-extern int radeon_bo_list_validate(struct list_head *head, void *fence);
-extern void radeon_bo_list_unvalidate(struct list_head *head, void *fence);
+extern int radeon_bo_list_validate(struct list_head *head);
+extern void radeon_bo_list_fence(struct list_head *head, void *fence);
 extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
                                 struct vm_area_struct *vma);
 extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 4d12b2d17b4d..6579eb4c1f28 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -41,68 +41,55 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
 {
         struct radeon_fence *fence;
         struct radeon_ib *nib;
-        unsigned long i;
-        int r = 0;
+        int r = 0, i, c;
 
         *ib = NULL;
         r = radeon_fence_create(rdev, &fence);
         if (r) {
-                DRM_ERROR("failed to create fence for new IB\n");
+                dev_err(rdev->dev, "failed to create fence for new IB\n");
                 return r;
         }
         mutex_lock(&rdev->ib_pool.mutex);
-        i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
-        if (i < RADEON_IB_POOL_SIZE) {
-                set_bit(i, rdev->ib_pool.alloc_bm);
-                rdev->ib_pool.ibs[i].length_dw = 0;
-                *ib = &rdev->ib_pool.ibs[i];
-                mutex_unlock(&rdev->ib_pool.mutex);
-                goto out;
+        for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
+                i &= (RADEON_IB_POOL_SIZE - 1);
+                if (rdev->ib_pool.ibs[i].free) {
+                        nib = &rdev->ib_pool.ibs[i];
+                        break;
+                }
         }
-        if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
-                /* we go do nothings here */
+        if (nib == NULL) {
+                /* This should never happen, it means we allocated all
+                 * IB and haven't scheduled one yet, return EBUSY to
+                 * userspace hoping that on ioctl recall we get better
+                 * luck
+                 */
+                dev_err(rdev->dev, "no free indirect buffer !\n");
                 mutex_unlock(&rdev->ib_pool.mutex);
-                DRM_ERROR("all IB allocated none scheduled.\n");
-                r = -EINVAL;
-                goto out;
+                radeon_fence_unref(&fence);
+                return -EBUSY;
         }
-        /* get the first ib on the scheduled list */
-        nib = list_entry(rdev->ib_pool.scheduled_ibs.next,
-                         struct radeon_ib, list);
-        if (nib->fence == NULL) {
-                /* we go do nothings here */
+        rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
+        nib->free = false;
+        if (nib->fence) {
                 mutex_unlock(&rdev->ib_pool.mutex);
-                DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
-                r = -EINVAL;
-                goto out;
-        }
-        mutex_unlock(&rdev->ib_pool.mutex);
-
-        r = radeon_fence_wait(nib->fence, false);
-        if (r) {
-                DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
-                          (unsigned long)nib->gpu_addr, nib->length_dw);
-                DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");
-                goto out;
+                r = radeon_fence_wait(nib->fence, false);
+                if (r) {
+                        dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
+                                nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
+                        mutex_lock(&rdev->ib_pool.mutex);
+                        nib->free = true;
+                        mutex_unlock(&rdev->ib_pool.mutex);
+                        radeon_fence_unref(&fence);
+                        return r;
+                }
+                mutex_lock(&rdev->ib_pool.mutex);
         }
         radeon_fence_unref(&nib->fence);
-
+        nib->fence = fence;
         nib->length_dw = 0;
-
-        /* scheduled list is accessed here */
-        mutex_lock(&rdev->ib_pool.mutex);
-        list_del(&nib->list);
-        INIT_LIST_HEAD(&nib->list);
         mutex_unlock(&rdev->ib_pool.mutex);
-
         *ib = nib;
-out:
-        if (r) {
-                radeon_fence_unref(&fence);
-        } else {
-                (*ib)->fence = fence;
-        }
-        return r;
+        return 0;
 }
 
 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
@@ -113,19 +100,10 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
         if (tmp == NULL) {
                 return;
         }
-        mutex_lock(&rdev->ib_pool.mutex);
-        if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {
-                /* IB is scheduled & not signaled don't do anythings */
-                mutex_unlock(&rdev->ib_pool.mutex);
-                return;
-        }
-        list_del(&tmp->list);
-        INIT_LIST_HEAD(&tmp->list);
-        if (tmp->fence)
+        if (!tmp->fence->emited)
                 radeon_fence_unref(&tmp->fence);
-
-        tmp->length_dw = 0;
-        clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
+        mutex_lock(&rdev->ib_pool.mutex);
+        tmp->free = true;
         mutex_unlock(&rdev->ib_pool.mutex);
 }
 
@@ -135,7 +113,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 
         if (!ib->length_dw || !rdev->cp.ready) {
                 /* TODO: Nothings in the ib we should report. */
-                DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
+                DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
                 return -EINVAL;
         }
 
@@ -148,7 +126,8 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
         radeon_ring_ib_execute(rdev, ib);
         radeon_fence_emit(rdev, ib->fence);
         mutex_lock(&rdev->ib_pool.mutex);
-        list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
+        /* once scheduled IB is considered free and protected by the fence */
+        ib->free = true;
         mutex_unlock(&rdev->ib_pool.mutex);
         radeon_ring_unlock_commit(rdev);
         return 0;
@@ -164,7 +143,6 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
         if (rdev->ib_pool.robj)
                 return 0;
         /* Allocate 1M object buffer */
-        INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
         r = radeon_bo_create(rdev, NULL,  RADEON_IB_POOL_SIZE*64*1024,
                                 true, RADEON_GEM_DOMAIN_GTT,
                                 &rdev->ib_pool.robj);
@@ -195,9 +173,9 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
                 rdev->ib_pool.ibs[i].ptr = ptr + offset;
                 rdev->ib_pool.ibs[i].idx = i;
                 rdev->ib_pool.ibs[i].length_dw = 0;
-                INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);
+                rdev->ib_pool.ibs[i].free = true;
         }
-        bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
+        rdev->ib_pool.head_id = 0;
         rdev->ib_pool.ready = true;
         DRM_INFO("radeon: ib pool ready.\n");
         if (radeon_debugfs_ib_init(rdev)) {
@@ -214,7 +192,6 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
                 return;
         }
         mutex_lock(&rdev->ib_pool.mutex);
-        bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
         if (rdev->ib_pool.robj) {
                 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
                 if (likely(r == 0)) {
@@ -363,7 +340,7 @@ static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
         if (ib == NULL) {
                 return 0;
         }
-        seq_printf(m, "IB %04lu\n", ib->idx);
+        seq_printf(m, "IB %04u\n", ib->idx);
         seq_printf(m, "IB fence %p\n", ib->fence);
         seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
         for (i = 0; i < ib->length_dw; i++) {
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 3b0c07b444a2..58b5adf974ca 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -215,7 +215,10 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
         rbo = container_of(bo, struct radeon_bo, tbo);
         switch (bo->mem.mem_type) {
         case TTM_PL_VRAM:
-                radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
+                if (rbo->rdev->cp.ready == false)
+                        radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
+                else
+                        radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
                 break;
         case TTM_PL_TT:
         default:
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
index 6021c8849a16..c29ac434ac9c 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r200
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -91,6 +91,8 @@ r200 0x3294
 0x22b8 SE_TCL_TEX_CYL_WRAP_CTL
 0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
 0x22c4 SE_TCL_POINT_SPRITE_CNTL
+0x22d0 SE_PVS_CNTL
+0x22d4 SE_PVS_CONST_CNTL
 0x2648 RE_POINTSIZE
 0x26c0 RE_TOP_LEFT
 0x26c4 RE_MISC
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
new file mode 100644
index 000000000000..989f7a020832
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -0,0 +1,795 @@
+r420 0x4f60
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4310 RS_IP_0
+0x4314 RS_IP_1
+0x4318 RS_IP_2
+0x431C RS_IP_3
+0x4320 RS_IP_4
+0x4324 RS_IP_5
+0x4328 RS_IP_6
+0x432C RS_IP_7
+0x4330 RS_INST_0
+0x4334 RS_INST_1
+0x4338 RS_INST_2
+0x433C RS_INST_3
+0x4340 RS_INST_4
+0x4344 RS_INST_5
+0x4348 RS_INST_6
+0x434C RS_INST_7
+0x4350 RS_INST_8
+0x4354 RS_INST_9
+0x4358 RS_INST_10
+0x435C RS_INST_11
+0x4360 RS_INST_12
+0x4364 RS_INST_13
+0x4368 RS_INST_14
+0x436C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4608 US_CODE_OFFSET
+0x460C US_RESET
+0x4610 US_CODE_ADDR_0
+0x4614 US_CODE_ADDR_1
+0x4618 US_CODE_ADDR_2
+0x461C US_CODE_ADDR_3
+0x4620 US_TEX_INST_0
+0x4624 US_TEX_INST_1
+0x4628 US_TEX_INST_2
+0x462C US_TEX_INST_3
+0x4630 US_TEX_INST_4
+0x4634 US_TEX_INST_5
+0x4638 US_TEX_INST_6
+0x463C US_TEX_INST_7
+0x4640 US_TEX_INST_8
+0x4644 US_TEX_INST_9
+0x4648 US_TEX_INST_10
+0x464C US_TEX_INST_11
+0x4650 US_TEX_INST_12
+0x4654 US_TEX_INST_13
+0x4658 US_TEX_INST_14
+0x465C US_TEX_INST_15
+0x4660 US_TEX_INST_16
+0x4664 US_TEX_INST_17
+0x4668 US_TEX_INST_18
+0x466C US_TEX_INST_19
+0x4670 US_TEX_INST_20
+0x4674 US_TEX_INST_21
+0x4678 US_TEX_INST_22
+0x467C US_TEX_INST_23
+0x4680 US_TEX_INST_24
+0x4684 US_TEX_INST_25
+0x4688 US_TEX_INST_26
+0x468C US_TEX_INST_27
+0x4690 US_TEX_INST_28
+0x4694 US_TEX_INST_29
+0x4698 US_TEX_INST_30
+0x469C US_TEX_INST_31
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x46B8 US_CODE_BANK
+0x46BC US_CODE_EXT
+0x46C0 US_ALU_RGB_ADDR_0
+0x46C4 US_ALU_RGB_ADDR_1
+0x46C8 US_ALU_RGB_ADDR_2
+0x46CC US_ALU_RGB_ADDR_3
+0x46D0 US_ALU_RGB_ADDR_4
+0x46D4 US_ALU_RGB_ADDR_5
+0x46D8 US_ALU_RGB_ADDR_6
+0x46DC US_ALU_RGB_ADDR_7
+0x46E0 US_ALU_RGB_ADDR_8
+0x46E4 US_ALU_RGB_ADDR_9
+0x46E8 US_ALU_RGB_ADDR_10
+0x46EC US_ALU_RGB_ADDR_11
+0x46F0 US_ALU_RGB_ADDR_12
+0x46F4 US_ALU_RGB_ADDR_13
+0x46F8 US_ALU_RGB_ADDR_14
+0x46FC US_ALU_RGB_ADDR_15
+0x4700 US_ALU_RGB_ADDR_16
+0x4704 US_ALU_RGB_ADDR_17
+0x4708 US_ALU_RGB_ADDR_18
+0x470C US_ALU_RGB_ADDR_19
+0x4710 US_ALU_RGB_ADDR_20
+0x4714 US_ALU_RGB_ADDR_21
+0x4718 US_ALU_RGB_ADDR_22
+0x471C US_ALU_RGB_ADDR_23
+0x4720 US_ALU_RGB_ADDR_24
+0x4724 US_ALU_RGB_ADDR_25
+0x4728 US_ALU_RGB_ADDR_26
+0x472C US_ALU_RGB_ADDR_27
+0x4730 US_ALU_RGB_ADDR_28
+0x4734 US_ALU_RGB_ADDR_29
+0x4738 US_ALU_RGB_ADDR_30
+0x473C US_ALU_RGB_ADDR_31
+0x4740 US_ALU_RGB_ADDR_32
+0x4744 US_ALU_RGB_ADDR_33
+0x4748 US_ALU_RGB_ADDR_34
+0x474C US_ALU_RGB_ADDR_35
+0x4750 US_ALU_RGB_ADDR_36
+0x4754 US_ALU_RGB_ADDR_37
+0x4758 US_ALU_RGB_ADDR_38
+0x475C US_ALU_RGB_ADDR_39
+0x4760 US_ALU_RGB_ADDR_40
+0x4764 US_ALU_RGB_ADDR_41
+0x4768 US_ALU_RGB_ADDR_42
+0x476C US_ALU_RGB_ADDR_43
+0x4770 US_ALU_RGB_ADDR_44
+0x4774 US_ALU_RGB_ADDR_45
+0x4778 US_ALU_RGB_ADDR_46
+0x477C US_ALU_RGB_ADDR_47
+0x4780 US_ALU_RGB_ADDR_48
+0x4784 US_ALU_RGB_ADDR_49
+0x4788 US_ALU_RGB_ADDR_50
+0x478C US_ALU_RGB_ADDR_51
+0x4790 US_ALU_RGB_ADDR_52
+0x4794 US_ALU_RGB_ADDR_53
+0x4798 US_ALU_RGB_ADDR_54
+0x479C US_ALU_RGB_ADDR_55
+0x47A0 US_ALU_RGB_ADDR_56
+0x47A4 US_ALU_RGB_ADDR_57
+0x47A8 US_ALU_RGB_ADDR_58
+0x47AC US_ALU_RGB_ADDR_59
+0x47B0 US_ALU_RGB_ADDR_60
+0x47B4 US_ALU_RGB_ADDR_61
+0x47B8 US_ALU_RGB_ADDR_62
+0x47BC US_ALU_RGB_ADDR_63
+0x47C0 US_ALU_ALPHA_ADDR_0
+0x47C4 US_ALU_ALPHA_ADDR_1
+0x47C8 US_ALU_ALPHA_ADDR_2
+0x47CC US_ALU_ALPHA_ADDR_3
+0x47D0 US_ALU_ALPHA_ADDR_4
+0x47D4 US_ALU_ALPHA_ADDR_5
+0x47D8 US_ALU_ALPHA_ADDR_6
+0x47DC US_ALU_ALPHA_ADDR_7
+0x47E0 US_ALU_ALPHA_ADDR_8
+0x47E4 US_ALU_ALPHA_ADDR_9
+0x47E8 US_ALU_ALPHA_ADDR_10
+0x47EC US_ALU_ALPHA_ADDR_11
+0x47F0 US_ALU_ALPHA_ADDR_12
+0x47F4 US_ALU_ALPHA_ADDR_13
+0x47F8 US_ALU_ALPHA_ADDR_14
+0x47FC US_ALU_ALPHA_ADDR_15
+0x4800 US_ALU_ALPHA_ADDR_16
+0x4804 US_ALU_ALPHA_ADDR_17
+0x4808 US_ALU_ALPHA_ADDR_18
+0x480C US_ALU_ALPHA_ADDR_19
+0x4810 US_ALU_ALPHA_ADDR_20
+0x4814 US_ALU_ALPHA_ADDR_21
+0x4818 US_ALU_ALPHA_ADDR_22
+0x481C US_ALU_ALPHA_ADDR_23
+0x4820 US_ALU_ALPHA_ADDR_24
+0x4824 US_ALU_ALPHA_ADDR_25
+0x4828 US_ALU_ALPHA_ADDR_26
+0x482C US_ALU_ALPHA_ADDR_27
+0x4830 US_ALU_ALPHA_ADDR_28
+0x4834 US_ALU_ALPHA_ADDR_29
+0x4838 US_ALU_ALPHA_ADDR_30
+0x483C US_ALU_ALPHA_ADDR_31
+0x4840 US_ALU_ALPHA_ADDR_32
+0x4844 US_ALU_ALPHA_ADDR_33
+0x4848 US_ALU_ALPHA_ADDR_34
+0x484C US_ALU_ALPHA_ADDR_35
+0x4850 US_ALU_ALPHA_ADDR_36
+0x4854 US_ALU_ALPHA_ADDR_37
+0x4858 US_ALU_ALPHA_ADDR_38
+0x485C US_ALU_ALPHA_ADDR_39
+0x4860 US_ALU_ALPHA_ADDR_40
+0x4864 US_ALU_ALPHA_ADDR_41
+0x4868 US_ALU_ALPHA_ADDR_42
+0x486C US_ALU_ALPHA_ADDR_43
+0x4870 US_ALU_ALPHA_ADDR_44
+0x4874 US_ALU_ALPHA_ADDR_45
+0x4878 US_ALU_ALPHA_ADDR_46
+0x487C US_ALU_ALPHA_ADDR_47
+0x4880 US_ALU_ALPHA_ADDR_48
+0x4884 US_ALU_ALPHA_ADDR_49
+0x4888 US_ALU_ALPHA_ADDR_50
+0x488C US_ALU_ALPHA_ADDR_51
+0x4890 US_ALU_ALPHA_ADDR_52
+0x4894 US_ALU_ALPHA_ADDR_53
+0x4898 US_ALU_ALPHA_ADDR_54
+0x489C US_ALU_ALPHA_ADDR_55
+0x48A0 US_ALU_ALPHA_ADDR_56
+0x48A4 US_ALU_ALPHA_ADDR_57
+0x48A8 US_ALU_ALPHA_ADDR_58
+0x48AC US_ALU_ALPHA_ADDR_59
+0x48B0 US_ALU_ALPHA_ADDR_60
+0x48B4 US_ALU_ALPHA_ADDR_61
+0x48B8 US_ALU_ALPHA_ADDR_62
+0x48BC US_ALU_ALPHA_ADDR_63
+0x48C0 US_ALU_RGB_INST_0
+0x48C4 US_ALU_RGB_INST_1
+0x48C8 US_ALU_RGB_INST_2
+0x48CC US_ALU_RGB_INST_3
+0x48D0 US_ALU_RGB_INST_4
+0x48D4 US_ALU_RGB_INST_5
+0x48D8 US_ALU_RGB_INST_6
+0x48DC US_ALU_RGB_INST_7
+0x48E0 US_ALU_RGB_INST_8
+0x48E4 US_ALU_RGB_INST_9
+0x48E8 US_ALU_RGB_INST_10
+0x48EC US_ALU_RGB_INST_11
+0x48F0 US_ALU_RGB_INST_12
+0x48F4 US_ALU_RGB_INST_13
+0x48F8 US_ALU_RGB_INST_14
+0x48FC US_ALU_RGB_INST_15
+0x4900 US_ALU_RGB_INST_16
+0x4904 US_ALU_RGB_INST_17
+0x4908 US_ALU_RGB_INST_18
+0x490C US_ALU_RGB_INST_19
+0x4910 US_ALU_RGB_INST_20
+0x4914 US_ALU_RGB_INST_21
+0x4918 US_ALU_RGB_INST_22
+0x491C US_ALU_RGB_INST_23
+0x4920 US_ALU_RGB_INST_24
+0x4924 US_ALU_RGB_INST_25
+0x4928 US_ALU_RGB_INST_26
+0x492C US_ALU_RGB_INST_27
+0x4930 US_ALU_RGB_INST_28
+0x4934 US_ALU_RGB_INST_29
+0x4938 US_ALU_RGB_INST_30
+0x493C US_ALU_RGB_INST_31
+0x4940 US_ALU_RGB_INST_32
+0x4944 US_ALU_RGB_INST_33
+0x4948 US_ALU_RGB_INST_34
+0x494C US_ALU_RGB_INST_35
+0x4950 US_ALU_RGB_INST_36
+0x4954 US_ALU_RGB_INST_37
+0x4958 US_ALU_RGB_INST_38
+0x495C US_ALU_RGB_INST_39
+0x4960 US_ALU_RGB_INST_40
+0x4964 US_ALU_RGB_INST_41
+0x4968 US_ALU_RGB_INST_42
+0x496C US_ALU_RGB_INST_43
+0x4970 US_ALU_RGB_INST_44
+0x4974 US_ALU_RGB_INST_45
+0x4978 US_ALU_RGB_INST_46
+0x497C US_ALU_RGB_INST_47
+0x4980 US_ALU_RGB_INST_48
+0x4984 US_ALU_RGB_INST_49
+0x4988 US_ALU_RGB_INST_50
+0x498C US_ALU_RGB_INST_51
+0x4990 US_ALU_RGB_INST_52
+0x4994 US_ALU_RGB_INST_53
+0x4998 US_ALU_RGB_INST_54
+0x499C US_ALU_RGB_INST_55
+0x49A0 US_ALU_RGB_INST_56
+0x49A4 US_ALU_RGB_INST_57
+0x49A8 US_ALU_RGB_INST_58
+0x49AC US_ALU_RGB_INST_59
+0x49B0 US_ALU_RGB_INST_60
+0x49B4 US_ALU_RGB_INST_61
+0x49B8 US_ALU_RGB_INST_62
+0x49BC US_ALU_RGB_INST_63
+0x49C0 US_ALU_ALPHA_INST_0
+0x49C4 US_ALU_ALPHA_INST_1
+0x49C8 US_ALU_ALPHA_INST_2
+0x49CC US_ALU_ALPHA_INST_3
+0x49D0 US_ALU_ALPHA_INST_4
+0x49D4 US_ALU_ALPHA_INST_5
+0x49D8 US_ALU_ALPHA_INST_6
+0x49DC US_ALU_ALPHA_INST_7
+0x49E0 US_ALU_ALPHA_INST_8
+0x49E4 US_ALU_ALPHA_INST_9
+0x49E8 US_ALU_ALPHA_INST_10
+0x49EC US_ALU_ALPHA_INST_11
+0x49F0 US_ALU_ALPHA_INST_12
+0x49F4 US_ALU_ALPHA_INST_13
+0x49F8 US_ALU_ALPHA_INST_14
+0x49FC US_ALU_ALPHA_INST_15
+0x4A00 US_ALU_ALPHA_INST_16
+0x4A04 US_ALU_ALPHA_INST_17
+0x4A08 US_ALU_ALPHA_INST_18
+0x4A0C US_ALU_ALPHA_INST_19
+0x4A10 US_ALU_ALPHA_INST_20
+0x4A14 US_ALU_ALPHA_INST_21
+0x4A18 US_ALU_ALPHA_INST_22
+0x4A1C US_ALU_ALPHA_INST_23
+0x4A20 US_ALU_ALPHA_INST_24
+0x4A24 US_ALU_ALPHA_INST_25
+0x4A28 US_ALU_ALPHA_INST_26
+0x4A2C US_ALU_ALPHA_INST_27
+0x4A30 US_ALU_ALPHA_INST_28
+0x4A34 US_ALU_ALPHA_INST_29
+0x4A38 US_ALU_ALPHA_INST_30
+0x4A3C US_ALU_ALPHA_INST_31
+0x4A40 US_ALU_ALPHA_INST_32
+0x4A44 US_ALU_ALPHA_INST_33
+0x4A48 US_ALU_ALPHA_INST_34
+0x4A4C US_ALU_ALPHA_INST_35
+0x4A50 US_ALU_ALPHA_INST_36
+0x4A54 US_ALU_ALPHA_INST_37
+0x4A58 US_ALU_ALPHA_INST_38
+0x4A5C US_ALU_ALPHA_INST_39
+0x4A60 US_ALU_ALPHA_INST_40
+0x4A64 US_ALU_ALPHA_INST_41
+0x4A68 US_ALU_ALPHA_INST_42
+0x4A6C US_ALU_ALPHA_INST_43
+0x4A70 US_ALU_ALPHA_INST_44
+0x4A74 US_ALU_ALPHA_INST_45
+0x4A78 US_ALU_ALPHA_INST_46
+0x4A7C US_ALU_ALPHA_INST_47
+0x4A80 US_ALU_ALPHA_INST_48
+0x4A84 US_ALU_ALPHA_INST_49
+0x4A88 US_ALU_ALPHA_INST_50
+0x4A8C US_ALU_ALPHA_INST_51
+0x4A90 US_ALU_ALPHA_INST_52
+0x4A94 US_ALU_ALPHA_INST_53
+0x4A98 US_ALU_ALPHA_INST_54
+0x4A9C US_ALU_ALPHA_INST_55
+0x4AA0 US_ALU_ALPHA_INST_56
+0x4AA4 US_ALU_ALPHA_INST_57
+0x4AA8 US_ALU_ALPHA_INST_58
+0x4AAC US_ALU_ALPHA_INST_59
+0x4AB0 US_ALU_ALPHA_INST_60
+0x4AB4 US_ALU_ALPHA_INST_61
+0x4AB8 US_ALU_ALPHA_INST_62
+0x4ABC US_ALU_ALPHA_INST_63
+0x4AC0 US_ALU_EXT_ADDR_0
+0x4AC4 US_ALU_EXT_ADDR_1
+0x4AC8 US_ALU_EXT_ADDR_2
+0x4ACC US_ALU_EXT_ADDR_3
+0x4AD0 US_ALU_EXT_ADDR_4
+0x4AD4 US_ALU_EXT_ADDR_5
+0x4AD8 US_ALU_EXT_ADDR_6
+0x4ADC US_ALU_EXT_ADDR_7
+0x4AE0 US_ALU_EXT_ADDR_8
+0x4AE4 US_ALU_EXT_ADDR_9
+0x4AE8 US_ALU_EXT_ADDR_10
+0x4AEC US_ALU_EXT_ADDR_11
+0x4AF0 US_ALU_EXT_ADDR_12
+0x4AF4 US_ALU_EXT_ADDR_13
+0x4AF8 US_ALU_EXT_ADDR_14
+0x4AFC US_ALU_EXT_ADDR_15
+0x4B00 US_ALU_EXT_ADDR_16
+0x4B04 US_ALU_EXT_ADDR_17
+0x4B08 US_ALU_EXT_ADDR_18
+0x4B0C US_ALU_EXT_ADDR_19
+0x4B10 US_ALU_EXT_ADDR_20
+0x4B14 US_ALU_EXT_ADDR_21
+0x4B18 US_ALU_EXT_ADDR_22
+0x4B1C US_ALU_EXT_ADDR_23
+0x4B20 US_ALU_EXT_ADDR_24
+0x4B24 US_ALU_EXT_ADDR_25
+0x4B28 US_ALU_EXT_ADDR_26
+0x4B2C US_ALU_EXT_ADDR_27
+0x4B30 US_ALU_EXT_ADDR_28
+0x4B34 US_ALU_EXT_ADDR_29
+0x4B38 US_ALU_EXT_ADDR_30
+0x4B3C US_ALU_EXT_ADDR_31
+0x4B40 US_ALU_EXT_ADDR_32
+0x4B44 US_ALU_EXT_ADDR_33
+0x4B48 US_ALU_EXT_ADDR_34
+0x4B4C US_ALU_EXT_ADDR_35
+0x4B50 US_ALU_EXT_ADDR_36
+0x4B54 US_ALU_EXT_ADDR_37
+0x4B58 US_ALU_EXT_ADDR_38
+0x4B5C US_ALU_EXT_ADDR_39
+0x4B60 US_ALU_EXT_ADDR_40
+0x4B64 US_ALU_EXT_ADDR_41
+0x4B68 US_ALU_EXT_ADDR_42
+0x4B6C US_ALU_EXT_ADDR_43
+0x4B70 US_ALU_EXT_ADDR_44
+0x4B74 US_ALU_EXT_ADDR_45
+0x4B78 US_ALU_EXT_ADDR_46
+0x4B7C US_ALU_EXT_ADDR_47
+0x4B80 US_ALU_EXT_ADDR_48
+0x4B84 US_ALU_EXT_ADDR_49
+0x4B88 US_ALU_EXT_ADDR_50
+0x4B8C US_ALU_EXT_ADDR_51
+0x4B90 US_ALU_EXT_ADDR_52
+0x4B94 US_ALU_EXT_ADDR_53
+0x4B98 US_ALU_EXT_ADDR_54
+0x4B9C US_ALU_EXT_ADDR_55
+0x4BA0 US_ALU_EXT_ADDR_56
+0x4BA4 US_ALU_EXT_ADDR_57
+0x4BA8 US_ALU_EXT_ADDR_58
+0x4BAC US_ALU_EXT_ADDR_59
+0x4BB0 US_ALU_EXT_ADDR_60
+0x4BB4 US_ALU_EXT_ADDR_61
+0x4BB8 US_ALU_EXT_ADDR_62
+0x4BBC US_ALU_EXT_ADDR_63
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 8e3c0b807add..6801b865d1c4 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -153,7 +153,7 @@ rs600 0x6d40
 0x42A4 SU_POLY_OFFSET_FRONT_SCALE
 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
 0x42AC SU_POLY_OFFSET_BACK_SCALE
-0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
 0x42B4 SU_POLY_OFFSET_ENABLE
 0x42B8 SU_CULL_MODE
 0x42C0 SU_DEPTH_SCALE
@@ -291,6 +291,8 @@ rs600 0x6d40
 0x46AC US_OUT_FMT_2
 0x46B0 US_OUT_FMT_3
 0x46B4 US_W_FMT
+0x46B8 US_CODE_BANK
+0x46BC US_CODE_EXT
 0x46C0 US_ALU_RGB_ADDR_0
 0x46C4 US_ALU_RGB_ADDR_1
 0x46C8 US_ALU_RGB_ADDR_2
@@ -547,6 +549,70 @@ rs600 0x6d40
 0x4AB4 US_ALU_ALPHA_INST_61
 0x4AB8 US_ALU_ALPHA_INST_62
 0x4ABC US_ALU_ALPHA_INST_63
+0x4AC0 US_ALU_EXT_ADDR_0
+0x4AC4 US_ALU_EXT_ADDR_1
+0x4AC8 US_ALU_EXT_ADDR_2
+0x4ACC US_ALU_EXT_ADDR_3
+0x4AD0 US_ALU_EXT_ADDR_4
+0x4AD4 US_ALU_EXT_ADDR_5
+0x4AD8 US_ALU_EXT_ADDR_6
+0x4ADC US_ALU_EXT_ADDR_7
+0x4AE0 US_ALU_EXT_ADDR_8
+0x4AE4 US_ALU_EXT_ADDR_9
+0x4AE8 US_ALU_EXT_ADDR_10
+0x4AEC US_ALU_EXT_ADDR_11
+0x4AF0 US_ALU_EXT_ADDR_12
+0x4AF4 US_ALU_EXT_ADDR_13
+0x4AF8 US_ALU_EXT_ADDR_14
+0x4AFC US_ALU_EXT_ADDR_15
+0x4B00 US_ALU_EXT_ADDR_16
+0x4B04 US_ALU_EXT_ADDR_17
+0x4B08 US_ALU_EXT_ADDR_18
+0x4B0C US_ALU_EXT_ADDR_19
+0x4B10 US_ALU_EXT_ADDR_20
+0x4B14 US_ALU_EXT_ADDR_21
+0x4B18 US_ALU_EXT_ADDR_22
+0x4B1C US_ALU_EXT_ADDR_23
+0x4B20 US_ALU_EXT_ADDR_24
+0x4B24 US_ALU_EXT_ADDR_25
+0x4B28 US_ALU_EXT_ADDR_26
+0x4B2C US_ALU_EXT_ADDR_27
+0x4B30 US_ALU_EXT_ADDR_28
+0x4B34 US_ALU_EXT_ADDR_29
+0x4B38 US_ALU_EXT_ADDR_30
+0x4B3C US_ALU_EXT_ADDR_31
+0x4B40 US_ALU_EXT_ADDR_32
+0x4B44 US_ALU_EXT_ADDR_33
+0x4B48 US_ALU_EXT_ADDR_34
+0x4B4C US_ALU_EXT_ADDR_35
+0x4B50 US_ALU_EXT_ADDR_36
+0x4B54 US_ALU_EXT_ADDR_37
+0x4B58 US_ALU_EXT_ADDR_38
+0x4B5C US_ALU_EXT_ADDR_39
+0x4B60 US_ALU_EXT_ADDR_40
+0x4B64 US_ALU_EXT_ADDR_41
+0x4B68 US_ALU_EXT_ADDR_42
+0x4B6C US_ALU_EXT_ADDR_43
+0x4B70 US_ALU_EXT_ADDR_44
+0x4B74 US_ALU_EXT_ADDR_45
+0x4B78 US_ALU_EXT_ADDR_46
+0x4B7C US_ALU_EXT_ADDR_47
+0x4B80 US_ALU_EXT_ADDR_48
+0x4B84 US_ALU_EXT_ADDR_49
+0x4B88 US_ALU_EXT_ADDR_50
+0x4B8C US_ALU_EXT_ADDR_51
+0x4B90 US_ALU_EXT_ADDR_52
+0x4B94 US_ALU_EXT_ADDR_53
+0x4B98 US_ALU_EXT_ADDR_54
+0x4B9C US_ALU_EXT_ADDR_55
+0x4BA0 US_ALU_EXT_ADDR_56
+0x4BA4 US_ALU_EXT_ADDR_57
+0x4BA8 US_ALU_EXT_ADDR_58
+0x4BAC US_ALU_EXT_ADDR_59
+0x4BB0 US_ALU_EXT_ADDR_60
+0x4BB4 US_ALU_EXT_ADDR_61
+0x4BB8 US_ALU_EXT_ADDR_62
+0x4BBC US_ALU_EXT_ADDR_63
 0x4BC0 FG_FOG_BLEND
 0x4BC4 FG_FOG_FACTOR
 0x4BC8 FG_FOG_COLOR_R
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 0102a0d5735c..38abf63bf2cd 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -161,7 +161,12 @@ rv515 0x6d40
 0x401C GB_SELECT
 0x4020 GB_AA_CONFIG
 0x4024 GB_FIFO_SIZE
+0x4028 GB_Z_PEQ_CONFIG
 0x4100 TX_INVALTAGS
+0x4114 SU_TEX_WRAP_PS3
+0x4118 PS3_ENABLE
+0x411c PS3_VTX_FMT
+0x4120 PS3_TEX_SOURCE
 0x4200 GA_POINT_S0
 0x4204 GA_POINT_T0
 0x4208 GA_POINT_S1
@@ -171,6 +176,7 @@ rv515 0x6d40
 0x4230 GA_POINT_MINMAX
 0x4234 GA_LINE_CNTL
 0x4238 GA_LINE_STIPPLE_CONFIG
+0x4258 GA_COLOR_CONTROL_PS3
 0x4260 GA_LINE_STIPPLE_VALUE
 0x4264 GA_LINE_S0
 0x4268 GA_LINE_S1
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 368415df5f3a..287fcebfb4e6 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -223,15 +223,31 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
         return 0;
 }
 
+int rs400_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32(0x0150);
+                if (tmp & (1 << 2)) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
 void rs400_gpu_init(struct radeon_device *rdev)
 {
         /* FIXME: HDP same place on rs400 ? */
         r100_hdp_reset(rdev);
         /* FIXME: is this correct ? */
         r420_pipes_init(rdev);
-        if (r300_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
+        if (rs400_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "rs400: Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
         }
 }
 
@@ -356,6 +372,7 @@ static int rs400_mc_init(struct radeon_device *rdev)
         rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
         rdev->mc.gtt_location = 0xFFFFFFFFUL;
         r = radeon_mc_setup(rdev);
+        rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
         if (r)
                 return r;
         return 0;
@@ -369,8 +386,8 @@ void rs400_mc_program(struct radeon_device *rdev)
         r100_mc_stop(rdev, &save);
 
         /* Wait for mc idle */
-        if (r300_mc_wait_for_idle(rdev))
-                dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
+        if (rs400_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
         WREG32(R_000148_MC_FB_LOCATION,
                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
@@ -395,6 +412,7 @@ static int rs400_startup(struct radeon_device *rdev)
                 return r;
         /* Enable IRQ */
         r100_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -446,7 +464,6 @@ int rs400_suspend(struct radeon_device *rdev)
 
 void rs400_fini(struct radeon_device *rdev)
 {
-        rs400_suspend(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
@@ -525,7 +542,6 @@ int rs400_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rs400_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 4f8ea4260572..c3818562a13e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -56,6 +56,7 @@ int rs600_mc_init(struct radeon_device *rdev)
         rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
         rdev->mc.gtt_location = 0xffffffffUL;
         r = radeon_mc_setup(rdev);
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         if (r)
                 return r;
         return 0;
@@ -134,7 +135,8 @@ void rs600_hpd_init(struct radeon_device *rdev)
                         break;
                 }
         }
-        rs600_irq_set(rdev);
+        if (rdev->irq.installed)
+                rs600_irq_set(rdev);
 }
 
 void rs600_hpd_fini(struct radeon_device *rdev)
@@ -315,6 +317,11 @@ int rs600_irq_set(struct radeon_device *rdev)
         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WREG32(R_000040_GEN_INT_CNTL, 0);
+                return -EINVAL;
+        }
         if (rdev->irq.sw_int) {
                 tmp |= S_000040_SW_INT_EN(1);
         }
@@ -396,7 +403,7 @@ int rs600_irq_process(struct radeon_device *rdev)
         }
         while (status || r500_disp_int) {
                 /* SW interrupt */
-                if (G_000040_SW_INT_EN(status))
+                if (G_000044_SW_INT(status))
                         radeon_fence_process(rdev);
                 /* Vertical blank interrupts */
                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
@@ -553,6 +560,7 @@ static int rs600_startup(struct radeon_device *rdev)
                 return r;
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -602,7 +610,6 @@ int rs600_suspend(struct radeon_device *rdev)
 
 void rs600_fini(struct radeon_device *rdev)
 {
-        rs600_suspend(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
@@ -681,7 +688,6 @@ int rs600_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rs600_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1e22f52d6039..06e2771aee5a 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -172,6 +172,7 @@ static int rs690_mc_init(struct radeon_device *rdev)
         rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
         rdev->mc.gtt_location = 0xFFFFFFFFUL;
         r = radeon_mc_setup(rdev);
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         if (r)
                 return r;
         return 0;
@@ -625,6 +626,7 @@ static int rs690_startup(struct radeon_device *rdev)
                 return r;
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -674,7 +676,6 @@ int rs690_suspend(struct radeon_device *rdev)
 
 void rs690_fini(struct radeon_device *rdev)
 {
-        rs690_suspend(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
@@ -754,7 +755,6 @@ int rs690_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rs690_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 59632a506b46..0e1e6b8632b8 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -479,6 +479,7 @@ static int rv515_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -536,7 +537,6 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 
 void rv515_fini(struct radeon_device *rdev)
 {
-        rv515_suspend(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
@@ -614,13 +614,12 @@ int rv515_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rv515_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 rv370_pcie_gart_fini(rdev);
                 radeon_agp_fini(rdev);
-                radeon_irq_kms_fini(rdev);
                 rdev->accel_working = false;
         }
         return 0;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 3bcb66e52786..03021674d097 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -549,9 +549,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
         gb_tiling_config |= BANK_SWAPS(1);
 
-        backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
-                                                        rdev->config.rv770.max_backends,
-                                                        (0xff << rdev->config.rv770.max_backends) & 0xff);
+        if (rdev->family == CHIP_RV740)
+                backend_map = 0x28;
+        else
+                backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
+                                                                rdev->config.rv770.max_backends,
+                                                                (0xff << rdev->config.rv770.max_backends) & 0xff);
         gb_tiling_config |= BACKEND_MAP(backend_map);
 
         cc_gc_shader_pipe_config =
@@ -779,7 +782,6 @@ int rv770_mc_init(struct radeon_device *rdev)
         fixed20_12 a;
         u32 tmp;
         int chansize, numchan;
-        int r;
 
         /* Get VRAM informations */
         rdev->mc.vram_is_ddr = true;
@@ -822,9 +824,6 @@ int rv770_mc_init(struct radeon_device *rdev)
                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 
         if (rdev->flags & RADEON_IS_AGP) {
-                r = radeon_agp_init(rdev);
-                if (r)
-                        return r;
                 /* gtt_size is setup by radeon_agp_init */
                 rdev->mc.gtt_location = rdev->mc.agp_base;
                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
@@ -891,26 +890,25 @@ static int rv770_startup(struct radeon_device *rdev)
                         return r;
         }
         rv770_gpu_init(rdev);
-
-        if (!rdev->r600_blit.shader_obj) {
-                r = r600_blit_init(rdev);
+        r = r600_blit_init(rdev);
+        if (r) {
+                r600_blit_fini(rdev);
+                rdev->asic->copy = NULL;
+                dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
+        }
+        /* pin copy shader into vram */
+        if (rdev->r600_blit.shader_obj) {
+                r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+                if (unlikely(r != 0))
+                        return r;
+                r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+                                &rdev->r600_blit.shader_gpu_addr);
+                radeon_bo_unreserve(rdev->r600_blit.shader_obj);
                 if (r) {
-                        DRM_ERROR("radeon: failed blitter (%d).\n", r);
+                        DRM_ERROR("failed to pin blit object %d\n", r);
                         return r;
                 }
         }
-
-        r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
-        if (unlikely(r != 0))
-                return r;
-        r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
-                        &rdev->r600_blit.shader_gpu_addr);
-        radeon_bo_unreserve(rdev->r600_blit.shader_obj);
-        if (r) {
-                DRM_ERROR("failed to pin blit object %d\n", r);
-                return r;
-        }
-
         /* Enable IRQ */
         r = r600_irq_init(rdev);
         if (r) {
@@ -972,13 +970,16 @@ int rv770_suspend(struct radeon_device *rdev)
         /* FIXME: we should wait for ring to be empty */
         r700_cp_stop(rdev);
         rdev->cp.ready = false;
+        r600_irq_suspend(rdev);
         r600_wb_disable(rdev);
         rv770_pcie_gart_disable(rdev);
         /* unpin shaders bo */
-        r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
-        if (likely(r == 0)) {
-                radeon_bo_unpin(rdev->r600_blit.shader_obj);
-                radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+        if (rdev->r600_blit.shader_obj) {
+                r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+                if (likely(r == 0)) {
+                        radeon_bo_unpin(rdev->r600_blit.shader_obj);
+                        radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+                }
         }
         return 0;
 }
@@ -1037,6 +1038,11 @@ int rv770_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r)
+                        radeon_agp_disable(rdev);
+        }
         r = rv770_mc_init(rdev);
         if (r)
                 return r;
@@ -1062,22 +1068,25 @@ int rv770_init(struct radeon_device *rdev)
         rdev->accel_working = true;
         r = rv770_startup(rdev);
         if (r) {
-                rv770_suspend(rdev);
+                dev_err(rdev->dev, "disabling GPU acceleration\n");
+                r600_cp_fini(rdev);
                 r600_wb_fini(rdev);
-                radeon_ring_fini(rdev);
+                r600_irq_fini(rdev);
+                radeon_irq_kms_fini(rdev);
                 rv770_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
         }
         if (rdev->accel_working) {
                 r = radeon_ib_pool_init(rdev);
                 if (r) {
-                        DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
-                        rdev->accel_working = false;
-                }
-                r = r600_ib_test(rdev);
-                if (r) {
-                        DRM_ERROR("radeon: failed testing IB (%d).\n", r);
+                        dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
                         rdev->accel_working = false;
+                } else {
+                        r = r600_ib_test(rdev);
+                        if (r) {
+                                dev_err(rdev->dev, "IB test failed (%d).\n", r);
+                                rdev->accel_working = false;
+                        }
                 }
         }
         return 0;
@@ -1085,19 +1094,16 @@ int rv770_init(struct radeon_device *rdev)
 
 void rv770_fini(struct radeon_device *rdev)
 {
-        rv770_suspend(rdev);
-
         r600_blit_fini(rdev);
+        r600_cp_fini(rdev);
+        r600_wb_fini(rdev);
         r600_irq_fini(rdev);
         radeon_irq_kms_fini(rdev);
-        radeon_ring_fini(rdev);
-        r600_wb_fini(rdev);
         rv770_pcie_gart_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_clocks_fini(rdev);
-        if (rdev->flags & RADEON_IS_AGP)
-                radeon_agp_fini(rdev);
+        radeon_agp_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);