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-rw-r--r--drivers/gpu/drm/radeon/atombios.h2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c100
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c80
-rw-r--r--drivers/gpu/drm/radeon/r100.c27
-rw-r--r--drivers/gpu/drm/radeon/r600.c25
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c27
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.h24
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon.h9
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c93
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c58
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c177
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c120
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c30
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c29
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c223
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c83
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h7
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c56
-rw-r--r--drivers/gpu/drm/radeon/rs600.c1
-rw-r--r--drivers/gpu/drm/radeon/rs690.c1
-rw-r--r--drivers/gpu/drm/radeon/rv770.c63
34 files changed, 796 insertions, 529 deletions
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 1bc72c3190a9..fe359a239df3 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -4999,7 +4999,7 @@ typedef struct _SW_I2C_IO_DATA_PARAMETERS
4999#define SW_I2C_CNTL_WRITE1BIT 6 4999#define SW_I2C_CNTL_WRITE1BIT 6
5000 5000
5001//==============================VESA definition Portion=============================== 5001//==============================VESA definition Portion===============================
5002#define VESA_OEM_PRODUCT_REV '01.00' 5002#define VESA_OEM_PRODUCT_REV "01.00"
5003#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 5003#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
5004#define VESA_MODE_WIN_ATTRIBUTE 7 5004#define VESA_MODE_WIN_ATTRIBUTE 7
5005#define VESA_WIN_SIZE 64 5005#define VESA_WIN_SIZE 64
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 12ad512bd3d3..cd0290f946cf 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -332,6 +332,11 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
332 args.usV_SyncWidth = 332 args.usV_SyncWidth =
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
334 334
335 args.ucOverscanRight = radeon_crtc->h_border;
336 args.ucOverscanLeft = radeon_crtc->h_border;
337 args.ucOverscanBottom = radeon_crtc->v_border;
338 args.ucOverscanTop = radeon_crtc->v_border;
339
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 340 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY; 341 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 342 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
@@ -471,6 +476,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
471 struct radeon_encoder *radeon_encoder = NULL; 476 struct radeon_encoder *radeon_encoder = NULL;
472 u32 adjusted_clock = mode->clock; 477 u32 adjusted_clock = mode->clock;
473 int encoder_mode = 0; 478 int encoder_mode = 0;
479 u32 dp_clock = mode->clock;
480 int bpc = 8;
474 481
475 /* reset the pll flags */ 482 /* reset the pll flags */
476 pll->flags = 0; 483 pll->flags = 0;
@@ -513,6 +520,17 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
513 if (encoder->crtc == crtc) { 520 if (encoder->crtc == crtc) {
514 radeon_encoder = to_radeon_encoder(encoder); 521 radeon_encoder = to_radeon_encoder(encoder);
515 encoder_mode = atombios_get_encoder_mode(encoder); 522 encoder_mode = atombios_get_encoder_mode(encoder);
523 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
524 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
525 if (connector) {
526 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
527 struct radeon_connector_atom_dig *dig_connector =
528 radeon_connector->con_priv;
529
530 dp_clock = dig_connector->dp_clock;
531 }
532 }
533
516 if (ASIC_IS_AVIVO(rdev)) { 534 if (ASIC_IS_AVIVO(rdev)) {
517 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 535 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
518 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 536 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
@@ -521,6 +539,21 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
521 pll->algo = PLL_ALGO_LEGACY; 539 pll->algo = PLL_ALGO_LEGACY;
522 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 540 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
523 } 541 }
542 /* There is some evidence (often anecdotal) that RV515/RV620 LVDS
543 * (on some boards at least) prefers the legacy algo. I'm not
544 * sure whether this should handled generically or on a
545 * case-by-case quirk basis. Both algos should work fine in the
546 * majority of cases.
547 */
548 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) &&
549 ((rdev->family == CHIP_RV515) ||
550 (rdev->family == CHIP_RV620))) {
551 /* allow the user to overrride just in case */
552 if (radeon_new_pll == 1)
553 pll->algo = PLL_ALGO_NEW;
554 else
555 pll->algo = PLL_ALGO_LEGACY;
556 }
524 } else { 557 } else {
525 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 558 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
526 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 559 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -555,6 +588,14 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
555 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 588 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
556 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 589 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
557 args.v1.ucEncodeMode = encoder_mode; 590 args.v1.ucEncodeMode = encoder_mode;
591 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
592 /* may want to enable SS on DP eventually */
593 /* args.v1.ucConfig |=
594 ADJUST_DISPLAY_CONFIG_SS_ENABLE;*/
595 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
596 args.v1.ucConfig |=
597 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
598 }
558 599
559 atom_execute_table(rdev->mode_info.atom_context, 600 atom_execute_table(rdev->mode_info.atom_context,
560 index, (uint32_t *)&args); 601 index, (uint32_t *)&args);
@@ -568,10 +609,20 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
568 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 609 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
569 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 610 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
570 611
571 if (encoder_mode == ATOM_ENCODER_MODE_DP) 612 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
613 /* may want to enable SS on DP/eDP eventually */
614 /*args.v3.sInput.ucDispPllConfig |=
615 DISPPLL_CONFIG_SS_ENABLE;*/
572 args.v3.sInput.ucDispPllConfig |= 616 args.v3.sInput.ucDispPllConfig |=
573 DISPPLL_CONFIG_COHERENT_MODE; 617 DISPPLL_CONFIG_COHERENT_MODE;
574 else { 618 /* 16200 or 27000 */
619 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
620 } else {
621 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
622 /* deep color support */
623 args.v3.sInput.usPixelClock =
624 cpu_to_le16((mode->clock * bpc / 8) / 10);
625 }
575 if (dig->coherent_mode) 626 if (dig->coherent_mode)
576 args.v3.sInput.ucDispPllConfig |= 627 args.v3.sInput.ucDispPllConfig |=
577 DISPPLL_CONFIG_COHERENT_MODE; 628 DISPPLL_CONFIG_COHERENT_MODE;
@@ -580,13 +631,19 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
580 DISPPLL_CONFIG_DUAL_LINK; 631 DISPPLL_CONFIG_DUAL_LINK;
581 } 632 }
582 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 633 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
583 /* may want to enable SS on DP/eDP eventually */ 634 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
584 /*args.v3.sInput.ucDispPllConfig |= 635 /* may want to enable SS on DP/eDP eventually */
585 DISPPLL_CONFIG_SS_ENABLE;*/ 636 /*args.v3.sInput.ucDispPllConfig |=
586 if (encoder_mode == ATOM_ENCODER_MODE_DP) 637 DISPPLL_CONFIG_SS_ENABLE;*/
587 args.v3.sInput.ucDispPllConfig |= 638 args.v3.sInput.ucDispPllConfig |=
588 DISPPLL_CONFIG_COHERENT_MODE; 639 DISPPLL_CONFIG_COHERENT_MODE;
589 else { 640 /* 16200 or 27000 */
641 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
642 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
643 /* want to enable SS on LVDS eventually */
644 /*args.v3.sInput.ucDispPllConfig |=
645 DISPPLL_CONFIG_SS_ENABLE;*/
646 } else {
590 if (mode->clock > 165000) 647 if (mode->clock > 165000)
591 args.v3.sInput.ucDispPllConfig |= 648 args.v3.sInput.ucDispPllConfig |=
592 DISPPLL_CONFIG_DUAL_LINK; 649 DISPPLL_CONFIG_DUAL_LINK;
@@ -1019,11 +1076,11 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1019 1076
1020 if (rdev->family >= CHIP_RV770) { 1077 if (rdev->family >= CHIP_RV770) {
1021 if (radeon_crtc->crtc_id) { 1078 if (radeon_crtc->crtc_id) {
1022 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 1079 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1023 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 1080 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1024 } else { 1081 } else {
1025 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); 1082 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1026 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); 1083 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1027 } 1084 }
1028 } 1085 }
1029 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1086 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
@@ -1160,8 +1217,18 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1160 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1161 struct drm_device *dev = crtc->dev; 1218 struct drm_device *dev = crtc->dev;
1162 struct radeon_device *rdev = dev->dev_private; 1219 struct radeon_device *rdev = dev->dev_private;
1220 struct drm_encoder *encoder;
1221 bool is_tvcv = false;
1163 1222
1164 /* TODO color tiling */ 1223 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1224 /* find tv std */
1225 if (encoder->crtc == crtc) {
1226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1227 if (radeon_encoder->active_device &
1228 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1229 is_tvcv = true;
1230 }
1231 }
1165 1232
1166 atombios_disable_ss(crtc); 1233 atombios_disable_ss(crtc);
1167 /* always set DCPLL */ 1234 /* always set DCPLL */
@@ -1170,9 +1237,14 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1170 atombios_crtc_set_pll(crtc, adjusted_mode); 1237 atombios_crtc_set_pll(crtc, adjusted_mode);
1171 atombios_enable_ss(crtc); 1238 atombios_enable_ss(crtc);
1172 1239
1173 if (ASIC_IS_AVIVO(rdev)) 1240 if (ASIC_IS_DCE4(rdev))
1174 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1241 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1175 else { 1242 else if (ASIC_IS_AVIVO(rdev)) {
1243 if (is_tvcv)
1244 atombios_crtc_set_timing(crtc, adjusted_mode);
1245 else
1246 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1247 } else {
1176 atombios_crtc_set_timing(crtc, adjusted_mode); 1248 atombios_crtc_set_timing(crtc, adjusted_mode);
1177 if (radeon_crtc->crtc_id == 0) 1249 if (radeon_crtc->crtc_id == 0)
1178 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1250 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 36e0d4b545e6..4e7778d44b8d 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -610,7 +610,7 @@ void dp_link_train(struct drm_encoder *encoder,
610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
611 else 611 else
612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
613 if (dig_connector->linkb) 613 if (dig->linkb)
614 enc_id |= ATOM_DP_CONFIG_LINK_B; 614 enc_id |= ATOM_DP_CONFIG_LINK_B;
615 else 615 else
616 enc_id |= ATOM_DP_CONFIG_LINK_A; 616 enc_id |= ATOM_DP_CONFIG_LINK_A;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 957d5067ad9c..2f93d46ae69a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -675,6 +675,43 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
675 return 0; 675 return 0;
676} 676}
677 677
678static int evergreen_cp_start(struct radeon_device *rdev)
679{
680 int r;
681 uint32_t cp_me;
682
683 r = radeon_ring_lock(rdev, 7);
684 if (r) {
685 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
686 return r;
687 }
688 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
689 radeon_ring_write(rdev, 0x1);
690 radeon_ring_write(rdev, 0x0);
691 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
692 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
693 radeon_ring_write(rdev, 0);
694 radeon_ring_write(rdev, 0);
695 radeon_ring_unlock_commit(rdev);
696
697 cp_me = 0xff;
698 WREG32(CP_ME_CNTL, cp_me);
699
700 r = radeon_ring_lock(rdev, 4);
701 if (r) {
702 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
703 return r;
704 }
705 /* init some VGT regs */
706 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
707 radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2);
708 radeon_ring_write(rdev, 0xe);
709 radeon_ring_write(rdev, 0x10);
710 radeon_ring_unlock_commit(rdev);
711
712 return 0;
713}
714
678int evergreen_cp_resume(struct radeon_device *rdev) 715int evergreen_cp_resume(struct radeon_device *rdev)
679{ 716{
680 u32 tmp; 717 u32 tmp;
@@ -719,7 +756,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
719 rdev->cp.rptr = RREG32(CP_RB_RPTR); 756 rdev->cp.rptr = RREG32(CP_RB_RPTR);
720 rdev->cp.wptr = RREG32(CP_RB_WPTR); 757 rdev->cp.wptr = RREG32(CP_RB_WPTR);
721 758
722 r600_cp_start(rdev); 759 evergreen_cp_start(rdev);
723 rdev->cp.ready = true; 760 rdev->cp.ready = true;
724 r = radeon_ring_test(rdev); 761 r = radeon_ring_test(rdev);
725 if (r) { 762 if (r) {
@@ -1100,7 +1137,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1100 1137
1101 WREG32(RCU_IND_INDEX, 0x203); 1138 WREG32(RCU_IND_INDEX, 0x203);
1102 efuse_straps_3 = RREG32(RCU_IND_DATA); 1139 efuse_straps_3 = RREG32(RCU_IND_DATA);
1103 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28; 1140 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1104 1141
1105 switch(efuse_box_bit_127_124) { 1142 switch(efuse_box_bit_127_124) {
1106 case 0x0: 1143 case 0x0:
@@ -1123,14 +1160,25 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1123 EVERGREEN_MAX_BACKENDS_MASK)); 1160 EVERGREEN_MAX_BACKENDS_MASK));
1124 break; 1161 break;
1125 } 1162 }
1126 } else 1163 } else {
1127 gb_backend_map = 1164 switch (rdev->family) {
1128 evergreen_get_tile_pipe_to_backend_map(rdev, 1165 case CHIP_CYPRESS:
1129 rdev->config.evergreen.max_tile_pipes, 1166 case CHIP_HEMLOCK:
1130 rdev->config.evergreen.max_backends, 1167 gb_backend_map = 0x66442200;
1131 ((EVERGREEN_MAX_BACKENDS_MASK << 1168 break;
1132 rdev->config.evergreen.max_backends) & 1169 case CHIP_JUNIPER:
1133 EVERGREEN_MAX_BACKENDS_MASK)); 1170 gb_backend_map = 0x00006420;
1171 break;
1172 default:
1173 gb_backend_map =
1174 evergreen_get_tile_pipe_to_backend_map(rdev,
1175 rdev->config.evergreen.max_tile_pipes,
1176 rdev->config.evergreen.max_backends,
1177 ((EVERGREEN_MAX_BACKENDS_MASK <<
1178 rdev->config.evergreen.max_backends) &
1179 EVERGREEN_MAX_BACKENDS_MASK));
1180 }
1181 }
1134 1182
1135 rdev->config.evergreen.tile_config = gb_addr_config; 1183 rdev->config.evergreen.tile_config = gb_addr_config;
1136 WREG32(GB_BACKEND_MAP, gb_backend_map); 1184 WREG32(GB_BACKEND_MAP, gb_backend_map);
@@ -1359,6 +1407,7 @@ int evergreen_mc_init(struct radeon_device *rdev)
1359 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1407 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1360 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1408 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1361 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1409 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1410 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1362 r600_vram_gtt_location(rdev, &rdev->mc); 1411 r600_vram_gtt_location(rdev, &rdev->mc);
1363 radeon_update_bandwidth_info(rdev); 1412 radeon_update_bandwidth_info(rdev);
1364 1413
@@ -1472,7 +1521,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1472{ 1521{
1473 u32 tmp; 1522 u32 tmp;
1474 1523
1475 WREG32(CP_INT_CNTL, 0); 1524 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1476 WREG32(GRBM_INT_CNTL, 0); 1525 WREG32(GRBM_INT_CNTL, 0);
1477 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1526 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1478 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1527 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -2054,11 +2103,6 @@ int evergreen_resume(struct radeon_device *rdev)
2054 */ 2103 */
2055 /* post card */ 2104 /* post card */
2056 atom_asic_init(rdev->mode_info.atom_context); 2105 atom_asic_init(rdev->mode_info.atom_context);
2057 /* Initialize clocks */
2058 r = radeon_clocks_init(rdev);
2059 if (r) {
2060 return r;
2061 }
2062 2106
2063 r = evergreen_startup(rdev); 2107 r = evergreen_startup(rdev);
2064 if (r) { 2108 if (r) {
@@ -2164,9 +2208,6 @@ int evergreen_init(struct radeon_device *rdev)
2164 radeon_surface_init(rdev); 2208 radeon_surface_init(rdev);
2165 /* Initialize clocks */ 2209 /* Initialize clocks */
2166 radeon_get_clock_info(rdev->ddev); 2210 radeon_get_clock_info(rdev->ddev);
2167 r = radeon_clocks_init(rdev);
2168 if (r)
2169 return r;
2170 /* Fence driver */ 2211 /* Fence driver */
2171 r = radeon_fence_driver_init(rdev); 2212 r = radeon_fence_driver_init(rdev);
2172 if (r) 2213 if (r)
@@ -2236,7 +2277,6 @@ void evergreen_fini(struct radeon_device *rdev)
2236 evergreen_pcie_gart_fini(rdev); 2277 evergreen_pcie_gart_fini(rdev);
2237 radeon_gem_fini(rdev); 2278 radeon_gem_fini(rdev);
2238 radeon_fence_driver_fini(rdev); 2279 radeon_fence_driver_fini(rdev);
2239 radeon_clocks_fini(rdev);
2240 radeon_agp_fini(rdev); 2280 radeon_agp_fini(rdev);
2241 radeon_bo_fini(rdev); 2281 radeon_bo_fini(rdev);
2242 radeon_atombios_fini(rdev); 2282 radeon_atombios_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e817a0bb5eb4..e59422320bb6 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1030,6 +1030,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1030 return r; 1030 return r;
1031 } 1031 }
1032 rdev->cp.ready = true; 1032 rdev->cp.ready = true;
1033 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
1033 return 0; 1034 return 0;
1034} 1035}
1035 1036
@@ -1047,6 +1048,7 @@ void r100_cp_fini(struct radeon_device *rdev)
1047void r100_cp_disable(struct radeon_device *rdev) 1048void r100_cp_disable(struct radeon_device *rdev)
1048{ 1049{
1049 /* Disable ring */ 1050 /* Disable ring */
1051 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1050 rdev->cp.ready = false; 1052 rdev->cp.ready = false;
1051 WREG32(RADEON_CP_CSQ_MODE, 0); 1053 WREG32(RADEON_CP_CSQ_MODE, 0);
1052 WREG32(RADEON_CP_CSQ_CNTL, 0); 1054 WREG32(RADEON_CP_CSQ_CNTL, 0);
@@ -2020,18 +2022,7 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *l
2020 return false; 2022 return false;
2021 } 2023 }
2022 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 2024 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2023 if (elapsed >= 3000) { 2025 if (elapsed >= 10000) {
2024 /* very likely the improbable case where current
2025 * rptr is equal to last recorded, a while ago, rptr
2026 * this is more likely a false positive update tracking
2027 * information which should force us to be recall at
2028 * latter point
2029 */
2030 lockup->last_cp_rptr = cp->rptr;
2031 lockup->last_jiffies = jiffies;
2032 return false;
2033 }
2034 if (elapsed >= 1000) {
2035 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 2026 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2036 return true; 2027 return true;
2037 } 2028 }
@@ -2306,6 +2297,7 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
2306 /* FIXME we don't use the second aperture yet when we could use it */ 2297 /* FIXME we don't use the second aperture yet when we could use it */
2307 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2298 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2308 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2299 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2300 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2309 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2301 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2310 if (rdev->flags & RADEON_IS_IGP) { 2302 if (rdev->flags & RADEON_IS_IGP) {
2311 uint32_t tom; 2303 uint32_t tom;
@@ -3308,13 +3300,14 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3308 unsigned long size; 3300 unsigned long size;
3309 unsigned prim_walk; 3301 unsigned prim_walk;
3310 unsigned nverts; 3302 unsigned nverts;
3303 unsigned num_cb = track->num_cb;
3311 3304
3312 for (i = 0; i < track->num_cb; i++) { 3305 if (!track->zb_cb_clear && !track->color_channel_mask &&
3306 !track->blend_read_enable)
3307 num_cb = 0;
3308
3309 for (i = 0; i < num_cb; i++) {
3313 if (track->cb[i].robj == NULL) { 3310 if (track->cb[i].robj == NULL) {
3314 if (!(track->zb_cb_clear || track->color_channel_mask ||
3315 track->blend_read_enable)) {
3316 continue;
3317 }
3318 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3311 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3319 return -EINVAL; 3312 return -EINVAL;
3320 } 3313 }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index d0ebae9dde25..7b65e4efe8af 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1248,6 +1248,7 @@ int r600_mc_init(struct radeon_device *rdev)
1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1250 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1250 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1251 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1251 r600_vram_gtt_location(rdev, &rdev->mc); 1252 r600_vram_gtt_location(rdev, &rdev->mc);
1252 1253
1253 if (rdev->flags & RADEON_IS_IGP) { 1254 if (rdev->flags & RADEON_IS_IGP) {
@@ -1917,6 +1918,7 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1917 */ 1918 */
1918void r600_cp_stop(struct radeon_device *rdev) 1919void r600_cp_stop(struct radeon_device *rdev)
1919{ 1920{
1921 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1920 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1922 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1921} 1923}
1922 1924
@@ -2119,10 +2121,7 @@ int r600_cp_start(struct radeon_device *rdev)
2119 } 2121 }
2120 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2122 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2121 radeon_ring_write(rdev, 0x1); 2123 radeon_ring_write(rdev, 0x1);
2122 if (rdev->family >= CHIP_CEDAR) { 2124 if (rdev->family >= CHIP_RV770) {
2123 radeon_ring_write(rdev, 0x0);
2124 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2125 } else if (rdev->family >= CHIP_RV770) {
2126 radeon_ring_write(rdev, 0x0); 2125 radeon_ring_write(rdev, 0x0);
2127 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); 2126 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2128 } else { 2127 } else {
@@ -2489,11 +2488,6 @@ int r600_resume(struct radeon_device *rdev)
2489 */ 2488 */
2490 /* post card */ 2489 /* post card */
2491 atom_asic_init(rdev->mode_info.atom_context); 2490 atom_asic_init(rdev->mode_info.atom_context);
2492 /* Initialize clocks */
2493 r = radeon_clocks_init(rdev);
2494 if (r) {
2495 return r;
2496 }
2497 2491
2498 r = r600_startup(rdev); 2492 r = r600_startup(rdev);
2499 if (r) { 2493 if (r) {
@@ -2586,9 +2580,6 @@ int r600_init(struct radeon_device *rdev)
2586 radeon_surface_init(rdev); 2580 radeon_surface_init(rdev);
2587 /* Initialize clocks */ 2581 /* Initialize clocks */
2588 radeon_get_clock_info(rdev->ddev); 2582 radeon_get_clock_info(rdev->ddev);
2589 r = radeon_clocks_init(rdev);
2590 if (r)
2591 return r;
2592 /* Fence driver */ 2583 /* Fence driver */
2593 r = radeon_fence_driver_init(rdev); 2584 r = radeon_fence_driver_init(rdev);
2594 if (r) 2585 if (r)
@@ -2663,7 +2654,6 @@ void r600_fini(struct radeon_device *rdev)
2663 radeon_agp_fini(rdev); 2654 radeon_agp_fini(rdev);
2664 radeon_gem_fini(rdev); 2655 radeon_gem_fini(rdev);
2665 radeon_fence_driver_fini(rdev); 2656 radeon_fence_driver_fini(rdev);
2666 radeon_clocks_fini(rdev);
2667 radeon_bo_fini(rdev); 2657 radeon_bo_fini(rdev);
2668 radeon_atombios_fini(rdev); 2658 radeon_atombios_fini(rdev);
2669 kfree(rdev->bios); 2659 kfree(rdev->bios);
@@ -2741,7 +2731,7 @@ int r600_ib_test(struct radeon_device *rdev)
2741 if (i < rdev->usec_timeout) { 2731 if (i < rdev->usec_timeout) {
2742 DRM_INFO("ib test succeeded in %u usecs\n", i); 2732 DRM_INFO("ib test succeeded in %u usecs\n", i);
2743 } else { 2733 } else {
2744 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 2734 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2745 scratch, tmp); 2735 scratch, tmp);
2746 r = -EINVAL; 2736 r = -EINVAL;
2747 } 2737 }
@@ -2922,7 +2912,7 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev)
2922{ 2912{
2923 u32 tmp; 2913 u32 tmp;
2924 2914
2925 WREG32(CP_INT_CNTL, 0); 2915 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2926 WREG32(GRBM_INT_CNTL, 0); 2916 WREG32(GRBM_INT_CNTL, 0);
2927 WREG32(DxMODE_INT_MASK, 0); 2917 WREG32(DxMODE_INT_MASK, 0);
2928 if (ASIC_IS_DCE3(rdev)) { 2918 if (ASIC_IS_DCE3(rdev)) {
@@ -3540,8 +3530,9 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3540 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 3530 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3541 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 3531 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3542 */ 3532 */
3543 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { 3533 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3544 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 3534 rdev->vram_scratch.ptr) {
3535 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3545 u32 tmp; 3536 u32 tmp;
3546 3537
3547 WREG32(HDP_DEBUG1, 0); 3538 WREG32(HDP_DEBUG1, 0);
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index d13622ae74e9..3473c00781ff 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -1,3 +1,28 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
1#include "drmP.h" 26#include "drmP.h"
2#include "drm.h" 27#include "drm.h"
3#include "radeon_drm.h" 28#include "radeon_drm.h"
@@ -507,6 +532,7 @@ int r600_blit_init(struct radeon_device *rdev)
507 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); 532 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
508 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 533 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
509 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 534 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
535 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
510 return 0; 536 return 0;
511} 537}
512 538
@@ -514,6 +540,7 @@ void r600_blit_fini(struct radeon_device *rdev)
514{ 540{
515 int r; 541 int r;
516 542
543 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
517 if (rdev->r600_blit.shader_obj == NULL) 544 if (rdev->r600_blit.shader_obj == NULL)
518 return; 545 return;
519 /* If we can't reserve the bo, unref should be enough to destroy 546 /* If we can't reserve the bo, unref should be enough to destroy
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h
index fdc3b378cbb0..f437d36dd98c 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.h
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h
@@ -1,3 +1,27 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
1 25
2#ifndef R600_BLIT_SHADERS_H 26#ifndef R600_BLIT_SHADERS_H
3#define R600_BLIT_SHADERS_H 27#define R600_BLIT_SHADERS_H
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index d8864949e387..250a3a918193 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -1170,9 +1170,8 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1170 /* using get ib will give us the offset into the mipmap bo */ 1170 /* using get ib will give us the offset into the mipmap bo */
1171 word0 = radeon_get_ib_value(p, idx + 3) << 8; 1171 word0 = radeon_get_ib_value(p, idx + 3) << 8;
1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) { 1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1173 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1173 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture)); 1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
1175 return -EINVAL;
1176 } 1175 }
1177 return 0; 1176 return 0;
1178} 1177}
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3dfcfa3ca425..9ff38c99a6ea 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -344,6 +344,7 @@ struct radeon_mc {
344 * about vram size near mc fb location */ 344 * about vram size near mc fb location */
345 u64 mc_vram_size; 345 u64 mc_vram_size;
346 u64 visible_vram_size; 346 u64 visible_vram_size;
347 u64 active_vram_size;
347 u64 gtt_size; 348 u64 gtt_size;
348 u64 gtt_start; 349 u64 gtt_start;
349 u64 gtt_end; 350 u64 gtt_end;
@@ -1013,6 +1014,11 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1013int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1014int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *filp); 1015 struct drm_file *filp);
1015 1016
1017/* VRAM scratch page for HDP bug */
1018struct r700_vram_scratch {
1019 struct radeon_bo *robj;
1020 volatile uint32_t *ptr;
1021};
1016 1022
1017/* 1023/*
1018 * Core structure, functions and helpers. 1024 * Core structure, functions and helpers.
@@ -1079,6 +1085,7 @@ struct radeon_device {
1079 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1085 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1080 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1086 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1081 struct r600_blit r600_blit; 1087 struct r600_blit r600_blit;
1088 struct r700_vram_scratch vram_scratch;
1082 int msi_enabled; /* msi enabled */ 1089 int msi_enabled; /* msi enabled */
1083 struct r600_ih ih; /* r6/700 interrupt ring */ 1090 struct r600_ih ih; /* r6/700 interrupt ring */
1084 struct workqueue_struct *wq; 1091 struct workqueue_struct *wq;
@@ -1333,8 +1340,6 @@ extern bool radeon_card_posted(struct radeon_device *rdev);
1333extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1340extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1334extern void radeon_update_display_priority(struct radeon_device *rdev); 1341extern void radeon_update_display_priority(struct radeon_device *rdev);
1335extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1342extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1336extern int radeon_clocks_init(struct radeon_device *rdev);
1337extern void radeon_clocks_fini(struct radeon_device *rdev);
1338extern void radeon_scratch_init(struct radeon_device *rdev); 1343extern void radeon_scratch_init(struct radeon_device *rdev);
1339extern void radeon_surface_init(struct radeon_device *rdev); 1344extern void radeon_surface_init(struct radeon_device *rdev);
1340extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1345extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index f40dfb77f9b1..bd2f33e5c91a 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -156,7 +156,13 @@ int radeon_agp_init(struct radeon_device *rdev)
156 } 156 }
157 157
158 mode.mode = info.mode; 158 mode.mode = info.mode;
159 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; 159 /* chips with the agp to pcie bridge don't have the AGP_STATUS register
160 * Just use the whatever mode the host sets up.
161 */
162 if (rdev->family <= CHIP_RV350)
163 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
164 else
165 agp_status = mode.mode;
160 is_v3 = !!(agp_status & RADEON_AGPv3_MODE); 166 is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
161 167
162 if (is_v3) { 168 if (is_v3) {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 646f96f97c77..25e1dd197791 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -733,6 +733,7 @@ static struct radeon_asic evergreen_asic = {
733 .set_engine_clock = &radeon_atom_set_engine_clock, 733 .set_engine_clock = &radeon_atom_set_engine_clock,
734 .get_memory_clock = &radeon_atom_get_memory_clock, 734 .get_memory_clock = &radeon_atom_get_memory_clock,
735 .set_memory_clock = &radeon_atom_set_memory_clock, 735 .set_memory_clock = &radeon_atom_set_memory_clock,
736 .get_pcie_lanes = NULL,
736 .set_pcie_lanes = NULL, 737 .set_pcie_lanes = NULL,
737 .set_clock_gating = NULL, 738 .set_clock_gating = NULL,
738 .set_surface_reg = r600_set_surface_reg, 739 .set_surface_reg = r600_set_surface_reg,
@@ -857,21 +858,3 @@ int radeon_asic_init(struct radeon_device *rdev)
857 return 0; 858 return 0;
858} 859}
859 860
860/*
861 * Wrapper around modesetting bits. Move to radeon_clocks.c?
862 */
863int radeon_clocks_init(struct radeon_device *rdev)
864{
865 int r;
866
867 r = radeon_static_clocks_init(rdev->ddev);
868 if (r) {
869 return r;
870 }
871 DRM_INFO("Clocks initialized !\n");
872 return 0;
873}
874
875void radeon_clocks_fini(struct radeon_device *rdev)
876{
877}
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 6d30868744ee..8e43ddae70cc 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -32,11 +32,11 @@
32 32
33/* from radeon_encoder.c */ 33/* from radeon_encoder.c */
34extern uint32_t 34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac); 36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev); 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void 38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device); 40 uint32_t supported_device);
41 41
42/* from radeon_connector.c */ 42/* from radeon_connector.c */
@@ -46,14 +46,14 @@ radeon_add_atom_connector(struct drm_device *dev,
46 uint32_t supported_device, 46 uint32_t supported_device,
47 int connector_type, 47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus, 48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info, 49 uint32_t igp_lane_info,
50 uint16_t connector_object_id, 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd, 51 struct radeon_hpd *hpd,
52 struct radeon_router *router); 52 struct radeon_router *router);
53 53
54/* from radeon_legacy_encoder.c */ 54/* from radeon_legacy_encoder.c */
55extern void 55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device); 57 uint32_t supported_device);
58 58
59union atom_supported_devices { 59union atom_supported_devices {
@@ -85,6 +85,19 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
85 for (i = 0; i < num_indices; i++) { 85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i]; 86 gpio = &i2c_info->asGPIO_Info[i];
87 87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
88 if (gpio->sucI2cId.ucAccess == id) { 101 if (gpio->sucI2cId.ucAccess == id) {
89 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
90 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
@@ -147,6 +160,20 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev)
147 for (i = 0; i < num_indices; i++) { 160 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i]; 161 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false; 162 i2c.valid = false;
163
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev)) {
166 if ((i == 7) &&
167 (gpio->usClkMaskRegisterIndex == 0x1936) &&
168 (gpio->sucI2cId.ucAccess == 0)) {
169 gpio->sucI2cId.ucAccess = 0x97;
170 gpio->ucDataMaskShift = 8;
171 gpio->ucDataEnShift = 8;
172 gpio->ucDataY_Shift = 8;
173 gpio->ucDataA_Shift = 8;
174 }
175 }
176
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
@@ -226,6 +253,8 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device
226 struct radeon_hpd hpd; 253 struct radeon_hpd hpd;
227 u32 reg; 254 u32 reg;
228 255
256 memset(&hpd, 0, sizeof(struct radeon_hpd));
257
229 if (ASIC_IS_DCE4(rdev)) 258 if (ASIC_IS_DCE4(rdev))
230 reg = EVERGREEN_DC_GPIO_HPD_A; 259 reg = EVERGREEN_DC_GPIO_HPD_A;
231 else 260 else
@@ -288,6 +317,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
288 *connector_type = DRM_MODE_CONNECTOR_DVID; 317 *connector_type = DRM_MODE_CONNECTOR_DVID;
289 } 318 }
290 319
320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev->pdev->device == 0x796e) &&
322 (dev->pdev->subsystem_vendor == 0x1462) &&
323 (dev->pdev->subsystem_device == 0x7302)) {
324 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
325 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 return false;
327 }
328
291 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
292 if ((dev->pdev->device == 0x7941) && 330 if ((dev->pdev->device == 0x7941) &&
293 (dev->pdev->subsystem_vendor == 0x147b) && 331 (dev->pdev->subsystem_vendor == 0x147b) &&
@@ -477,7 +515,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
477 int i, j, k, path_size, device_support; 515 int i, j, k, path_size, device_support;
478 int connector_type; 516 int connector_type;
479 u16 igp_lane_info, conn_id, connector_object_id; 517 u16 igp_lane_info, conn_id, connector_object_id;
480 bool linkb;
481 struct radeon_i2c_bus_rec ddc_bus; 518 struct radeon_i2c_bus_rec ddc_bus;
482 struct radeon_router router; 519 struct radeon_router router;
483 struct radeon_gpio_rec gpio; 520 struct radeon_gpio_rec gpio;
@@ -510,7 +547,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
510 addr += path_size; 547 addr += path_size;
511 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 548 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
512 path_size += le16_to_cpu(path->usSize); 549 path_size += le16_to_cpu(path->usSize);
513 linkb = false; 550
514 if (device_support & le16_to_cpu(path->usDeviceTag)) { 551 if (device_support & le16_to_cpu(path->usDeviceTag)) {
515 uint8_t con_obj_id, con_obj_num, con_obj_type; 552 uint8_t con_obj_id, con_obj_num, con_obj_type;
516 553
@@ -601,13 +638,10 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
601 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 638 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
602 639
603 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 640 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
604 if (grph_obj_num == 2) 641 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
605 linkb = true;
606 else
607 linkb = false;
608 642
609 radeon_add_atom_encoder(dev, 643 radeon_add_atom_encoder(dev,
610 grph_obj_id, 644 encoder_obj,
611 le16_to_cpu 645 le16_to_cpu
612 (path-> 646 (path->
613 usDeviceTag)); 647 usDeviceTag));
@@ -744,7 +778,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
744 le16_to_cpu(path-> 778 le16_to_cpu(path->
745 usDeviceTag), 779 usDeviceTag),
746 connector_type, &ddc_bus, 780 connector_type, &ddc_bus,
747 linkb, igp_lane_info, 781 igp_lane_info,
748 connector_object_id, 782 connector_object_id,
749 &hpd, 783 &hpd,
750 &router); 784 &router);
@@ -933,13 +967,13 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
933 967
934 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 968 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
935 radeon_add_atom_encoder(dev, 969 radeon_add_atom_encoder(dev,
936 radeon_get_encoder_id(dev, 970 radeon_get_encoder_enum(dev,
937 (1 << i), 971 (1 << i),
938 dac), 972 dac),
939 (1 << i)); 973 (1 << i));
940 else 974 else
941 radeon_add_legacy_encoder(dev, 975 radeon_add_legacy_encoder(dev,
942 radeon_get_encoder_id(dev, 976 radeon_get_encoder_enum(dev,
943 (1 << i), 977 (1 << i),
944 dac), 978 dac),
945 (1 << i)); 979 (1 << i));
@@ -996,7 +1030,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
996 bios_connectors[i]. 1030 bios_connectors[i].
997 connector_type, 1031 connector_type,
998 &bios_connectors[i].ddc_bus, 1032 &bios_connectors[i].ddc_bus,
999 false, 0, 1033 0,
1000 connector_object_id, 1034 connector_object_id,
1001 &bios_connectors[i].hpd, 1035 &bios_connectors[i].hpd,
1002 &router); 1036 &router);
@@ -1183,7 +1217,7 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1183 return true; 1217 return true;
1184 break; 1218 break;
1185 case 2: 1219 case 2:
1186 if (igp_info->info_2.ucMemoryType & 0x0f) 1220 if (igp_info->info_2.ulBootUpSidePortClock)
1187 return true; 1221 return true;
1188 break; 1222 break;
1189 default: 1223 default:
@@ -1305,6 +1339,7 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1305 union lvds_info *lvds_info; 1339 union lvds_info *lvds_info;
1306 uint8_t frev, crev; 1340 uint8_t frev, crev;
1307 struct radeon_encoder_atom_dig *lvds = NULL; 1341 struct radeon_encoder_atom_dig *lvds = NULL;
1342 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1308 1343
1309 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1344 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1310 &frev, &crev, &data_offset)) { 1345 &frev, &crev, &data_offset)) {
@@ -1368,6 +1403,12 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1368 } 1403 }
1369 1404
1370 encoder->native_mode = lvds->native_mode; 1405 encoder->native_mode = lvds->native_mode;
1406
1407 if (encoder_enum == 2)
1408 lvds->linkb = true;
1409 else
1410 lvds->linkb = false;
1411
1371 } 1412 }
1372 return lvds; 1413 return lvds;
1373} 1414}
@@ -1517,39 +1558,39 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev)
1517 switch (tv_info->ucTV_BootUpDefaultStandard) { 1558 switch (tv_info->ucTV_BootUpDefaultStandard) {
1518 case ATOM_TV_NTSC: 1559 case ATOM_TV_NTSC:
1519 tv_std = TV_STD_NTSC; 1560 tv_std = TV_STD_NTSC;
1520 DRM_INFO("Default TV standard: NTSC\n"); 1561 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1521 break; 1562 break;
1522 case ATOM_TV_NTSCJ: 1563 case ATOM_TV_NTSCJ:
1523 tv_std = TV_STD_NTSC_J; 1564 tv_std = TV_STD_NTSC_J;
1524 DRM_INFO("Default TV standard: NTSC-J\n"); 1565 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1525 break; 1566 break;
1526 case ATOM_TV_PAL: 1567 case ATOM_TV_PAL:
1527 tv_std = TV_STD_PAL; 1568 tv_std = TV_STD_PAL;
1528 DRM_INFO("Default TV standard: PAL\n"); 1569 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1529 break; 1570 break;
1530 case ATOM_TV_PALM: 1571 case ATOM_TV_PALM:
1531 tv_std = TV_STD_PAL_M; 1572 tv_std = TV_STD_PAL_M;
1532 DRM_INFO("Default TV standard: PAL-M\n"); 1573 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1533 break; 1574 break;
1534 case ATOM_TV_PALN: 1575 case ATOM_TV_PALN:
1535 tv_std = TV_STD_PAL_N; 1576 tv_std = TV_STD_PAL_N;
1536 DRM_INFO("Default TV standard: PAL-N\n"); 1577 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1537 break; 1578 break;
1538 case ATOM_TV_PALCN: 1579 case ATOM_TV_PALCN:
1539 tv_std = TV_STD_PAL_CN; 1580 tv_std = TV_STD_PAL_CN;
1540 DRM_INFO("Default TV standard: PAL-CN\n"); 1581 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1541 break; 1582 break;
1542 case ATOM_TV_PAL60: 1583 case ATOM_TV_PAL60:
1543 tv_std = TV_STD_PAL_60; 1584 tv_std = TV_STD_PAL_60;
1544 DRM_INFO("Default TV standard: PAL-60\n"); 1585 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1545 break; 1586 break;
1546 case ATOM_TV_SECAM: 1587 case ATOM_TV_SECAM:
1547 tv_std = TV_STD_SECAM; 1588 tv_std = TV_STD_SECAM;
1548 DRM_INFO("Default TV standard: SECAM\n"); 1589 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1549 break; 1590 break;
1550 default: 1591 default:
1551 tv_std = TV_STD_NTSC; 1592 tv_std = TV_STD_NTSC;
1552 DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); 1593 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1553 break; 1594 break;
1554 } 1595 }
1555 } 1596 }
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 14448a740ba6..5249af8931e6 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -327,6 +327,14 @@ void radeon_get_clock_info(struct drm_device *dev)
327 mpll->max_feedback_div = 0xff; 327 mpll->max_feedback_div = 0xff;
328 mpll->best_vco = 0; 328 mpll->best_vco = 0;
329 329
330 if (!rdev->clock.default_sclk)
331 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
332 if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)
333 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
334
335 rdev->pm.current_sclk = rdev->clock.default_sclk;
336 rdev->pm.current_mclk = rdev->clock.default_mclk;
337
330} 338}
331 339
332/* 10 khz */ 340/* 10 khz */
@@ -897,53 +905,3 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
897 } 905 }
898} 906}
899 907
900static void radeon_apply_clock_quirks(struct radeon_device *rdev)
901{
902 uint32_t tmp;
903
904 /* XXX make sure engine is idle */
905
906 if (rdev->family < CHIP_RS600) {
907 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
908 if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
909 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
910 if ((rdev->family == CHIP_RV250)
911 || (rdev->family == CHIP_RV280))
912 tmp |=
913 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
914 if ((rdev->family == CHIP_RV350)
915 || (rdev->family == CHIP_RV380))
916 tmp |= R300_SCLK_FORCE_VAP;
917 if (rdev->family == CHIP_R420)
918 tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
919 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
920 } else if (rdev->family < CHIP_R600) {
921 tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
922 tmp |= AVIVO_CP_FORCEON;
923 WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
924
925 tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
926 tmp |= AVIVO_E2_FORCEON;
927 WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
928
929 tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
930 tmp |= AVIVO_IDCT_FORCEON;
931 WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
932 }
933}
934
935int radeon_static_clocks_init(struct drm_device *dev)
936{
937 struct radeon_device *rdev = dev->dev_private;
938
939 /* XXX make sure engine is idle */
940
941 if (radeon_dynclks != -1) {
942 if (radeon_dynclks) {
943 if (rdev->asic->set_clock_gating)
944 radeon_set_clock_gating(rdev, 1);
945 }
946 }
947 radeon_apply_clock_quirks(rdev);
948 return 0;
949}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 885dcfac1838..7b7ea269549c 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -39,8 +39,8 @@
39 39
40/* from radeon_encoder.c */ 40/* from radeon_encoder.c */
41extern uint32_t 41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, 42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac); 43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev); 44extern void radeon_link_encoder_connector(struct drm_device *dev);
45 45
46/* from radeon_connector.c */ 46/* from radeon_connector.c */
@@ -55,7 +55,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
55 55
56/* from radeon_legacy_encoder.c */ 56/* from radeon_legacy_encoder.c */
57extern void 57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, 58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device); 59 uint32_t supported_device);
60 60
61/* old legacy ATI BIOS routines */ 61/* old legacy ATI BIOS routines */
@@ -913,47 +913,47 @@ radeon_combios_get_tv_info(struct radeon_device *rdev)
913 switch (RBIOS8(tv_info + 7) & 0xf) { 913 switch (RBIOS8(tv_info + 7) & 0xf) {
914 case 1: 914 case 1:
915 tv_std = TV_STD_NTSC; 915 tv_std = TV_STD_NTSC;
916 DRM_INFO("Default TV standard: NTSC\n"); 916 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
917 break; 917 break;
918 case 2: 918 case 2:
919 tv_std = TV_STD_PAL; 919 tv_std = TV_STD_PAL;
920 DRM_INFO("Default TV standard: PAL\n"); 920 DRM_DEBUG_KMS("Default TV standard: PAL\n");
921 break; 921 break;
922 case 3: 922 case 3:
923 tv_std = TV_STD_PAL_M; 923 tv_std = TV_STD_PAL_M;
924 DRM_INFO("Default TV standard: PAL-M\n"); 924 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
925 break; 925 break;
926 case 4: 926 case 4:
927 tv_std = TV_STD_PAL_60; 927 tv_std = TV_STD_PAL_60;
928 DRM_INFO("Default TV standard: PAL-60\n"); 928 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
929 break; 929 break;
930 case 5: 930 case 5:
931 tv_std = TV_STD_NTSC_J; 931 tv_std = TV_STD_NTSC_J;
932 DRM_INFO("Default TV standard: NTSC-J\n"); 932 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
933 break; 933 break;
934 case 6: 934 case 6:
935 tv_std = TV_STD_SCART_PAL; 935 tv_std = TV_STD_SCART_PAL;
936 DRM_INFO("Default TV standard: SCART-PAL\n"); 936 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
937 break; 937 break;
938 default: 938 default:
939 tv_std = TV_STD_NTSC; 939 tv_std = TV_STD_NTSC;
940 DRM_INFO 940 DRM_DEBUG_KMS
941 ("Unknown TV standard; defaulting to NTSC\n"); 941 ("Unknown TV standard; defaulting to NTSC\n");
942 break; 942 break;
943 } 943 }
944 944
945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
946 case 0: 946 case 0:
947 DRM_INFO("29.498928713 MHz TV ref clk\n"); 947 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
948 break; 948 break;
949 case 1: 949 case 1:
950 DRM_INFO("28.636360000 MHz TV ref clk\n"); 950 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
951 break; 951 break;
952 case 2: 952 case 2:
953 DRM_INFO("14.318180000 MHz TV ref clk\n"); 953 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
954 break; 954 break;
955 case 3: 955 case 3:
956 DRM_INFO("27.000000000 MHz TV ref clk\n"); 956 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
957 break; 957 break;
958 default: 958 default:
959 break; 959 break;
@@ -1324,7 +1324,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1324 1324
1325 if (tmds_info) { 1325 if (tmds_info) {
1326 ver = RBIOS8(tmds_info); 1326 ver = RBIOS8(tmds_info);
1327 DRM_INFO("DFP table revision: %d\n", ver); 1327 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1328 if (ver == 3) { 1328 if (ver == 3) {
1329 n = RBIOS8(tmds_info + 5) + 1; 1329 n = RBIOS8(tmds_info + 5) + 1;
1330 if (n > 4) 1330 if (n > 4)
@@ -1408,7 +1408,7 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1409 if (offset) { 1409 if (offset) {
1410 ver = RBIOS8(offset); 1410 ver = RBIOS8(offset);
1411 DRM_INFO("External TMDS Table revision: %d\n", ver); 1411 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1412 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1413 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1414 gpio = RBIOS8(offset + 4 + 3); 1414 gpio = RBIOS8(offset + 4 + 3);
@@ -1485,6 +1485,11 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1485 /* PowerMac8,1 ? */ 1485 /* PowerMac8,1 ? */
1486 /* imac g5 isight */ 1486 /* imac g5 isight */
1487 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1487 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1488 } else if ((rdev->pdev->device == 0x4a48) &&
1489 (rdev->pdev->subsystem_vendor == 0x1002) &&
1490 (rdev->pdev->subsystem_device == 0x4a48)) {
1491 /* Mac X800 */
1492 rdev->mode_info.connector_table = CT_MAC_X800;
1488 } else 1493 } else
1489#endif /* CONFIG_PPC_PMAC */ 1494#endif /* CONFIG_PPC_PMAC */
1490#ifdef CONFIG_PPC64 1495#ifdef CONFIG_PPC64
@@ -1505,7 +1510,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1510 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1506 hpd.hpd = RADEON_HPD_NONE; 1511 hpd.hpd = RADEON_HPD_NONE;
1507 radeon_add_legacy_encoder(dev, 1512 radeon_add_legacy_encoder(dev,
1508 radeon_get_encoder_id(dev, 1513 radeon_get_encoder_enum(dev,
1509 ATOM_DEVICE_CRT1_SUPPORT, 1514 ATOM_DEVICE_CRT1_SUPPORT,
1510 1), 1515 1),
1511 ATOM_DEVICE_CRT1_SUPPORT); 1516 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1520,7 +1525,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1520 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1521 hpd.hpd = RADEON_HPD_NONE; 1526 hpd.hpd = RADEON_HPD_NONE;
1522 radeon_add_legacy_encoder(dev, 1527 radeon_add_legacy_encoder(dev,
1523 radeon_get_encoder_id(dev, 1528 radeon_get_encoder_enum(dev,
1524 ATOM_DEVICE_LCD1_SUPPORT, 1529 ATOM_DEVICE_LCD1_SUPPORT,
1525 0), 1530 0),
1526 ATOM_DEVICE_LCD1_SUPPORT); 1531 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1535,7 +1540,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1535 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1540 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1536 hpd.hpd = RADEON_HPD_NONE; 1541 hpd.hpd = RADEON_HPD_NONE;
1537 radeon_add_legacy_encoder(dev, 1542 radeon_add_legacy_encoder(dev,
1538 radeon_get_encoder_id(dev, 1543 radeon_get_encoder_enum(dev,
1539 ATOM_DEVICE_CRT1_SUPPORT, 1544 ATOM_DEVICE_CRT1_SUPPORT,
1540 1), 1545 1),
1541 ATOM_DEVICE_CRT1_SUPPORT); 1546 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1550,12 +1555,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1555 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1551 hpd.hpd = RADEON_HPD_1; 1556 hpd.hpd = RADEON_HPD_1;
1552 radeon_add_legacy_encoder(dev, 1557 radeon_add_legacy_encoder(dev,
1553 radeon_get_encoder_id(dev, 1558 radeon_get_encoder_enum(dev,
1554 ATOM_DEVICE_DFP1_SUPPORT, 1559 ATOM_DEVICE_DFP1_SUPPORT,
1555 0), 1560 0),
1556 ATOM_DEVICE_DFP1_SUPPORT); 1561 ATOM_DEVICE_DFP1_SUPPORT);
1557 radeon_add_legacy_encoder(dev, 1562 radeon_add_legacy_encoder(dev,
1558 radeon_get_encoder_id(dev, 1563 radeon_get_encoder_enum(dev,
1559 ATOM_DEVICE_CRT2_SUPPORT, 1564 ATOM_DEVICE_CRT2_SUPPORT,
1560 2), 1565 2),
1561 ATOM_DEVICE_CRT2_SUPPORT); 1566 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1571,7 +1576,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1576 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1572 hpd.hpd = RADEON_HPD_NONE; 1577 hpd.hpd = RADEON_HPD_NONE;
1573 radeon_add_legacy_encoder(dev, 1578 radeon_add_legacy_encoder(dev,
1574 radeon_get_encoder_id(dev, 1579 radeon_get_encoder_enum(dev,
1575 ATOM_DEVICE_CRT1_SUPPORT, 1580 ATOM_DEVICE_CRT1_SUPPORT,
1576 1), 1581 1),
1577 ATOM_DEVICE_CRT1_SUPPORT); 1582 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1588,7 +1593,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1588 ddc_i2c.valid = false; 1593 ddc_i2c.valid = false;
1589 hpd.hpd = RADEON_HPD_NONE; 1594 hpd.hpd = RADEON_HPD_NONE;
1590 radeon_add_legacy_encoder(dev, 1595 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_id(dev, 1596 radeon_get_encoder_enum(dev,
1592 ATOM_DEVICE_TV1_SUPPORT, 1597 ATOM_DEVICE_TV1_SUPPORT,
1593 2), 1598 2),
1594 ATOM_DEVICE_TV1_SUPPORT); 1599 ATOM_DEVICE_TV1_SUPPORT);
@@ -1607,7 +1612,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1612 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1608 hpd.hpd = RADEON_HPD_NONE; 1613 hpd.hpd = RADEON_HPD_NONE;
1609 radeon_add_legacy_encoder(dev, 1614 radeon_add_legacy_encoder(dev,
1610 radeon_get_encoder_id(dev, 1615 radeon_get_encoder_enum(dev,
1611 ATOM_DEVICE_LCD1_SUPPORT, 1616 ATOM_DEVICE_LCD1_SUPPORT,
1612 0), 1617 0),
1613 ATOM_DEVICE_LCD1_SUPPORT); 1618 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1619,7 +1624,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1619 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1624 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1620 hpd.hpd = RADEON_HPD_NONE; 1625 hpd.hpd = RADEON_HPD_NONE;
1621 radeon_add_legacy_encoder(dev, 1626 radeon_add_legacy_encoder(dev,
1622 radeon_get_encoder_id(dev, 1627 radeon_get_encoder_enum(dev,
1623 ATOM_DEVICE_CRT2_SUPPORT, 1628 ATOM_DEVICE_CRT2_SUPPORT,
1624 2), 1629 2),
1625 ATOM_DEVICE_CRT2_SUPPORT); 1630 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1631,7 +1636,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1631 ddc_i2c.valid = false; 1636 ddc_i2c.valid = false;
1632 hpd.hpd = RADEON_HPD_NONE; 1637 hpd.hpd = RADEON_HPD_NONE;
1633 radeon_add_legacy_encoder(dev, 1638 radeon_add_legacy_encoder(dev,
1634 radeon_get_encoder_id(dev, 1639 radeon_get_encoder_enum(dev,
1635 ATOM_DEVICE_TV1_SUPPORT, 1640 ATOM_DEVICE_TV1_SUPPORT,
1636 2), 1641 2),
1637 ATOM_DEVICE_TV1_SUPPORT); 1642 ATOM_DEVICE_TV1_SUPPORT);
@@ -1648,7 +1653,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1648 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1653 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1649 hpd.hpd = RADEON_HPD_NONE; 1654 hpd.hpd = RADEON_HPD_NONE;
1650 radeon_add_legacy_encoder(dev, 1655 radeon_add_legacy_encoder(dev,
1651 radeon_get_encoder_id(dev, 1656 radeon_get_encoder_enum(dev,
1652 ATOM_DEVICE_LCD1_SUPPORT, 1657 ATOM_DEVICE_LCD1_SUPPORT,
1653 0), 1658 0),
1654 ATOM_DEVICE_LCD1_SUPPORT); 1659 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1660,12 +1665,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1665 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1661 hpd.hpd = RADEON_HPD_2; /* ??? */ 1666 hpd.hpd = RADEON_HPD_2; /* ??? */
1662 radeon_add_legacy_encoder(dev, 1667 radeon_add_legacy_encoder(dev,
1663 radeon_get_encoder_id(dev, 1668 radeon_get_encoder_enum(dev,
1664 ATOM_DEVICE_DFP2_SUPPORT, 1669 ATOM_DEVICE_DFP2_SUPPORT,
1665 0), 1670 0),
1666 ATOM_DEVICE_DFP2_SUPPORT); 1671 ATOM_DEVICE_DFP2_SUPPORT);
1667 radeon_add_legacy_encoder(dev, 1672 radeon_add_legacy_encoder(dev,
1668 radeon_get_encoder_id(dev, 1673 radeon_get_encoder_enum(dev,
1669 ATOM_DEVICE_CRT1_SUPPORT, 1674 ATOM_DEVICE_CRT1_SUPPORT,
1670 1), 1675 1),
1671 ATOM_DEVICE_CRT1_SUPPORT); 1676 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1680,7 +1685,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1680 ddc_i2c.valid = false; 1685 ddc_i2c.valid = false;
1681 hpd.hpd = RADEON_HPD_NONE; 1686 hpd.hpd = RADEON_HPD_NONE;
1682 radeon_add_legacy_encoder(dev, 1687 radeon_add_legacy_encoder(dev,
1683 radeon_get_encoder_id(dev, 1688 radeon_get_encoder_enum(dev,
1684 ATOM_DEVICE_TV1_SUPPORT, 1689 ATOM_DEVICE_TV1_SUPPORT,
1685 2), 1690 2),
1686 ATOM_DEVICE_TV1_SUPPORT); 1691 ATOM_DEVICE_TV1_SUPPORT);
@@ -1697,7 +1702,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1702 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1698 hpd.hpd = RADEON_HPD_NONE; 1703 hpd.hpd = RADEON_HPD_NONE;
1699 radeon_add_legacy_encoder(dev, 1704 radeon_add_legacy_encoder(dev,
1700 radeon_get_encoder_id(dev, 1705 radeon_get_encoder_enum(dev,
1701 ATOM_DEVICE_LCD1_SUPPORT, 1706 ATOM_DEVICE_LCD1_SUPPORT,
1702 0), 1707 0),
1703 ATOM_DEVICE_LCD1_SUPPORT); 1708 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1709,12 +1714,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1709 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1714 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1710 hpd.hpd = RADEON_HPD_1; /* ??? */ 1715 hpd.hpd = RADEON_HPD_1; /* ??? */
1711 radeon_add_legacy_encoder(dev, 1716 radeon_add_legacy_encoder(dev,
1712 radeon_get_encoder_id(dev, 1717 radeon_get_encoder_enum(dev,
1713 ATOM_DEVICE_DFP1_SUPPORT, 1718 ATOM_DEVICE_DFP1_SUPPORT,
1714 0), 1719 0),
1715 ATOM_DEVICE_DFP1_SUPPORT); 1720 ATOM_DEVICE_DFP1_SUPPORT);
1716 radeon_add_legacy_encoder(dev, 1721 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_id(dev, 1722 radeon_get_encoder_enum(dev,
1718 ATOM_DEVICE_CRT1_SUPPORT, 1723 ATOM_DEVICE_CRT1_SUPPORT,
1719 1), 1724 1),
1720 ATOM_DEVICE_CRT1_SUPPORT); 1725 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1728,7 +1733,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1728 ddc_i2c.valid = false; 1733 ddc_i2c.valid = false;
1729 hpd.hpd = RADEON_HPD_NONE; 1734 hpd.hpd = RADEON_HPD_NONE;
1730 radeon_add_legacy_encoder(dev, 1735 radeon_add_legacy_encoder(dev,
1731 radeon_get_encoder_id(dev, 1736 radeon_get_encoder_enum(dev,
1732 ATOM_DEVICE_TV1_SUPPORT, 1737 ATOM_DEVICE_TV1_SUPPORT,
1733 2), 1738 2),
1734 ATOM_DEVICE_TV1_SUPPORT); 1739 ATOM_DEVICE_TV1_SUPPORT);
@@ -1745,7 +1750,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1745 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1750 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1746 hpd.hpd = RADEON_HPD_NONE; 1751 hpd.hpd = RADEON_HPD_NONE;
1747 radeon_add_legacy_encoder(dev, 1752 radeon_add_legacy_encoder(dev,
1748 radeon_get_encoder_id(dev, 1753 radeon_get_encoder_enum(dev,
1749 ATOM_DEVICE_LCD1_SUPPORT, 1754 ATOM_DEVICE_LCD1_SUPPORT,
1750 0), 1755 0),
1751 ATOM_DEVICE_LCD1_SUPPORT); 1756 ATOM_DEVICE_LCD1_SUPPORT);
@@ -1757,7 +1762,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1757 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1762 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1758 hpd.hpd = RADEON_HPD_NONE; 1763 hpd.hpd = RADEON_HPD_NONE;
1759 radeon_add_legacy_encoder(dev, 1764 radeon_add_legacy_encoder(dev,
1760 radeon_get_encoder_id(dev, 1765 radeon_get_encoder_enum(dev,
1761 ATOM_DEVICE_CRT1_SUPPORT, 1766 ATOM_DEVICE_CRT1_SUPPORT,
1762 1), 1767 1),
1763 ATOM_DEVICE_CRT1_SUPPORT); 1768 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1769,7 +1774,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1769 ddc_i2c.valid = false; 1774 ddc_i2c.valid = false;
1770 hpd.hpd = RADEON_HPD_NONE; 1775 hpd.hpd = RADEON_HPD_NONE;
1771 radeon_add_legacy_encoder(dev, 1776 radeon_add_legacy_encoder(dev,
1772 radeon_get_encoder_id(dev, 1777 radeon_get_encoder_enum(dev,
1773 ATOM_DEVICE_TV1_SUPPORT, 1778 ATOM_DEVICE_TV1_SUPPORT,
1774 2), 1779 2),
1775 ATOM_DEVICE_TV1_SUPPORT); 1780 ATOM_DEVICE_TV1_SUPPORT);
@@ -1786,12 +1791,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1786 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1791 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1787 hpd.hpd = RADEON_HPD_2; /* ??? */ 1792 hpd.hpd = RADEON_HPD_2; /* ??? */
1788 radeon_add_legacy_encoder(dev, 1793 radeon_add_legacy_encoder(dev,
1789 radeon_get_encoder_id(dev, 1794 radeon_get_encoder_enum(dev,
1790 ATOM_DEVICE_DFP2_SUPPORT, 1795 ATOM_DEVICE_DFP2_SUPPORT,
1791 0), 1796 0),
1792 ATOM_DEVICE_DFP2_SUPPORT); 1797 ATOM_DEVICE_DFP2_SUPPORT);
1793 radeon_add_legacy_encoder(dev, 1798 radeon_add_legacy_encoder(dev,
1794 radeon_get_encoder_id(dev, 1799 radeon_get_encoder_enum(dev,
1795 ATOM_DEVICE_CRT2_SUPPORT, 1800 ATOM_DEVICE_CRT2_SUPPORT,
1796 2), 1801 2),
1797 ATOM_DEVICE_CRT2_SUPPORT); 1802 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1806,7 +1811,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1806 ddc_i2c.valid = false; 1811 ddc_i2c.valid = false;
1807 hpd.hpd = RADEON_HPD_NONE; 1812 hpd.hpd = RADEON_HPD_NONE;
1808 radeon_add_legacy_encoder(dev, 1813 radeon_add_legacy_encoder(dev,
1809 radeon_get_encoder_id(dev, 1814 radeon_get_encoder_enum(dev,
1810 ATOM_DEVICE_TV1_SUPPORT, 1815 ATOM_DEVICE_TV1_SUPPORT,
1811 2), 1816 2),
1812 ATOM_DEVICE_TV1_SUPPORT); 1817 ATOM_DEVICE_TV1_SUPPORT);
@@ -1823,12 +1828,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1828 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1824 hpd.hpd = RADEON_HPD_1; /* ??? */ 1829 hpd.hpd = RADEON_HPD_1; /* ??? */
1825 radeon_add_legacy_encoder(dev, 1830 radeon_add_legacy_encoder(dev,
1826 radeon_get_encoder_id(dev, 1831 radeon_get_encoder_enum(dev,
1827 ATOM_DEVICE_DFP1_SUPPORT, 1832 ATOM_DEVICE_DFP1_SUPPORT,
1828 0), 1833 0),
1829 ATOM_DEVICE_DFP1_SUPPORT); 1834 ATOM_DEVICE_DFP1_SUPPORT);
1830 radeon_add_legacy_encoder(dev, 1835 radeon_add_legacy_encoder(dev,
1831 radeon_get_encoder_id(dev, 1836 radeon_get_encoder_enum(dev,
1832 ATOM_DEVICE_CRT2_SUPPORT, 1837 ATOM_DEVICE_CRT2_SUPPORT,
1833 2), 1838 2),
1834 ATOM_DEVICE_CRT2_SUPPORT); 1839 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1842,7 +1847,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1842 ddc_i2c.valid = false; 1847 ddc_i2c.valid = false;
1843 hpd.hpd = RADEON_HPD_NONE; 1848 hpd.hpd = RADEON_HPD_NONE;
1844 radeon_add_legacy_encoder(dev, 1849 radeon_add_legacy_encoder(dev,
1845 radeon_get_encoder_id(dev, 1850 radeon_get_encoder_enum(dev,
1846 ATOM_DEVICE_TV1_SUPPORT, 1851 ATOM_DEVICE_TV1_SUPPORT,
1847 2), 1852 2),
1848 ATOM_DEVICE_TV1_SUPPORT); 1853 ATOM_DEVICE_TV1_SUPPORT);
@@ -1859,7 +1864,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1859 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1864 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1860 hpd.hpd = RADEON_HPD_1; /* ??? */ 1865 hpd.hpd = RADEON_HPD_1; /* ??? */
1861 radeon_add_legacy_encoder(dev, 1866 radeon_add_legacy_encoder(dev,
1862 radeon_get_encoder_id(dev, 1867 radeon_get_encoder_enum(dev,
1863 ATOM_DEVICE_DFP1_SUPPORT, 1868 ATOM_DEVICE_DFP1_SUPPORT,
1864 0), 1869 0),
1865 ATOM_DEVICE_DFP1_SUPPORT); 1870 ATOM_DEVICE_DFP1_SUPPORT);
@@ -1871,7 +1876,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1871 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1876 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1872 hpd.hpd = RADEON_HPD_NONE; 1877 hpd.hpd = RADEON_HPD_NONE;
1873 radeon_add_legacy_encoder(dev, 1878 radeon_add_legacy_encoder(dev,
1874 radeon_get_encoder_id(dev, 1879 radeon_get_encoder_enum(dev,
1875 ATOM_DEVICE_CRT2_SUPPORT, 1880 ATOM_DEVICE_CRT2_SUPPORT,
1876 2), 1881 2),
1877 ATOM_DEVICE_CRT2_SUPPORT); 1882 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1883,7 +1888,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1883 ddc_i2c.valid = false; 1888 ddc_i2c.valid = false;
1884 hpd.hpd = RADEON_HPD_NONE; 1889 hpd.hpd = RADEON_HPD_NONE;
1885 radeon_add_legacy_encoder(dev, 1890 radeon_add_legacy_encoder(dev,
1886 radeon_get_encoder_id(dev, 1891 radeon_get_encoder_enum(dev,
1887 ATOM_DEVICE_TV1_SUPPORT, 1892 ATOM_DEVICE_TV1_SUPPORT,
1888 2), 1893 2),
1889 ATOM_DEVICE_TV1_SUPPORT); 1894 ATOM_DEVICE_TV1_SUPPORT);
@@ -1900,7 +1905,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1900 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1905 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1901 hpd.hpd = RADEON_HPD_NONE; 1906 hpd.hpd = RADEON_HPD_NONE;
1902 radeon_add_legacy_encoder(dev, 1907 radeon_add_legacy_encoder(dev,
1903 radeon_get_encoder_id(dev, 1908 radeon_get_encoder_enum(dev,
1904 ATOM_DEVICE_CRT1_SUPPORT, 1909 ATOM_DEVICE_CRT1_SUPPORT,
1905 1), 1910 1),
1906 ATOM_DEVICE_CRT1_SUPPORT); 1911 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1912,7 +1917,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1917 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1913 hpd.hpd = RADEON_HPD_NONE; 1918 hpd.hpd = RADEON_HPD_NONE;
1914 radeon_add_legacy_encoder(dev, 1919 radeon_add_legacy_encoder(dev,
1915 radeon_get_encoder_id(dev, 1920 radeon_get_encoder_enum(dev,
1916 ATOM_DEVICE_CRT2_SUPPORT, 1921 ATOM_DEVICE_CRT2_SUPPORT,
1917 2), 1922 2),
1918 ATOM_DEVICE_CRT2_SUPPORT); 1923 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1924,7 +1929,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1924 ddc_i2c.valid = false; 1929 ddc_i2c.valid = false;
1925 hpd.hpd = RADEON_HPD_NONE; 1930 hpd.hpd = RADEON_HPD_NONE;
1926 radeon_add_legacy_encoder(dev, 1931 radeon_add_legacy_encoder(dev,
1927 radeon_get_encoder_id(dev, 1932 radeon_get_encoder_enum(dev,
1928 ATOM_DEVICE_TV1_SUPPORT, 1933 ATOM_DEVICE_TV1_SUPPORT,
1929 2), 1934 2),
1930 ATOM_DEVICE_TV1_SUPPORT); 1935 ATOM_DEVICE_TV1_SUPPORT);
@@ -1941,7 +1946,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1941 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1946 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1942 hpd.hpd = RADEON_HPD_NONE; 1947 hpd.hpd = RADEON_HPD_NONE;
1943 radeon_add_legacy_encoder(dev, 1948 radeon_add_legacy_encoder(dev,
1944 radeon_get_encoder_id(dev, 1949 radeon_get_encoder_enum(dev,
1945 ATOM_DEVICE_CRT1_SUPPORT, 1950 ATOM_DEVICE_CRT1_SUPPORT,
1946 1), 1951 1),
1947 ATOM_DEVICE_CRT1_SUPPORT); 1952 ATOM_DEVICE_CRT1_SUPPORT);
@@ -1952,7 +1957,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1957 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1953 hpd.hpd = RADEON_HPD_NONE; 1958 hpd.hpd = RADEON_HPD_NONE;
1954 radeon_add_legacy_encoder(dev, 1959 radeon_add_legacy_encoder(dev,
1955 radeon_get_encoder_id(dev, 1960 radeon_get_encoder_enum(dev,
1956 ATOM_DEVICE_CRT2_SUPPORT, 1961 ATOM_DEVICE_CRT2_SUPPORT,
1957 2), 1962 2),
1958 ATOM_DEVICE_CRT2_SUPPORT); 1963 ATOM_DEVICE_CRT2_SUPPORT);
@@ -1961,6 +1966,48 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1961 CONNECTOR_OBJECT_ID_VGA, 1966 CONNECTOR_OBJECT_ID_VGA,
1962 &hpd); 1967 &hpd);
1963 break; 1968 break;
1969 case CT_MAC_X800:
1970 DRM_INFO("Connector Table: %d (mac x800)\n",
1971 rdev->mode_info.connector_table);
1972 /* DVI - primary dac, internal tmds */
1973 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1974 hpd.hpd = RADEON_HPD_1; /* ??? */
1975 radeon_add_legacy_encoder(dev,
1976 radeon_get_encoder_enum(dev,
1977 ATOM_DEVICE_DFP1_SUPPORT,
1978 0),
1979 ATOM_DEVICE_DFP1_SUPPORT);
1980 radeon_add_legacy_encoder(dev,
1981 radeon_get_encoder_enum(dev,
1982 ATOM_DEVICE_CRT1_SUPPORT,
1983 1),
1984 ATOM_DEVICE_CRT1_SUPPORT);
1985 radeon_add_legacy_connector(dev, 0,
1986 ATOM_DEVICE_DFP1_SUPPORT |
1987 ATOM_DEVICE_CRT1_SUPPORT,
1988 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1989 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1990 &hpd);
1991 /* DVI - tv dac, dvo */
1992 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1993 hpd.hpd = RADEON_HPD_2; /* ??? */
1994 radeon_add_legacy_encoder(dev,
1995 radeon_get_encoder_enum(dev,
1996 ATOM_DEVICE_DFP2_SUPPORT,
1997 0),
1998 ATOM_DEVICE_DFP2_SUPPORT);
1999 radeon_add_legacy_encoder(dev,
2000 radeon_get_encoder_enum(dev,
2001 ATOM_DEVICE_CRT2_SUPPORT,
2002 2),
2003 ATOM_DEVICE_CRT2_SUPPORT);
2004 radeon_add_legacy_connector(dev, 1,
2005 ATOM_DEVICE_DFP2_SUPPORT |
2006 ATOM_DEVICE_CRT2_SUPPORT,
2007 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2008 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2009 &hpd);
2010 break;
1964 default: 2011 default:
1965 DRM_INFO("Connector table: %d (invalid)\n", 2012 DRM_INFO("Connector table: %d (invalid)\n",
1966 rdev->mode_info.connector_table); 2013 rdev->mode_info.connector_table);
@@ -2109,7 +2156,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2109 else 2156 else
2110 devices = ATOM_DEVICE_DFP1_SUPPORT; 2157 devices = ATOM_DEVICE_DFP1_SUPPORT;
2111 radeon_add_legacy_encoder(dev, 2158 radeon_add_legacy_encoder(dev,
2112 radeon_get_encoder_id 2159 radeon_get_encoder_enum
2113 (dev, devices, 0), 2160 (dev, devices, 0),
2114 devices); 2161 devices);
2115 radeon_add_legacy_connector(dev, i, devices, 2162 radeon_add_legacy_connector(dev, i, devices,
@@ -2123,7 +2170,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2123 if (tmp & 0x1) { 2170 if (tmp & 0x1) {
2124 devices = ATOM_DEVICE_CRT2_SUPPORT; 2171 devices = ATOM_DEVICE_CRT2_SUPPORT;
2125 radeon_add_legacy_encoder(dev, 2172 radeon_add_legacy_encoder(dev,
2126 radeon_get_encoder_id 2173 radeon_get_encoder_enum
2127 (dev, 2174 (dev,
2128 ATOM_DEVICE_CRT2_SUPPORT, 2175 ATOM_DEVICE_CRT2_SUPPORT,
2129 2), 2176 2),
@@ -2131,7 +2178,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2131 } else { 2178 } else {
2132 devices = ATOM_DEVICE_CRT1_SUPPORT; 2179 devices = ATOM_DEVICE_CRT1_SUPPORT;
2133 radeon_add_legacy_encoder(dev, 2180 radeon_add_legacy_encoder(dev,
2134 radeon_get_encoder_id 2181 radeon_get_encoder_enum
2135 (dev, 2182 (dev,
2136 ATOM_DEVICE_CRT1_SUPPORT, 2183 ATOM_DEVICE_CRT1_SUPPORT,
2137 1), 2184 1),
@@ -2151,7 +2198,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2151 if (tmp & 0x1) { 2198 if (tmp & 0x1) {
2152 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2199 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2153 radeon_add_legacy_encoder(dev, 2200 radeon_add_legacy_encoder(dev,
2154 radeon_get_encoder_id 2201 radeon_get_encoder_enum
2155 (dev, 2202 (dev,
2156 ATOM_DEVICE_CRT2_SUPPORT, 2203 ATOM_DEVICE_CRT2_SUPPORT,
2157 2), 2204 2),
@@ -2159,7 +2206,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2159 } else { 2206 } else {
2160 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2207 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2161 radeon_add_legacy_encoder(dev, 2208 radeon_add_legacy_encoder(dev,
2162 radeon_get_encoder_id 2209 radeon_get_encoder_enum
2163 (dev, 2210 (dev,
2164 ATOM_DEVICE_CRT1_SUPPORT, 2211 ATOM_DEVICE_CRT1_SUPPORT,
2165 1), 2212 1),
@@ -2168,7 +2215,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2168 if ((tmp >> 4) & 0x1) { 2215 if ((tmp >> 4) & 0x1) {
2169 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2216 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2170 radeon_add_legacy_encoder(dev, 2217 radeon_add_legacy_encoder(dev,
2171 radeon_get_encoder_id 2218 radeon_get_encoder_enum
2172 (dev, 2219 (dev,
2173 ATOM_DEVICE_DFP2_SUPPORT, 2220 ATOM_DEVICE_DFP2_SUPPORT,
2174 0), 2221 0),
@@ -2177,7 +2224,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2177 } else { 2224 } else {
2178 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2225 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2179 radeon_add_legacy_encoder(dev, 2226 radeon_add_legacy_encoder(dev,
2180 radeon_get_encoder_id 2227 radeon_get_encoder_enum
2181 (dev, 2228 (dev,
2182 ATOM_DEVICE_DFP1_SUPPORT, 2229 ATOM_DEVICE_DFP1_SUPPORT,
2183 0), 2230 0),
@@ -2202,7 +2249,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2202 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2249 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2203 } 2250 }
2204 radeon_add_legacy_encoder(dev, 2251 radeon_add_legacy_encoder(dev,
2205 radeon_get_encoder_id 2252 radeon_get_encoder_enum
2206 (dev, devices, 0), 2253 (dev, devices, 0),
2207 devices); 2254 devices);
2208 radeon_add_legacy_connector(dev, i, devices, 2255 radeon_add_legacy_connector(dev, i, devices,
@@ -2215,7 +2262,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2215 case CONNECTOR_CTV_LEGACY: 2262 case CONNECTOR_CTV_LEGACY:
2216 case CONNECTOR_STV_LEGACY: 2263 case CONNECTOR_STV_LEGACY:
2217 radeon_add_legacy_encoder(dev, 2264 radeon_add_legacy_encoder(dev,
2218 radeon_get_encoder_id 2265 radeon_get_encoder_enum
2219 (dev, 2266 (dev,
2220 ATOM_DEVICE_TV1_SUPPORT, 2267 ATOM_DEVICE_TV1_SUPPORT,
2221 2), 2268 2),
@@ -2242,12 +2289,12 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2242 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2289 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2243 2290
2244 radeon_add_legacy_encoder(dev, 2291 radeon_add_legacy_encoder(dev,
2245 radeon_get_encoder_id(dev, 2292 radeon_get_encoder_enum(dev,
2246 ATOM_DEVICE_CRT1_SUPPORT, 2293 ATOM_DEVICE_CRT1_SUPPORT,
2247 1), 2294 1),
2248 ATOM_DEVICE_CRT1_SUPPORT); 2295 ATOM_DEVICE_CRT1_SUPPORT);
2249 radeon_add_legacy_encoder(dev, 2296 radeon_add_legacy_encoder(dev,
2250 radeon_get_encoder_id(dev, 2297 radeon_get_encoder_enum(dev,
2251 ATOM_DEVICE_DFP1_SUPPORT, 2298 ATOM_DEVICE_DFP1_SUPPORT,
2252 0), 2299 0),
2253 ATOM_DEVICE_DFP1_SUPPORT); 2300 ATOM_DEVICE_DFP1_SUPPORT);
@@ -2268,7 +2315,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2268 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2315 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2269 if (crt_info) { 2316 if (crt_info) {
2270 radeon_add_legacy_encoder(dev, 2317 radeon_add_legacy_encoder(dev,
2271 radeon_get_encoder_id(dev, 2318 radeon_get_encoder_enum(dev,
2272 ATOM_DEVICE_CRT1_SUPPORT, 2319 ATOM_DEVICE_CRT1_SUPPORT,
2273 1), 2320 1),
2274 ATOM_DEVICE_CRT1_SUPPORT); 2321 ATOM_DEVICE_CRT1_SUPPORT);
@@ -2297,7 +2344,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2297 COMBIOS_LCD_DDC_INFO_TABLE); 2344 COMBIOS_LCD_DDC_INFO_TABLE);
2298 2345
2299 radeon_add_legacy_encoder(dev, 2346 radeon_add_legacy_encoder(dev,
2300 radeon_get_encoder_id(dev, 2347 radeon_get_encoder_enum(dev,
2301 ATOM_DEVICE_LCD1_SUPPORT, 2348 ATOM_DEVICE_LCD1_SUPPORT,
2302 0), 2349 0),
2303 ATOM_DEVICE_LCD1_SUPPORT); 2350 ATOM_DEVICE_LCD1_SUPPORT);
@@ -2351,7 +2398,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2351 hpd.hpd = RADEON_HPD_NONE; 2398 hpd.hpd = RADEON_HPD_NONE;
2352 ddc_i2c.valid = false; 2399 ddc_i2c.valid = false;
2353 radeon_add_legacy_encoder(dev, 2400 radeon_add_legacy_encoder(dev,
2354 radeon_get_encoder_id 2401 radeon_get_encoder_enum
2355 (dev, 2402 (dev,
2356 ATOM_DEVICE_TV1_SUPPORT, 2403 ATOM_DEVICE_TV1_SUPPORT,
2357 2), 2404 2),
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 47c4b276d30c..ecc1a8fafbfd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -481,7 +481,8 @@ static int radeon_lvds_mode_valid(struct drm_connector *connector,
481 return MODE_OK; 481 return MODE_OK;
482} 482}
483 483
484static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector) 484static enum drm_connector_status
485radeon_lvds_detect(struct drm_connector *connector, bool force)
485{ 486{
486 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 487 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
487 struct drm_encoder *encoder = radeon_best_single_encoder(connector); 488 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
@@ -594,7 +595,8 @@ static int radeon_vga_mode_valid(struct drm_connector *connector,
594 return MODE_OK; 595 return MODE_OK;
595} 596}
596 597
597static enum drm_connector_status radeon_vga_detect(struct drm_connector *connector) 598static enum drm_connector_status
599radeon_vga_detect(struct drm_connector *connector, bool force)
598{ 600{
599 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 601 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
600 struct drm_encoder *encoder; 602 struct drm_encoder *encoder;
@@ -691,7 +693,8 @@ static int radeon_tv_mode_valid(struct drm_connector *connector,
691 return MODE_OK; 693 return MODE_OK;
692} 694}
693 695
694static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector) 696static enum drm_connector_status
697radeon_tv_detect(struct drm_connector *connector, bool force)
695{ 698{
696 struct drm_encoder *encoder; 699 struct drm_encoder *encoder;
697 struct drm_encoder_helper_funcs *encoder_funcs; 700 struct drm_encoder_helper_funcs *encoder_funcs;
@@ -748,7 +751,8 @@ static int radeon_dvi_get_modes(struct drm_connector *connector)
748 * we have to check if this analog encoder is shared with anyone else (TV) 751 * we have to check if this analog encoder is shared with anyone else (TV)
749 * if its shared we have to set the other connector to disconnected. 752 * if its shared we have to set the other connector to disconnected.
750 */ 753 */
751static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector) 754static enum drm_connector_status
755radeon_dvi_detect(struct drm_connector *connector, bool force)
752{ 756{
753 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 757 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
754 struct drm_encoder *encoder = NULL; 758 struct drm_encoder *encoder = NULL;
@@ -972,32 +976,35 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
972 return ret; 976 return ret;
973} 977}
974 978
975static enum drm_connector_status radeon_dp_detect(struct drm_connector *connector) 979static enum drm_connector_status
980radeon_dp_detect(struct drm_connector *connector, bool force)
976{ 981{
977 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 982 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
978 enum drm_connector_status ret = connector_status_disconnected; 983 enum drm_connector_status ret = connector_status_disconnected;
979 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 984 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
980 u8 sink_type;
981 985
982 if (radeon_connector->edid) { 986 if (radeon_connector->edid) {
983 kfree(radeon_connector->edid); 987 kfree(radeon_connector->edid);
984 radeon_connector->edid = NULL; 988 radeon_connector->edid = NULL;
985 } 989 }
986 990
987 sink_type = radeon_dp_getsinktype(radeon_connector); 991 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
988 if ((sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 992 /* eDP is always DP */
989 (sink_type == CONNECTOR_OBJECT_ID_eDP)) { 993 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
990 if (radeon_dp_getdpcd(radeon_connector)) { 994 if (radeon_dp_getdpcd(radeon_connector))
991 radeon_dig_connector->dp_sink_type = sink_type;
992 ret = connector_status_connected; 995 ret = connector_status_connected;
993 }
994 } else { 996 } else {
995 if (radeon_ddc_probe(radeon_connector)) { 997 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
996 radeon_dig_connector->dp_sink_type = sink_type; 998 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
997 ret = connector_status_connected; 999 if (radeon_dp_getdpcd(radeon_connector))
1000 ret = connector_status_connected;
1001 } else {
1002 if (radeon_ddc_probe(radeon_connector))
1003 ret = connector_status_connected;
998 } 1004 }
999 } 1005 }
1000 1006
1007 radeon_connector_update_scratch_regs(connector, ret);
1001 return ret; 1008 return ret;
1002} 1009}
1003 1010
@@ -1037,7 +1044,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1037 uint32_t supported_device, 1044 uint32_t supported_device,
1038 int connector_type, 1045 int connector_type,
1039 struct radeon_i2c_bus_rec *i2c_bus, 1046 struct radeon_i2c_bus_rec *i2c_bus,
1040 bool linkb,
1041 uint32_t igp_lane_info, 1047 uint32_t igp_lane_info,
1042 uint16_t connector_object_id, 1048 uint16_t connector_object_id,
1043 struct radeon_hpd *hpd, 1049 struct radeon_hpd *hpd,
@@ -1050,10 +1056,16 @@ radeon_add_atom_connector(struct drm_device *dev,
1050 uint32_t subpixel_order = SubPixelNone; 1056 uint32_t subpixel_order = SubPixelNone;
1051 bool shared_ddc = false; 1057 bool shared_ddc = false;
1052 1058
1053 /* fixme - tv/cv/din */
1054 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1059 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1055 return; 1060 return;
1056 1061
1062 /* if the user selected tv=0 don't try and add the connector */
1063 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1064 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1065 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1066 (radeon_tv == 0))
1067 return;
1068
1057 /* see if we already added it */ 1069 /* see if we already added it */
1058 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1059 radeon_connector = to_radeon_connector(connector); 1071 radeon_connector = to_radeon_connector(connector);
@@ -1128,7 +1140,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1128 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1140 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1129 if (!radeon_dig_connector) 1141 if (!radeon_dig_connector)
1130 goto failed; 1142 goto failed;
1131 radeon_dig_connector->linkb = linkb;
1132 radeon_dig_connector->igp_lane_info = igp_lane_info; 1143 radeon_dig_connector->igp_lane_info = igp_lane_info;
1133 radeon_connector->con_priv = radeon_dig_connector; 1144 radeon_connector->con_priv = radeon_dig_connector;
1134 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1145 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
@@ -1158,7 +1169,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1158 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1169 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1159 if (!radeon_dig_connector) 1170 if (!radeon_dig_connector)
1160 goto failed; 1171 goto failed;
1161 radeon_dig_connector->linkb = linkb;
1162 radeon_dig_connector->igp_lane_info = igp_lane_info; 1172 radeon_dig_connector->igp_lane_info = igp_lane_info;
1163 radeon_connector->con_priv = radeon_dig_connector; 1173 radeon_connector->con_priv = radeon_dig_connector;
1164 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1174 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
@@ -1182,7 +1192,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1182 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1192 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1183 if (!radeon_dig_connector) 1193 if (!radeon_dig_connector)
1184 goto failed; 1194 goto failed;
1185 radeon_dig_connector->linkb = linkb;
1186 radeon_dig_connector->igp_lane_info = igp_lane_info; 1195 radeon_dig_connector->igp_lane_info = igp_lane_info;
1187 radeon_connector->con_priv = radeon_dig_connector; 1196 radeon_connector->con_priv = radeon_dig_connector;
1188 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type); 1197 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
@@ -1211,25 +1220,22 @@ radeon_add_atom_connector(struct drm_device *dev,
1211 case DRM_MODE_CONNECTOR_SVIDEO: 1220 case DRM_MODE_CONNECTOR_SVIDEO:
1212 case DRM_MODE_CONNECTOR_Composite: 1221 case DRM_MODE_CONNECTOR_Composite:
1213 case DRM_MODE_CONNECTOR_9PinDIN: 1222 case DRM_MODE_CONNECTOR_9PinDIN:
1214 if (radeon_tv == 1) { 1223 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
1215 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); 1224 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
1216 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); 1225 radeon_connector->dac_load_detect = true;
1217 radeon_connector->dac_load_detect = true; 1226 drm_connector_attach_property(&radeon_connector->base,
1218 drm_connector_attach_property(&radeon_connector->base, 1227 rdev->mode_info.load_detect_property,
1219 rdev->mode_info.load_detect_property, 1228 1);
1220 1); 1229 drm_connector_attach_property(&radeon_connector->base,
1221 drm_connector_attach_property(&radeon_connector->base, 1230 rdev->mode_info.tv_std_property,
1222 rdev->mode_info.tv_std_property, 1231 radeon_atombios_get_tv_info(rdev));
1223 radeon_atombios_get_tv_info(rdev)); 1232 /* no HPD on analog connectors */
1224 /* no HPD on analog connectors */ 1233 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1225 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1226 }
1227 break; 1234 break;
1228 case DRM_MODE_CONNECTOR_LVDS: 1235 case DRM_MODE_CONNECTOR_LVDS:
1229 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1236 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1230 if (!radeon_dig_connector) 1237 if (!radeon_dig_connector)
1231 goto failed; 1238 goto failed;
1232 radeon_dig_connector->linkb = linkb;
1233 radeon_dig_connector->igp_lane_info = igp_lane_info; 1239 radeon_dig_connector->igp_lane_info = igp_lane_info;
1234 radeon_connector->con_priv = radeon_dig_connector; 1240 radeon_connector->con_priv = radeon_dig_connector;
1235 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1241 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
@@ -1275,10 +1281,16 @@ radeon_add_legacy_connector(struct drm_device *dev,
1275 struct radeon_connector *radeon_connector; 1281 struct radeon_connector *radeon_connector;
1276 uint32_t subpixel_order = SubPixelNone; 1282 uint32_t subpixel_order = SubPixelNone;
1277 1283
1278 /* fixme - tv/cv/din */
1279 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1284 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1280 return; 1285 return;
1281 1286
1287 /* if the user selected tv=0 don't try and add the connector */
1288 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1289 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1290 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1291 (radeon_tv == 0))
1292 return;
1293
1282 /* see if we already added it */ 1294 /* see if we already added it */
1283 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1295 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1284 radeon_connector = to_radeon_connector(connector); 1296 radeon_connector = to_radeon_connector(connector);
@@ -1350,26 +1362,24 @@ radeon_add_legacy_connector(struct drm_device *dev,
1350 case DRM_MODE_CONNECTOR_SVIDEO: 1362 case DRM_MODE_CONNECTOR_SVIDEO:
1351 case DRM_MODE_CONNECTOR_Composite: 1363 case DRM_MODE_CONNECTOR_Composite:
1352 case DRM_MODE_CONNECTOR_9PinDIN: 1364 case DRM_MODE_CONNECTOR_9PinDIN:
1353 if (radeon_tv == 1) { 1365 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
1354 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); 1366 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
1355 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); 1367 radeon_connector->dac_load_detect = true;
1356 radeon_connector->dac_load_detect = true; 1368 /* RS400,RC410,RS480 chipset seems to report a lot
1357 /* RS400,RC410,RS480 chipset seems to report a lot 1369 * of false positive on load detect, we haven't yet
1358 * of false positive on load detect, we haven't yet 1370 * found a way to make load detect reliable on those
1359 * found a way to make load detect reliable on those 1371 * chipset, thus just disable it for TV.
1360 * chipset, thus just disable it for TV. 1372 */
1361 */ 1373 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
1362 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) 1374 radeon_connector->dac_load_detect = false;
1363 radeon_connector->dac_load_detect = false; 1375 drm_connector_attach_property(&radeon_connector->base,
1364 drm_connector_attach_property(&radeon_connector->base, 1376 rdev->mode_info.load_detect_property,
1365 rdev->mode_info.load_detect_property, 1377 radeon_connector->dac_load_detect);
1366 radeon_connector->dac_load_detect); 1378 drm_connector_attach_property(&radeon_connector->base,
1367 drm_connector_attach_property(&radeon_connector->base, 1379 rdev->mode_info.tv_std_property,
1368 rdev->mode_info.tv_std_property, 1380 radeon_combios_get_tv_info(rdev));
1369 radeon_combios_get_tv_info(rdev)); 1381 /* no HPD on analog connectors */
1370 /* no HPD on analog connectors */ 1382 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1371 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1372 }
1373 break; 1383 break;
1374 case DRM_MODE_CONNECTOR_LVDS: 1384 case DRM_MODE_CONNECTOR_LVDS:
1375 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1385 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 4f7a170d1566..256d204a6d24 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -199,7 +199,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
199 mc->mc_vram_size = mc->aper_size; 199 mc->mc_vram_size = mc->aper_size;
200 } 200 }
201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
202 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) { 202 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
203 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 203 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
204 mc->real_vram_size = mc->aper_size; 204 mc->real_vram_size = mc->aper_size;
205 mc->mc_vram_size = mc->aper_size; 205 mc->mc_vram_size = mc->aper_size;
@@ -293,30 +293,20 @@ bool radeon_card_posted(struct radeon_device *rdev)
293void radeon_update_bandwidth_info(struct radeon_device *rdev) 293void radeon_update_bandwidth_info(struct radeon_device *rdev)
294{ 294{
295 fixed20_12 a; 295 fixed20_12 a;
296 u32 sclk, mclk; 296 u32 sclk = rdev->pm.current_sclk;
297 u32 mclk = rdev->pm.current_mclk;
297 298
298 if (rdev->flags & RADEON_IS_IGP) { 299 /* sclk/mclk in Mhz */
299 sclk = radeon_get_engine_clock(rdev); 300 a.full = dfixed_const(100);
300 mclk = rdev->clock.default_mclk; 301 rdev->pm.sclk.full = dfixed_const(sclk);
301 302 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
302 a.full = dfixed_const(100); 303 rdev->pm.mclk.full = dfixed_const(mclk);
303 rdev->pm.sclk.full = dfixed_const(sclk); 304 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
304 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
305 rdev->pm.mclk.full = dfixed_const(mclk);
306 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
307 305
306 if (rdev->flags & RADEON_IS_IGP) {
308 a.full = dfixed_const(16); 307 a.full = dfixed_const(16);
309 /* core_bandwidth = sclk(Mhz) * 16 */ 308 /* core_bandwidth = sclk(Mhz) * 16 */
310 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 309 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
311 } else {
312 sclk = radeon_get_engine_clock(rdev);
313 mclk = radeon_get_memory_clock(rdev);
314
315 a.full = dfixed_const(100);
316 rdev->pm.sclk.full = dfixed_const(sclk);
317 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
318 rdev->pm.mclk.full = dfixed_const(mclk);
319 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
320 } 310 }
321} 311}
322 312
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 5764f4d3b4f1..b92d2f2fcbed 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -349,6 +349,8 @@ static void radeon_print_display_setup(struct drm_device *dev)
349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 350 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
353 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_TV1_SUPPORT) 354 if (devices & ATOM_DEVICE_TV1_SUPPORT)
353 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 355 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
354 if (devices & ATOM_DEVICE_CV_SUPPORT) 356 if (devices & ATOM_DEVICE_CV_SUPPORT)
@@ -841,8 +843,9 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
841{ 843{
842 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 844 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
843 845
844 if (radeon_fb->obj) 846 if (radeon_fb->obj) {
845 drm_gem_object_unreference_unlocked(radeon_fb->obj); 847 drm_gem_object_unreference_unlocked(radeon_fb->obj);
848 }
846 drm_framebuffer_cleanup(fb); 849 drm_framebuffer_cleanup(fb);
847 kfree(radeon_fb); 850 kfree(radeon_fb);
848} 851}
@@ -1094,6 +1097,18 @@ void radeon_modeset_fini(struct radeon_device *rdev)
1094 radeon_i2c_fini(rdev); 1097 radeon_i2c_fini(rdev);
1095} 1098}
1096 1099
1100static bool is_hdtv_mode(struct drm_display_mode *mode)
1101{
1102 /* try and guess if this is a tv or a monitor */
1103 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1104 (mode->vdisplay == 576) || /* 576p */
1105 (mode->vdisplay == 720) || /* 720p */
1106 (mode->vdisplay == 1080)) /* 1080p */
1107 return true;
1108 else
1109 return false;
1110}
1111
1097bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1112bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1098 struct drm_display_mode *mode, 1113 struct drm_display_mode *mode,
1099 struct drm_display_mode *adjusted_mode) 1114 struct drm_display_mode *adjusted_mode)
@@ -1128,20 +1143,22 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1128 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1143 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1129 else 1144 else
1130 radeon_crtc->rmx_type = RMX_OFF; 1145 radeon_crtc->rmx_type = RMX_OFF;
1131 src_v = crtc->mode.vdisplay;
1132 dst_v = radeon_crtc->native_mode.vdisplay;
1133 src_h = crtc->mode.hdisplay;
1134 dst_h = radeon_crtc->native_mode.vdisplay;
1135 /* copy native mode */ 1146 /* copy native mode */
1136 memcpy(&radeon_crtc->native_mode, 1147 memcpy(&radeon_crtc->native_mode,
1137 &radeon_encoder->native_mode, 1148 &radeon_encoder->native_mode,
1138 sizeof(struct drm_display_mode)); 1149 sizeof(struct drm_display_mode));
1150 src_v = crtc->mode.vdisplay;
1151 dst_v = radeon_crtc->native_mode.vdisplay;
1152 src_h = crtc->mode.hdisplay;
1153 dst_h = radeon_crtc->native_mode.hdisplay;
1139 1154
1140 /* fix up for overscan on hdmi */ 1155 /* fix up for overscan on hdmi */
1141 if (ASIC_IS_AVIVO(rdev) && 1156 if (ASIC_IS_AVIVO(rdev) &&
1157 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1142 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1158 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1143 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1159 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1144 drm_detect_hdmi_monitor(radeon_connector->edid)))) { 1160 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1161 is_hdtv_mode(mode)))) {
1145 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1162 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1146 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1163 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1147 radeon_crtc->rmx_type = RMX_FULL; 1164 radeon_crtc->rmx_type = RMX_FULL;
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 263c8098d7dd..2c293e8304d6 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -81,7 +81,7 @@ void radeon_setup_encoder_clones(struct drm_device *dev)
81} 81}
82 82
83uint32_t 83uint32_t
84radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 84radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85{ 85{
86 struct radeon_device *rdev = dev->dev_private; 86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0; 87 uint32_t ret = 0;
@@ -97,59 +97,59 @@ radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t
97 if ((rdev->family == CHIP_RS300) || 97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) || 98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480)) 99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev)) 101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else 103 else
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break; 105 break;
106 case 2: /* dac b */ 106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev)) 107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else { 109 else {
110 /*if (rdev->family == CHIP_R200) 110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/ 112 else*/
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 } 114 }
115 break; 115 break;
116 case 3: /* external dac */ 116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev)) 117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else 119 else
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break; 121 break;
122 } 122 }
123 break; 123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT: 124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev)) 125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else 127 else
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break; 129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT: 130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) || 131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) || 132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480)) 133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev)) 135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else 137 else
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break; 139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT: 140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT: 141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) || 142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) || 143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740)) 144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI; 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev)) 146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else 148 else
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break; 150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT: 151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break; 153 break;
154 } 154 }
155 155
@@ -228,32 +228,6 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
228 return NULL; 228 return NULL;
229} 229}
230 230
231static struct radeon_connector_atom_dig *
232radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
233{
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct drm_connector *connector;
237 struct radeon_connector *radeon_connector;
238 struct radeon_connector_atom_dig *dig_connector;
239
240 if (!rdev->is_atom_bios)
241 return NULL;
242
243 connector = radeon_get_connector_for_encoder(encoder);
244 if (!connector)
245 return NULL;
246
247 radeon_connector = to_radeon_connector(connector);
248
249 if (!radeon_connector->con_priv)
250 return NULL;
251
252 dig_connector = radeon_connector->con_priv;
253
254 return dig_connector;
255}
256
257void radeon_panel_mode_fixup(struct drm_encoder *encoder, 231void radeon_panel_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *adjusted_mode) 232 struct drm_display_mode *adjusted_mode)
259{ 233{
@@ -512,14 +486,12 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
512 struct radeon_device *rdev = dev->dev_private; 486 struct radeon_device *rdev = dev->dev_private;
513 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 487 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
514 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 488 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
515 struct radeon_connector_atom_dig *dig_connector =
516 radeon_get_atom_connector_priv_from_encoder(encoder);
517 union lvds_encoder_control args; 489 union lvds_encoder_control args;
518 int index = 0; 490 int index = 0;
519 int hdmi_detected = 0; 491 int hdmi_detected = 0;
520 uint8_t frev, crev; 492 uint8_t frev, crev;
521 493
522 if (!dig || !dig_connector) 494 if (!dig)
523 return; 495 return;
524 496
525 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 497 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
@@ -562,7 +534,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
562 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 534 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
563 args.v1.ucMisc |= (1 << 1); 535 args.v1.ucMisc |= (1 << 1);
564 } else { 536 } else {
565 if (dig_connector->linkb) 537 if (dig->linkb)
566 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 538 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
567 if (radeon_encoder->pixel_clock > 165000) 539 if (radeon_encoder->pixel_clock > 165000)
568 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 540 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
@@ -601,7 +573,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
601 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 573 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
602 } 574 }
603 } else { 575 } else {
604 if (dig_connector->linkb) 576 if (dig->linkb)
605 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 577 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
606 if (radeon_encoder->pixel_clock > 165000) 578 if (radeon_encoder->pixel_clock > 165000)
607 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 579 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
@@ -623,6 +595,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
623int 595int
624atombios_get_encoder_mode(struct drm_encoder *encoder) 596atombios_get_encoder_mode(struct drm_encoder *encoder)
625{ 597{
598 struct drm_device *dev = encoder->dev;
599 struct radeon_device *rdev = dev->dev_private;
626 struct drm_connector *connector; 600 struct drm_connector *connector;
627 struct radeon_connector *radeon_connector; 601 struct radeon_connector *radeon_connector;
628 struct radeon_connector_atom_dig *dig_connector; 602 struct radeon_connector_atom_dig *dig_connector;
@@ -636,9 +610,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
636 switch (connector->connector_type) { 610 switch (connector->connector_type) {
637 case DRM_MODE_CONNECTOR_DVII: 611 case DRM_MODE_CONNECTOR_DVII:
638 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 612 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
639 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 613 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
640 return ATOM_ENCODER_MODE_HDMI; 614 /* fix me */
641 else if (radeon_connector->use_digital) 615 if (ASIC_IS_DCE4(rdev))
616 return ATOM_ENCODER_MODE_DVI;
617 else
618 return ATOM_ENCODER_MODE_HDMI;
619 } else if (radeon_connector->use_digital)
642 return ATOM_ENCODER_MODE_DVI; 620 return ATOM_ENCODER_MODE_DVI;
643 else 621 else
644 return ATOM_ENCODER_MODE_CRT; 622 return ATOM_ENCODER_MODE_CRT;
@@ -646,9 +624,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
646 case DRM_MODE_CONNECTOR_DVID: 624 case DRM_MODE_CONNECTOR_DVID:
647 case DRM_MODE_CONNECTOR_HDMIA: 625 case DRM_MODE_CONNECTOR_HDMIA:
648 default: 626 default:
649 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 627 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
650 return ATOM_ENCODER_MODE_HDMI; 628 /* fix me */
651 else 629 if (ASIC_IS_DCE4(rdev))
630 return ATOM_ENCODER_MODE_DVI;
631 else
632 return ATOM_ENCODER_MODE_HDMI;
633 } else
652 return ATOM_ENCODER_MODE_DVI; 634 return ATOM_ENCODER_MODE_DVI;
653 break; 635 break;
654 case DRM_MODE_CONNECTOR_LVDS: 636 case DRM_MODE_CONNECTOR_LVDS:
@@ -660,9 +642,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
660 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 642 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
661 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 643 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
662 return ATOM_ENCODER_MODE_DP; 644 return ATOM_ENCODER_MODE_DP;
663 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) 645 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
664 return ATOM_ENCODER_MODE_HDMI; 646 /* fix me */
665 else 647 if (ASIC_IS_DCE4(rdev))
648 return ATOM_ENCODER_MODE_DVI;
649 else
650 return ATOM_ENCODER_MODE_HDMI;
651 } else
666 return ATOM_ENCODER_MODE_DVI; 652 return ATOM_ENCODER_MODE_DVI;
667 break; 653 break;
668 case DRM_MODE_CONNECTOR_DVIA: 654 case DRM_MODE_CONNECTOR_DVIA:
@@ -729,13 +715,24 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
729 struct radeon_device *rdev = dev->dev_private; 715 struct radeon_device *rdev = dev->dev_private;
730 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 716 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
731 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 717 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
732 struct radeon_connector_atom_dig *dig_connector = 718 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
733 radeon_get_atom_connector_priv_from_encoder(encoder);
734 union dig_encoder_control args; 719 union dig_encoder_control args;
735 int index = 0; 720 int index = 0;
736 uint8_t frev, crev; 721 uint8_t frev, crev;
722 int dp_clock = 0;
723 int dp_lane_count = 0;
724
725 if (connector) {
726 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
727 struct radeon_connector_atom_dig *dig_connector =
728 radeon_connector->con_priv;
737 729
738 if (!dig || !dig_connector) 730 dp_clock = dig_connector->dp_clock;
731 dp_lane_count = dig_connector->dp_lane_count;
732 }
733
734 /* no dig encoder assigned */
735 if (dig->dig_encoder == -1)
739 return; 736 return;
740 737
741 memset(&args, 0, sizeof(args)); 738 memset(&args, 0, sizeof(args));
@@ -757,9 +754,9 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
757 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 754 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
758 755
759 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 756 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
760 if (dig_connector->dp_clock == 270000) 757 if (dp_clock == 270000)
761 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 758 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
762 args.v1.ucLaneNum = dig_connector->dp_lane_count; 759 args.v1.ucLaneNum = dp_lane_count;
763 } else if (radeon_encoder->pixel_clock > 165000) 760 } else if (radeon_encoder->pixel_clock > 165000)
764 args.v1.ucLaneNum = 8; 761 args.v1.ucLaneNum = 8;
765 else 762 else
@@ -781,7 +778,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
781 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 778 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
782 break; 779 break;
783 } 780 }
784 if (dig_connector->linkb) 781 if (dig->linkb)
785 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 782 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
786 else 783 else
787 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 784 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
@@ -804,38 +801,47 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
804 struct radeon_device *rdev = dev->dev_private; 801 struct radeon_device *rdev = dev->dev_private;
805 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 802 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
806 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 803 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
807 struct radeon_connector_atom_dig *dig_connector = 804 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
808 radeon_get_atom_connector_priv_from_encoder(encoder);
809 struct drm_connector *connector;
810 struct radeon_connector *radeon_connector;
811 union dig_transmitter_control args; 805 union dig_transmitter_control args;
812 int index = 0; 806 int index = 0;
813 uint8_t frev, crev; 807 uint8_t frev, crev;
814 bool is_dp = false; 808 bool is_dp = false;
815 int pll_id = 0; 809 int pll_id = 0;
810 int dp_clock = 0;
811 int dp_lane_count = 0;
812 int connector_object_id = 0;
813 int igp_lane_info = 0;
816 814
817 if (!dig || !dig_connector) 815 if (connector) {
818 return; 816 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
817 struct radeon_connector_atom_dig *dig_connector =
818 radeon_connector->con_priv;
819 819
820 connector = radeon_get_connector_for_encoder(encoder); 820 dp_clock = dig_connector->dp_clock;
821 radeon_connector = to_radeon_connector(connector); 821 dp_lane_count = dig_connector->dp_lane_count;
822 connector_object_id =
823 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
824 igp_lane_info = dig_connector->igp_lane_info;
825 }
826
827 /* no dig encoder assigned */
828 if (dig->dig_encoder == -1)
829 return;
822 830
823 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 831 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
824 is_dp = true; 832 is_dp = true;
825 833
826 memset(&args, 0, sizeof(args)); 834 memset(&args, 0, sizeof(args));
827 835
828 if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) 836 switch (radeon_encoder->encoder_id) {
837 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
838 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
829 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 840 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
830 else { 841 break;
831 switch (radeon_encoder->encoder_id) { 842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
832 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 843 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
833 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); 844 break;
834 break;
835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
836 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
837 break;
838 }
839 } 845 }
840 846
841 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 847 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
@@ -843,14 +849,14 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
843 849
844 args.v1.ucAction = action; 850 args.v1.ucAction = action;
845 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 851 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
846 args.v1.usInitInfo = radeon_connector->connector_object_id; 852 args.v1.usInitInfo = connector_object_id;
847 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 853 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
848 args.v1.asMode.ucLaneSel = lane_num; 854 args.v1.asMode.ucLaneSel = lane_num;
849 args.v1.asMode.ucLaneSet = lane_set; 855 args.v1.asMode.ucLaneSet = lane_set;
850 } else { 856 } else {
851 if (is_dp) 857 if (is_dp)
852 args.v1.usPixelClock = 858 args.v1.usPixelClock =
853 cpu_to_le16(dig_connector->dp_clock / 10); 859 cpu_to_le16(dp_clock / 10);
854 else if (radeon_encoder->pixel_clock > 165000) 860 else if (radeon_encoder->pixel_clock > 165000)
855 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 861 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
856 else 862 else
@@ -858,13 +864,13 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
858 } 864 }
859 if (ASIC_IS_DCE4(rdev)) { 865 if (ASIC_IS_DCE4(rdev)) {
860 if (is_dp) 866 if (is_dp)
861 args.v3.ucLaneNum = dig_connector->dp_lane_count; 867 args.v3.ucLaneNum = dp_lane_count;
862 else if (radeon_encoder->pixel_clock > 165000) 868 else if (radeon_encoder->pixel_clock > 165000)
863 args.v3.ucLaneNum = 8; 869 args.v3.ucLaneNum = 8;
864 else 870 else
865 args.v3.ucLaneNum = 4; 871 args.v3.ucLaneNum = 4;
866 872
867 if (dig_connector->linkb) { 873 if (dig->linkb) {
868 args.v3.acConfig.ucLinkSel = 1; 874 args.v3.acConfig.ucLinkSel = 1;
869 args.v3.acConfig.ucEncoderSel = 1; 875 args.v3.acConfig.ucEncoderSel = 1;
870 } 876 }
@@ -904,7 +910,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
904 } 910 }
905 } else if (ASIC_IS_DCE32(rdev)) { 911 } else if (ASIC_IS_DCE32(rdev)) {
906 args.v2.acConfig.ucEncoderSel = dig->dig_encoder; 912 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
907 if (dig_connector->linkb) 913 if (dig->linkb)
908 args.v2.acConfig.ucLinkSel = 1; 914 args.v2.acConfig.ucLinkSel = 1;
909 915
910 switch (radeon_encoder->encoder_id) { 916 switch (radeon_encoder->encoder_id) {
@@ -938,23 +944,23 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
938 if ((rdev->flags & RADEON_IS_IGP) && 944 if ((rdev->flags & RADEON_IS_IGP) &&
939 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 945 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
940 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { 946 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
941 if (dig_connector->igp_lane_info & 0x1) 947 if (igp_lane_info & 0x1)
942 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 948 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
943 else if (dig_connector->igp_lane_info & 0x2) 949 else if (igp_lane_info & 0x2)
944 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 950 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
945 else if (dig_connector->igp_lane_info & 0x4) 951 else if (igp_lane_info & 0x4)
946 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 952 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
947 else if (dig_connector->igp_lane_info & 0x8) 953 else if (igp_lane_info & 0x8)
948 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 954 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
949 } else { 955 } else {
950 if (dig_connector->igp_lane_info & 0x3) 956 if (igp_lane_info & 0x3)
951 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 957 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
952 else if (dig_connector->igp_lane_info & 0xc) 958 else if (igp_lane_info & 0xc)
953 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 959 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
954 } 960 }
955 } 961 }
956 962
957 if (dig_connector->linkb) 963 if (dig->linkb)
958 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 964 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
959 else 965 else
960 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 966 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
@@ -1072,8 +1078,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1072 if (is_dig) { 1078 if (is_dig) {
1073 switch (mode) { 1079 switch (mode) {
1074 case DRM_MODE_DPMS_ON: 1080 case DRM_MODE_DPMS_ON:
1075 if (!ASIC_IS_DCE4(rdev)) 1081 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1076 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1077 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1082 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1078 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1083 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1079 1084
@@ -1085,8 +1090,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1085 case DRM_MODE_DPMS_STANDBY: 1090 case DRM_MODE_DPMS_STANDBY:
1086 case DRM_MODE_DPMS_SUSPEND: 1091 case DRM_MODE_DPMS_SUSPEND:
1087 case DRM_MODE_DPMS_OFF: 1092 case DRM_MODE_DPMS_OFF:
1088 if (!ASIC_IS_DCE4(rdev)) 1093 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1089 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1090 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1094 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1091 if (ASIC_IS_DCE4(rdev)) 1095 if (ASIC_IS_DCE4(rdev))
1092 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); 1096 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
@@ -1290,24 +1294,22 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1290 uint32_t dig_enc_in_use = 0; 1294 uint32_t dig_enc_in_use = 0;
1291 1295
1292 if (ASIC_IS_DCE4(rdev)) { 1296 if (ASIC_IS_DCE4(rdev)) {
1293 struct radeon_connector_atom_dig *dig_connector = 1297 dig = radeon_encoder->enc_priv;
1294 radeon_get_atom_connector_priv_from_encoder(encoder);
1295
1296 switch (radeon_encoder->encoder_id) { 1298 switch (radeon_encoder->encoder_id) {
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1299 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1298 if (dig_connector->linkb) 1300 if (dig->linkb)
1299 return 1; 1301 return 1;
1300 else 1302 else
1301 return 0; 1303 return 0;
1302 break; 1304 break;
1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1304 if (dig_connector->linkb) 1306 if (dig->linkb)
1305 return 3; 1307 return 3;
1306 else 1308 else
1307 return 2; 1309 return 2;
1308 break; 1310 break;
1309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1310 if (dig_connector->linkb) 1312 if (dig->linkb)
1311 return 5; 1313 return 5;
1312 else 1314 else
1313 return 4; 1315 return 4;
@@ -1641,6 +1643,7 @@ radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1641struct radeon_encoder_atom_dig * 1643struct radeon_encoder_atom_dig *
1642radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 1644radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1643{ 1645{
1646 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1644 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1647 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1645 1648
1646 if (!dig) 1649 if (!dig)
@@ -1650,11 +1653,16 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1650 dig->coherent_mode = true; 1653 dig->coherent_mode = true;
1651 dig->dig_encoder = -1; 1654 dig->dig_encoder = -1;
1652 1655
1656 if (encoder_enum == 2)
1657 dig->linkb = true;
1658 else
1659 dig->linkb = false;
1660
1653 return dig; 1661 return dig;
1654} 1662}
1655 1663
1656void 1664void
1657radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1665radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1658{ 1666{
1659 struct radeon_device *rdev = dev->dev_private; 1667 struct radeon_device *rdev = dev->dev_private;
1660 struct drm_encoder *encoder; 1668 struct drm_encoder *encoder;
@@ -1663,7 +1671,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1663 /* see if we already added it */ 1671 /* see if we already added it */
1664 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1672 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1665 radeon_encoder = to_radeon_encoder(encoder); 1673 radeon_encoder = to_radeon_encoder(encoder);
1666 if (radeon_encoder->encoder_id == encoder_id) { 1674 if (radeon_encoder->encoder_enum == encoder_enum) {
1667 radeon_encoder->devices |= supported_device; 1675 radeon_encoder->devices |= supported_device;
1668 return; 1676 return;
1669 } 1677 }
@@ -1691,7 +1699,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1691 1699
1692 radeon_encoder->enc_priv = NULL; 1700 radeon_encoder->enc_priv = NULL;
1693 1701
1694 radeon_encoder->encoder_id = encoder_id; 1702 radeon_encoder->encoder_enum = encoder_enum;
1703 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1695 radeon_encoder->devices = supported_device; 1704 radeon_encoder->devices = supported_device;
1696 radeon_encoder->rmx_type = RMX_OFF; 1705 radeon_encoder->rmx_type = RMX_OFF;
1697 radeon_encoder->underscan_type = UNDERSCAN_OFF; 1706 radeon_encoder->underscan_type = UNDERSCAN_OFF;
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index dbf86962bdd1..40b0c087b592 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -94,6 +94,7 @@ static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
94 ret = radeon_bo_reserve(rbo, false); 94 ret = radeon_bo_reserve(rbo, false);
95 if (likely(ret == 0)) { 95 if (likely(ret == 0)) {
96 radeon_bo_kunmap(rbo); 96 radeon_bo_kunmap(rbo);
97 radeon_bo_unpin(rbo);
97 radeon_bo_unreserve(rbo); 98 radeon_bo_unreserve(rbo);
98 } 99 }
99 drm_gem_object_unreference_unlocked(gobj); 100 drm_gem_object_unreference_unlocked(gobj);
@@ -118,7 +119,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
118 aligned_size = ALIGN(size, PAGE_SIZE); 119 aligned_size = ALIGN(size, PAGE_SIZE);
119 ret = radeon_gem_object_create(rdev, aligned_size, 0, 120 ret = radeon_gem_object_create(rdev, aligned_size, 0,
120 RADEON_GEM_DOMAIN_VRAM, 121 RADEON_GEM_DOMAIN_VRAM,
121 false, ttm_bo_type_kernel, 122 false, true,
122 &gobj); 123 &gobj);
123 if (ret) { 124 if (ret) {
124 printk(KERN_ERR "failed to allocate framebuffer (%d)\n", 125 printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
@@ -325,8 +326,6 @@ static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfb
325{ 326{
326 struct fb_info *info; 327 struct fb_info *info;
327 struct radeon_framebuffer *rfb = &rfbdev->rfb; 328 struct radeon_framebuffer *rfb = &rfbdev->rfb;
328 struct radeon_bo *rbo;
329 int r;
330 329
331 if (rfbdev->helper.fbdev) { 330 if (rfbdev->helper.fbdev) {
332 info = rfbdev->helper.fbdev; 331 info = rfbdev->helper.fbdev;
@@ -338,14 +337,8 @@ static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfb
338 } 337 }
339 338
340 if (rfb->obj) { 339 if (rfb->obj) {
341 rbo = rfb->obj->driver_private; 340 radeonfb_destroy_pinned_object(rfb->obj);
342 r = radeon_bo_reserve(rbo, false); 341 rfb->obj = NULL;
343 if (likely(r == 0)) {
344 radeon_bo_kunmap(rbo);
345 radeon_bo_unpin(rbo);
346 radeon_bo_unreserve(rbo);
347 }
348 drm_gem_object_unreference_unlocked(rfb->obj);
349 } 342 }
350 drm_fb_helper_fini(&rfbdev->helper); 343 drm_fb_helper_fini(&rfbdev->helper);
351 drm_framebuffer_cleanup(&rfb->base); 344 drm_framebuffer_cleanup(&rfb->base);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index c578f265b24c..d1e595d91723 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -201,11 +201,11 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
201 return r; 201 return r;
202 } 202 }
203 r = drm_gem_handle_create(filp, gobj, &handle); 203 r = drm_gem_handle_create(filp, gobj, &handle);
204 /* drop reference from allocate - handle holds it now */
205 drm_gem_object_unreference_unlocked(gobj);
204 if (r) { 206 if (r) {
205 drm_gem_object_unreference_unlocked(gobj);
206 return r; 207 return r;
207 } 208 }
208 drm_gem_object_handle_unreference_unlocked(gobj);
209 args->handle = handle; 209 args->handle = handle;
210 return 0; 210 return 0;
211} 211}
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index bfd2ce5f5372..6a13ee38a5b9 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -99,6 +99,13 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
99 } 99 }
100 } 100 }
101 101
102 /* switch the pads to ddc mode */
103 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
104 temp = RREG32(rec->mask_clk_reg);
105 temp &= ~(1 << 16);
106 WREG32(rec->mask_clk_reg, temp);
107 }
108
102 /* clear the output pin values */ 109 /* clear the output pin values */
103 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 110 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
104 WREG32(rec->a_clk_reg, temp); 111 WREG32(rec->a_clk_reg, temp);
@@ -206,7 +213,7 @@ static void post_xfer(struct i2c_adapter *i2c_adap)
206 213
207static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 214static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
208{ 215{
209 u32 sclk = radeon_get_engine_clock(rdev); 216 u32 sclk = rdev->pm.current_sclk;
210 u32 prescale = 0; 217 u32 prescale = 0;
211 u32 nm; 218 u32 nm;
212 u8 n, m, loop; 219 u8 n, m, loop;
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 059bfa4098d7..a108c7ed14f5 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -121,11 +121,12 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
121 * chips. Disable MSI on them for now. 121 * chips. Disable MSI on them for now.
122 */ 122 */
123 if ((rdev->family >= CHIP_RV380) && 123 if ((rdev->family >= CHIP_RV380) &&
124 (!(rdev->flags & RADEON_IS_IGP))) { 124 (!(rdev->flags & RADEON_IS_IGP)) &&
125 (!(rdev->flags & RADEON_IS_AGP))) {
125 int ret = pci_enable_msi(rdev->pdev); 126 int ret = pci_enable_msi(rdev->pdev);
126 if (!ret) { 127 if (!ret) {
127 rdev->msi_enabled = 1; 128 rdev->msi_enabled = 1;
128 DRM_INFO("radeon: using MSI.\n"); 129 dev_info(rdev->dev, "radeon: using MSI.\n");
129 } 130 }
130 } 131 }
131 rdev->irq.installed = true; 132 rdev->irq.installed = true;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index b1c8ace5f080..8fbbe1c6ebbd 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -161,6 +161,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
161 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 161 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
162 return -EINVAL; 162 return -EINVAL;
163 } 163 }
164 break;
164 case RADEON_INFO_WANT_HYPERZ: 165 case RADEON_INFO_WANT_HYPERZ:
165 /* The "value" here is both an input and output parameter. 166 /* The "value" here is both an input and output parameter.
166 * If the input value is 1, filp requests hyper-z access. 167 * If the input value is 1, filp requests hyper-z access.
@@ -202,6 +203,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
202 */ 203 */
203int radeon_driver_firstopen_kms(struct drm_device *dev) 204int radeon_driver_firstopen_kms(struct drm_device *dev)
204{ 205{
206 struct radeon_device *rdev = dev->dev_private;
207
208 if (rdev->powered_down)
209 return -EINVAL;
205 return 0; 210 return 0;
206} 211}
207 212
@@ -323,45 +328,45 @@ KMS_INVALID_IOCTL(radeon_surface_free_kms)
323 328
324 329
325struct drm_ioctl_desc radeon_ioctls_kms[] = { 330struct drm_ioctl_desc radeon_ioctls_kms[] = {
326 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 331 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
327 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 332 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
328 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 333 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
329 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 334 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
330 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 335 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
331 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 336 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
332 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 337 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
333 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 338 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
334 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 339 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
335 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 340 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
336 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 341 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
337 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 342 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
338 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 343 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
339 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 344 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
340 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 345 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
341 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 346 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
342 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 347 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
343 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 348 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
344 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 349 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
345 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 350 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
346 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 351 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
347 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 352 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
348 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 353 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
349 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 354 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
350 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 355 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
351 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 356 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
352 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 357 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
353 /* KMS */ 358 /* KMS */
354 DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 359 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
355 DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), 360 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
356 DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), 361 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
357 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), 362 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
358 DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 363 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
359 DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 364 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
360 DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), 365 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
361 DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), 366 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
362 DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 367 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
363 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 368 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
364 DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 369 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
365 DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 370 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
366}; 371};
367int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 372int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 989df519a1e4..305049afde15 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -272,7 +272,7 @@ static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
272 if (!ref_div) 272 if (!ref_div)
273 return 1; 273 return 1;
274 274
275 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; 275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276 276
277 /* 277 /*
278 * This is horribly crude: the VCO frequency range is divided into 278 * This is horribly crude: the VCO frequency range is divided into
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index b8149cbc0c70..0b8397000f4c 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -1345,7 +1345,7 @@ static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct ra
1345} 1345}
1346 1346
1347void 1347void
1348radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1348radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1349{ 1349{
1350 struct radeon_device *rdev = dev->dev_private; 1350 struct radeon_device *rdev = dev->dev_private;
1351 struct drm_encoder *encoder; 1351 struct drm_encoder *encoder;
@@ -1354,7 +1354,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
1354 /* see if we already added it */ 1354 /* see if we already added it */
1355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1356 radeon_encoder = to_radeon_encoder(encoder); 1356 radeon_encoder = to_radeon_encoder(encoder);
1357 if (radeon_encoder->encoder_id == encoder_id) { 1357 if (radeon_encoder->encoder_enum == encoder_enum) {
1358 radeon_encoder->devices |= supported_device; 1358 radeon_encoder->devices |= supported_device;
1359 return; 1359 return;
1360 } 1360 }
@@ -1374,7 +1374,8 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
1374 1374
1375 radeon_encoder->enc_priv = NULL; 1375 radeon_encoder->enc_priv = NULL;
1376 1376
1377 radeon_encoder->encoder_id = encoder_id; 1377 radeon_encoder->encoder_enum = encoder_enum;
1378 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1378 radeon_encoder->devices = supported_device; 1379 radeon_encoder->devices = supported_device;
1379 radeon_encoder->rmx_type = RMX_OFF; 1380 radeon_encoder->rmx_type = RMX_OFF;
1380 1381
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 5bbc086b9267..17a6602b5885 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -204,7 +204,7 @@ struct radeon_i2c_chan {
204 204
205/* mostly for macs, but really any system without connector tables */ 205/* mostly for macs, but really any system without connector tables */
206enum radeon_connector_table { 206enum radeon_connector_table {
207 CT_NONE, 207 CT_NONE = 0,
208 CT_GENERIC, 208 CT_GENERIC,
209 CT_IBOOK, 209 CT_IBOOK,
210 CT_POWERBOOK_EXTERNAL, 210 CT_POWERBOOK_EXTERNAL,
@@ -215,6 +215,7 @@ enum radeon_connector_table {
215 CT_IMAC_G5_ISIGHT, 215 CT_IMAC_G5_ISIGHT,
216 CT_EMAC, 216 CT_EMAC,
217 CT_RN50_POWER, 217 CT_RN50_POWER,
218 CT_MAC_X800,
218}; 219};
219 220
220enum radeon_dvo_chip { 221enum radeon_dvo_chip {
@@ -342,6 +343,7 @@ struct radeon_atom_ss {
342}; 343};
343 344
344struct radeon_encoder_atom_dig { 345struct radeon_encoder_atom_dig {
346 bool linkb;
345 /* atom dig */ 347 /* atom dig */
346 bool coherent_mode; 348 bool coherent_mode;
347 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ 349 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
@@ -360,6 +362,7 @@ struct radeon_encoder_atom_dac {
360 362
361struct radeon_encoder { 363struct radeon_encoder {
362 struct drm_encoder base; 364 struct drm_encoder base;
365 uint32_t encoder_enum;
363 uint32_t encoder_id; 366 uint32_t encoder_id;
364 uint32_t devices; 367 uint32_t devices;
365 uint32_t active_device; 368 uint32_t active_device;
@@ -378,7 +381,6 @@ struct radeon_encoder {
378 381
379struct radeon_connector_atom_dig { 382struct radeon_connector_atom_dig {
380 uint32_t igp_lane_info; 383 uint32_t igp_lane_info;
381 bool linkb;
382 /* displayport */ 384 /* displayport */
383 struct radeon_i2c_chan *dp_i2c_bus; 385 struct radeon_i2c_chan *dp_i2c_bus;
384 u8 dpcd[8]; 386 u8 dpcd[8];
@@ -599,7 +601,6 @@ extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct d
599void radeon_enc_destroy(struct drm_encoder *encoder); 601void radeon_enc_destroy(struct drm_encoder *encoder);
600void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 602void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
601void radeon_combios_asic_init(struct drm_device *dev); 603void radeon_combios_asic_init(struct drm_device *dev);
602extern int radeon_static_clocks_init(struct drm_device *dev);
603bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 604bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
604 struct drm_display_mode *mode, 605 struct drm_display_mode *mode,
605 struct drm_display_mode *adjusted_mode); 606 struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 0afd1e62347d..b3b5306bb578 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -69,7 +69,7 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
69 u32 c = 0; 69 u32 c = 0;
70 70
71 rbo->placement.fpfn = 0; 71 rbo->placement.fpfn = 0;
72 rbo->placement.lpfn = 0; 72 rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT;
73 rbo->placement.placement = rbo->placements; 73 rbo->placement.placement = rbo->placements;
74 rbo->placement.busy_placement = rbo->placements; 74 rbo->placement.busy_placement = rbo->placements;
75 if (domain & RADEON_GEM_DOMAIN_VRAM) 75 if (domain & RADEON_GEM_DOMAIN_VRAM)
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 353998dc2c03..3481bc7f6f58 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -124,11 +124,8 @@ static inline int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
124 int r; 124 int r;
125 125
126 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 126 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
127 if (unlikely(r != 0)) { 127 if (unlikely(r != 0))
128 if (r != -ERESTARTSYS)
129 dev_err(bo->rdev->dev, "%p reserve failed for wait\n", bo);
130 return r; 128 return r;
131 }
132 spin_lock(&bo->tbo.lock); 129 spin_lock(&bo->tbo.lock);
133 if (mem_type) 130 if (mem_type)
134 *mem_type = bo->tbo.mem.mem_type; 131 *mem_type = bo->tbo.mem.mem_type;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 58038f5cab38..f87efec76236 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -226,6 +226,11 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
226{ 226{
227 int i; 227 int i;
228 228
229 /* no need to take locks, etc. if nothing's going to change */
230 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
231 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
232 return;
233
229 mutex_lock(&rdev->ddev->struct_mutex); 234 mutex_lock(&rdev->ddev->struct_mutex);
230 mutex_lock(&rdev->vram_mutex); 235 mutex_lock(&rdev->vram_mutex);
231 mutex_lock(&rdev->cp.mutex); 236 mutex_lock(&rdev->cp.mutex);
@@ -632,8 +637,6 @@ void radeon_pm_fini(struct radeon_device *rdev)
632 } 637 }
633 638
634 radeon_hwmon_fini(rdev); 639 radeon_hwmon_fini(rdev);
635 if (rdev->pm.i2c_bus)
636 radeon_i2c_destroy(rdev->pm.i2c_bus);
637} 640}
638 641
639void radeon_pm_compute_clocks(struct radeon_device *rdev) 642void radeon_pm_compute_clocks(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index b3ba44c0a818..4ae5a3d1074e 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -3228,34 +3228,34 @@ void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
3228} 3228}
3229 3229
3230struct drm_ioctl_desc radeon_ioctls[] = { 3230struct drm_ioctl_desc radeon_ioctls[] = {
3231 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3231 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3232 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3232 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3233 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3233 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3234 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3234 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3235 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH), 3235 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
3236 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH), 3236 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
3237 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH), 3237 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
3238 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH), 3238 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
3239 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH), 3239 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
3240 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH), 3240 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
3241 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH), 3241 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
3242 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH), 3242 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
3243 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH), 3243 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
3244 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH), 3244 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
3245 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3245 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3246 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH), 3246 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
3247 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH), 3247 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
3248 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH), 3248 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
3249 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH), 3249 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
3250 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH), 3250 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
3251 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH), 3251 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
3252 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 3252 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3253 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH), 3253 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
3254 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), 3254 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3255 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), 3255 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3256 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), 3256 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3257 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH), 3257 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3258 DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH) 3258 DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
3259}; 3259};
3260 3260
3261int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); 3261int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index cc05b230d7ef..51d5f7b5ab21 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -693,6 +693,7 @@ void rs600_mc_init(struct radeon_device *rdev)
693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
694 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 694 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
695 rdev->mc.visible_vram_size = rdev->mc.aper_size; 695 rdev->mc.visible_vram_size = rdev->mc.aper_size;
696 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
696 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 697 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
697 base = RREG32_MC(R_000004_MC_FB_LOCATION); 698 base = RREG32_MC(R_000004_MC_FB_LOCATION);
698 base = G_000004_MC_FB_START(base) << 16; 699 base = G_000004_MC_FB_START(base) << 16;
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3e3f75718be3..4dc2a87ea680 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -157,6 +157,7 @@ void rs690_mc_init(struct radeon_device *rdev)
157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 161 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 162 base = G_000100_MC_FB_START(base) << 16;
162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index f1c796810117..9490da700749 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -267,6 +267,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
267 */ 267 */
268void r700_cp_stop(struct radeon_device *rdev) 268void r700_cp_stop(struct radeon_device *rdev)
269{ 269{
270 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
270 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
271} 272}
272 273
@@ -905,6 +906,54 @@ static void rv770_gpu_init(struct radeon_device *rdev)
905 906
906} 907}
907 908
909static int rv770_vram_scratch_init(struct radeon_device *rdev)
910{
911 int r;
912 u64 gpu_addr;
913
914 if (rdev->vram_scratch.robj == NULL) {
915 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
916 true, RADEON_GEM_DOMAIN_VRAM,
917 &rdev->vram_scratch.robj);
918 if (r) {
919 return r;
920 }
921 }
922
923 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
924 if (unlikely(r != 0))
925 return r;
926 r = radeon_bo_pin(rdev->vram_scratch.robj,
927 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
928 if (r) {
929 radeon_bo_unreserve(rdev->vram_scratch.robj);
930 return r;
931 }
932 r = radeon_bo_kmap(rdev->vram_scratch.robj,
933 (void **)&rdev->vram_scratch.ptr);
934 if (r)
935 radeon_bo_unpin(rdev->vram_scratch.robj);
936 radeon_bo_unreserve(rdev->vram_scratch.robj);
937
938 return r;
939}
940
941static void rv770_vram_scratch_fini(struct radeon_device *rdev)
942{
943 int r;
944
945 if (rdev->vram_scratch.robj == NULL) {
946 return;
947 }
948 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
949 if (likely(r == 0)) {
950 radeon_bo_kunmap(rdev->vram_scratch.robj);
951 radeon_bo_unpin(rdev->vram_scratch.robj);
952 radeon_bo_unreserve(rdev->vram_scratch.robj);
953 }
954 radeon_bo_unref(&rdev->vram_scratch.robj);
955}
956
908int rv770_mc_init(struct radeon_device *rdev) 957int rv770_mc_init(struct radeon_device *rdev)
909{ 958{
910 u32 tmp; 959 u32 tmp;
@@ -944,6 +993,7 @@ int rv770_mc_init(struct radeon_device *rdev)
944 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 993 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
945 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 994 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
946 rdev->mc.visible_vram_size = rdev->mc.aper_size; 995 rdev->mc.visible_vram_size = rdev->mc.aper_size;
996 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
947 r600_vram_gtt_location(rdev, &rdev->mc); 997 r600_vram_gtt_location(rdev, &rdev->mc);
948 radeon_update_bandwidth_info(rdev); 998 radeon_update_bandwidth_info(rdev);
949 999
@@ -970,6 +1020,9 @@ static int rv770_startup(struct radeon_device *rdev)
970 if (r) 1020 if (r)
971 return r; 1021 return r;
972 } 1022 }
1023 r = rv770_vram_scratch_init(rdev);
1024 if (r)
1025 return r;
973 rv770_gpu_init(rdev); 1026 rv770_gpu_init(rdev);
974 r = r600_blit_init(rdev); 1027 r = r600_blit_init(rdev);
975 if (r) { 1028 if (r) {
@@ -1023,11 +1076,6 @@ int rv770_resume(struct radeon_device *rdev)
1023 */ 1076 */
1024 /* post card */ 1077 /* post card */
1025 atom_asic_init(rdev->mode_info.atom_context); 1078 atom_asic_init(rdev->mode_info.atom_context);
1026 /* Initialize clocks */
1027 r = radeon_clocks_init(rdev);
1028 if (r) {
1029 return r;
1030 }
1031 1079
1032 r = rv770_startup(rdev); 1080 r = rv770_startup(rdev);
1033 if (r) { 1081 if (r) {
@@ -1118,9 +1166,6 @@ int rv770_init(struct radeon_device *rdev)
1118 radeon_surface_init(rdev); 1166 radeon_surface_init(rdev);
1119 /* Initialize clocks */ 1167 /* Initialize clocks */
1120 radeon_get_clock_info(rdev->ddev); 1168 radeon_get_clock_info(rdev->ddev);
1121 r = radeon_clocks_init(rdev);
1122 if (r)
1123 return r;
1124 /* Fence driver */ 1169 /* Fence driver */
1125 r = radeon_fence_driver_init(rdev); 1170 r = radeon_fence_driver_init(rdev);
1126 if (r) 1171 if (r)
@@ -1195,9 +1240,9 @@ void rv770_fini(struct radeon_device *rdev)
1195 r600_irq_fini(rdev); 1240 r600_irq_fini(rdev);
1196 radeon_irq_kms_fini(rdev); 1241 radeon_irq_kms_fini(rdev);
1197 rv770_pcie_gart_fini(rdev); 1242 rv770_pcie_gart_fini(rdev);
1243 rv770_vram_scratch_fini(rdev);
1198 radeon_gem_fini(rdev); 1244 radeon_gem_fini(rdev);
1199 radeon_fence_driver_fini(rdev); 1245 radeon_fence_driver_fini(rdev);
1200 radeon_clocks_fini(rdev);
1201 radeon_agp_fini(rdev); 1246 radeon_agp_fini(rdev);
1202 radeon_bo_fini(rdev); 1247 radeon_bo_fini(rdev);
1203 radeon_atombios_fini(rdev); 1248 radeon_atombios_fini(rdev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 20:05:58 -0500