diff options
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 28 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r100_track.h | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 20 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_clocks.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_combios.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_connectors.c | 71 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_cs.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 123 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_fence.c | 51 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 3 |
18 files changed, 286 insertions, 95 deletions
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index 49611e2365d9..1b50ad8919d5 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h | |||
@@ -1200,6 +1200,7 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 | |||
1200 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 | 1200 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 |
1201 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 | 1201 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 |
1202 | #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 | 1202 | #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 |
1203 | #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 | ||
1203 | 1204 | ||
1204 | // ucConfig | 1205 | // ucConfig |
1205 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 | 1206 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 |
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 84a69e7fa11e..9541995e4b21 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -671,6 +671,13 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
671 | DISPPLL_CONFIG_DUAL_LINK; | 671 | DISPPLL_CONFIG_DUAL_LINK; |
672 | } | 672 | } |
673 | } | 673 | } |
674 | if (radeon_encoder_is_dp_bridge(encoder)) { | ||
675 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); | ||
676 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); | ||
677 | args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id; | ||
678 | } else | ||
679 | args.v3.sInput.ucExtTransmitterID = 0; | ||
680 | |||
674 | atom_execute_table(rdev->mode_info.atom_context, | 681 | atom_execute_table(rdev->mode_info.atom_context, |
675 | index, (uint32_t *)&args); | 682 | index, (uint32_t *)&args); |
676 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; | 683 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 98ea597bc76d..445af7981637 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -88,7 +88,8 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) | |||
88 | /* get temperature in millidegrees */ | 88 | /* get temperature in millidegrees */ |
89 | int evergreen_get_temp(struct radeon_device *rdev) | 89 | int evergreen_get_temp(struct radeon_device *rdev) |
90 | { | 90 | { |
91 | u32 temp, toffset, actual_temp = 0; | 91 | u32 temp, toffset; |
92 | int actual_temp = 0; | ||
92 | 93 | ||
93 | if (rdev->family == CHIP_JUNIPER) { | 94 | if (rdev->family == CHIP_JUNIPER) { |
94 | toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> | 95 | toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> |
@@ -139,11 +140,17 @@ void evergreen_pm_misc(struct radeon_device *rdev) | |||
139 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | 140 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
140 | 141 | ||
141 | if (voltage->type == VOLTAGE_SW) { | 142 | if (voltage->type == VOLTAGE_SW) { |
143 | /* 0xff01 is a flag rather then an actual voltage */ | ||
144 | if (voltage->voltage == 0xff01) | ||
145 | return; | ||
142 | if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { | 146 | if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { |
143 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); | 147 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
144 | rdev->pm.current_vddc = voltage->voltage; | 148 | rdev->pm.current_vddc = voltage->voltage; |
145 | DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); | 149 | DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); |
146 | } | 150 | } |
151 | /* 0xff01 is a flag rather then an actual voltage */ | ||
152 | if (voltage->vddci == 0xff01) | ||
153 | return; | ||
147 | if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { | 154 | if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { |
148 | radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); | 155 | radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); |
149 | rdev->pm.current_vddci = voltage->vddci; | 156 | rdev->pm.current_vddci = voltage->vddci; |
@@ -2694,28 +2701,25 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev) | |||
2694 | 2701 | ||
2695 | int evergreen_irq_process(struct radeon_device *rdev) | 2702 | int evergreen_irq_process(struct radeon_device *rdev) |
2696 | { | 2703 | { |
2697 | u32 wptr = evergreen_get_ih_wptr(rdev); | 2704 | u32 wptr; |
2698 | u32 rptr = rdev->ih.rptr; | 2705 | u32 rptr; |
2699 | u32 src_id, src_data; | 2706 | u32 src_id, src_data; |
2700 | u32 ring_index; | 2707 | u32 ring_index; |
2701 | unsigned long flags; | 2708 | unsigned long flags; |
2702 | bool queue_hotplug = false; | 2709 | bool queue_hotplug = false; |
2703 | 2710 | ||
2704 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | 2711 | if (!rdev->ih.enabled || rdev->shutdown) |
2705 | if (!rdev->ih.enabled) | ||
2706 | return IRQ_NONE; | 2712 | return IRQ_NONE; |
2707 | 2713 | ||
2708 | spin_lock_irqsave(&rdev->ih.lock, flags); | 2714 | wptr = evergreen_get_ih_wptr(rdev); |
2715 | rptr = rdev->ih.rptr; | ||
2716 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | ||
2709 | 2717 | ||
2718 | spin_lock_irqsave(&rdev->ih.lock, flags); | ||
2710 | if (rptr == wptr) { | 2719 | if (rptr == wptr) { |
2711 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | 2720 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
2712 | return IRQ_NONE; | 2721 | return IRQ_NONE; |
2713 | } | 2722 | } |
2714 | if (rdev->shutdown) { | ||
2715 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | ||
2716 | return IRQ_NONE; | ||
2717 | } | ||
2718 | |||
2719 | restart_ih: | 2723 | restart_ih: |
2720 | /* display interrupts */ | 2724 | /* display interrupts */ |
2721 | evergreen_irq_ack(rdev); | 2725 | evergreen_irq_ack(rdev); |
@@ -2944,7 +2948,7 @@ restart_ih: | |||
2944 | radeon_fence_process(rdev); | 2948 | radeon_fence_process(rdev); |
2945 | break; | 2949 | break; |
2946 | case 233: /* GUI IDLE */ | 2950 | case 233: /* GUI IDLE */ |
2947 | DRM_DEBUG("IH: CP EOP\n"); | 2951 | DRM_DEBUG("IH: GUI idle\n"); |
2948 | rdev->pm.gui_idle = true; | 2952 | rdev->pm.gui_idle = true; |
2949 | wake_up(&rdev->irq.idle_queue); | 2953 | wake_up(&rdev->irq.idle_queue); |
2950 | break; | 2954 | break; |
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h index 2fef9de7f363..686f9dc5d4bd 100644 --- a/drivers/gpu/drm/radeon/r100_track.h +++ b/drivers/gpu/drm/radeon/r100_track.h | |||
@@ -63,7 +63,7 @@ struct r100_cs_track { | |||
63 | unsigned num_arrays; | 63 | unsigned num_arrays; |
64 | unsigned max_indx; | 64 | unsigned max_indx; |
65 | unsigned color_channel_mask; | 65 | unsigned color_channel_mask; |
66 | struct r100_cs_track_array arrays[11]; | 66 | struct r100_cs_track_array arrays[16]; |
67 | struct r100_cs_track_cb cb[R300_MAX_CB]; | 67 | struct r100_cs_track_cb cb[R300_MAX_CB]; |
68 | struct r100_cs_track_cb zb; | 68 | struct r100_cs_track_cb zb; |
69 | struct r100_cs_track_cb aa; | 69 | struct r100_cs_track_cb aa; |
@@ -146,6 +146,12 @@ static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | |||
146 | ib = p->ib->ptr; | 146 | ib = p->ib->ptr; |
147 | track = (struct r100_cs_track *)p->track; | 147 | track = (struct r100_cs_track *)p->track; |
148 | c = radeon_get_ib_value(p, idx++) & 0x1F; | 148 | c = radeon_get_ib_value(p, idx++) & 0x1F; |
149 | if (c > 16) { | ||
150 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", | ||
151 | pkt->opcode); | ||
152 | r100_cs_dump_packet(p, pkt); | ||
153 | return -EINVAL; | ||
154 | } | ||
149 | track->num_arrays = c; | 155 | track->num_arrays = c; |
150 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | 156 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
151 | r = r100_cs_packet_next_reloc(p, &reloc); | 157 | r = r100_cs_packet_next_reloc(p, &reloc); |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index d74d4d71437f..f79d2ccb6755 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -590,6 +590,9 @@ void r600_pm_misc(struct radeon_device *rdev) | |||
590 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | 590 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
591 | 591 | ||
592 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { | 592 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
593 | /* 0xff01 is a flag rather then an actual voltage */ | ||
594 | if (voltage->voltage == 0xff01) | ||
595 | return; | ||
593 | if (voltage->voltage != rdev->pm.current_vddc) { | 596 | if (voltage->voltage != rdev->pm.current_vddc) { |
594 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); | 597 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
595 | rdev->pm.current_vddc = voltage->voltage; | 598 | rdev->pm.current_vddc = voltage->voltage; |
@@ -3294,27 +3297,26 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) | |||
3294 | 3297 | ||
3295 | int r600_irq_process(struct radeon_device *rdev) | 3298 | int r600_irq_process(struct radeon_device *rdev) |
3296 | { | 3299 | { |
3297 | u32 wptr = r600_get_ih_wptr(rdev); | 3300 | u32 wptr; |
3298 | u32 rptr = rdev->ih.rptr; | 3301 | u32 rptr; |
3299 | u32 src_id, src_data; | 3302 | u32 src_id, src_data; |
3300 | u32 ring_index; | 3303 | u32 ring_index; |
3301 | unsigned long flags; | 3304 | unsigned long flags; |
3302 | bool queue_hotplug = false; | 3305 | bool queue_hotplug = false; |
3303 | 3306 | ||
3304 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | 3307 | if (!rdev->ih.enabled || rdev->shutdown) |
3305 | if (!rdev->ih.enabled) | ||
3306 | return IRQ_NONE; | 3308 | return IRQ_NONE; |
3307 | 3309 | ||
3310 | wptr = r600_get_ih_wptr(rdev); | ||
3311 | rptr = rdev->ih.rptr; | ||
3312 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | ||
3313 | |||
3308 | spin_lock_irqsave(&rdev->ih.lock, flags); | 3314 | spin_lock_irqsave(&rdev->ih.lock, flags); |
3309 | 3315 | ||
3310 | if (rptr == wptr) { | 3316 | if (rptr == wptr) { |
3311 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | 3317 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
3312 | return IRQ_NONE; | 3318 | return IRQ_NONE; |
3313 | } | 3319 | } |
3314 | if (rdev->shutdown) { | ||
3315 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | ||
3316 | return IRQ_NONE; | ||
3317 | } | ||
3318 | 3320 | ||
3319 | restart_ih: | 3321 | restart_ih: |
3320 | /* display interrupts */ | 3322 | /* display interrupts */ |
@@ -3444,7 +3446,7 @@ restart_ih: | |||
3444 | radeon_fence_process(rdev); | 3446 | radeon_fence_process(rdev); |
3445 | break; | 3447 | break; |
3446 | case 233: /* GUI IDLE */ | 3448 | case 233: /* GUI IDLE */ |
3447 | DRM_DEBUG("IH: CP EOP\n"); | 3449 | DRM_DEBUG("IH: GUI idle\n"); |
3448 | rdev->pm.gui_idle = true; | 3450 | rdev->pm.gui_idle = true; |
3449 | wake_up(&rdev->irq.idle_queue); | 3451 | wake_up(&rdev->irq.idle_queue); |
3450 | break; | 3452 | break; |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index ba643b576054..27f45579e64b 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -165,6 +165,7 @@ struct radeon_clock { | |||
165 | uint32_t default_sclk; | 165 | uint32_t default_sclk; |
166 | uint32_t default_dispclk; | 166 | uint32_t default_dispclk; |
167 | uint32_t dp_extclk; | 167 | uint32_t dp_extclk; |
168 | uint32_t max_pixel_clock; | ||
168 | }; | 169 | }; |
169 | 170 | ||
170 | /* | 171 | /* |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 9bd162fc9b0c..b2449629537d 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -938,6 +938,13 @@ static struct radeon_asic cayman_asic = { | |||
938 | int radeon_asic_init(struct radeon_device *rdev) | 938 | int radeon_asic_init(struct radeon_device *rdev) |
939 | { | 939 | { |
940 | radeon_register_accessor_init(rdev); | 940 | radeon_register_accessor_init(rdev); |
941 | |||
942 | /* set the number of crtcs */ | ||
943 | if (rdev->flags & RADEON_SINGLE_CRTC) | ||
944 | rdev->num_crtc = 1; | ||
945 | else | ||
946 | rdev->num_crtc = 2; | ||
947 | |||
941 | switch (rdev->family) { | 948 | switch (rdev->family) { |
942 | case CHIP_R100: | 949 | case CHIP_R100: |
943 | case CHIP_RV100: | 950 | case CHIP_RV100: |
@@ -1017,6 +1024,11 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
1017 | case CHIP_JUNIPER: | 1024 | case CHIP_JUNIPER: |
1018 | case CHIP_CYPRESS: | 1025 | case CHIP_CYPRESS: |
1019 | case CHIP_HEMLOCK: | 1026 | case CHIP_HEMLOCK: |
1027 | /* set num crtcs */ | ||
1028 | if (rdev->family == CHIP_CEDAR) | ||
1029 | rdev->num_crtc = 4; | ||
1030 | else | ||
1031 | rdev->num_crtc = 6; | ||
1020 | rdev->asic = &evergreen_asic; | 1032 | rdev->asic = &evergreen_asic; |
1021 | break; | 1033 | break; |
1022 | case CHIP_PALM: | 1034 | case CHIP_PALM: |
@@ -1027,10 +1039,17 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
1027 | case CHIP_BARTS: | 1039 | case CHIP_BARTS: |
1028 | case CHIP_TURKS: | 1040 | case CHIP_TURKS: |
1029 | case CHIP_CAICOS: | 1041 | case CHIP_CAICOS: |
1042 | /* set num crtcs */ | ||
1043 | if (rdev->family == CHIP_CAICOS) | ||
1044 | rdev->num_crtc = 4; | ||
1045 | else | ||
1046 | rdev->num_crtc = 6; | ||
1030 | rdev->asic = &btc_asic; | 1047 | rdev->asic = &btc_asic; |
1031 | break; | 1048 | break; |
1032 | case CHIP_CAYMAN: | 1049 | case CHIP_CAYMAN: |
1033 | rdev->asic = &cayman_asic; | 1050 | rdev->asic = &cayman_asic; |
1051 | /* set num crtcs */ | ||
1052 | rdev->num_crtc = 6; | ||
1034 | break; | 1053 | break; |
1035 | default: | 1054 | default: |
1036 | /* FIXME: not supported yet */ | 1055 | /* FIXME: not supported yet */ |
@@ -1042,18 +1061,6 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
1042 | rdev->asic->set_memory_clock = NULL; | 1061 | rdev->asic->set_memory_clock = NULL; |
1043 | } | 1062 | } |
1044 | 1063 | ||
1045 | /* set the number of crtcs */ | ||
1046 | if (rdev->flags & RADEON_SINGLE_CRTC) | ||
1047 | rdev->num_crtc = 1; | ||
1048 | else { | ||
1049 | if (ASIC_IS_DCE41(rdev)) | ||
1050 | rdev->num_crtc = 2; | ||
1051 | else if (ASIC_IS_DCE4(rdev)) | ||
1052 | rdev->num_crtc = 6; | ||
1053 | else | ||
1054 | rdev->num_crtc = 2; | ||
1055 | } | ||
1056 | |||
1057 | return 0; | 1064 | return 0; |
1058 | } | 1065 | } |
1059 | 1066 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 90dfb2b8cf03..1e725d9f767f 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -1246,6 +1246,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) | |||
1246 | } | 1246 | } |
1247 | *dcpll = *p1pll; | 1247 | *dcpll = *p1pll; |
1248 | 1248 | ||
1249 | rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); | ||
1250 | if (rdev->clock.max_pixel_clock == 0) | ||
1251 | rdev->clock.max_pixel_clock = 40000; | ||
1252 | |||
1249 | return true; | 1253 | return true; |
1250 | } | 1254 | } |
1251 | 1255 | ||
@@ -2603,6 +2607,10 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v | |||
2603 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | 2607 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
2604 | return; | 2608 | return; |
2605 | 2609 | ||
2610 | /* 0xff01 is a flag rather then an actual voltage */ | ||
2611 | if (voltage_level == 0xff01) | ||
2612 | return; | ||
2613 | |||
2606 | switch (crev) { | 2614 | switch (crev) { |
2607 | case 1: | 2615 | case 1: |
2608 | args.v1.ucVoltageType = voltage_type; | 2616 | args.v1.ucVoltageType = voltage_type; |
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c index 5249af8931e6..2d48e7a1474b 100644 --- a/drivers/gpu/drm/radeon/radeon_clocks.c +++ b/drivers/gpu/drm/radeon/radeon_clocks.c | |||
@@ -117,7 +117,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev) | |||
117 | p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; | 117 | p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
118 | if (p1pll->reference_div < 2) | 118 | if (p1pll->reference_div < 2) |
119 | p1pll->reference_div = 12; | 119 | p1pll->reference_div = 12; |
120 | p2pll->reference_div = p1pll->reference_div; | 120 | p2pll->reference_div = p1pll->reference_div; |
121 | 121 | ||
122 | /* These aren't in the device-tree */ | 122 | /* These aren't in the device-tree */ |
123 | if (rdev->family >= CHIP_R420) { | 123 | if (rdev->family >= CHIP_R420) { |
@@ -139,6 +139,8 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev) | |||
139 | p2pll->pll_out_min = 12500; | 139 | p2pll->pll_out_min = 12500; |
140 | p2pll->pll_out_max = 35000; | 140 | p2pll->pll_out_max = 35000; |
141 | } | 141 | } |
142 | /* not sure what the max should be in all cases */ | ||
143 | rdev->clock.max_pixel_clock = 35000; | ||
142 | 144 | ||
143 | spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; | 145 | spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; |
144 | spll->reference_div = mpll->reference_div = | 146 | spll->reference_div = mpll->reference_div = |
@@ -151,7 +153,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev) | |||
151 | else | 153 | else |
152 | rdev->clock.default_sclk = | 154 | rdev->clock.default_sclk = |
153 | radeon_legacy_get_engine_clock(rdev); | 155 | radeon_legacy_get_engine_clock(rdev); |
154 | 156 | ||
155 | val = of_get_property(dp, "ATY,MCLK", NULL); | 157 | val = of_get_property(dp, "ATY,MCLK", NULL); |
156 | if (val && *val) | 158 | if (val && *val) |
157 | rdev->clock.default_mclk = (*val) / 10; | 159 | rdev->clock.default_mclk = (*val) / 10; |
@@ -160,7 +162,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev) | |||
160 | radeon_legacy_get_memory_clock(rdev); | 162 | radeon_legacy_get_memory_clock(rdev); |
161 | 163 | ||
162 | DRM_INFO("Using device-tree clock info\n"); | 164 | DRM_INFO("Using device-tree clock info\n"); |
163 | 165 | ||
164 | return true; | 166 | return true; |
165 | } | 167 | } |
166 | #else | 168 | #else |
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 5b991f7c6e2a..e4594676a07c 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c | |||
@@ -866,6 +866,11 @@ bool radeon_combios_get_clock_info(struct drm_device *dev) | |||
866 | rdev->clock.default_sclk = sclk; | 866 | rdev->clock.default_sclk = sclk; |
867 | rdev->clock.default_mclk = mclk; | 867 | rdev->clock.default_mclk = mclk; |
868 | 868 | ||
869 | if (RBIOS32(pll_info + 0x16)) | ||
870 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); | ||
871 | else | ||
872 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ | ||
873 | |||
869 | return true; | 874 | return true; |
870 | } | 875 | } |
871 | return false; | 876 | return false; |
@@ -1548,10 +1553,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) | |||
1548 | (rdev->pdev->subsystem_device == 0x4a48)) { | 1553 | (rdev->pdev->subsystem_device == 0x4a48)) { |
1549 | /* Mac X800 */ | 1554 | /* Mac X800 */ |
1550 | rdev->mode_info.connector_table = CT_MAC_X800; | 1555 | rdev->mode_info.connector_table = CT_MAC_X800; |
1551 | } else if ((rdev->pdev->device == 0x4150) && | 1556 | } else if ((of_machine_is_compatible("PowerMac7,2") || |
1557 | of_machine_is_compatible("PowerMac7,3")) && | ||
1558 | (rdev->pdev->device == 0x4150) && | ||
1552 | (rdev->pdev->subsystem_vendor == 0x1002) && | 1559 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1553 | (rdev->pdev->subsystem_device == 0x4150)) { | 1560 | (rdev->pdev->subsystem_device == 0x4150)) { |
1554 | /* Mac G5 9600 */ | 1561 | /* Mac G5 tower 9600 */ |
1555 | rdev->mode_info.connector_table = CT_MAC_G5_9600; | 1562 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
1556 | } else | 1563 | } else |
1557 | #endif /* CONFIG_PPC_PMAC */ | 1564 | #endif /* CONFIG_PPC_PMAC */ |
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index ee1dccb3fec9..cbfca3a24fdf 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c | |||
@@ -44,6 +44,8 @@ extern void | |||
44 | radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, | 44 | radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, |
45 | struct drm_connector *drm_connector); | 45 | struct drm_connector *drm_connector); |
46 | 46 | ||
47 | bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector); | ||
48 | |||
47 | void radeon_connector_hotplug(struct drm_connector *connector) | 49 | void radeon_connector_hotplug(struct drm_connector *connector) |
48 | { | 50 | { |
49 | struct drm_device *dev = connector->dev; | 51 | struct drm_device *dev = connector->dev; |
@@ -626,8 +628,14 @@ static int radeon_vga_get_modes(struct drm_connector *connector) | |||
626 | static int radeon_vga_mode_valid(struct drm_connector *connector, | 628 | static int radeon_vga_mode_valid(struct drm_connector *connector, |
627 | struct drm_display_mode *mode) | 629 | struct drm_display_mode *mode) |
628 | { | 630 | { |
631 | struct drm_device *dev = connector->dev; | ||
632 | struct radeon_device *rdev = dev->dev_private; | ||
633 | |||
629 | /* XXX check mode bandwidth */ | 634 | /* XXX check mode bandwidth */ |
630 | /* XXX verify against max DAC output frequency */ | 635 | |
636 | if ((mode->clock / 10) > rdev->clock.max_pixel_clock) | ||
637 | return MODE_CLOCK_HIGH; | ||
638 | |||
631 | return MODE_OK; | 639 | return MODE_OK; |
632 | } | 640 | } |
633 | 641 | ||
@@ -830,6 +838,13 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) | |||
830 | if (!radeon_connector->edid) { | 838 | if (!radeon_connector->edid) { |
831 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", | 839 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
832 | drm_get_connector_name(connector)); | 840 | drm_get_connector_name(connector)); |
841 | /* rs690 seems to have a problem with connectors not existing and always | ||
842 | * return a block of 0's. If we see this just stop polling on this output */ | ||
843 | if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) && radeon_connector->base.null_edid_counter) { | ||
844 | ret = connector_status_disconnected; | ||
845 | DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector)); | ||
846 | radeon_connector->ddc_bus = NULL; | ||
847 | } | ||
833 | } else { | 848 | } else { |
834 | radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | 849 | radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); |
835 | 850 | ||
@@ -1015,6 +1030,11 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector, | |||
1015 | } else | 1030 | } else |
1016 | return MODE_CLOCK_HIGH; | 1031 | return MODE_CLOCK_HIGH; |
1017 | } | 1032 | } |
1033 | |||
1034 | /* check against the max pixel clock */ | ||
1035 | if ((mode->clock / 10) > rdev->clock.max_pixel_clock) | ||
1036 | return MODE_CLOCK_HIGH; | ||
1037 | |||
1018 | return MODE_OK; | 1038 | return MODE_OK; |
1019 | } | 1039 | } |
1020 | 1040 | ||
@@ -1052,10 +1072,11 @@ static int radeon_dp_get_modes(struct drm_connector *connector) | |||
1052 | { | 1072 | { |
1053 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 1073 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1054 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; | 1074 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
1075 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | ||
1055 | int ret; | 1076 | int ret; |
1056 | 1077 | ||
1057 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | 1078 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1058 | struct drm_encoder *encoder; | 1079 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { |
1059 | struct drm_display_mode *mode; | 1080 | struct drm_display_mode *mode; |
1060 | 1081 | ||
1061 | if (!radeon_dig_connector->edp_on) | 1082 | if (!radeon_dig_connector->edp_on) |
@@ -1067,7 +1088,6 @@ static int radeon_dp_get_modes(struct drm_connector *connector) | |||
1067 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | 1088 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1068 | 1089 | ||
1069 | if (ret > 0) { | 1090 | if (ret > 0) { |
1070 | encoder = radeon_best_single_encoder(connector); | ||
1071 | if (encoder) { | 1091 | if (encoder) { |
1072 | radeon_fixup_lvds_native_mode(encoder, connector); | 1092 | radeon_fixup_lvds_native_mode(encoder, connector); |
1073 | /* add scaled modes */ | 1093 | /* add scaled modes */ |
@@ -1091,8 +1111,14 @@ static int radeon_dp_get_modes(struct drm_connector *connector) | |||
1091 | /* add scaled modes */ | 1111 | /* add scaled modes */ |
1092 | radeon_add_common_modes(encoder, connector); | 1112 | radeon_add_common_modes(encoder, connector); |
1093 | } | 1113 | } |
1094 | } else | 1114 | } else { |
1115 | /* need to setup ddc on the bridge */ | ||
1116 | if (radeon_connector_encoder_is_dp_bridge(connector)) { | ||
1117 | if (encoder) | ||
1118 | radeon_atom_ext_encoder_setup_ddc(encoder); | ||
1119 | } | ||
1095 | ret = radeon_ddc_get_modes(radeon_connector); | 1120 | ret = radeon_ddc_get_modes(radeon_connector); |
1121 | } | ||
1096 | 1122 | ||
1097 | return ret; | 1123 | return ret; |
1098 | } | 1124 | } |
@@ -1176,14 +1202,15 @@ radeon_dp_detect(struct drm_connector *connector, bool force) | |||
1176 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 1202 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1177 | enum drm_connector_status ret = connector_status_disconnected; | 1203 | enum drm_connector_status ret = connector_status_disconnected; |
1178 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; | 1204 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
1205 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | ||
1179 | 1206 | ||
1180 | if (radeon_connector->edid) { | 1207 | if (radeon_connector->edid) { |
1181 | kfree(radeon_connector->edid); | 1208 | kfree(radeon_connector->edid); |
1182 | radeon_connector->edid = NULL; | 1209 | radeon_connector->edid = NULL; |
1183 | } | 1210 | } |
1184 | 1211 | ||
1185 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | 1212 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1186 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | 1213 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { |
1187 | if (encoder) { | 1214 | if (encoder) { |
1188 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1215 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1189 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | 1216 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
@@ -1203,6 +1230,11 @@ radeon_dp_detect(struct drm_connector *connector, bool force) | |||
1203 | atombios_set_edp_panel_power(connector, | 1230 | atombios_set_edp_panel_power(connector, |
1204 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | 1231 | ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1205 | } else { | 1232 | } else { |
1233 | /* need to setup ddc on the bridge */ | ||
1234 | if (radeon_connector_encoder_is_dp_bridge(connector)) { | ||
1235 | if (encoder) | ||
1236 | radeon_atom_ext_encoder_setup_ddc(encoder); | ||
1237 | } | ||
1206 | radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); | 1238 | radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); |
1207 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { | 1239 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { |
1208 | ret = connector_status_connected; | 1240 | ret = connector_status_connected; |
@@ -1217,6 +1249,16 @@ radeon_dp_detect(struct drm_connector *connector, bool force) | |||
1217 | ret = connector_status_connected; | 1249 | ret = connector_status_connected; |
1218 | } | 1250 | } |
1219 | } | 1251 | } |
1252 | |||
1253 | if ((ret == connector_status_disconnected) && | ||
1254 | radeon_connector->dac_load_detect) { | ||
1255 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | ||
1256 | struct drm_encoder_helper_funcs *encoder_funcs; | ||
1257 | if (encoder) { | ||
1258 | encoder_funcs = encoder->helper_private; | ||
1259 | ret = encoder_funcs->detect(encoder, connector); | ||
1260 | } | ||
1261 | } | ||
1220 | } | 1262 | } |
1221 | 1263 | ||
1222 | radeon_connector_update_scratch_regs(connector, ret); | 1264 | radeon_connector_update_scratch_regs(connector, ret); |
@@ -1231,7 +1273,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector, | |||
1231 | 1273 | ||
1232 | /* XXX check mode bandwidth */ | 1274 | /* XXX check mode bandwidth */ |
1233 | 1275 | ||
1234 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { | 1276 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1277 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | ||
1235 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | 1278 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
1236 | 1279 | ||
1237 | if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) | 1280 | if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) |
@@ -1241,7 +1284,7 @@ static int radeon_dp_mode_valid(struct drm_connector *connector, | |||
1241 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 1284 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
1242 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | 1285 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
1243 | 1286 | ||
1244 | /* AVIVO hardware supports downscaling modes larger than the panel | 1287 | /* AVIVO hardware supports downscaling modes larger than the panel |
1245 | * to the panel size, but I'm not sure this is desirable. | 1288 | * to the panel size, but I'm not sure this is desirable. |
1246 | */ | 1289 | */ |
1247 | if ((mode->hdisplay > native_mode->hdisplay) || | 1290 | if ((mode->hdisplay > native_mode->hdisplay) || |
@@ -1390,6 +1433,10 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
1390 | default: | 1433 | default: |
1391 | connector->interlace_allowed = true; | 1434 | connector->interlace_allowed = true; |
1392 | connector->doublescan_allowed = true; | 1435 | connector->doublescan_allowed = true; |
1436 | radeon_connector->dac_load_detect = true; | ||
1437 | drm_connector_attach_property(&radeon_connector->base, | ||
1438 | rdev->mode_info.load_detect_property, | ||
1439 | 1); | ||
1393 | break; | 1440 | break; |
1394 | case DRM_MODE_CONNECTOR_DVII: | 1441 | case DRM_MODE_CONNECTOR_DVII: |
1395 | case DRM_MODE_CONNECTOR_DVID: | 1442 | case DRM_MODE_CONNECTOR_DVID: |
@@ -1411,6 +1458,12 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
1411 | connector->doublescan_allowed = true; | 1458 | connector->doublescan_allowed = true; |
1412 | else | 1459 | else |
1413 | connector->doublescan_allowed = false; | 1460 | connector->doublescan_allowed = false; |
1461 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { | ||
1462 | radeon_connector->dac_load_detect = true; | ||
1463 | drm_connector_attach_property(&radeon_connector->base, | ||
1464 | rdev->mode_info.load_detect_property, | ||
1465 | 1); | ||
1466 | } | ||
1414 | break; | 1467 | break; |
1415 | case DRM_MODE_CONNECTOR_LVDS: | 1468 | case DRM_MODE_CONNECTOR_LVDS: |
1416 | case DRM_MODE_CONNECTOR_eDP: | 1469 | case DRM_MODE_CONNECTOR_eDP: |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 8c1916941871..fae00c0d75aa 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
@@ -228,6 +228,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |||
228 | parser.filp = filp; | 228 | parser.filp = filp; |
229 | parser.rdev = rdev; | 229 | parser.rdev = rdev; |
230 | parser.dev = rdev->dev; | 230 | parser.dev = rdev->dev; |
231 | parser.family = rdev->family; | ||
231 | r = radeon_cs_parser_init(&parser, data); | 232 | r = radeon_cs_parser_init(&parser, data); |
232 | if (r) { | 233 | if (r) { |
233 | DRM_ERROR("Failed to initialize parser !\n"); | 234 | DRM_ERROR("Failed to initialize parser !\n"); |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index d77ede3e67ce..7cfaa7e2f3b5 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -215,6 +215,8 @@ int radeon_wb_init(struct radeon_device *rdev) | |||
215 | return r; | 215 | return r; |
216 | } | 216 | } |
217 | 217 | ||
218 | /* clear wb memory */ | ||
219 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); | ||
218 | /* disable event_write fences */ | 220 | /* disable event_write fences */ |
219 | rdev->wb.use_event = false; | 221 | rdev->wb.use_event = false; |
220 | /* disabled via module param */ | 222 | /* disabled via module param */ |
@@ -754,6 +756,7 @@ int radeon_device_init(struct radeon_device *rdev, | |||
754 | dma_bits = rdev->need_dma32 ? 32 : 40; | 756 | dma_bits = rdev->need_dma32 ? 32 : 40; |
755 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); | 757 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
756 | if (r) { | 758 | if (r) { |
759 | rdev->need_dma32 = true; | ||
757 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); | 760 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
758 | } | 761 | } |
759 | 762 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 1d330606292f..73dfbe8e5f9e 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -113,7 +113,7 @@ int radeon_benchmarking = 0; | |||
113 | int radeon_testing = 0; | 113 | int radeon_testing = 0; |
114 | int radeon_connector_table = 0; | 114 | int radeon_connector_table = 0; |
115 | int radeon_tv = 1; | 115 | int radeon_tv = 1; |
116 | int radeon_audio = 1; | 116 | int radeon_audio = 0; |
117 | int radeon_disp_priority = 0; | 117 | int radeon_disp_priority = 0; |
118 | int radeon_hw_i2c = 0; | 118 | int radeon_hw_i2c = 0; |
119 | int radeon_pcie_gen2 = 0; | 119 | int radeon_pcie_gen2 = 0; |
@@ -151,7 +151,7 @@ module_param_named(connector_table, radeon_connector_table, int, 0444); | |||
151 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); | 151 | MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); |
152 | module_param_named(tv, radeon_tv, int, 0444); | 152 | module_param_named(tv, radeon_tv, int, 0444); |
153 | 153 | ||
154 | MODULE_PARM_DESC(audio, "Audio enable (0 = disable)"); | 154 | MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); |
155 | module_param_named(audio, radeon_audio, int, 0444); | 155 | module_param_named(audio, radeon_audio, int, 0444); |
156 | 156 | ||
157 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); | 157 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 03f124d626c2..b293487e5aa3 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -367,7 +367,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, | |||
367 | } | 367 | } |
368 | 368 | ||
369 | if (ASIC_IS_DCE3(rdev) && | 369 | if (ASIC_IS_DCE3(rdev) && |
370 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { | 370 | ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
371 | radeon_encoder_is_dp_bridge(encoder))) { | ||
371 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | 372 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
372 | radeon_dp_set_link_config(connector, mode); | 373 | radeon_dp_set_link_config(connector, mode); |
373 | } | 374 | } |
@@ -660,21 +661,16 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
660 | if (radeon_encoder_is_dp_bridge(encoder)) | 661 | if (radeon_encoder_is_dp_bridge(encoder)) |
661 | return ATOM_ENCODER_MODE_DP; | 662 | return ATOM_ENCODER_MODE_DP; |
662 | 663 | ||
664 | /* DVO is always DVO */ | ||
665 | if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) | ||
666 | return ATOM_ENCODER_MODE_DVO; | ||
667 | |||
663 | connector = radeon_get_connector_for_encoder(encoder); | 668 | connector = radeon_get_connector_for_encoder(encoder); |
664 | if (!connector) { | 669 | /* if we don't have an active device yet, just use one of |
665 | switch (radeon_encoder->encoder_id) { | 670 | * the connectors tied to the encoder. |
666 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | 671 | */ |
667 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | 672 | if (!connector) |
668 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | 673 | connector = radeon_get_connector_for_encoder_init(encoder); |
669 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | ||
670 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | ||
671 | return ATOM_ENCODER_MODE_DVI; | ||
672 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | ||
673 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | ||
674 | default: | ||
675 | return ATOM_ENCODER_MODE_CRT; | ||
676 | } | ||
677 | } | ||
678 | radeon_connector = to_radeon_connector(connector); | 674 | radeon_connector = to_radeon_connector(connector); |
679 | 675 | ||
680 | switch (connector->connector_type) { | 676 | switch (connector->connector_type) { |
@@ -1094,9 +1090,10 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
1094 | break; | 1090 | break; |
1095 | } | 1091 | } |
1096 | 1092 | ||
1097 | if (is_dp) | 1093 | if (is_dp) { |
1098 | args.v2.acConfig.fCoherentMode = 1; | 1094 | args.v2.acConfig.fCoherentMode = 1; |
1099 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | 1095 | args.v2.acConfig.fDPConnector = 1; |
1096 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | ||
1100 | if (dig->coherent_mode) | 1097 | if (dig->coherent_mode) |
1101 | args.v2.acConfig.fCoherentMode = 1; | 1098 | args.v2.acConfig.fCoherentMode = 1; |
1102 | if (radeon_encoder->pixel_clock > 165000) | 1099 | if (radeon_encoder->pixel_clock > 165000) |
@@ -1435,7 +1432,11 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
1435 | if (is_dig) { | 1432 | if (is_dig) { |
1436 | switch (mode) { | 1433 | switch (mode) { |
1437 | case DRM_MODE_DPMS_ON: | 1434 | case DRM_MODE_DPMS_ON: |
1438 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | 1435 | /* some early dce3.2 boards have a bug in their transmitter control table */ |
1436 | if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) | ||
1437 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | ||
1438 | else | ||
1439 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | ||
1439 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { | 1440 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
1440 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | 1441 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1441 | 1442 | ||
@@ -1526,26 +1527,29 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
1526 | } | 1527 | } |
1527 | 1528 | ||
1528 | if (ext_encoder) { | 1529 | if (ext_encoder) { |
1529 | int action; | ||
1530 | |||
1531 | switch (mode) { | 1530 | switch (mode) { |
1532 | case DRM_MODE_DPMS_ON: | 1531 | case DRM_MODE_DPMS_ON: |
1533 | default: | 1532 | default: |
1534 | if (ASIC_IS_DCE41(rdev)) | 1533 | if (ASIC_IS_DCE41(rdev)) { |
1535 | action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; | 1534 | atombios_external_encoder_setup(encoder, ext_encoder, |
1536 | else | 1535 | EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); |
1537 | action = ATOM_ENABLE; | 1536 | atombios_external_encoder_setup(encoder, ext_encoder, |
1537 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); | ||
1538 | } else | ||
1539 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); | ||
1538 | break; | 1540 | break; |
1539 | case DRM_MODE_DPMS_STANDBY: | 1541 | case DRM_MODE_DPMS_STANDBY: |
1540 | case DRM_MODE_DPMS_SUSPEND: | 1542 | case DRM_MODE_DPMS_SUSPEND: |
1541 | case DRM_MODE_DPMS_OFF: | 1543 | case DRM_MODE_DPMS_OFF: |
1542 | if (ASIC_IS_DCE41(rdev)) | 1544 | if (ASIC_IS_DCE41(rdev)) { |
1543 | action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; | 1545 | atombios_external_encoder_setup(encoder, ext_encoder, |
1544 | else | 1546 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); |
1545 | action = ATOM_DISABLE; | 1547 | atombios_external_encoder_setup(encoder, ext_encoder, |
1548 | EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); | ||
1549 | } else | ||
1550 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); | ||
1546 | break; | 1551 | break; |
1547 | } | 1552 | } |
1548 | atombios_external_encoder_setup(encoder, ext_encoder, action); | ||
1549 | } | 1553 | } |
1550 | 1554 | ||
1551 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); | 1555 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
@@ -2004,6 +2008,65 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec | |||
2004 | return connector_status_disconnected; | 2008 | return connector_status_disconnected; |
2005 | } | 2009 | } |
2006 | 2010 | ||
2011 | static enum drm_connector_status | ||
2012 | radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) | ||
2013 | { | ||
2014 | struct drm_device *dev = encoder->dev; | ||
2015 | struct radeon_device *rdev = dev->dev_private; | ||
2016 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
2017 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | ||
2018 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); | ||
2019 | u32 bios_0_scratch; | ||
2020 | |||
2021 | if (!ASIC_IS_DCE4(rdev)) | ||
2022 | return connector_status_unknown; | ||
2023 | |||
2024 | if (!ext_encoder) | ||
2025 | return connector_status_unknown; | ||
2026 | |||
2027 | if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) | ||
2028 | return connector_status_unknown; | ||
2029 | |||
2030 | /* load detect on the dp bridge */ | ||
2031 | atombios_external_encoder_setup(encoder, ext_encoder, | ||
2032 | EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); | ||
2033 | |||
2034 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | ||
2035 | |||
2036 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); | ||
2037 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { | ||
2038 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) | ||
2039 | return connector_status_connected; | ||
2040 | } | ||
2041 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | ||
2042 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) | ||
2043 | return connector_status_connected; | ||
2044 | } | ||
2045 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | ||
2046 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) | ||
2047 | return connector_status_connected; | ||
2048 | } | ||
2049 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | ||
2050 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) | ||
2051 | return connector_status_connected; /* CTV */ | ||
2052 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | ||
2053 | return connector_status_connected; /* STV */ | ||
2054 | } | ||
2055 | return connector_status_disconnected; | ||
2056 | } | ||
2057 | |||
2058 | void | ||
2059 | radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) | ||
2060 | { | ||
2061 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); | ||
2062 | |||
2063 | if (ext_encoder) | ||
2064 | /* ddc_setup on the dp bridge */ | ||
2065 | atombios_external_encoder_setup(encoder, ext_encoder, | ||
2066 | EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); | ||
2067 | |||
2068 | } | ||
2069 | |||
2007 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | 2070 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
2008 | { | 2071 | { |
2009 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 2072 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
@@ -2167,7 +2230,7 @@ static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { | |||
2167 | .mode_set = radeon_atom_encoder_mode_set, | 2230 | .mode_set = radeon_atom_encoder_mode_set, |
2168 | .commit = radeon_atom_encoder_commit, | 2231 | .commit = radeon_atom_encoder_commit, |
2169 | .disable = radeon_atom_encoder_disable, | 2232 | .disable = radeon_atom_encoder_disable, |
2170 | /* no detect for TMDS/LVDS yet */ | 2233 | .detect = radeon_atom_dig_detect, |
2171 | }; | 2234 | }; |
2172 | 2235 | ||
2173 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | 2236 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index 1f8229436570..021d2b6b556f 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c | |||
@@ -40,6 +40,35 @@ | |||
40 | #include "radeon.h" | 40 | #include "radeon.h" |
41 | #include "radeon_trace.h" | 41 | #include "radeon_trace.h" |
42 | 42 | ||
43 | static void radeon_fence_write(struct radeon_device *rdev, u32 seq) | ||
44 | { | ||
45 | if (rdev->wb.enabled) { | ||
46 | u32 scratch_index; | ||
47 | if (rdev->wb.use_event) | ||
48 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | ||
49 | else | ||
50 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | ||
51 | rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);; | ||
52 | } else | ||
53 | WREG32(rdev->fence_drv.scratch_reg, seq); | ||
54 | } | ||
55 | |||
56 | static u32 radeon_fence_read(struct radeon_device *rdev) | ||
57 | { | ||
58 | u32 seq; | ||
59 | |||
60 | if (rdev->wb.enabled) { | ||
61 | u32 scratch_index; | ||
62 | if (rdev->wb.use_event) | ||
63 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | ||
64 | else | ||
65 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | ||
66 | seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]); | ||
67 | } else | ||
68 | seq = RREG32(rdev->fence_drv.scratch_reg); | ||
69 | return seq; | ||
70 | } | ||
71 | |||
43 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) | 72 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) |
44 | { | 73 | { |
45 | unsigned long irq_flags; | 74 | unsigned long irq_flags; |
@@ -50,12 +79,12 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) | |||
50 | return 0; | 79 | return 0; |
51 | } | 80 | } |
52 | fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); | 81 | fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); |
53 | if (!rdev->cp.ready) { | 82 | if (!rdev->cp.ready) |
54 | /* FIXME: cp is not running assume everythings is done right | 83 | /* FIXME: cp is not running assume everythings is done right |
55 | * away | 84 | * away |
56 | */ | 85 | */ |
57 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); | 86 | radeon_fence_write(rdev, fence->seq); |
58 | } else | 87 | else |
59 | radeon_fence_ring_emit(rdev, fence); | 88 | radeon_fence_ring_emit(rdev, fence); |
60 | 89 | ||
61 | trace_radeon_fence_emit(rdev->ddev, fence->seq); | 90 | trace_radeon_fence_emit(rdev->ddev, fence->seq); |
@@ -73,15 +102,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev) | |||
73 | bool wake = false; | 102 | bool wake = false; |
74 | unsigned long cjiffies; | 103 | unsigned long cjiffies; |
75 | 104 | ||
76 | if (rdev->wb.enabled) { | 105 | seq = radeon_fence_read(rdev); |
77 | u32 scratch_index; | ||
78 | if (rdev->wb.use_event) | ||
79 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | ||
80 | else | ||
81 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; | ||
82 | seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]); | ||
83 | } else | ||
84 | seq = RREG32(rdev->fence_drv.scratch_reg); | ||
85 | if (seq != rdev->fence_drv.last_seq) { | 106 | if (seq != rdev->fence_drv.last_seq) { |
86 | rdev->fence_drv.last_seq = seq; | 107 | rdev->fence_drv.last_seq = seq; |
87 | rdev->fence_drv.last_jiffies = jiffies; | 108 | rdev->fence_drv.last_jiffies = jiffies; |
@@ -251,7 +272,7 @@ retry: | |||
251 | r = radeon_gpu_reset(rdev); | 272 | r = radeon_gpu_reset(rdev); |
252 | if (r) | 273 | if (r) |
253 | return r; | 274 | return r; |
254 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); | 275 | radeon_fence_write(rdev, fence->seq); |
255 | rdev->gpu_lockup = false; | 276 | rdev->gpu_lockup = false; |
256 | } | 277 | } |
257 | timeout = RADEON_FENCE_JIFFIES_TIMEOUT; | 278 | timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
@@ -351,7 +372,7 @@ int radeon_fence_driver_init(struct radeon_device *rdev) | |||
351 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); | 372 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
352 | return r; | 373 | return r; |
353 | } | 374 | } |
354 | WREG32(rdev->fence_drv.scratch_reg, 0); | 375 | radeon_fence_write(rdev, 0); |
355 | atomic_set(&rdev->fence_drv.seq, 0); | 376 | atomic_set(&rdev->fence_drv.seq, 0); |
356 | INIT_LIST_HEAD(&rdev->fence_drv.created); | 377 | INIT_LIST_HEAD(&rdev->fence_drv.created); |
357 | INIT_LIST_HEAD(&rdev->fence_drv.emited); | 378 | INIT_LIST_HEAD(&rdev->fence_drv.emited); |
@@ -391,7 +412,7 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data) | |||
391 | struct radeon_fence *fence; | 412 | struct radeon_fence *fence; |
392 | 413 | ||
393 | seq_printf(m, "Last signaled fence 0x%08X\n", | 414 | seq_printf(m, "Last signaled fence 0x%08X\n", |
394 | RREG32(rdev->fence_drv.scratch_reg)); | 415 | radeon_fence_read(rdev)); |
395 | if (!list_empty(&rdev->fence_drv.emited)) { | 416 | if (!list_empty(&rdev->fence_drv.emited)) { |
396 | fence = list_entry(rdev->fence_drv.emited.prev, | 417 | fence = list_entry(rdev->fence_drv.emited.prev, |
397 | struct radeon_fence, list); | 418 | struct radeon_fence, list); |
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 977a341266b6..6df4e3cec0c2 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -483,6 +483,8 @@ extern void radeon_atom_encoder_init(struct radeon_device *rdev); | |||
483 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, | 483 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
484 | int action, uint8_t lane_num, | 484 | int action, uint8_t lane_num, |
485 | uint8_t lane_set); | 485 | uint8_t lane_set); |
486 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); | ||
487 | extern struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder); | ||
486 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | 488 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
487 | u8 write_byte, u8 *read_byte); | 489 | u8 write_byte, u8 *read_byte); |
488 | 490 | ||
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index ef8a5babe9f7..6f508ffd1035 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -105,6 +105,9 @@ void rv770_pm_misc(struct radeon_device *rdev) | |||
105 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | 105 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
106 | 106 | ||
107 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { | 107 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
108 | /* 0xff01 is a flag rather then an actual voltage */ | ||
109 | if (voltage->voltage == 0xff01) | ||
110 | return; | ||
108 | if (voltage->voltage != rdev->pm.current_vddc) { | 111 | if (voltage->voltage != rdev->pm.current_vddc) { |
109 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); | 112 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
110 | rdev->pm.current_vddc = voltage->voltage; | 113 | rdev->pm.current_vddc = voltage->voltage; |