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-rw-r--r--drivers/gpu/drm/radeon/Makefile1
-rw-r--r--drivers/gpu/drm/radeon/atom.c9
-rw-r--r--drivers/gpu/drm/radeon/atom.h2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c212
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c18
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c22
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h5
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h5
-rw-r--r--drivers/gpu/drm/radeon/r100.c55
-rw-r--r--drivers/gpu/drm/radeon/r100d.h2
-rw-r--r--drivers/gpu/drm/radeon/r300.c46
-rw-r--r--drivers/gpu/drm/radeon/r300d.h2
-rw-r--r--drivers/gpu/drm/radeon/r420.c2
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h5
-rw-r--r--drivers/gpu/drm/radeon/r520.c2
-rw-r--r--drivers/gpu/drm/radeon/r600.c49
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c22
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_shaders.c1115
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c232
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c6
-rw-r--r--drivers/gpu/drm/radeon/r600d.h12
-rw-r--r--drivers/gpu/drm/radeon/radeon.h53
-rw-r--r--drivers/gpu/drm/radeon/radeon_acpi.c67
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c75
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c51
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c48
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c45
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c77
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c37
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c30
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_tv.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h18
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c114
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c20
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r30013
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r42014
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs60013
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv51513
-rw-r--r--drivers/gpu/drm/radeon/rs400.c10
-rw-r--r--drivers/gpu/drm/radeon/rs600.c16
-rw-r--r--drivers/gpu/drm/radeon/rs690.c44
-rw-r--r--drivers/gpu/drm/radeon/rv515.c25
-rw-r--r--drivers/gpu/drm/radeon/rv770.c27
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h6
51 files changed, 1527 insertions, 1195 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 84b1f2729d43..aebe00875041 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -69,5 +69,6 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
69 69
70radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 70radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
71radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 71radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
72radeon-$(CONFIG_ACPI) += radeon_acpi.o
72 73
73obj-$(CONFIG_DRM_RADEON)+= radeon.o 74obj-$(CONFIG_DRM_RADEON)+= radeon.o
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 1d569830ed99..8e421f644a54 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -108,12 +108,11 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
108 base++; 108 base++;
109 break; 109 break;
110 case ATOM_IIO_READ: 110 case ATOM_IIO_READ:
111 temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); 111 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
112 base += 3; 112 base += 3;
113 break; 113 break;
114 case ATOM_IIO_WRITE: 114 case ATOM_IIO_WRITE:
115 (void)ctx->card->reg_read(ctx->card, CU16(base + 1)); 115 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
116 ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
117 base += 3; 116 base += 3;
118 break; 117 break;
119 case ATOM_IIO_CLEAR: 118 case ATOM_IIO_CLEAR:
@@ -715,8 +714,8 @@ static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
715 cjiffies = jiffies; 714 cjiffies = jiffies;
716 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 715 if (time_after(cjiffies, ctx->last_jump_jiffies)) {
717 cjiffies -= ctx->last_jump_jiffies; 716 cjiffies -= ctx->last_jump_jiffies;
718 if ((jiffies_to_msecs(cjiffies) > 1000)) { 717 if ((jiffies_to_msecs(cjiffies) > 5000)) {
719 DRM_ERROR("atombios stuck in loop for more than 1sec aborting\n"); 718 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
720 ctx->abort = true; 719 ctx->abort = true;
721 } 720 }
722 } else { 721 } else {
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index cd1b64ab5ca7..a589a55b223e 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -113,6 +113,8 @@ struct card_info {
113 struct drm_device *dev; 113 struct drm_device *dev;
114 void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ 114 void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
115 uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */ 115 uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */
116 void (* ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
117 uint32_t (* ioreg_read)(struct card_info *, uint32_t); /* filled by driver */
116 void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ 118 void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
117 uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */ 119 uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */
118 void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ 120 void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 8c2d6478a221..12ad512bd3d3 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -44,10 +44,6 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
44 44
45 memset(&args, 0, sizeof(args)); 45 memset(&args, 0, sizeof(args));
46 46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id; 47 args.ucCRTC = radeon_crtc->crtc_id;
52 48
53 switch (radeon_crtc->rmx_type) { 49 switch (radeon_crtc->rmx_type) {
@@ -56,7 +52,6 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break; 55 break;
61 case RMX_ASPECT: 56 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
@@ -69,17 +64,16 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 } 66 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break; 67 break;
74 case RMX_FULL: 68 case RMX_FULL:
75 default: 69 default:
76 args.usOverscanRight = 0; 70 args.usOverscanRight = radeon_crtc->h_border;
77 args.usOverscanLeft = 0; 71 args.usOverscanLeft = radeon_crtc->h_border;
78 args.usOverscanBottom = 0; 72 args.usOverscanBottom = radeon_crtc->v_border;
79 args.usOverscanTop = 0; 73 args.usOverscanTop = radeon_crtc->v_border;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break; 74 break;
82 } 75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
83} 77}
84 78
85static void atombios_scaler_setup(struct drm_crtc *crtc) 79static void atombios_scaler_setup(struct drm_crtc *crtc)
@@ -282,22 +276,22 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
282 u16 misc = 0; 276 u16 misc = 0;
283 277
284 memset(&args, 0, sizeof(args)); 278 memset(&args, 0, sizeof(args));
285 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay); 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
286 args.usH_Blanking_Time = 280 args.usH_Blanking_Time =
287 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay); 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
288 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay); 282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
289 args.usV_Blanking_Time = 283 args.usV_Blanking_Time =
290 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay); 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
291 args.usH_SyncOffset = 285 args.usH_SyncOffset =
292 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay); 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
293 args.usH_SyncWidth = 287 args.usH_SyncWidth =
294 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
295 args.usV_SyncOffset = 289 args.usV_SyncOffset =
296 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay); 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
297 args.usV_SyncWidth = 291 args.usV_SyncWidth =
298 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
299 /*args.ucH_Border = mode->hborder;*/ 293 args.ucH_Border = radeon_crtc->h_border;
300 /*args.ucV_Border = mode->vborder;*/ 294 args.ucV_Border = radeon_crtc->v_border;
301 295
302 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
303 misc |= ATOM_VSYNC_POLARITY; 297 misc |= ATOM_VSYNC_POLARITY;
@@ -669,56 +663,25 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 663 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
670} 664}
671 665
672static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 666static void atombios_crtc_program_pll(struct drm_crtc *crtc,
667 int crtc_id,
668 int pll_id,
669 u32 encoder_mode,
670 u32 encoder_id,
671 u32 clock,
672 u32 ref_div,
673 u32 fb_div,
674 u32 frac_fb_div,
675 u32 post_div)
673{ 676{
674 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
675 struct drm_device *dev = crtc->dev; 677 struct drm_device *dev = crtc->dev;
676 struct radeon_device *rdev = dev->dev_private; 678 struct radeon_device *rdev = dev->dev_private;
677 struct drm_encoder *encoder = NULL;
678 struct radeon_encoder *radeon_encoder = NULL;
679 u8 frev, crev; 679 u8 frev, crev;
680 int index; 680 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
681 union set_pixel_clock args; 681 union set_pixel_clock args;
682 u32 pll_clock = mode->clock;
683 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
684 struct radeon_pll *pll;
685 u32 adjusted_clock;
686 int encoder_mode = 0;
687 682
688 memset(&args, 0, sizeof(args)); 683 memset(&args, 0, sizeof(args));
689 684
690 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
691 if (encoder->crtc == crtc) {
692 radeon_encoder = to_radeon_encoder(encoder);
693 encoder_mode = atombios_get_encoder_mode(encoder);
694 break;
695 }
696 }
697
698 if (!radeon_encoder)
699 return;
700
701 switch (radeon_crtc->pll_id) {
702 case ATOM_PPLL1:
703 pll = &rdev->clock.p1pll;
704 break;
705 case ATOM_PPLL2:
706 pll = &rdev->clock.p2pll;
707 break;
708 case ATOM_DCPLL:
709 case ATOM_PPLL_INVALID:
710 default:
711 pll = &rdev->clock.dcpll;
712 break;
713 }
714
715 /* adjust pixel clock as needed */
716 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
717
718 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
719 &ref_div, &post_div);
720
721 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
722 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 685 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
723 &crev)) 686 &crev))
724 return; 687 return;
@@ -727,47 +690,49 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
727 case 1: 690 case 1:
728 switch (crev) { 691 switch (crev) {
729 case 1: 692 case 1:
730 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 693 if (clock == ATOM_DISABLE)
694 return;
695 args.v1.usPixelClock = cpu_to_le16(clock / 10);
731 args.v1.usRefDiv = cpu_to_le16(ref_div); 696 args.v1.usRefDiv = cpu_to_le16(ref_div);
732 args.v1.usFbDiv = cpu_to_le16(fb_div); 697 args.v1.usFbDiv = cpu_to_le16(fb_div);
733 args.v1.ucFracFbDiv = frac_fb_div; 698 args.v1.ucFracFbDiv = frac_fb_div;
734 args.v1.ucPostDiv = post_div; 699 args.v1.ucPostDiv = post_div;
735 args.v1.ucPpll = radeon_crtc->pll_id; 700 args.v1.ucPpll = pll_id;
736 args.v1.ucCRTC = radeon_crtc->crtc_id; 701 args.v1.ucCRTC = crtc_id;
737 args.v1.ucRefDivSrc = 1; 702 args.v1.ucRefDivSrc = 1;
738 break; 703 break;
739 case 2: 704 case 2:
740 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10); 705 args.v2.usPixelClock = cpu_to_le16(clock / 10);
741 args.v2.usRefDiv = cpu_to_le16(ref_div); 706 args.v2.usRefDiv = cpu_to_le16(ref_div);
742 args.v2.usFbDiv = cpu_to_le16(fb_div); 707 args.v2.usFbDiv = cpu_to_le16(fb_div);
743 args.v2.ucFracFbDiv = frac_fb_div; 708 args.v2.ucFracFbDiv = frac_fb_div;
744 args.v2.ucPostDiv = post_div; 709 args.v2.ucPostDiv = post_div;
745 args.v2.ucPpll = radeon_crtc->pll_id; 710 args.v2.ucPpll = pll_id;
746 args.v2.ucCRTC = radeon_crtc->crtc_id; 711 args.v2.ucCRTC = crtc_id;
747 args.v2.ucRefDivSrc = 1; 712 args.v2.ucRefDivSrc = 1;
748 break; 713 break;
749 case 3: 714 case 3:
750 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10); 715 args.v3.usPixelClock = cpu_to_le16(clock / 10);
751 args.v3.usRefDiv = cpu_to_le16(ref_div); 716 args.v3.usRefDiv = cpu_to_le16(ref_div);
752 args.v3.usFbDiv = cpu_to_le16(fb_div); 717 args.v3.usFbDiv = cpu_to_le16(fb_div);
753 args.v3.ucFracFbDiv = frac_fb_div; 718 args.v3.ucFracFbDiv = frac_fb_div;
754 args.v3.ucPostDiv = post_div; 719 args.v3.ucPostDiv = post_div;
755 args.v3.ucPpll = radeon_crtc->pll_id; 720 args.v3.ucPpll = pll_id;
756 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2); 721 args.v3.ucMiscInfo = (pll_id << 2);
757 args.v3.ucTransmitterId = radeon_encoder->encoder_id; 722 args.v3.ucTransmitterId = encoder_id;
758 args.v3.ucEncoderMode = encoder_mode; 723 args.v3.ucEncoderMode = encoder_mode;
759 break; 724 break;
760 case 5: 725 case 5:
761 args.v5.ucCRTC = radeon_crtc->crtc_id; 726 args.v5.ucCRTC = crtc_id;
762 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10); 727 args.v5.usPixelClock = cpu_to_le16(clock / 10);
763 args.v5.ucRefDiv = ref_div; 728 args.v5.ucRefDiv = ref_div;
764 args.v5.usFbDiv = cpu_to_le16(fb_div); 729 args.v5.usFbDiv = cpu_to_le16(fb_div);
765 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 730 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
766 args.v5.ucPostDiv = post_div; 731 args.v5.ucPostDiv = post_div;
767 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 732 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
768 args.v5.ucTransmitterID = radeon_encoder->encoder_id; 733 args.v5.ucTransmitterID = encoder_id;
769 args.v5.ucEncoderMode = encoder_mode; 734 args.v5.ucEncoderMode = encoder_mode;
770 args.v5.ucPpll = radeon_crtc->pll_id; 735 args.v5.ucPpll = pll_id;
771 break; 736 break;
772 default: 737 default:
773 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 738 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
@@ -782,6 +747,56 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
782 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 747 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
783} 748}
784 749
750static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
751{
752 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
753 struct drm_device *dev = crtc->dev;
754 struct radeon_device *rdev = dev->dev_private;
755 struct drm_encoder *encoder = NULL;
756 struct radeon_encoder *radeon_encoder = NULL;
757 u32 pll_clock = mode->clock;
758 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
759 struct radeon_pll *pll;
760 u32 adjusted_clock;
761 int encoder_mode = 0;
762
763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
764 if (encoder->crtc == crtc) {
765 radeon_encoder = to_radeon_encoder(encoder);
766 encoder_mode = atombios_get_encoder_mode(encoder);
767 break;
768 }
769 }
770
771 if (!radeon_encoder)
772 return;
773
774 switch (radeon_crtc->pll_id) {
775 case ATOM_PPLL1:
776 pll = &rdev->clock.p1pll;
777 break;
778 case ATOM_PPLL2:
779 pll = &rdev->clock.p2pll;
780 break;
781 case ATOM_DCPLL:
782 case ATOM_PPLL_INVALID:
783 default:
784 pll = &rdev->clock.dcpll;
785 break;
786 }
787
788 /* adjust pixel clock as needed */
789 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
790
791 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
792 &ref_div, &post_div);
793
794 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
795 encoder_mode, radeon_encoder->encoder_id, mode->clock,
796 ref_div, fb_div, frac_fb_div, post_div);
797
798}
799
785static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, 800static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
786 struct drm_framebuffer *old_fb) 801 struct drm_framebuffer *old_fb)
787{ 802{
@@ -797,7 +812,7 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
797 812
798 /* no fb bound */ 813 /* no fb bound */
799 if (!crtc->fb) { 814 if (!crtc->fb) {
800 DRM_DEBUG("No FB bound\n"); 815 DRM_DEBUG_KMS("No FB bound\n");
801 return 0; 816 return 0;
802 } 817 }
803 818
@@ -841,6 +856,11 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
841 return -EINVAL; 856 return -EINVAL;
842 } 857 }
843 858
859 if (tiling_flags & RADEON_TILING_MACRO)
860 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
861 else if (tiling_flags & RADEON_TILING_MICRO)
862 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
863
844 switch (radeon_crtc->crtc_id) { 864 switch (radeon_crtc->crtc_id) {
845 case 0: 865 case 0:
846 WREG32(AVIVO_D1VGA_CONTROL, 0); 866 WREG32(AVIVO_D1VGA_CONTROL, 0);
@@ -931,7 +951,7 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
931 951
932 /* no fb bound */ 952 /* no fb bound */
933 if (!crtc->fb) { 953 if (!crtc->fb) {
934 DRM_DEBUG("No FB bound\n"); 954 DRM_DEBUG_KMS("No FB bound\n");
935 return 0; 955 return 0;
936 } 956 }
937 957
@@ -979,11 +999,18 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
979 return -EINVAL; 999 return -EINVAL;
980 } 1000 }
981 1001
982 if (tiling_flags & RADEON_TILING_MACRO) 1002 if (rdev->family >= CHIP_R600) {
983 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1003 if (tiling_flags & RADEON_TILING_MACRO)
1004 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1005 else if (tiling_flags & RADEON_TILING_MICRO)
1006 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1007 } else {
1008 if (tiling_flags & RADEON_TILING_MACRO)
1009 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
984 1010
985 if (tiling_flags & RADEON_TILING_MICRO) 1011 if (tiling_flags & RADEON_TILING_MICRO)
986 fb_format |= AVIVO_D1GRPH_TILED; 1012 fb_format |= AVIVO_D1GRPH_TILED;
1013 }
987 1014
988 if (radeon_crtc->crtc_id == 0) 1015 if (radeon_crtc->crtc_id == 0)
989 WREG32(AVIVO_D1VGA_CONTROL, 0); 1016 WREG32(AVIVO_D1VGA_CONTROL, 0);
@@ -1143,10 +1170,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1143 atombios_crtc_set_pll(crtc, adjusted_mode); 1170 atombios_crtc_set_pll(crtc, adjusted_mode);
1144 atombios_enable_ss(crtc); 1171 atombios_enable_ss(crtc);
1145 1172
1146 if (ASIC_IS_DCE4(rdev)) 1173 if (ASIC_IS_AVIVO(rdev))
1147 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1174 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1148 else if (ASIC_IS_AVIVO(rdev))
1149 atombios_crtc_set_timing(crtc, adjusted_mode);
1150 else { 1175 else {
1151 atombios_crtc_set_timing(crtc, adjusted_mode); 1176 atombios_crtc_set_timing(crtc, adjusted_mode);
1152 if (radeon_crtc->crtc_id == 0) 1177 if (radeon_crtc->crtc_id == 0)
@@ -1191,6 +1216,24 @@ static void atombios_crtc_commit(struct drm_crtc *crtc)
1191 atombios_lock_crtc(crtc, ATOM_DISABLE); 1216 atombios_lock_crtc(crtc, ATOM_DISABLE);
1192} 1217}
1193 1218
1219static void atombios_crtc_disable(struct drm_crtc *crtc)
1220{
1221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1222 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1223
1224 switch (radeon_crtc->pll_id) {
1225 case ATOM_PPLL1:
1226 case ATOM_PPLL2:
1227 /* disable the ppll */
1228 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1229 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1230 break;
1231 default:
1232 break;
1233 }
1234 radeon_crtc->pll_id = -1;
1235}
1236
1194static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1237static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1195 .dpms = atombios_crtc_dpms, 1238 .dpms = atombios_crtc_dpms,
1196 .mode_fixup = atombios_crtc_mode_fixup, 1239 .mode_fixup = atombios_crtc_mode_fixup,
@@ -1199,6 +1242,7 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1199 .prepare = atombios_crtc_prepare, 1242 .prepare = atombios_crtc_prepare,
1200 .commit = atombios_crtc_commit, 1243 .commit = atombios_crtc_commit,
1201 .load_lut = radeon_crtc_load_lut, 1244 .load_lut = radeon_crtc_load_lut,
1245 .disable = atombios_crtc_disable,
1202}; 1246};
1203 1247
1204void radeon_atombios_init_crtc(struct drm_device *dev, 1248void radeon_atombios_init_crtc(struct drm_device *dev,
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index abffb1499e22..36e0d4b545e6 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -296,7 +296,7 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
296 u8 this_v = dp_get_adjust_request_voltage(link_status, lane); 296 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
297 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); 297 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
298 298
299 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n", 299 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
300 lane, 300 lane,
301 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 301 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
302 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 302 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
@@ -313,7 +313,7 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
313 if (p >= dp_pre_emphasis_max(v)) 313 if (p >= dp_pre_emphasis_max(v))
314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315 315
316 DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n", 316 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
318 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 318 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
319 319
@@ -358,7 +358,7 @@ retry:
358 if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { 358 if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) {
359 if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) 359 if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10)
360 goto retry; 360 goto retry;
361 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n", 361 DRM_DEBUG_KMS("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
362 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], 362 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
363 chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count); 363 chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count);
364 return false; 364 return false;
@@ -461,10 +461,10 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
461 memcpy(dig_connector->dpcd, msg, 8); 461 memcpy(dig_connector->dpcd, msg, 8);
462 { 462 {
463 int i; 463 int i;
464 DRM_DEBUG("DPCD: "); 464 DRM_DEBUG_KMS("DPCD: ");
465 for (i = 0; i < 8; i++) 465 for (i = 0; i < 8; i++)
466 DRM_DEBUG("%02x ", msg[i]); 466 DRM_DEBUG_KMS("%02x ", msg[i]);
467 DRM_DEBUG("\n"); 467 DRM_DEBUG_KMS("\n");
468 } 468 }
469 return true; 469 return true;
470 } 470 }
@@ -512,7 +512,7 @@ static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
512 return false; 512 return false;
513 } 513 }
514 514
515 DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n", 515 DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n",
516 link_status[0], link_status[1], link_status[2], 516 link_status[0], link_status[1], link_status[2],
517 link_status[3], link_status[4], link_status[5]); 517 link_status[3], link_status[4], link_status[5]);
518 return true; 518 return true;
@@ -695,7 +695,7 @@ void dp_link_train(struct drm_encoder *encoder,
695 if (!clock_recovery) 695 if (!clock_recovery)
696 DRM_ERROR("clock recovery failed\n"); 696 DRM_ERROR("clock recovery failed\n");
697 else 697 else
698 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n", 698 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
699 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 699 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
700 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 700 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
701 DP_TRAIN_PRE_EMPHASIS_SHIFT); 701 DP_TRAIN_PRE_EMPHASIS_SHIFT);
@@ -739,7 +739,7 @@ void dp_link_train(struct drm_encoder *encoder,
739 if (!channel_eq) 739 if (!channel_eq)
740 DRM_ERROR("channel eq failed\n"); 740 DRM_ERROR("channel eq failed\n");
741 else 741 else
742 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n", 742 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
743 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 743 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
744 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 744 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
745 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 745 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 1caf625e472b..957d5067ad9c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -39,6 +39,23 @@
39static void evergreen_gpu_init(struct radeon_device *rdev); 39static void evergreen_gpu_init(struct radeon_device *rdev);
40void evergreen_fini(struct radeon_device *rdev); 40void evergreen_fini(struct radeon_device *rdev);
41 41
42/* get temperature in millidegrees */
43u32 evergreen_get_temp(struct radeon_device *rdev)
44{
45 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
46 ASIC_T_SHIFT;
47 u32 actual_temp = 0;
48
49 if ((temp >> 10) & 1)
50 actual_temp = 0;
51 else if ((temp >> 9) & 1)
52 actual_temp = 255;
53 else
54 actual_temp = (temp >> 1) & 0xff;
55
56 return actual_temp * 1000;
57}
58
42void evergreen_pm_misc(struct radeon_device *rdev) 59void evergreen_pm_misc(struct radeon_device *rdev)
43{ 60{
44 int req_ps_idx = rdev->pm.requested_power_state_index; 61 int req_ps_idx = rdev->pm.requested_power_state_index;
@@ -1115,6 +1132,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1115 rdev->config.evergreen.max_backends) & 1132 rdev->config.evergreen.max_backends) &
1116 EVERGREEN_MAX_BACKENDS_MASK)); 1133 EVERGREEN_MAX_BACKENDS_MASK));
1117 1134
1135 rdev->config.evergreen.tile_config = gb_addr_config;
1118 WREG32(GB_BACKEND_MAP, gb_backend_map); 1136 WREG32(GB_BACKEND_MAP, gb_backend_map);
1119 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1137 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1120 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1138 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
@@ -1334,8 +1352,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
1334 } 1352 }
1335 rdev->mc.vram_width = numchan * chansize; 1353 rdev->mc.vram_width = numchan * chansize;
1336 /* Could aper size report 0 ? */ 1354 /* Could aper size report 0 ? */
1337 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1355 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1338 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1356 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1339 /* Setup GPU memory space */ 1357 /* Setup GPU memory space */
1340 /* size in MB on evergreen */ 1358 /* size in MB on evergreen */
1341 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1359 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index e028c1cd9d9b..2330f3a36fd5 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -61,6 +61,11 @@
61# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 61# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
62# define EVERGREEN_GRPH_FORMAT_RGB111110 6 62# define EVERGREEN_GRPH_FORMAT_RGB111110 6
63# define EVERGREEN_GRPH_FORMAT_BGR101111 7 63# define EVERGREEN_GRPH_FORMAT_BGR101111 7
64# define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
65# define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0
66# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
67# define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2
68# define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4
64#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c 69#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
65# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 70# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
66# define EVERGREEN_GRPH_ENDIAN_NONE 0 71# define EVERGREEN_GRPH_ENDIAN_NONE 0
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index a1cd621780e2..9b7532dd30f7 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -165,6 +165,11 @@
165#define SE_DB_BUSY (1 << 30) 165#define SE_DB_BUSY (1 << 30)
166#define SE_CB_BUSY (1 << 31) 166#define SE_CB_BUSY (1 << 31)
167 167
168#define CG_MULT_THERMAL_STATUS 0x740
169#define ASIC_T(x) ((x) << 16)
170#define ASIC_T_MASK 0x7FF0000
171#define ASIC_T_SHIFT 16
172
168#define HDP_HOST_PATH_CNTL 0x2C00 173#define HDP_HOST_PATH_CNTL 0x2C00
169#define HDP_NONSURFACE_BASE 0x2C04 174#define HDP_NONSURFACE_BASE 0x2C04
170#define HDP_NONSURFACE_INFO 0x2C08 175#define HDP_NONSURFACE_INFO 0x2C08
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index a89a15ab524d..e817a0bb5eb4 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -141,7 +141,7 @@ void r100_pm_get_dynpm_state(struct radeon_device *rdev)
141 /* only one clock mode per power state */ 141 /* only one clock mode per power state */
142 rdev->pm.requested_clock_mode_index = 0; 142 rdev->pm.requested_clock_mode_index = 0;
143 143
144 DRM_DEBUG("Requested: e: %d m: %d p: %d\n", 144 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
145 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 145 rdev->pm.power_state[rdev->pm.requested_power_state_index].
146 clock_info[rdev->pm.requested_clock_mode_index].sclk, 146 clock_info[rdev->pm.requested_clock_mode_index].sclk,
147 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 147 rdev->pm.power_state[rdev->pm.requested_power_state_index].
@@ -276,7 +276,7 @@ void r100_pm_misc(struct radeon_device *rdev)
276 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 276 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
277 radeon_set_pcie_lanes(rdev, 277 radeon_set_pcie_lanes(rdev,
278 ps->pcie_lanes); 278 ps->pcie_lanes);
279 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 279 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
280 } 280 }
281} 281}
282 282
@@ -849,7 +849,7 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
849 const char *fw_name = NULL; 849 const char *fw_name = NULL;
850 int err; 850 int err;
851 851
852 DRM_DEBUG("\n"); 852 DRM_DEBUG_KMS("\n");
853 853
854 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 854 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
855 err = IS_ERR(pdev); 855 err = IS_ERR(pdev);
@@ -1803,6 +1803,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1803 return r; 1803 return r;
1804 break; 1804 break;
1805 /* triggers drawing using indices to vertex buffer */ 1805 /* triggers drawing using indices to vertex buffer */
1806 case PACKET3_3D_CLEAR_HIZ:
1807 case PACKET3_3D_CLEAR_ZMASK:
1808 if (p->rdev->hyperz_filp != p->filp)
1809 return -EINVAL;
1810 break;
1806 case PACKET3_NOP: 1811 case PACKET3_NOP:
1807 break; 1812 break;
1808 default: 1813 default:
@@ -2295,8 +2300,8 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
2295 u64 config_aper_size; 2300 u64 config_aper_size;
2296 2301
2297 /* work out accessible VRAM */ 2302 /* work out accessible VRAM */
2298 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 2303 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2299 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 2304 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2300 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2305 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2301 /* FIXME we don't use the second aperture yet when we could use it */ 2306 /* FIXME we don't use the second aperture yet when we could use it */
2302 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2307 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
@@ -2364,11 +2369,10 @@ void r100_mc_init(struct radeon_device *rdev)
2364 */ 2369 */
2365void r100_pll_errata_after_index(struct radeon_device *rdev) 2370void r100_pll_errata_after_index(struct radeon_device *rdev)
2366{ 2371{
2367 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { 2372 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2368 return; 2373 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2374 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2369 } 2375 }
2370 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2371 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2372} 2376}
2373 2377
2374static void r100_pll_errata_after_data(struct radeon_device *rdev) 2378static void r100_pll_errata_after_data(struct radeon_device *rdev)
@@ -2643,7 +2647,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2643 flags |= pitch / 8; 2647 flags |= pitch / 8;
2644 2648
2645 2649
2646 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2650 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2647 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2651 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2648 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2652 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2649 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2653 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
@@ -3039,7 +3043,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
3039 } 3043 }
3040#endif 3044#endif
3041 3045
3042 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", 3046 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3043 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3047 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3044 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3048 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3045 } 3049 }
@@ -3135,7 +3139,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
3135 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3139 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3136 } 3140 }
3137 3141
3138 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", 3142 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3139 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3143 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3140 } 3144 }
3141} 3145}
@@ -3809,6 +3813,31 @@ void r100_fini(struct radeon_device *rdev)
3809 rdev->bios = NULL; 3813 rdev->bios = NULL;
3810} 3814}
3811 3815
3816/*
3817 * Due to how kexec works, it can leave the hw fully initialised when it
3818 * boots the new kernel. However doing our init sequence with the CP and
3819 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3820 * do some quick sanity checks and restore sane values to avoid this
3821 * problem.
3822 */
3823void r100_restore_sanity(struct radeon_device *rdev)
3824{
3825 u32 tmp;
3826
3827 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3828 if (tmp) {
3829 WREG32(RADEON_CP_CSQ_CNTL, 0);
3830 }
3831 tmp = RREG32(RADEON_CP_RB_CNTL);
3832 if (tmp) {
3833 WREG32(RADEON_CP_RB_CNTL, 0);
3834 }
3835 tmp = RREG32(RADEON_SCRATCH_UMSK);
3836 if (tmp) {
3837 WREG32(RADEON_SCRATCH_UMSK, 0);
3838 }
3839}
3840
3812int r100_init(struct radeon_device *rdev) 3841int r100_init(struct radeon_device *rdev)
3813{ 3842{
3814 int r; 3843 int r;
@@ -3821,6 +3850,8 @@ int r100_init(struct radeon_device *rdev)
3821 radeon_scratch_init(rdev); 3850 radeon_scratch_init(rdev);
3822 /* Initialize surface registers */ 3851 /* Initialize surface registers */
3823 radeon_surface_init(rdev); 3852 radeon_surface_init(rdev);
3853 /* sanity check some register to avoid hangs like after kexec */
3854 r100_restore_sanity(rdev);
3824 /* TODO: disable VGA need to use VGA request */ 3855 /* TODO: disable VGA need to use VGA request */
3825 /* BIOS*/ 3856 /* BIOS*/
3826 if (!radeon_get_bios(rdev)) { 3857 if (!radeon_get_bios(rdev)) {
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index d016b16fa116..b121b6c678d4 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -48,10 +48,12 @@
48#define PACKET3_3D_DRAW_IMMD 0x29 48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A 49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F 50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_3D_CLEAR_ZMASK 0x32
51#define PACKET3_INDX_BUFFER 0x33 52#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34 53#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35 54#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36 55#define PACKET3_3D_DRAW_INDX_2 0x36
56#define PACKET3_3D_CLEAR_HIZ 0x37
55#define PACKET3_BITBLT_MULTI 0x9B 57#define PACKET3_BITBLT_MULTI 0x9B
56 58
57#define PACKET0(reg, n) (CP_PACKET0 | \ 59#define PACKET0(reg, n) (CP_PACKET0 | \
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 19a7ef7ee344..c827738ad7dd 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1048,14 +1048,47 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1048 /* RB3D_COLOR_CHANNEL_MASK */ 1048 /* RB3D_COLOR_CHANNEL_MASK */
1049 track->color_channel_mask = idx_value; 1049 track->color_channel_mask = idx_value;
1050 break; 1050 break;
1051 case 0x4d1c: 1051 case 0x43a4:
1052 /* SC_HYPERZ_EN */
1053 /* r300c emits this register - we need to disable hyperz for it
1054 * without complaining */
1055 if (p->rdev->hyperz_filp != p->filp) {
1056 if (idx_value & 0x1)
1057 ib[idx] = idx_value & ~1;
1058 }
1059 break;
1060 case 0x4f1c:
1052 /* ZB_BW_CNTL */ 1061 /* ZB_BW_CNTL */
1053 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1062 track->zb_cb_clear = !!(idx_value & (1 << 5));
1063 if (p->rdev->hyperz_filp != p->filp) {
1064 if (idx_value & (R300_HIZ_ENABLE |
1065 R300_RD_COMP_ENABLE |
1066 R300_WR_COMP_ENABLE |
1067 R300_FAST_FILL_ENABLE))
1068 goto fail;
1069 }
1054 break; 1070 break;
1055 case 0x4e04: 1071 case 0x4e04:
1056 /* RB3D_BLENDCNTL */ 1072 /* RB3D_BLENDCNTL */
1057 track->blend_read_enable = !!(idx_value & (1 << 2)); 1073 track->blend_read_enable = !!(idx_value & (1 << 2));
1058 break; 1074 break;
1075 case 0x4f28: /* ZB_DEPTHCLEARVALUE */
1076 break;
1077 case 0x4f30: /* ZB_MASK_OFFSET */
1078 case 0x4f34: /* ZB_ZMASK_PITCH */
1079 case 0x4f44: /* ZB_HIZ_OFFSET */
1080 case 0x4f54: /* ZB_HIZ_PITCH */
1081 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1082 goto fail;
1083 break;
1084 case 0x4028:
1085 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1086 goto fail;
1087 /* GB_Z_PEQ_CONFIG */
1088 if (p->rdev->family >= CHIP_RV350)
1089 break;
1090 goto fail;
1091 break;
1059 case 0x4be8: 1092 case 0x4be8:
1060 /* valid register only on RV530 */ 1093 /* valid register only on RV530 */
1061 if (p->rdev->family == CHIP_RV530) 1094 if (p->rdev->family == CHIP_RV530)
@@ -1066,8 +1099,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1066 } 1099 }
1067 return 0; 1100 return 0;
1068fail: 1101fail:
1069 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1102 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1070 reg, idx); 1103 reg, idx, idx_value);
1071 return -EINVAL; 1104 return -EINVAL;
1072} 1105}
1073 1106
@@ -1161,6 +1194,11 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1161 return r; 1194 return r;
1162 } 1195 }
1163 break; 1196 break;
1197 case PACKET3_3D_CLEAR_HIZ:
1198 case PACKET3_3D_CLEAR_ZMASK:
1199 if (p->rdev->hyperz_filp != p->filp)
1200 return -EINVAL;
1201 break;
1164 case PACKET3_NOP: 1202 case PACKET3_NOP:
1165 break; 1203 break;
1166 default: 1204 default:
@@ -1380,6 +1418,8 @@ int r300_init(struct radeon_device *rdev)
1380 /* Initialize surface registers */ 1418 /* Initialize surface registers */
1381 radeon_surface_init(rdev); 1419 radeon_surface_init(rdev);
1382 /* TODO: disable VGA need to use VGA request */ 1420 /* TODO: disable VGA need to use VGA request */
1421 /* restore some register to sane defaults */
1422 r100_restore_sanity(rdev);
1383 /* BIOS*/ 1423 /* BIOS*/
1384 if (!radeon_get_bios(rdev)) { 1424 if (!radeon_get_bios(rdev)) {
1385 if (ASIC_IS_AVIVO(rdev)) 1425 if (ASIC_IS_AVIVO(rdev))
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
index 968a33317fbf..0c036c60d9df 100644
--- a/drivers/gpu/drm/radeon/r300d.h
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -48,10 +48,12 @@
48#define PACKET3_3D_DRAW_IMMD 0x29 48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A 49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F 50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_3D_CLEAR_ZMASK 0x32
51#define PACKET3_INDX_BUFFER 0x33 52#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34 53#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35 54#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36 55#define PACKET3_3D_DRAW_INDX_2 0x36
56#define PACKET3_3D_CLEAR_HIZ 0x37
55#define PACKET3_BITBLT_MULTI 0x9B 57#define PACKET3_BITBLT_MULTI 0x9B
56 58
57#define PACKET0(reg, n) (CP_PACKET0 | \ 59#define PACKET0(reg, n) (CP_PACKET0 | \
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index e6c89142bb4d..59f7bccc5be0 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -343,6 +343,8 @@ int r420_init(struct radeon_device *rdev)
343 /* Initialize surface registers */ 343 /* Initialize surface registers */
344 radeon_surface_init(rdev); 344 radeon_surface_init(rdev);
345 /* TODO: disable VGA need to use VGA request */ 345 /* TODO: disable VGA need to use VGA request */
346 /* restore some register to sane defaults */
347 r100_restore_sanity(rdev);
346 /* BIOS*/ 348 /* BIOS*/
347 if (!radeon_get_bios(rdev)) { 349 if (!radeon_get_bios(rdev)) {
348 if (ASIC_IS_AVIVO(rdev)) 350 if (ASIC_IS_AVIVO(rdev))
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 93c9a2bbccf8..6ac1f604e29b 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -386,6 +386,11 @@
386# define AVIVO_D1GRPH_TILED (1 << 20) 386# define AVIVO_D1GRPH_TILED (1 << 20)
387# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) 387# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
388 388
389# define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
390# define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
391# define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
392# define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)
393
389/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 394/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
390 * block and vice versa. This applies to GRPH, CUR, etc. 395 * block and vice versa. This applies to GRPH, CUR, etc.
391 */ 396 */
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 694af7cc23ac..1458dee902dd 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -231,6 +231,8 @@ int r520_init(struct radeon_device *rdev)
231 radeon_scratch_init(rdev); 231 radeon_scratch_init(rdev);
232 /* Initialize surface registers */ 232 /* Initialize surface registers */
233 radeon_surface_init(rdev); 233 radeon_surface_init(rdev);
234 /* restore some register to sane defaults */
235 r100_restore_sanity(rdev);
234 /* TODO: disable VGA need to use VGA request */ 236 /* TODO: disable VGA need to use VGA request */
235 /* BIOS*/ 237 /* BIOS*/
236 if (!radeon_get_bios(rdev)) { 238 if (!radeon_get_bios(rdev)) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e100f69faeec..d0ebae9dde25 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -92,6 +92,21 @@ void r600_gpu_init(struct radeon_device *rdev);
92void r600_fini(struct radeon_device *rdev); 92void r600_fini(struct radeon_device *rdev);
93void r600_irq_disable(struct radeon_device *rdev); 93void r600_irq_disable(struct radeon_device *rdev);
94 94
95/* get temperature in millidegrees */
96u32 rv6xx_get_temp(struct radeon_device *rdev)
97{
98 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
99 ASIC_T_SHIFT;
100 u32 actual_temp = 0;
101
102 if ((temp >> 7) & 1)
103 actual_temp = 0;
104 else
105 actual_temp = (temp >> 1) & 0xff;
106
107 return actual_temp * 1000;
108}
109
95void r600_pm_get_dynpm_state(struct radeon_device *rdev) 110void r600_pm_get_dynpm_state(struct radeon_device *rdev)
96{ 111{
97 int i; 112 int i;
@@ -256,7 +271,7 @@ void r600_pm_get_dynpm_state(struct radeon_device *rdev)
256 } 271 }
257 } 272 }
258 273
259 DRM_DEBUG("Requested: e: %d m: %d p: %d\n", 274 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
260 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 275 rdev->pm.power_state[rdev->pm.requested_power_state_index].
261 clock_info[rdev->pm.requested_clock_mode_index].sclk, 276 clock_info[rdev->pm.requested_clock_mode_index].sclk,
262 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 277 rdev->pm.power_state[rdev->pm.requested_power_state_index].
@@ -571,7 +586,7 @@ void r600_pm_misc(struct radeon_device *rdev)
571 if (voltage->voltage != rdev->pm.current_vddc) { 586 if (voltage->voltage != rdev->pm.current_vddc) {
572 radeon_atom_set_voltage(rdev, voltage->voltage); 587 radeon_atom_set_voltage(rdev, voltage->voltage);
573 rdev->pm.current_vddc = voltage->voltage; 588 rdev->pm.current_vddc = voltage->voltage;
574 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 589 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
575 } 590 }
576 } 591 }
577} 592}
@@ -869,7 +884,17 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
869 u32 tmp; 884 u32 tmp;
870 885
871 /* flush hdp cache so updates hit vram */ 886 /* flush hdp cache so updates hit vram */
872 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 887 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
888 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
889 u32 tmp;
890
891 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
892 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
893 */
894 WREG32(HDP_DEBUG1, 0);
895 tmp = readl((void __iomem *)ptr);
896 } else
897 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
873 898
874 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 899 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
875 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 900 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
@@ -1217,8 +1242,8 @@ int r600_mc_init(struct radeon_device *rdev)
1217 } 1242 }
1218 rdev->mc.vram_width = numchan * chansize; 1243 rdev->mc.vram_width = numchan * chansize;
1219 /* Could aper size report 0 ? */ 1244 /* Could aper size report 0 ? */
1220 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1245 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1221 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1246 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1222 /* Setup GPU memory space */ 1247 /* Setup GPU memory space */
1223 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1224 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
@@ -1609,7 +1634,7 @@ void r600_gpu_init(struct radeon_device *rdev)
1609 r600_count_pipe_bits((cc_rb_backend_disable & 1634 r600_count_pipe_bits((cc_rb_backend_disable &
1610 R6XX_MAX_BACKENDS_MASK) >> 16)), 1635 R6XX_MAX_BACKENDS_MASK) >> 16)),
1611 (cc_rb_backend_disable >> 16)); 1636 (cc_rb_backend_disable >> 16));
1612 1637 rdev->config.r600.tile_config = tiling_config;
1613 tiling_config |= BACKEND_MAP(backend_map); 1638 tiling_config |= BACKEND_MAP(backend_map);
1614 WREG32(GB_TILING_CONFIG, tiling_config); 1639 WREG32(GB_TILING_CONFIG, tiling_config);
1615 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1640 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
@@ -3512,5 +3537,15 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3512 */ 3537 */
3513void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 3538void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3514{ 3539{
3515 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 3540 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3541 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3542 */
3543 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
3544 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
3545 u32 tmp;
3546
3547 WREG32(HDP_DEBUG1, 0);
3548 tmp = readl((void __iomem *)ptr);
3549 } else
3550 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3516} 3551}
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 2b26553c352c..b5443fe1c1d1 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -63,7 +63,8 @@ int r600_audio_bits_per_sample(struct radeon_device *rdev)
63 case 0x4: return 32; 63 case 0x4: return 32;
64 } 64 }
65 65
66 DRM_ERROR("Unknown bits per sample 0x%x using 16 instead.\n", (int)value); 66 dev_err(rdev->dev, "Unknown bits per sample 0x%x using 16 instead\n",
67 (int)value);
67 68
68 return 16; 69 return 16;
69} 70}
@@ -150,7 +151,8 @@ static void r600_audio_update_hdmi(unsigned long param)
150 r600_hdmi_update_audio_settings(encoder); 151 r600_hdmi_update_audio_settings(encoder);
151 } 152 }
152 153
153 if(still_going) r600_audio_schedule_polling(rdev); 154 if (still_going)
155 r600_audio_schedule_polling(rdev);
154} 156}
155 157
156/* 158/*
@@ -158,8 +160,9 @@ static void r600_audio_update_hdmi(unsigned long param)
158 */ 160 */
159static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable) 161static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable)
160{ 162{
161 DRM_INFO("%s audio support", enable ? "Enabling" : "Disabling"); 163 DRM_INFO("%s audio support\n", enable ? "Enabling" : "Disabling");
162 WREG32_P(R600_AUDIO_ENABLE, enable ? 0x81000000 : 0x0, ~0x81000000); 164 WREG32_P(R600_AUDIO_ENABLE, enable ? 0x81000000 : 0x0, ~0x81000000);
165 rdev->audio_enabled = enable;
163} 166}
164 167
165/* 168/*
@@ -195,12 +198,14 @@ void r600_audio_enable_polling(struct drm_encoder *encoder)
195 struct radeon_device *rdev = dev->dev_private; 198 struct radeon_device *rdev = dev->dev_private;
196 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
197 200
198 DRM_DEBUG("r600_audio_enable_polling: %d", radeon_encoder->audio_polling_active); 201 DRM_DEBUG("r600_audio_enable_polling: %d\n",
202 radeon_encoder->audio_polling_active);
199 if (radeon_encoder->audio_polling_active) 203 if (radeon_encoder->audio_polling_active)
200 return; 204 return;
201 205
202 radeon_encoder->audio_polling_active = 1; 206 radeon_encoder->audio_polling_active = 1;
203 mod_timer(&rdev->audio_timer, jiffies + 1); 207 if (rdev->audio_enabled)
208 mod_timer(&rdev->audio_timer, jiffies + 1);
204} 209}
205 210
206/* 211/*
@@ -209,7 +214,8 @@ void r600_audio_enable_polling(struct drm_encoder *encoder)
209void r600_audio_disable_polling(struct drm_encoder *encoder) 214void r600_audio_disable_polling(struct drm_encoder *encoder)
210{ 215{
211 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 216 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
212 DRM_DEBUG("r600_audio_disable_polling: %d", radeon_encoder->audio_polling_active); 217 DRM_DEBUG("r600_audio_disable_polling: %d\n",
218 radeon_encoder->audio_polling_active);
213 radeon_encoder->audio_polling_active = 0; 219 radeon_encoder->audio_polling_active = 0;
214} 220}
215 221
@@ -236,7 +242,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
236 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301); 242 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
237 break; 243 break;
238 default: 244 default:
239 DRM_ERROR("Unsupported encoder type 0x%02X\n", 245 dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",
240 radeon_encoder->encoder_id); 246 radeon_encoder->encoder_id);
241 return; 247 return;
242 } 248 }
@@ -266,7 +272,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
266 */ 272 */
267void r600_audio_fini(struct radeon_device *rdev) 273void r600_audio_fini(struct radeon_device *rdev)
268{ 274{
269 if (!radeon_audio || !r600_audio_chipset_supported(rdev)) 275 if (!rdev->audio_enabled)
270 return; 276 return;
271 277
272 del_timer(&rdev->audio_timer); 278 del_timer(&rdev->audio_timer);
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
index 0271b53fa2dd..e8151c1d55b2 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.c
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -39,37 +39,45 @@
39 39
40const u32 r6xx_default_state[] = 40const u32 r6xx_default_state[] =
41{ 41{
42 0xc0002400, 42 0xc0002400, /* START_3D_CMDBUF */
43 0x00000000, 43 0x00000000,
44 0xc0012800, 44
45 0xc0012800, /* CONTEXT_CONTROL */
45 0x80000000, 46 0x80000000,
46 0x80000000, 47 0x80000000,
48
47 0xc0016800, 49 0xc0016800,
48 0x00000010, 50 0x00000010,
49 0x00008000, 51 0x00008000, /* WAIT_UNTIL */
52
50 0xc0016800, 53 0xc0016800,
51 0x00000542, 54 0x00000542,
52 0x07000003, 55 0x07000003, /* TA_CNTL_AUX */
56
53 0xc0016800, 57 0xc0016800,
54 0x000005c5, 58 0x000005c5,
55 0x00000000, 59 0x00000000, /* VC_ENHANCE */
60
56 0xc0016800, 61 0xc0016800,
57 0x00000363, 62 0x00000363,
58 0x00000000, 63 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
64
59 0xc0016800, 65 0xc0016800,
60 0x0000060c, 66 0x0000060c,
61 0x82000000, 67 0x82000000, /* DB_DEBUG */
68
62 0xc0016800, 69 0xc0016800,
63 0x0000060e, 70 0x0000060e,
64 0x01020204, 71 0x01020204, /* DB_WATERMARKS */
65 0xc0016f00, 72
66 0x00000000, 73 0xc0026f00,
67 0x00000000,
68 0xc0016f00,
69 0x00000001,
70 0x00000000, 74 0x00000000,
75 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
76 0x00000000, /* SQ_VTX_START_INST_LOC */
77
71 0xc0096900, 78 0xc0096900,
72 0x0000022a, 79 0x0000022a,
80 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
73 0x00000000, 81 0x00000000,
74 0x00000000, 82 0x00000000,
75 0x00000000, 83 0x00000000,
@@ -78,515 +86,317 @@ const u32 r6xx_default_state[] =
78 0x00000000, 86 0x00000000,
79 0x00000000, 87 0x00000000,
80 0x00000000, 88 0x00000000,
81 0x00000000, 89
82 0xc0016900, 90 0xc0016900,
83 0x00000004, 91 0x00000004,
84 0x00000000, 92 0x00000000, /* DB_DEPTH_INFO */
85 0xc0016900, 93
94 0xc0026900,
86 0x0000000a, 95 0x0000000a,
87 0x00000000, 96 0x00000000, /* DB_STENCIL_CLEAR */
88 0xc0016900, 97 0x00000000, /* DB_DEPTH_CLEAR */
89 0x0000000b, 98
90 0x00000000,
91 0xc0016900,
92 0x0000010c,
93 0x00000000,
94 0xc0016900,
95 0x0000010d,
96 0x00000000,
97 0xc0016900, 99 0xc0016900,
98 0x00000200, 100 0x00000200,
99 0x00000000, 101 0x00000000, /* DB_DEPTH_CONTROL */
100 0xc0016900, 102
103 0xc0026900,
101 0x00000343, 104 0x00000343,
102 0x00000060, 105 0x00000060, /* DB_RENDER_CONTROL */
103 0xc0016900, 106 0x00000040, /* DB_RENDER_OVERRIDE */
104 0x00000344, 107
105 0x00000040,
106 0xc0016900, 108 0xc0016900,
107 0x00000351, 109 0x00000351,
108 0x0000aa00, 110 0x0000aa00, /* DB_ALPHA_TO_MASK */
109 0xc0016900, 111
110 0x00000104, 112 0xc00f6900,
111 0x00000000, 113 0x00000100,
112 0xc0016900, 114 0x00000800, /* VGT_MAX_VTX_INDX */
113 0x0000010e, 115 0x00000000, /* VGT_MIN_VTX_INDX */
114 0x00000000, 116 0x00000000, /* VGT_INDX_OFFSET */
115 0xc0046900, 117 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
116 0x00000105, 118 0x00000000, /* SX_ALPHA_TEST_CONTROL */
117 0x00000000, 119 0x00000000, /* CB_BLEND_RED */
118 0x00000000,
119 0x00000000, 120 0x00000000,
120 0x00000000, 121 0x00000000,
121 0xc0036900,
122 0x00000109,
123 0x00000000, 122 0x00000000,
123 0x00000000, /* CB_FOG_RED */
124 0x00000000, 124 0x00000000,
125 0x00000000, 125 0x00000000,
126 0x00000000, /* DB_STENCILREFMASK */
127 0x00000000, /* DB_STENCILREFMASK_BF */
128 0x00000000, /* SX_ALPHA_REF */
129
126 0xc0046900, 130 0xc0046900,
127 0x0000030c, 131 0x0000030c,
128 0x01000000, 132 0x01000000, /* CB_CLRCMP_CNTL */
129 0x00000000, 133 0x00000000,
130 0x00000000, 134 0x00000000,
131 0x00000000, 135 0x00000000,
136
132 0xc0046900, 137 0xc0046900,
133 0x00000048, 138 0x00000048,
134 0x3f800000, 139 0x3f800000, /* CB_CLEAR_RED */
135 0x00000000, 140 0x00000000,
136 0x3f800000, 141 0x3f800000,
137 0x3f800000, 142 0x3f800000,
138 0xc0016900, 143
139 0x0000008e,
140 0x0000000f,
141 0xc0016900, 144 0xc0016900,
142 0x00000080, 145 0x00000080,
143 0x00000000, 146 0x00000000, /* PA_SC_WINDOW_OFFSET */
144 0xc0016900, 147
148 0xc00a6900,
145 0x00000083, 149 0x00000083,
146 0x0000ffff, 150 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
147 0xc0016900, 151 0x00000000, /* PA_SC_CLIPRECT_0_TL */
148 0x00000084,
149 0x00000000,
150 0xc0016900,
151 0x00000085,
152 0x20002000, 152 0x20002000,
153 0xc0016900,
154 0x00000086,
155 0x00000000, 153 0x00000000,
156 0xc0016900,
157 0x00000087,
158 0x20002000, 154 0x20002000,
159 0xc0016900,
160 0x00000088,
161 0x00000000, 155 0x00000000,
162 0xc0016900,
163 0x00000089,
164 0x20002000, 156 0x20002000,
165 0xc0016900,
166 0x0000008a,
167 0x00000000, 157 0x00000000,
168 0xc0016900,
169 0x0000008b,
170 0x20002000, 158 0x20002000,
171 0xc0016900, 159 0x00000000, /* PA_SC_EDGERULE */
172 0x0000008c, 160
173 0x00000000, 161 0xc0406900,
174 0xc0016900,
175 0x00000094, 162 0x00000094,
176 0x80000000, 163 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
177 0xc0016900, 164 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
178 0x00000095, 165 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
179 0x20002000, 166 0x20002000,
180 0xc0026900,
181 0x000000b4,
182 0x00000000,
183 0x3f800000,
184 0xc0016900,
185 0x00000096,
186 0x80000000, 167 0x80000000,
187 0xc0016900,
188 0x00000097,
189 0x20002000, 168 0x20002000,
190 0xc0026900,
191 0x000000b6,
192 0x00000000,
193 0x3f800000,
194 0xc0016900,
195 0x00000098,
196 0x80000000, 169 0x80000000,
197 0xc0016900,
198 0x00000099,
199 0x20002000, 170 0x20002000,
200 0xc0026900,
201 0x000000b8,
202 0x00000000,
203 0x3f800000,
204 0xc0016900,
205 0x0000009a,
206 0x80000000, 171 0x80000000,
207 0xc0016900,
208 0x0000009b,
209 0x20002000, 172 0x20002000,
210 0xc0026900,
211 0x000000ba,
212 0x00000000,
213 0x3f800000,
214 0xc0016900,
215 0x0000009c,
216 0x80000000, 173 0x80000000,
217 0xc0016900,
218 0x0000009d,
219 0x20002000, 174 0x20002000,
220 0xc0026900,
221 0x000000bc,
222 0x00000000,
223 0x3f800000,
224 0xc0016900,
225 0x0000009e,
226 0x80000000, 175 0x80000000,
227 0xc0016900,
228 0x0000009f,
229 0x20002000, 176 0x20002000,
230 0xc0026900,
231 0x000000be,
232 0x00000000,
233 0x3f800000,
234 0xc0016900,
235 0x000000a0,
236 0x80000000, 177 0x80000000,
237 0xc0016900,
238 0x000000a1,
239 0x20002000, 178 0x20002000,
240 0xc0026900,
241 0x000000c0,
242 0x00000000,
243 0x3f800000,
244 0xc0016900,
245 0x000000a2,
246 0x80000000, 179 0x80000000,
247 0xc0016900,
248 0x000000a3,
249 0x20002000, 180 0x20002000,
250 0xc0026900,
251 0x000000c2,
252 0x00000000,
253 0x3f800000,
254 0xc0016900,
255 0x000000a4,
256 0x80000000, 181 0x80000000,
257 0xc0016900,
258 0x000000a5,
259 0x20002000, 182 0x20002000,
260 0xc0026900,
261 0x000000c4,
262 0x00000000,
263 0x3f800000,
264 0xc0016900,
265 0x000000a6,
266 0x80000000, 183 0x80000000,
267 0xc0016900,
268 0x000000a7,
269 0x20002000, 184 0x20002000,
270 0xc0026900,
271 0x000000c6,
272 0x00000000,
273 0x3f800000,
274 0xc0016900,
275 0x000000a8,
276 0x80000000, 185 0x80000000,
277 0xc0016900,
278 0x000000a9,
279 0x20002000, 186 0x20002000,
280 0xc0026900,
281 0x000000c8,
282 0x00000000,
283 0x3f800000,
284 0xc0016900,
285 0x000000aa,
286 0x80000000, 187 0x80000000,
287 0xc0016900,
288 0x000000ab,
289 0x20002000, 188 0x20002000,
290 0xc0026900,
291 0x000000ca,
292 0x00000000,
293 0x3f800000,
294 0xc0016900,
295 0x000000ac,
296 0x80000000, 189 0x80000000,
297 0xc0016900,
298 0x000000ad,
299 0x20002000, 190 0x20002000,
300 0xc0026900,
301 0x000000cc,
302 0x00000000,
303 0x3f800000,
304 0xc0016900,
305 0x000000ae,
306 0x80000000, 191 0x80000000,
307 0xc0016900,
308 0x000000af,
309 0x20002000, 192 0x20002000,
310 0xc0026900,
311 0x000000ce,
312 0x00000000,
313 0x3f800000,
314 0xc0016900,
315 0x000000b0,
316 0x80000000, 193 0x80000000,
317 0xc0016900,
318 0x000000b1,
319 0x20002000, 194 0x20002000,
320 0xc0026900, 195 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
321 0x000000d0,
322 0x00000000,
323 0x3f800000, 196 0x3f800000,
324 0xc0016900,
325 0x000000b2,
326 0x80000000,
327 0xc0016900,
328 0x000000b3,
329 0x20002000,
330 0xc0026900,
331 0x000000d2,
332 0x00000000, 197 0x00000000,
333 0x3f800000, 198 0x3f800000,
334 0xc0016900,
335 0x00000293,
336 0x00004010,
337 0xc0016900,
338 0x00000300,
339 0x00000000, 199 0x00000000,
340 0xc0016900, 200 0x3f800000,
341 0x00000301,
342 0x00000000,
343 0xc0016900,
344 0x00000312,
345 0xffffffff,
346 0xc0016900,
347 0x00000307,
348 0x00000000, 201 0x00000000,
349 0xc0016900, 202 0x3f800000,
350 0x00000308,
351 0x00000000, 203 0x00000000,
352 0xc0016900, 204 0x3f800000,
353 0x00000283,
354 0x00000000, 205 0x00000000,
355 0xc0016900, 206 0x3f800000,
356 0x00000292,
357 0x00000000, 207 0x00000000,
358 0xc0066900, 208 0x3f800000,
359 0x0000010f,
360 0x00000000, 209 0x00000000,
210 0x3f800000,
361 0x00000000, 211 0x00000000,
212 0x3f800000,
362 0x00000000, 213 0x00000000,
214 0x3f800000,
363 0x00000000, 215 0x00000000,
216 0x3f800000,
364 0x00000000, 217 0x00000000,
218 0x3f800000,
365 0x00000000, 219 0x00000000,
366 0xc0016900, 220 0x3f800000,
367 0x00000206,
368 0x00000000, 221 0x00000000,
369 0xc0016900, 222 0x3f800000,
370 0x00000207,
371 0x00000000, 223 0x00000000,
372 0xc0016900, 224 0x3f800000,
373 0x00000208,
374 0x00000000, 225 0x00000000,
375 0xc0046900,
376 0x00000303,
377 0x3f800000, 226 0x3f800000,
227
228 0xc0026900,
229 0x00000292,
230 0x00000000, /* PA_SC_MPASS_PS_CNTL */
231 0x00004010, /* PA_SC_MODE_CNTL */
232
233 0xc0096900,
234 0x00000300,
235 0x00000000, /* PA_SC_LINE_CNTL */
236 0x00000000, /* PA_SC_AA_CONFIG */
237 0x0000002d, /* PA_SU_VTX_CNTL */
238 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
378 0x3f800000, 239 0x3f800000,
379 0x3f800000, 240 0x3f800000,
380 0x3f800000, 241 0x3f800000,
381 0xc0016900, 242 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
382 0x00000205,
383 0x00000004,
384 0xc0016900,
385 0x00000280,
386 0x00000000,
387 0xc0016900,
388 0x00000281,
389 0x00000000, 243 0x00000000,
244
390 0xc0016900, 245 0xc0016900,
246 0x00000312,
247 0xffffffff, /* PA_SC_AA_MASK */
248
249 0xc0066900,
391 0x0000037e, 250 0x0000037e,
392 0x00000000, 251 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
393 0xc0016900, 252 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
394 0x00000382, 253 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
395 0x00000000, 254 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
396 0xc0016900, 255 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
397 0x00000380, 256 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
398 0x00000000, 257
399 0xc0016900, 258 0xc0046900,
400 0x00000383,
401 0x00000000,
402 0xc0016900,
403 0x00000381,
404 0x00000000,
405 0xc0016900,
406 0x00000282,
407 0x00000008,
408 0xc0016900,
409 0x00000302,
410 0x0000002d,
411 0xc0016900,
412 0x0000037f,
413 0x00000000,
414 0xc0016900,
415 0x000001b2,
416 0x00000000,
417 0xc0016900,
418 0x000001b6, 259 0x000001b6,
419 0x00000000, 260 0x00000000, /* SPI_INPUT_Z */
420 0xc0016900, 261 0x00000000, /* SPI_FOG_CNTL */
421 0x000001b7, 262 0x00000000, /* SPI_FOG_FUNC_SCALE */
422 0x00000000, 263 0x00000000, /* SPI_FOG_FUNC_BIAS */
423 0xc0016900, 264
424 0x000001b8,
425 0x00000000,
426 0xc0016900,
427 0x000001b9,
428 0x00000000,
429 0xc0016900, 265 0xc0016900,
430 0x00000225, 266 0x00000225,
431 0x00000000, 267 0x00000000, /* SQ_PGM_START_FS */
268
432 0xc0016900, 269 0xc0016900,
433 0x00000229, 270 0x00000229,
434 0x00000000, 271 0x00000000, /* SQ_PGM_RESOURCES_FS */
272
435 0xc0016900, 273 0xc0016900,
436 0x00000237, 274 0x00000237,
437 0x00000000, 275 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
438 0xc0016900, 276
439 0x00000100, 277 0xc0026900,
440 0x00000800,
441 0xc0016900,
442 0x00000101,
443 0x00000000,
444 0xc0016900,
445 0x00000102,
446 0x00000000,
447 0xc0016900,
448 0x000002a8, 278 0x000002a8,
449 0x00000000, 279 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
450 0xc0016900, 280 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
451 0x000002a9, 281
452 0x00000000, 282 0xc0116900,
453 0xc0016900, 283 0x00000280,
454 0x00000103, 284 0x00000000, /* PA_SU_POINT_SIZE */
455 0x00000000, 285 0x00000000, /* PA_SU_POINT_MINMAX */
456 0xc0016900, 286 0x00000008, /* PA_SU_LINE_CNTL */
457 0x00000284, 287 0x00000000, /* PA_SC_LINE_STIPPLE */
458 0x00000000, 288 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
459 0xc0016900, 289 0x00000000, /* VGT_HOS_CNTL */
460 0x00000290, 290 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
461 0x00000000, 291 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
462 0xc0016900, 292 0x00000000, /* VGT_HOS_REUSE_DEPTH */
463 0x00000285, 293 0x00000000, /* VGT_GROUP_PRIM_TYPE */
464 0x00000000, 294 0x00000000, /* VGT_GROUP_FIRST_DECR */
465 0xc0016900, 295 0x00000000, /* VGT_GROUP_DECR */
466 0x00000286, 296 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
467 0x00000000, 297 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
468 0xc0016900, 298 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
469 0x00000287, 299 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
470 0x00000000, 300 0x00000000, /* VGT_GS_MODE */
471 0xc0016900, 301
472 0x00000288,
473 0x00000000,
474 0xc0016900,
475 0x00000289,
476 0x00000000,
477 0xc0016900,
478 0x0000028a,
479 0x00000000,
480 0xc0016900,
481 0x0000028b,
482 0x00000000,
483 0xc0016900,
484 0x0000028c,
485 0x00000000,
486 0xc0016900,
487 0x0000028d,
488 0x00000000,
489 0xc0016900,
490 0x0000028e,
491 0x00000000,
492 0xc0016900,
493 0x0000028f,
494 0x00000000,
495 0xc0016900, 302 0xc0016900,
496 0x000002a1, 303 0x000002a1,
497 0x00000000, 304 0x00000000, /* VGT_PRIMITIVEID_EN */
305
498 0xc0016900, 306 0xc0016900,
499 0x000002a5, 307 0x000002a5,
500 0x00000000, 308 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
501 0xc0016900, 309
310 0xc0036900,
502 0x000002ac, 311 0x000002ac,
503 0x00000000, 312 0x00000000, /* VGT_STRMOUT_EN */
504 0xc0016900, 313 0x00000000, /* VGT_REUSE_OFF */
505 0x000002ad, 314 0x00000000, /* VGT_VTX_CNT_EN */
506 0x00000000, 315
507 0xc0016900,
508 0x000002ae,
509 0x00000000,
510 0xc0016900, 316 0xc0016900,
511 0x000002c8, 317 0x000002c8,
512 0x00000000, 318 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
513 0xc0016900, 319
514 0x00000206, 320 0xc0076900,
515 0x00000100,
516 0xc0016900,
517 0x00000204,
518 0x00010000,
519 0xc0036e00,
520 0x00000000,
521 0x00000012,
522 0x00000000,
523 0x00000000,
524 0xc0016900,
525 0x0000008f,
526 0x0000000f,
527 0xc0016900,
528 0x000001e8,
529 0x00000001,
530 0xc0016900,
531 0x00000202, 321 0x00000202,
532 0x00cc0000, 322 0x00cc0000, /* CB_COLOR_CONTROL */
323 0x00000210, /* DB_SHADER_CNTL */
324 0x00010000, /* PA_CL_CLIP_CNTL */
325 0x00000244, /* PA_SU_SC_MODE_CNTL */
326 0x00000100, /* PA_CL_VTE_CNTL */
327 0x00000000, /* PA_CL_VS_OUT_CNTL */
328 0x00000000, /* PA_CL_NANINF_CNTL */
329
330 0xc0026900,
331 0x0000008e,
332 0x0000000f, /* CB_TARGET_MASK */
333 0x0000000f, /* CB_SHADER_MASK */
334
533 0xc0016900, 335 0xc0016900,
534 0x00000205, 336 0x000001e8,
535 0x00000244, 337 0x00000001, /* CB_SHADER_CONTROL */
338
536 0xc0016900, 339 0xc0016900,
537 0x00000203, 340 0x00000185,
538 0x00000210, 341 0x00000000, /* SPI_VS_OUT_ID_0 */
342
539 0xc0016900, 343 0xc0016900,
344 0x00000191,
345 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
346
347 0xc0056900,
540 0x000001b1, 348 0x000001b1,
349 0x00000000, /* SPI_VS_OUT_CONFIG */
350 0x00000000, /* SPI_THREAD_GROUPING */
351 0x00000001, /* SPI_PS_IN_CONTROL_0 */
352 0x00000000, /* SPI_PS_IN_CONTROL_1 */
353 0x00000000, /* SPI_INTERP_CONTROL_0 */
354
355 0xc0036e00, /* SET_SAMPLER */
541 0x00000000, 356 0x00000000,
542 0xc0016900, 357 0x00000012,
543 0x00000185,
544 0x00000000,
545 0xc0016900,
546 0x000001b3,
547 0x00000001,
548 0xc0016900,
549 0x000001b4,
550 0x00000000, 358 0x00000000,
551 0xc0016900,
552 0x00000191,
553 0x00000b00,
554 0xc0016900,
555 0x000001b5,
556 0x00000000, 359 0x00000000,
557}; 360};
558 361
559const u32 r7xx_default_state[] = 362const u32 r7xx_default_state[] =
560{ 363{
561 0xc0012800, 364 0xc0012800, /* CONTEXT_CONTROL */
562 0x80000000, 365 0x80000000,
563 0x80000000, 366 0x80000000,
367
564 0xc0016800, 368 0xc0016800,
565 0x00000010, 369 0x00000010,
566 0x00008000, 370 0x00008000, /* WAIT_UNTIL */
371
567 0xc0016800, 372 0xc0016800,
568 0x00000542, 373 0x00000542,
569 0x07000002, 374 0x07000002, /* TA_CNTL_AUX */
375
570 0xc0016800, 376 0xc0016800,
571 0x000005c5, 377 0x000005c5,
572 0x00000000, 378 0x00000000, /* VC_ENHANCE */
379
573 0xc0016800, 380 0xc0016800,
574 0x00000363, 381 0x00000363,
575 0x00004000, 382 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
383
576 0xc0016800, 384 0xc0016800,
577 0x0000060c, 385 0x0000060c,
578 0x00000000, 386 0x00000000, /* DB_DEBUG */
387
579 0xc0016800, 388 0xc0016800,
580 0x0000060e, 389 0x0000060e,
581 0x00420204, 390 0x00420204, /* DB_WATERMARKS */
582 0xc0016f00, 391
583 0x00000000, 392 0xc0026f00,
584 0x00000000,
585 0xc0016f00,
586 0x00000001,
587 0x00000000, 393 0x00000000,
394 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
395 0x00000000, /* SQ_VTX_START_INST_LOC */
396
588 0xc0096900, 397 0xc0096900,
589 0x0000022a, 398 0x0000022a,
399 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
590 0x00000000, 400 0x00000000,
591 0x00000000, 401 0x00000000,
592 0x00000000, 402 0x00000000,
@@ -595,470 +405,269 @@ const u32 r7xx_default_state[] =
595 0x00000000, 405 0x00000000,
596 0x00000000, 406 0x00000000,
597 0x00000000, 407 0x00000000,
598 0x00000000, 408
599 0xc0016900, 409 0xc0016900,
600 0x00000004, 410 0x00000004,
601 0x00000000, 411 0x00000000, /* DB_DEPTH_INFO */
602 0xc0016900, 412
413 0xc0026900,
603 0x0000000a, 414 0x0000000a,
604 0x00000000, 415 0x00000000, /* DB_STENCIL_CLEAR */
605 0xc0016900, 416 0x00000000, /* DB_DEPTH_CLEAR */
606 0x0000000b, 417
607 0x00000000,
608 0xc0016900,
609 0x0000010c,
610 0x00000000,
611 0xc0016900,
612 0x0000010d,
613 0x00000000,
614 0xc0016900, 418 0xc0016900,
615 0x00000200, 419 0x00000200,
616 0x00000000, 420 0x00000000, /* DB_DEPTH_CONTROL */
617 0xc0016900, 421
422 0xc0026900,
618 0x00000343, 423 0x00000343,
619 0x00000060, 424 0x00000060, /* DB_RENDER_CONTROL */
620 0xc0016900, 425 0x00000000, /* DB_RENDER_OVERRIDE */
621 0x00000344, 426
622 0x00000000,
623 0xc0016900, 427 0xc0016900,
624 0x00000351, 428 0x00000351,
625 0x0000aa00, 429 0x0000aa00, /* DB_ALPHA_TO_MASK */
626 0xc0016900, 430
627 0x00000104, 431 0xc0096900,
628 0x00000000, 432 0x00000100,
629 0xc0016900, 433 0x00000800, /* VGT_MAX_VTX_INDX */
630 0x0000010e, 434 0x00000000, /* VGT_MIN_VTX_INDX */
631 0x00000000, 435 0x00000000, /* VGT_INDX_OFFSET */
632 0xc0046900, 436 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
633 0x00000105, 437 0x00000000, /* SX_ALPHA_TEST_CONTROL */
634 0x00000000, 438 0x00000000, /* CB_BLEND_RED */
635 0x00000000, 439 0x00000000,
636 0x00000000, 440 0x00000000,
637 0x00000000, 441 0x00000000,
442
443 0xc0036900,
444 0x0000010c,
445 0x00000000, /* DB_STENCILREFMASK */
446 0x00000000, /* DB_STENCILREFMASK_BF */
447 0x00000000, /* SX_ALPHA_REF */
448
638 0xc0046900, 449 0xc0046900,
639 0x0000030c, 450 0x0000030c, /* CB_CLRCMP_CNTL */
640 0x01000000, 451 0x01000000,
641 0x00000000, 452 0x00000000,
642 0x00000000, 453 0x00000000,
643 0x00000000, 454 0x00000000,
644 0xc0016900, 455
645 0x0000008e,
646 0x0000000f,
647 0xc0016900, 456 0xc0016900,
648 0x00000080, 457 0x00000080,
649 0x00000000, 458 0x00000000, /* PA_SC_WINDOW_OFFSET */
650 0xc0016900, 459
460 0xc00a6900,
651 0x00000083, 461 0x00000083,
652 0x0000ffff, 462 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
653 0xc0016900, 463 0x00000000, /* PA_SC_CLIPRECT_0_TL */
654 0x00000084,
655 0x00000000,
656 0xc0016900,
657 0x00000085,
658 0x20002000, 464 0x20002000,
659 0xc0016900,
660 0x00000086,
661 0x00000000, 465 0x00000000,
662 0xc0016900,
663 0x00000087,
664 0x20002000, 466 0x20002000,
665 0xc0016900,
666 0x00000088,
667 0x00000000, 467 0x00000000,
668 0xc0016900,
669 0x00000089,
670 0x20002000, 468 0x20002000,
671 0xc0016900,
672 0x0000008a,
673 0x00000000, 469 0x00000000,
674 0xc0016900,
675 0x0000008b,
676 0x20002000, 470 0x20002000,
677 0xc0016900, 471 0xaaaaaaaa, /* PA_SC_EDGERULE */
678 0x0000008c, 472
679 0xaaaaaaaa, 473 0xc0406900,
680 0xc0016900,
681 0x00000094, 474 0x00000094,
682 0x80000000, 475 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
683 0xc0016900, 476 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
684 0x00000095, 477 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
685 0x20002000, 478 0x20002000,
686 0xc0026900,
687 0x000000b4,
688 0x00000000,
689 0x3f800000,
690 0xc0016900,
691 0x00000096,
692 0x80000000, 479 0x80000000,
693 0xc0016900,
694 0x00000097,
695 0x20002000, 480 0x20002000,
696 0xc0026900,
697 0x000000b6,
698 0x00000000,
699 0x3f800000,
700 0xc0016900,
701 0x00000098,
702 0x80000000, 481 0x80000000,
703 0xc0016900,
704 0x00000099,
705 0x20002000, 482 0x20002000,
706 0xc0026900,
707 0x000000b8,
708 0x00000000,
709 0x3f800000,
710 0xc0016900,
711 0x0000009a,
712 0x80000000, 483 0x80000000,
713 0xc0016900,
714 0x0000009b,
715 0x20002000, 484 0x20002000,
716 0xc0026900,
717 0x000000ba,
718 0x00000000,
719 0x3f800000,
720 0xc0016900,
721 0x0000009c,
722 0x80000000, 485 0x80000000,
723 0xc0016900,
724 0x0000009d,
725 0x20002000, 486 0x20002000,
726 0xc0026900,
727 0x000000bc,
728 0x00000000,
729 0x3f800000,
730 0xc0016900,
731 0x0000009e,
732 0x80000000, 487 0x80000000,
733 0xc0016900,
734 0x0000009f,
735 0x20002000, 488 0x20002000,
736 0xc0026900,
737 0x000000be,
738 0x00000000,
739 0x3f800000,
740 0xc0016900,
741 0x000000a0,
742 0x80000000, 489 0x80000000,
743 0xc0016900,
744 0x000000a1,
745 0x20002000, 490 0x20002000,
746 0xc0026900,
747 0x000000c0,
748 0x00000000,
749 0x3f800000,
750 0xc0016900,
751 0x000000a2,
752 0x80000000, 491 0x80000000,
753 0xc0016900,
754 0x000000a3,
755 0x20002000, 492 0x20002000,
756 0xc0026900,
757 0x000000c2,
758 0x00000000,
759 0x3f800000,
760 0xc0016900,
761 0x000000a4,
762 0x80000000, 493 0x80000000,
763 0xc0016900,
764 0x000000a5,
765 0x20002000, 494 0x20002000,
766 0xc0026900,
767 0x000000c4,
768 0x00000000,
769 0x3f800000,
770 0xc0016900,
771 0x000000a6,
772 0x80000000, 495 0x80000000,
773 0xc0016900,
774 0x000000a7,
775 0x20002000, 496 0x20002000,
776 0xc0026900,
777 0x000000c6,
778 0x00000000,
779 0x3f800000,
780 0xc0016900,
781 0x000000a8,
782 0x80000000, 497 0x80000000,
783 0xc0016900,
784 0x000000a9,
785 0x20002000, 498 0x20002000,
786 0xc0026900,
787 0x000000c8,
788 0x00000000,
789 0x3f800000,
790 0xc0016900,
791 0x000000aa,
792 0x80000000, 499 0x80000000,
793 0xc0016900,
794 0x000000ab,
795 0x20002000, 500 0x20002000,
796 0xc0026900,
797 0x000000ca,
798 0x00000000,
799 0x3f800000,
800 0xc0016900,
801 0x000000ac,
802 0x80000000, 501 0x80000000,
803 0xc0016900,
804 0x000000ad,
805 0x20002000, 502 0x20002000,
806 0xc0026900,
807 0x000000cc,
808 0x00000000,
809 0x3f800000,
810 0xc0016900,
811 0x000000ae,
812 0x80000000, 503 0x80000000,
813 0xc0016900,
814 0x000000af,
815 0x20002000, 504 0x20002000,
816 0xc0026900,
817 0x000000ce,
818 0x00000000,
819 0x3f800000,
820 0xc0016900,
821 0x000000b0,
822 0x80000000, 505 0x80000000,
823 0xc0016900,
824 0x000000b1,
825 0x20002000, 506 0x20002000,
826 0xc0026900, 507 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
827 0x000000d0,
828 0x00000000,
829 0x3f800000, 508 0x3f800000,
830 0xc0016900,
831 0x000000b2,
832 0x80000000,
833 0xc0016900,
834 0x000000b3,
835 0x20002000,
836 0xc0026900,
837 0x000000d2,
838 0x00000000, 509 0x00000000,
839 0x3f800000, 510 0x3f800000,
840 0xc0016900,
841 0x00000293,
842 0x00514000,
843 0xc0016900,
844 0x00000300,
845 0x00000000,
846 0xc0016900,
847 0x00000301,
848 0x00000000, 511 0x00000000,
849 0xc0016900, 512 0x3f800000,
850 0x00000312,
851 0xffffffff,
852 0xc0016900,
853 0x00000307,
854 0x00000000, 513 0x00000000,
855 0xc0016900, 514 0x3f800000,
856 0x00000308,
857 0x00000000, 515 0x00000000,
858 0xc0016900, 516 0x3f800000,
859 0x00000283,
860 0x00000000, 517 0x00000000,
861 0xc0016900, 518 0x3f800000,
862 0x00000292,
863 0x00000000, 519 0x00000000,
864 0xc0066900, 520 0x3f800000,
865 0x0000010f,
866 0x00000000, 521 0x00000000,
522 0x3f800000,
867 0x00000000, 523 0x00000000,
524 0x3f800000,
868 0x00000000, 525 0x00000000,
526 0x3f800000,
869 0x00000000, 527 0x00000000,
528 0x3f800000,
870 0x00000000, 529 0x00000000,
530 0x3f800000,
871 0x00000000, 531 0x00000000,
872 0xc0016900, 532 0x3f800000,
873 0x00000206,
874 0x00000000, 533 0x00000000,
875 0xc0016900, 534 0x3f800000,
876 0x00000207,
877 0x00000000, 535 0x00000000,
878 0xc0016900, 536 0x3f800000,
879 0x00000208,
880 0x00000000, 537 0x00000000,
881 0xc0046900,
882 0x00000303,
883 0x3f800000, 538 0x3f800000,
539
540 0xc0026900,
541 0x00000292,
542 0x00000000, /* PA_SC_MPASS_PS_CNTL */
543 0x00514000, /* PA_SC_MODE_CNTL */
544
545 0xc0096900,
546 0x00000300,
547 0x00000000, /* PA_SC_LINE_CNTL */
548 0x00000000, /* PA_SC_AA_CONFIG */
549 0x0000002d, /* PA_SU_VTX_CNTL */
550 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
884 0x3f800000, 551 0x3f800000,
885 0x3f800000, 552 0x3f800000,
886 0x3f800000, 553 0x3f800000,
887 0xc0016900, 554 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
888 0x00000205,
889 0x00000004,
890 0xc0016900,
891 0x00000280,
892 0x00000000,
893 0xc0016900,
894 0x00000281,
895 0x00000000, 555 0x00000000,
556
896 0xc0016900, 557 0xc0016900,
558 0x00000312,
559 0xffffffff, /* PA_SC_AA_MASK */
560
561 0xc0066900,
897 0x0000037e, 562 0x0000037e,
898 0x00000000, 563 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
899 0xc0016900, 564 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
900 0x00000382, 565 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
901 0x00000000, 566 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
902 0xc0016900, 567 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
903 0x00000380, 568 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
904 0x00000000, 569
905 0xc0016900, 570 0xc0046900,
906 0x00000383,
907 0x00000000,
908 0xc0016900,
909 0x00000381,
910 0x00000000,
911 0xc0016900,
912 0x00000282,
913 0x00000008,
914 0xc0016900,
915 0x00000302,
916 0x0000002d,
917 0xc0016900,
918 0x0000037f,
919 0x00000000,
920 0xc0016900,
921 0x000001b2,
922 0x00000001,
923 0xc0016900,
924 0x000001b6, 571 0x000001b6,
925 0x00000000, 572 0x00000000, /* SPI_INPUT_Z */
926 0xc0016900, 573 0x00000000, /* SPI_FOG_CNTL */
927 0x000001b7, 574 0x00000000, /* SPI_FOG_FUNC_SCALE */
928 0x00000000, 575 0x00000000, /* SPI_FOG_FUNC_BIAS */
929 0xc0016900, 576
930 0x000001b8,
931 0x00000000,
932 0xc0016900,
933 0x000001b9,
934 0x00000000,
935 0xc0016900, 577 0xc0016900,
936 0x00000225, 578 0x00000225,
937 0x00000000, 579 0x00000000, /* SQ_PGM_START_FS */
580
938 0xc0016900, 581 0xc0016900,
939 0x00000229, 582 0x00000229,
940 0x00000000, 583 0x00000000, /* SQ_PGM_RESOURCES_FS */
584
941 0xc0016900, 585 0xc0016900,
942 0x00000237, 586 0x00000237,
943 0x00000000, 587 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
944 0xc0016900, 588
945 0x00000100, 589 0xc0026900,
946 0x00000800,
947 0xc0016900,
948 0x00000101,
949 0x00000000,
950 0xc0016900,
951 0x00000102,
952 0x00000000,
953 0xc0016900,
954 0x000002a8, 590 0x000002a8,
955 0x00000000, 591 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
956 0xc0016900, 592 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
957 0x000002a9, 593
958 0x00000000, 594 0xc0116900,
959 0xc0016900, 595 0x00000280,
960 0x00000103, 596 0x00000000, /* PA_SU_POINT_SIZE */
961 0x00000000, 597 0x00000000, /* PA_SU_POINT_MINMAX */
962 0xc0016900, 598 0x00000008, /* PA_SU_LINE_CNTL */
963 0x00000284, 599 0x00000000, /* PA_SC_LINE_STIPPLE */
964 0x00000000, 600 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
965 0xc0016900, 601 0x00000000, /* VGT_HOS_CNTL */
966 0x00000290, 602 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
967 0x00000000, 603 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
968 0xc0016900, 604 0x00000000, /* VGT_HOS_REUSE_DEPTH */
969 0x00000285, 605 0x00000000, /* VGT_GROUP_PRIM_TYPE */
970 0x00000000, 606 0x00000000, /* VGT_GROUP_FIRST_DECR */
971 0xc0016900, 607 0x00000000, /* VGT_GROUP_DECR */
972 0x00000286, 608 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
973 0x00000000, 609 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
974 0xc0016900, 610 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
975 0x00000287, 611 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
976 0x00000000, 612 0x00000000, /* VGT_GS_MODE */
977 0xc0016900, 613
978 0x00000288,
979 0x00000000,
980 0xc0016900,
981 0x00000289,
982 0x00000000,
983 0xc0016900,
984 0x0000028a,
985 0x00000000,
986 0xc0016900,
987 0x0000028b,
988 0x00000000,
989 0xc0016900,
990 0x0000028c,
991 0x00000000,
992 0xc0016900,
993 0x0000028d,
994 0x00000000,
995 0xc0016900,
996 0x0000028e,
997 0x00000000,
998 0xc0016900,
999 0x0000028f,
1000 0x00000000,
1001 0xc0016900, 614 0xc0016900,
1002 0x000002a1, 615 0x000002a1,
1003 0x00000000, 616 0x00000000, /* VGT_PRIMITIVEID_EN */
617
1004 0xc0016900, 618 0xc0016900,
1005 0x000002a5, 619 0x000002a5,
1006 0x00000000, 620 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
1007 0xc0016900, 621
622 0xc0036900,
1008 0x000002ac, 623 0x000002ac,
1009 0x00000000, 624 0x00000000, /* VGT_STRMOUT_EN */
1010 0xc0016900, 625 0x00000000, /* VGT_REUSE_OFF */
1011 0x000002ad, 626 0x00000000, /* VGT_VTX_CNT_EN */
1012 0x00000000, 627
1013 0xc0016900,
1014 0x000002ae,
1015 0x00000000,
1016 0xc0016900, 628 0xc0016900,
1017 0x000002c8, 629 0x000002c8,
1018 0x00000000, 630 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
1019 0xc0016900, 631
1020 0x00000206, 632 0xc0076900,
1021 0x00000100,
1022 0xc0016900,
1023 0x00000204,
1024 0x00010000,
1025 0xc0036e00,
1026 0x00000000,
1027 0x00000012,
1028 0x00000000,
1029 0x00000000,
1030 0xc0016900,
1031 0x0000008f,
1032 0x0000000f,
1033 0xc0016900,
1034 0x000001e8,
1035 0x00000001,
1036 0xc0016900,
1037 0x00000202, 633 0x00000202,
1038 0x00cc0000, 634 0x00cc0000, /* CB_COLOR_CONTROL */
635 0x00000210, /* DB_SHADER_CNTL */
636 0x00010000, /* PA_CL_CLIP_CNTL */
637 0x00000244, /* PA_SU_SC_MODE_CNTL */
638 0x00000100, /* PA_CL_VTE_CNTL */
639 0x00000000, /* PA_CL_VS_OUT_CNTL */
640 0x00000000, /* PA_CL_NANINF_CNTL */
641
642 0xc0026900,
643 0x0000008e,
644 0x0000000f, /* CB_TARGET_MASK */
645 0x0000000f, /* CB_SHADER_MASK */
646
1039 0xc0016900, 647 0xc0016900,
1040 0x00000205, 648 0x000001e8,
1041 0x00000244, 649 0x00000001, /* CB_SHADER_CONTROL */
650
1042 0xc0016900, 651 0xc0016900,
1043 0x00000203, 652 0x00000185,
1044 0x00000210, 653 0x00000000, /* SPI_VS_OUT_ID_0 */
654
1045 0xc0016900, 655 0xc0016900,
656 0x00000191,
657 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
658
659 0xc0056900,
1046 0x000001b1, 660 0x000001b1,
661 0x00000000, /* SPI_VS_OUT_CONFIG */
662 0x00000001, /* SPI_THREAD_GROUPING */
663 0x00000001, /* SPI_PS_IN_CONTROL_0 */
664 0x00000000, /* SPI_PS_IN_CONTROL_1 */
665 0x00000000, /* SPI_INTERP_CONTROL_0 */
666
667 0xc0036e00, /* SET_SAMPLER */
1047 0x00000000, 668 0x00000000,
1048 0xc0016900, 669 0x00000012,
1049 0x00000185,
1050 0x00000000,
1051 0xc0016900,
1052 0x000001b3,
1053 0x00000001,
1054 0xc0016900,
1055 0x000001b4,
1056 0x00000000, 670 0x00000000,
1057 0xc0016900,
1058 0x00000191,
1059 0x00000b00,
1060 0xc0016900,
1061 0x000001b5,
1062 0x00000000, 671 0x00000000,
1063}; 672};
1064 673
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 144c32d37136..c3ea212e0c3c 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -25,6 +25,7 @@
25 * Alex Deucher 25 * Alex Deucher
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include <linux/kernel.h>
28#include "drmP.h" 29#include "drmP.h"
29#include "radeon.h" 30#include "radeon.h"
30#include "r600d.h" 31#include "r600d.h"
@@ -166,7 +167,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
166static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 167static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
167{ 168{
168 struct r600_cs_track *track = p->track; 169 struct r600_cs_track *track = p->track;
169 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height; 170 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
170 volatile u32 *ib = p->ib->ptr; 171 volatile u32 *ib = p->ib->ptr;
171 172
172 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) { 173 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
@@ -180,56 +181,57 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
180 i, track->cb_color_info[i]); 181 i, track->cb_color_info[i]);
181 return -EINVAL; 182 return -EINVAL;
182 } 183 }
183 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3; 184 /* pitch is the number of 8x8 tiles per row */
185 pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
184 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; 186 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
185 if (!pitch) { 187 height = size / (pitch * 8 * bpe);
186 dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid (0x%08X)\n",
187 __func__, __LINE__, pitch, i, track->cb_color_size[i]);
188 return -EINVAL;
189 }
190 height = size / (pitch * bpe);
191 if (height > 8192) 188 if (height > 8192)
192 height = 8192; 189 height = 8192;
190 if (height > 7)
191 height &= ~0x7;
193 switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) { 192 switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
194 case V_0280A0_ARRAY_LINEAR_GENERAL: 193 case V_0280A0_ARRAY_LINEAR_GENERAL:
194 /* technically height & 0x7 */
195 break;
195 case V_0280A0_ARRAY_LINEAR_ALIGNED: 196 case V_0280A0_ARRAY_LINEAR_ALIGNED:
196 if (pitch & 0x3f) { 197 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
197 dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) invalid\n", 198 if (!IS_ALIGNED(pitch, pitch_align)) {
198 __func__, __LINE__, pitch, bpe, pitch * bpe); 199 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
200 __func__, __LINE__, pitch);
199 return -EINVAL; 201 return -EINVAL;
200 } 202 }
201 if ((pitch * bpe) & (track->group_size - 1)) { 203 if (!IS_ALIGNED(height, 8)) {
202 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", 204 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
203 __func__, __LINE__, pitch); 205 __func__, __LINE__, height);
204 return -EINVAL; 206 return -EINVAL;
205 } 207 }
206 break; 208 break;
207 case V_0280A0_ARRAY_1D_TILED_THIN1: 209 case V_0280A0_ARRAY_1D_TILED_THIN1:
208 if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 1)) { 210 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
211 if (!IS_ALIGNED(pitch, pitch_align)) {
209 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", 212 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
210 __func__, __LINE__, pitch); 213 __func__, __LINE__, pitch);
214 return -EINVAL;
215 }
216 if (!IS_ALIGNED(height, 8)) {
217 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
218 __func__, __LINE__, height);
211 return -EINVAL; 219 return -EINVAL;
212 } 220 }
213 height &= ~0x7;
214 if (!height)
215 height = 8;
216 break; 221 break;
217 case V_0280A0_ARRAY_2D_TILED_THIN1: 222 case V_0280A0_ARRAY_2D_TILED_THIN1:
218 if (pitch & ((8 * track->nbanks) - 1)) { 223 pitch_align = max((u32)track->nbanks,
224 (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks));
225 if (!IS_ALIGNED(pitch, pitch_align)) {
219 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", 226 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
220 __func__, __LINE__, pitch); 227 __func__, __LINE__, pitch);
221 return -EINVAL; 228 return -EINVAL;
222 } 229 }
223 tmp = pitch * 8 * bpe * track->nsamples; 230 if (!IS_ALIGNED((height / 8), track->nbanks)) {
224 tmp = tmp / track->nbanks; 231 dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
225 if (tmp & (track->group_size - 1)) { 232 __func__, __LINE__, height);
226 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
227 __func__, __LINE__, pitch);
228 return -EINVAL; 233 return -EINVAL;
229 } 234 }
230 height &= ~((16 * track->npipes) - 1);
231 if (!height)
232 height = 16 * track->npipes;
233 break; 235 break;
234 default: 236 default:
235 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 237 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
@@ -238,16 +240,20 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
238 return -EINVAL; 240 return -EINVAL;
239 } 241 }
240 /* check offset */ 242 /* check offset */
241 tmp = height * pitch; 243 tmp = height * pitch * 8 * bpe;
242 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 244 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
243 dev_warn(p->dev, "%s offset[%d] %d to big\n", __func__, i, track->cb_color_bo_offset[i]); 245 dev_warn(p->dev, "%s offset[%d] %d too big\n", __func__, i, track->cb_color_bo_offset[i]);
246 return -EINVAL;
247 }
248 if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
249 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
244 return -EINVAL; 250 return -EINVAL;
245 } 251 }
246 /* limit max tile */ 252 /* limit max tile */
247 tmp = (height * pitch) >> 6; 253 tmp = (height * pitch * 8) >> 6;
248 if (tmp < slice_tile_max) 254 if (tmp < slice_tile_max)
249 slice_tile_max = tmp; 255 slice_tile_max = tmp;
250 tmp = S_028060_PITCH_TILE_MAX((pitch >> 3) - 1) | 256 tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
251 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 257 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
252 ib[track->cb_color_size_idx[i]] = tmp; 258 ib[track->cb_color_size_idx[i]] = tmp;
253 return 0; 259 return 0;
@@ -289,7 +295,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
289 /* Check depth buffer */ 295 /* Check depth buffer */
290 if (G_028800_STENCIL_ENABLE(track->db_depth_control) || 296 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
291 G_028800_Z_ENABLE(track->db_depth_control)) { 297 G_028800_Z_ENABLE(track->db_depth_control)) {
292 u32 nviews, bpe, ntiles; 298 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
293 if (track->db_bo == NULL) { 299 if (track->db_bo == NULL) {
294 dev_warn(p->dev, "z/stencil with no depth buffer\n"); 300 dev_warn(p->dev, "z/stencil with no depth buffer\n");
295 return -EINVAL; 301 return -EINVAL;
@@ -332,6 +338,51 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
332 } 338 }
333 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); 339 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
334 } else { 340 } else {
341 size = radeon_bo_size(track->db_bo);
342 pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
343 height = size / (pitch * 8 * bpe);
344 height &= ~0x7;
345 if (!height)
346 height = 8;
347
348 switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
349 case V_028010_ARRAY_1D_TILED_THIN1:
350 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
351 if (!IS_ALIGNED(pitch, pitch_align)) {
352 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
353 __func__, __LINE__, pitch);
354 return -EINVAL;
355 }
356 if (!IS_ALIGNED(height, 8)) {
357 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
358 __func__, __LINE__, height);
359 return -EINVAL;
360 }
361 break;
362 case V_028010_ARRAY_2D_TILED_THIN1:
363 pitch_align = max((u32)track->nbanks,
364 (u32)(((track->group_size / 8) / bpe) * track->nbanks));
365 if (!IS_ALIGNED(pitch, pitch_align)) {
366 dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
367 __func__, __LINE__, pitch);
368 return -EINVAL;
369 }
370 if ((height / 8) & (track->nbanks - 1)) {
371 dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
372 __func__, __LINE__, height);
373 return -EINVAL;
374 }
375 break;
376 default:
377 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
378 G_028010_ARRAY_MODE(track->db_depth_info),
379 track->db_depth_info);
380 return -EINVAL;
381 }
382 if (!IS_ALIGNED(track->db_offset, track->group_size)) {
383 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
384 return -EINVAL;
385 }
335 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 386 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
336 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 387 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
337 tmp = ntiles * bpe * 64 * nviews; 388 tmp = ntiles * bpe * 64 * nviews;
@@ -724,7 +775,25 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
724 track->db_depth_control = radeon_get_ib_value(p, idx); 775 track->db_depth_control = radeon_get_ib_value(p, idx);
725 break; 776 break;
726 case R_028010_DB_DEPTH_INFO: 777 case R_028010_DB_DEPTH_INFO:
727 track->db_depth_info = radeon_get_ib_value(p, idx); 778 if (r600_cs_packet_next_is_pkt3_nop(p)) {
779 r = r600_cs_packet_next_reloc(p, &reloc);
780 if (r) {
781 dev_warn(p->dev, "bad SET_CONTEXT_REG "
782 "0x%04X\n", reg);
783 return -EINVAL;
784 }
785 track->db_depth_info = radeon_get_ib_value(p, idx);
786 ib[idx] &= C_028010_ARRAY_MODE;
787 track->db_depth_info &= C_028010_ARRAY_MODE;
788 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
789 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
790 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
791 } else {
792 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
793 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
794 }
795 } else
796 track->db_depth_info = radeon_get_ib_value(p, idx);
728 break; 797 break;
729 case R_028004_DB_DEPTH_VIEW: 798 case R_028004_DB_DEPTH_VIEW:
730 track->db_depth_view = radeon_get_ib_value(p, idx); 799 track->db_depth_view = radeon_get_ib_value(p, idx);
@@ -757,8 +826,25 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
757 case R_0280B4_CB_COLOR5_INFO: 826 case R_0280B4_CB_COLOR5_INFO:
758 case R_0280B8_CB_COLOR6_INFO: 827 case R_0280B8_CB_COLOR6_INFO:
759 case R_0280BC_CB_COLOR7_INFO: 828 case R_0280BC_CB_COLOR7_INFO:
760 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 829 if (r600_cs_packet_next_is_pkt3_nop(p)) {
761 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 830 r = r600_cs_packet_next_reloc(p, &reloc);
831 if (r) {
832 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
833 return -EINVAL;
834 }
835 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
836 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
837 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
838 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
839 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
840 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
841 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
842 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
843 }
844 } else {
845 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
846 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
847 }
762 break; 848 break;
763 case R_028060_CB_COLOR0_SIZE: 849 case R_028060_CB_COLOR0_SIZE:
764 case R_028064_CB_COLOR1_SIZE: 850 case R_028064_CB_COLOR1_SIZE:
@@ -946,8 +1032,9 @@ static inline unsigned minify(unsigned size, unsigned levels)
946} 1032}
947 1033
948static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels, 1034static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
949 unsigned w0, unsigned h0, unsigned d0, unsigned bpe, 1035 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
950 unsigned *l0_size, unsigned *mipmap_size) 1036 unsigned pitch_align,
1037 unsigned *l0_size, unsigned *mipmap_size)
951{ 1038{
952 unsigned offset, i, level, face; 1039 unsigned offset, i, level, face;
953 unsigned width, height, depth, rowstride, size; 1040 unsigned width, height, depth, rowstride, size;
@@ -960,13 +1047,13 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
960 height = minify(h0, i); 1047 height = minify(h0, i);
961 depth = minify(d0, i); 1048 depth = minify(d0, i);
962 for(face = 0; face < nfaces; face++) { 1049 for(face = 0; face < nfaces; face++) {
963 rowstride = ((width * bpe) + 255) & ~255; 1050 rowstride = ALIGN((width * bpe), pitch_align);
964 size = height * rowstride * depth; 1051 size = height * rowstride * depth;
965 offset += size; 1052 offset += size;
966 offset = (offset + 0x1f) & ~0x1f; 1053 offset = (offset + 0x1f) & ~0x1f;
967 } 1054 }
968 } 1055 }
969 *l0_size = (((w0 * bpe) + 255) & ~255) * h0 * d0; 1056 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
970 *mipmap_size = offset; 1057 *mipmap_size = offset;
971 if (!blevel) 1058 if (!blevel)
972 *mipmap_size -= *l0_size; 1059 *mipmap_size -= *l0_size;
@@ -985,16 +1072,23 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
985 * the texture and mipmap bo object are big enough to cover this resource. 1072 * the texture and mipmap bo object are big enough to cover this resource.
986 */ 1073 */
987static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, 1074static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
988 struct radeon_bo *texture, 1075 struct radeon_bo *texture,
989 struct radeon_bo *mipmap) 1076 struct radeon_bo *mipmap,
1077 u32 tiling_flags)
990{ 1078{
1079 struct r600_cs_track *track = p->track;
991 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0; 1080 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
992 u32 word0, word1, l0_size, mipmap_size; 1081 u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
993 1082
994 /* on legacy kernel we don't perform advanced check */ 1083 /* on legacy kernel we don't perform advanced check */
995 if (p->rdev == NULL) 1084 if (p->rdev == NULL)
996 return 0; 1085 return 0;
1086
997 word0 = radeon_get_ib_value(p, idx + 0); 1087 word0 = radeon_get_ib_value(p, idx + 0);
1088 if (tiling_flags & RADEON_TILING_MACRO)
1089 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1090 else if (tiling_flags & RADEON_TILING_MICRO)
1091 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
998 word1 = radeon_get_ib_value(p, idx + 1); 1092 word1 = radeon_get_ib_value(p, idx + 1);
999 w0 = G_038000_TEX_WIDTH(word0) + 1; 1093 w0 = G_038000_TEX_WIDTH(word0) + 1;
1000 h0 = G_038004_TEX_HEIGHT(word1) + 1; 1094 h0 = G_038004_TEX_HEIGHT(word1) + 1;
@@ -1021,11 +1115,55 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1021 __func__, __LINE__, G_038004_DATA_FORMAT(word1)); 1115 __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1022 return -EINVAL; 1116 return -EINVAL;
1023 } 1117 }
1118
1119 pitch = G_038000_PITCH(word0) + 1;
1120 switch (G_038000_TILE_MODE(word0)) {
1121 case V_038000_ARRAY_LINEAR_GENERAL:
1122 pitch_align = 1;
1123 /* XXX check height align */
1124 break;
1125 case V_038000_ARRAY_LINEAR_ALIGNED:
1126 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
1127 if (!IS_ALIGNED(pitch, pitch_align)) {
1128 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1129 __func__, __LINE__, pitch);
1130 return -EINVAL;
1131 }
1132 /* XXX check height align */
1133 break;
1134 case V_038000_ARRAY_1D_TILED_THIN1:
1135 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
1136 if (!IS_ALIGNED(pitch, pitch_align)) {
1137 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1138 __func__, __LINE__, pitch);
1139 return -EINVAL;
1140 }
1141 /* XXX check height align */
1142 break;
1143 case V_038000_ARRAY_2D_TILED_THIN1:
1144 pitch_align = max((u32)track->nbanks,
1145 (u32)(((track->group_size / 8) / bpe) * track->nbanks));
1146 if (!IS_ALIGNED(pitch, pitch_align)) {
1147 dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1148 __func__, __LINE__, pitch);
1149 return -EINVAL;
1150 }
1151 /* XXX check height align */
1152 break;
1153 default:
1154 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1155 G_038000_TILE_MODE(word0), word0);
1156 return -EINVAL;
1157 }
1158 /* XXX check offset align */
1159
1024 word0 = radeon_get_ib_value(p, idx + 4); 1160 word0 = radeon_get_ib_value(p, idx + 4);
1025 word1 = radeon_get_ib_value(p, idx + 5); 1161 word1 = radeon_get_ib_value(p, idx + 5);
1026 blevel = G_038010_BASE_LEVEL(word0); 1162 blevel = G_038010_BASE_LEVEL(word0);
1027 nlevels = G_038014_LAST_LEVEL(word1); 1163 nlevels = G_038014_LAST_LEVEL(word1);
1028 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, &l0_size, &mipmap_size); 1164 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
1165 (pitch_align * bpe),
1166 &l0_size, &mipmap_size);
1029 /* using get ib will give us the offset into the texture bo */ 1167 /* using get ib will give us the offset into the texture bo */
1030 word0 = radeon_get_ib_value(p, idx + 2); 1168 word0 = radeon_get_ib_value(p, idx + 2);
1031 if ((l0_size + word0) > radeon_bo_size(texture)) { 1169 if ((l0_size + word0) > radeon_bo_size(texture)) {
@@ -1239,6 +1377,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1239 return -EINVAL; 1377 return -EINVAL;
1240 } 1378 }
1241 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1379 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1380 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1381 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1382 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1383 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1242 texture = reloc->robj; 1384 texture = reloc->robj;
1243 /* tex mip base */ 1385 /* tex mip base */
1244 r = r600_cs_packet_next_reloc(p, &reloc); 1386 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -1249,7 +1391,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1249 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1391 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1250 mipmap = reloc->robj; 1392 mipmap = reloc->robj;
1251 r = r600_check_texture_resource(p, idx+(i*7)+1, 1393 r = r600_check_texture_resource(p, idx+(i*7)+1,
1252 texture, mipmap); 1394 texture, mipmap, reloc->lobj.tiling_flags);
1253 if (r) 1395 if (r)
1254 return r; 1396 return r;
1255 break; 1397 break;
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 26b4bc9d89a5..e6a58ed48dcf 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -435,7 +435,8 @@ static int r600_hdmi_find_free_block(struct drm_device *dev)
435 } 435 }
436 } 436 }
437 437
438 if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690) { 438 if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 ||
439 rdev->family == CHIP_RS740) {
439 return free_blocks[0] ? R600_HDMI_BLOCK1 : 0; 440 return free_blocks[0] ? R600_HDMI_BLOCK1 : 0;
440 } else if (rdev->family >= CHIP_R600) { 441 } else if (rdev->family >= CHIP_R600) {
441 if (free_blocks[0]) 442 if (free_blocks[0])
@@ -466,7 +467,8 @@ static void r600_hdmi_assign_block(struct drm_encoder *encoder)
466 if (ASIC_IS_DCE32(rdev)) 467 if (ASIC_IS_DCE32(rdev))
467 radeon_encoder->hdmi_config_offset = dig->dig_encoder ? 468 radeon_encoder->hdmi_config_offset = dig->dig_encoder ?
468 R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1; 469 R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1;
469 } else if (rdev->family >= CHIP_R600) { 470 } else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 ||
471 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
470 radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev); 472 radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev);
471 } 473 }
472} 474}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 59c1f8793e60..858a1920c0d7 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -239,12 +239,18 @@
239#define GRBM_SOFT_RESET 0x8020 239#define GRBM_SOFT_RESET 0x8020
240#define SOFT_RESET_CP (1<<0) 240#define SOFT_RESET_CP (1<<0)
241 241
242#define CG_THERMAL_STATUS 0x7F4
243#define ASIC_T(x) ((x) << 0)
244#define ASIC_T_MASK 0x1FF
245#define ASIC_T_SHIFT 0
246
242#define HDP_HOST_PATH_CNTL 0x2C00 247#define HDP_HOST_PATH_CNTL 0x2C00
243#define HDP_NONSURFACE_BASE 0x2C04 248#define HDP_NONSURFACE_BASE 0x2C04
244#define HDP_NONSURFACE_INFO 0x2C08 249#define HDP_NONSURFACE_INFO 0x2C08
245#define HDP_NONSURFACE_SIZE 0x2C0C 250#define HDP_NONSURFACE_SIZE 0x2C0C
246#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 251#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
247#define HDP_TILING_CONFIG 0x2F3C 252#define HDP_TILING_CONFIG 0x2F3C
253#define HDP_DEBUG1 0x2F34
248 254
249#define MC_VM_AGP_TOP 0x2184 255#define MC_VM_AGP_TOP 0x2184
250#define MC_VM_AGP_BOT 0x2188 256#define MC_VM_AGP_BOT 0x2188
@@ -1154,6 +1160,10 @@
1154#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1160#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
1155#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1161#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
1156#define C_038000_TILE_MODE 0xFFFFFF87 1162#define C_038000_TILE_MODE 0xFFFFFF87
1163#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
1164#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
1165#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
1166#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
1157#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1167#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
1158#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1168#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
1159#define C_038000_TILE_TYPE 0xFFFFFF7F 1169#define C_038000_TILE_TYPE 0xFFFFFF7F
@@ -1357,6 +1367,8 @@
1357#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1367#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
1358#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1368#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
1359#define C_028010_ARRAY_MODE 0xFFF87FFF 1369#define C_028010_ARRAY_MODE 0xFFF87FFF
1370#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
1371#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
1360#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1372#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
1361#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1373#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
1362#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1374#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 2f94dc66c183..3cd1c470b777 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -178,6 +178,9 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev);
178void radeon_atombios_get_power_modes(struct radeon_device *rdev); 178void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level); 179void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
180void rs690_pm_info(struct radeon_device *rdev); 180void rs690_pm_info(struct radeon_device *rdev);
181extern u32 rv6xx_get_temp(struct radeon_device *rdev);
182extern u32 rv770_get_temp(struct radeon_device *rdev);
183extern u32 evergreen_get_temp(struct radeon_device *rdev);
181 184
182/* 185/*
183 * Fences. 186 * Fences.
@@ -232,7 +235,7 @@ struct radeon_surface_reg {
232 */ 235 */
233struct radeon_mman { 236struct radeon_mman {
234 struct ttm_bo_global_ref bo_global_ref; 237 struct ttm_bo_global_ref bo_global_ref;
235 struct ttm_global_reference mem_global_ref; 238 struct drm_global_reference mem_global_ref;
236 struct ttm_bo_device bdev; 239 struct ttm_bo_device bdev;
237 bool mem_global_referenced; 240 bool mem_global_referenced;
238 bool initialized; 241 bool initialized;
@@ -671,6 +674,13 @@ struct radeon_pm_profile {
671 int dpms_on_cm_idx; 674 int dpms_on_cm_idx;
672}; 675};
673 676
677enum radeon_int_thermal_type {
678 THERMAL_TYPE_NONE,
679 THERMAL_TYPE_RV6XX,
680 THERMAL_TYPE_RV770,
681 THERMAL_TYPE_EVERGREEN,
682};
683
674struct radeon_voltage { 684struct radeon_voltage {
675 enum radeon_voltage_type type; 685 enum radeon_voltage_type type;
676 /* gpio voltage */ 686 /* gpio voltage */
@@ -766,6 +776,9 @@ struct radeon_pm {
766 enum radeon_pm_profile_type profile; 776 enum radeon_pm_profile_type profile;
767 int profile_index; 777 int profile_index;
768 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 778 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
779 /* internal thermal controller on rv6xx+ */
780 enum radeon_int_thermal_type int_thermal_type;
781 struct device *int_hwmon_dev;
769}; 782};
770 783
771 784
@@ -902,6 +915,7 @@ struct r600_asic {
902 unsigned tiling_nbanks; 915 unsigned tiling_nbanks;
903 unsigned tiling_npipes; 916 unsigned tiling_npipes;
904 unsigned tiling_group_size; 917 unsigned tiling_group_size;
918 unsigned tile_config;
905 struct r100_gpu_lockup lockup; 919 struct r100_gpu_lockup lockup;
906}; 920};
907 921
@@ -926,6 +940,7 @@ struct rv770_asic {
926 unsigned tiling_nbanks; 940 unsigned tiling_nbanks;
927 unsigned tiling_npipes; 941 unsigned tiling_npipes;
928 unsigned tiling_group_size; 942 unsigned tiling_group_size;
943 unsigned tile_config;
929 struct r100_gpu_lockup lockup; 944 struct r100_gpu_lockup lockup;
930}; 945};
931 946
@@ -951,6 +966,7 @@ struct evergreen_asic {
951 unsigned tiling_nbanks; 966 unsigned tiling_nbanks;
952 unsigned tiling_npipes; 967 unsigned tiling_npipes;
953 unsigned tiling_group_size; 968 unsigned tiling_group_size;
969 unsigned tile_config;
954}; 970};
955 971
956union radeon_asic_config { 972union radeon_asic_config {
@@ -1033,6 +1049,9 @@ struct radeon_device {
1033 uint32_t pcie_reg_mask; 1049 uint32_t pcie_reg_mask;
1034 radeon_rreg_t pciep_rreg; 1050 radeon_rreg_t pciep_rreg;
1035 radeon_wreg_t pciep_wreg; 1051 radeon_wreg_t pciep_wreg;
1052 /* io port */
1053 void __iomem *rio_mem;
1054 resource_size_t rio_mem_size;
1036 struct radeon_clock clock; 1055 struct radeon_clock clock;
1037 struct radeon_mc mc; 1056 struct radeon_mc mc;
1038 struct radeon_gart gart; 1057 struct radeon_gart gart;
@@ -1069,6 +1088,7 @@ struct radeon_device {
1069 struct mutex vram_mutex; 1088 struct mutex vram_mutex;
1070 1089
1071 /* audio stuff */ 1090 /* audio stuff */
1091 bool audio_enabled;
1072 struct timer_list audio_timer; 1092 struct timer_list audio_timer;
1073 int audio_channels; 1093 int audio_channels;
1074 int audio_rate; 1094 int audio_rate;
@@ -1078,6 +1098,8 @@ struct radeon_device {
1078 1098
1079 bool powered_down; 1099 bool powered_down;
1080 struct notifier_block acpi_nb; 1100 struct notifier_block acpi_nb;
1101 /* only one userspace can use Hyperz features at a time */
1102 struct drm_file *hyperz_filp;
1081}; 1103};
1082 1104
1083int radeon_device_init(struct radeon_device *rdev, 1105int radeon_device_init(struct radeon_device *rdev,
@@ -1114,6 +1136,26 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
1114 } 1136 }
1115} 1137}
1116 1138
1139static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1140{
1141 if (reg < rdev->rio_mem_size)
1142 return ioread32(rdev->rio_mem + reg);
1143 else {
1144 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1145 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1146 }
1147}
1148
1149static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1150{
1151 if (reg < rdev->rio_mem_size)
1152 iowrite32(v, rdev->rio_mem + reg);
1153 else {
1154 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1155 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1156 }
1157}
1158
1117/* 1159/*
1118 * Cast helper 1160 * Cast helper
1119 */ 1161 */
@@ -1152,6 +1194,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
1152 WREG32_PLL(reg, tmp_); \ 1194 WREG32_PLL(reg, tmp_); \
1153 } while (0) 1195 } while (0)
1154#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) 1196#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1197#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1198#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1155 1199
1156/* 1200/*
1157 * Indirect registers accessor 1201 * Indirect registers accessor
@@ -1415,6 +1459,13 @@ extern void r700_cp_fini(struct radeon_device *rdev);
1415extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); 1459extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1416extern int evergreen_irq_set(struct radeon_device *rdev); 1460extern int evergreen_irq_set(struct radeon_device *rdev);
1417 1461
1462/* radeon_acpi.c */
1463#if defined(CONFIG_ACPI)
1464extern int radeon_acpi_init(struct radeon_device *rdev);
1465#else
1466static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1467#endif
1468
1418/* evergreen */ 1469/* evergreen */
1419struct evergreen_mc_save { 1470struct evergreen_mc_save {
1420 u32 vga_control[6]; 1471 u32 vga_control[6];
diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c
new file mode 100644
index 000000000000..3f6636bb2d7f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_acpi.c
@@ -0,0 +1,67 @@
1#include <linux/pci.h>
2#include <linux/acpi.h>
3#include <linux/slab.h>
4#include <acpi/acpi_drivers.h>
5#include <acpi/acpi_bus.h>
6
7#include "drmP.h"
8#include "drm.h"
9#include "drm_sarea.h"
10#include "drm_crtc_helper.h"
11#include "radeon.h"
12
13#include <linux/vga_switcheroo.h>
14
15/* Call the ATIF method
16 *
17 * Note: currently we discard the output
18 */
19static int radeon_atif_call(acpi_handle handle)
20{
21 acpi_status status;
22 union acpi_object atif_arg_elements[2];
23 struct acpi_object_list atif_arg;
24 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
25
26 atif_arg.count = 2;
27 atif_arg.pointer = &atif_arg_elements[0];
28
29 atif_arg_elements[0].type = ACPI_TYPE_INTEGER;
30 atif_arg_elements[0].integer.value = 0;
31 atif_arg_elements[1].type = ACPI_TYPE_INTEGER;
32 atif_arg_elements[1].integer.value = 0;
33
34 status = acpi_evaluate_object(handle, "ATIF", &atif_arg, &buffer);
35
36 /* Fail only if calling the method fails and ATIF is supported */
37 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
38 printk(KERN_DEBUG "failed to evaluate ATIF got %s\n", acpi_format_exception(status));
39 kfree(buffer.pointer);
40 return 1;
41 }
42
43 kfree(buffer.pointer);
44 return 0;
45}
46
47/* Call all ACPI methods here */
48int radeon_acpi_init(struct radeon_device *rdev)
49{
50 acpi_handle handle;
51 int ret;
52
53 /* No need to proceed if we're sure that ATIF is not supported */
54 if (!ASIC_IS_AVIVO(rdev) || !rdev->bios)
55 return 0;
56
57 /* Get the device handle */
58 handle = DEVICE_ACPI_HANDLE(&rdev->pdev->dev);
59
60 /* Call the ATIF method */
61 ret = radeon_atif_call(handle);
62 if (ret)
63 return ret;
64
65 return 0;
66}
67
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c0bbaa64157a..a5aff755f0d2 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -113,6 +113,7 @@ void r100_wb_fini(struct radeon_device *rdev);
113int r100_wb_init(struct radeon_device *rdev); 113int r100_wb_init(struct radeon_device *rdev);
114int r100_cp_reset(struct radeon_device *rdev); 114int r100_cp_reset(struct radeon_device *rdev);
115void r100_vga_render_disable(struct radeon_device *rdev); 115void r100_vga_render_disable(struct radeon_device *rdev);
116void r100_restore_sanity(struct radeon_device *rdev);
116int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 117int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
117 struct radeon_cs_packet *pkt, 118 struct radeon_cs_packet *pkt,
118 struct radeon_bo *robj); 119 struct radeon_bo *robj);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 10673ae59cfa..3bc2bcdf5308 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -723,7 +723,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
723 } 723 }
724 724
725 if (i == ATOM_DEVICE_CV_INDEX) { 725 if (i == ATOM_DEVICE_CV_INDEX) {
726 DRM_DEBUG("Skipping Component Video\n"); 726 DRM_DEBUG_KMS("Skipping Component Video\n");
727 continue; 727 continue;
728 } 728 }
729 729
@@ -1032,21 +1032,18 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1032 u8 frev, crev; 1032 u8 frev, crev;
1033 u16 data_offset; 1033 u16 data_offset;
1034 1034
1035 /* sideport is AMD only */
1036 if (rdev->family == CHIP_RS600)
1037 return false;
1038
1035 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1039 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1036 &frev, &crev, &data_offset)) { 1040 &frev, &crev, &data_offset)) {
1037 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1041 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1038 data_offset); 1042 data_offset);
1039 switch (crev) { 1043 switch (crev) {
1040 case 1: 1044 case 1:
1041 /* AMD IGPS */ 1045 if (igp_info->info.ulBootUpMemoryClock)
1042 if ((rdev->family == CHIP_RS690) || 1046 return true;
1043 (rdev->family == CHIP_RS740)) {
1044 if (igp_info->info.ulBootUpMemoryClock)
1045 return true;
1046 } else {
1047 if (igp_info->info.ucMemoryType & 0xf0)
1048 return true;
1049 }
1050 break; 1047 break;
1051 case 2: 1048 case 2:
1052 if (igp_info->info_2.ucMemoryType & 0x0f) 1049 if (igp_info->info_2.ucMemoryType & 0x0f)
@@ -1095,7 +1092,7 @@ bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1095 (tmds_info->asMiscInfo[i]. 1092 (tmds_info->asMiscInfo[i].
1096 ucPLL_VoltageSwing & 0xf) << 16; 1093 ucPLL_VoltageSwing & 0xf) << 16;
1097 1094
1098 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", 1095 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1099 tmds->tmds_pll[i].freq, 1096 tmds->tmds_pll[i].freq,
1100 tmds->tmds_pll[i].value); 1097 tmds->tmds_pll[i].value);
1101 1098
@@ -1789,14 +1786,22 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1789 } 1786 }
1790 1787
1791 /* add the i2c bus for thermal/fan chip */ 1788 /* add the i2c bus for thermal/fan chip */
1792 /* no support for internal controller yet */
1793 if (controller->ucType > 0) { 1789 if (controller->ucType > 0) {
1794 if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) || 1790 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
1795 (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) || 1791 DRM_INFO("Internal thermal controller %s fan control\n",
1796 (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) { 1792 (controller->ucFanParameters &
1793 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1794 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1795 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1796 DRM_INFO("Internal thermal controller %s fan control\n",
1797 (controller->ucFanParameters &
1798 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1799 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1800 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1797 DRM_INFO("Internal thermal controller %s fan control\n", 1801 DRM_INFO("Internal thermal controller %s fan control\n",
1798 (controller->ucFanParameters & 1802 (controller->ucFanParameters &
1799 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 1803 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1804 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
1800 } else if ((controller->ucType == 1805 } else if ((controller->ucType ==
1801 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || 1806 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1802 (controller->ucType == 1807 (controller->ucType ==
@@ -2179,11 +2184,11 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2179 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 2184 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2180 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 2185 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2181 if (connected) { 2186 if (connected) {
2182 DRM_DEBUG("TV1 connected\n"); 2187 DRM_DEBUG_KMS("TV1 connected\n");
2183 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 2188 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2184 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 2189 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2185 } else { 2190 } else {
2186 DRM_DEBUG("TV1 disconnected\n"); 2191 DRM_DEBUG_KMS("TV1 disconnected\n");
2187 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 2192 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2188 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 2193 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2189 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 2194 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
@@ -2192,11 +2197,11 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2192 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 2197 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2193 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 2198 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2194 if (connected) { 2199 if (connected) {
2195 DRM_DEBUG("CV connected\n"); 2200 DRM_DEBUG_KMS("CV connected\n");
2196 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 2201 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2197 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 2202 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2198 } else { 2203 } else {
2199 DRM_DEBUG("CV disconnected\n"); 2204 DRM_DEBUG_KMS("CV disconnected\n");
2200 bios_0_scratch &= ~ATOM_S0_CV_MASK; 2205 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2201 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 2206 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2202 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 2207 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
@@ -2205,12 +2210,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2205 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 2210 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2206 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 2211 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2207 if (connected) { 2212 if (connected) {
2208 DRM_DEBUG("LCD1 connected\n"); 2213 DRM_DEBUG_KMS("LCD1 connected\n");
2209 bios_0_scratch |= ATOM_S0_LCD1; 2214 bios_0_scratch |= ATOM_S0_LCD1;
2210 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 2215 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2211 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 2216 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2212 } else { 2217 } else {
2213 DRM_DEBUG("LCD1 disconnected\n"); 2218 DRM_DEBUG_KMS("LCD1 disconnected\n");
2214 bios_0_scratch &= ~ATOM_S0_LCD1; 2219 bios_0_scratch &= ~ATOM_S0_LCD1;
2215 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 2220 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2216 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 2221 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
@@ -2219,12 +2224,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2219 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 2224 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2220 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 2225 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2221 if (connected) { 2226 if (connected) {
2222 DRM_DEBUG("CRT1 connected\n"); 2227 DRM_DEBUG_KMS("CRT1 connected\n");
2223 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 2228 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2224 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 2229 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2225 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 2230 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2226 } else { 2231 } else {
2227 DRM_DEBUG("CRT1 disconnected\n"); 2232 DRM_DEBUG_KMS("CRT1 disconnected\n");
2228 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 2233 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2229 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 2234 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2230 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 2235 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
@@ -2233,12 +2238,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2233 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 2238 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2234 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 2239 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2235 if (connected) { 2240 if (connected) {
2236 DRM_DEBUG("CRT2 connected\n"); 2241 DRM_DEBUG_KMS("CRT2 connected\n");
2237 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 2242 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2238 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 2243 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2239 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 2244 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2240 } else { 2245 } else {
2241 DRM_DEBUG("CRT2 disconnected\n"); 2246 DRM_DEBUG_KMS("CRT2 disconnected\n");
2242 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 2247 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2243 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 2248 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2244 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 2249 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
@@ -2247,12 +2252,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2247 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 2252 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2248 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 2253 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2249 if (connected) { 2254 if (connected) {
2250 DRM_DEBUG("DFP1 connected\n"); 2255 DRM_DEBUG_KMS("DFP1 connected\n");
2251 bios_0_scratch |= ATOM_S0_DFP1; 2256 bios_0_scratch |= ATOM_S0_DFP1;
2252 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 2257 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2253 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 2258 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2254 } else { 2259 } else {
2255 DRM_DEBUG("DFP1 disconnected\n"); 2260 DRM_DEBUG_KMS("DFP1 disconnected\n");
2256 bios_0_scratch &= ~ATOM_S0_DFP1; 2261 bios_0_scratch &= ~ATOM_S0_DFP1;
2257 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 2262 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2258 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 2263 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
@@ -2261,12 +2266,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2261 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 2266 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2262 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 2267 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2263 if (connected) { 2268 if (connected) {
2264 DRM_DEBUG("DFP2 connected\n"); 2269 DRM_DEBUG_KMS("DFP2 connected\n");
2265 bios_0_scratch |= ATOM_S0_DFP2; 2270 bios_0_scratch |= ATOM_S0_DFP2;
2266 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 2271 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2267 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 2272 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2268 } else { 2273 } else {
2269 DRM_DEBUG("DFP2 disconnected\n"); 2274 DRM_DEBUG_KMS("DFP2 disconnected\n");
2270 bios_0_scratch &= ~ATOM_S0_DFP2; 2275 bios_0_scratch &= ~ATOM_S0_DFP2;
2271 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 2276 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2272 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 2277 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
@@ -2275,12 +2280,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2275 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 2280 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2276 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 2281 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2277 if (connected) { 2282 if (connected) {
2278 DRM_DEBUG("DFP3 connected\n"); 2283 DRM_DEBUG_KMS("DFP3 connected\n");
2279 bios_0_scratch |= ATOM_S0_DFP3; 2284 bios_0_scratch |= ATOM_S0_DFP3;
2280 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 2285 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2281 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 2286 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2282 } else { 2287 } else {
2283 DRM_DEBUG("DFP3 disconnected\n"); 2288 DRM_DEBUG_KMS("DFP3 disconnected\n");
2284 bios_0_scratch &= ~ATOM_S0_DFP3; 2289 bios_0_scratch &= ~ATOM_S0_DFP3;
2285 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 2290 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2286 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 2291 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
@@ -2289,12 +2294,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2289 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 2294 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2290 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 2295 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2291 if (connected) { 2296 if (connected) {
2292 DRM_DEBUG("DFP4 connected\n"); 2297 DRM_DEBUG_KMS("DFP4 connected\n");
2293 bios_0_scratch |= ATOM_S0_DFP4; 2298 bios_0_scratch |= ATOM_S0_DFP4;
2294 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 2299 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2295 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 2300 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2296 } else { 2301 } else {
2297 DRM_DEBUG("DFP4 disconnected\n"); 2302 DRM_DEBUG_KMS("DFP4 disconnected\n");
2298 bios_0_scratch &= ~ATOM_S0_DFP4; 2303 bios_0_scratch &= ~ATOM_S0_DFP4;
2299 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 2304 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2300 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 2305 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
@@ -2303,12 +2308,12 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2303 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 2308 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2304 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 2309 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2305 if (connected) { 2310 if (connected) {
2306 DRM_DEBUG("DFP5 connected\n"); 2311 DRM_DEBUG_KMS("DFP5 connected\n");
2307 bios_0_scratch |= ATOM_S0_DFP5; 2312 bios_0_scratch |= ATOM_S0_DFP5;
2308 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 2313 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2309 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 2314 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2310 } else { 2315 } else {
2311 DRM_DEBUG("DFP5 disconnected\n"); 2316 DRM_DEBUG_KMS("DFP5 disconnected\n");
2312 bios_0_scratch &= ~ATOM_S0_DFP5; 2317 bios_0_scratch &= ~ATOM_S0_DFP5;
2313 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 2318 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2314 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 2319 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 2c9213739999..654787ec43f4 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -53,7 +53,7 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
53 return false; 53 return false;
54 54
55 rdev->bios = NULL; 55 rdev->bios = NULL;
56 vram_base = drm_get_resource_start(rdev->ddev, 0); 56 vram_base = pci_resource_start(rdev->pdev, 0);
57 bios = ioremap(vram_base, size); 57 bios = ioremap(vram_base, size);
58 if (!bios) { 58 if (!bios) {
59 return false; 59 return false;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 2417d7b06fdb..5e1474cde4b4 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -693,6 +693,10 @@ bool radeon_combios_sideport_present(struct radeon_device *rdev)
693 struct drm_device *dev = rdev->ddev; 693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info; 694 u16 igp_info;
695 695
696 /* sideport is AMD only */
697 if (rdev->family == CHIP_RS400)
698 return false;
699
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 700 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697 701
698 if (igp_info) { 702 if (igp_info) {
@@ -1205,7 +1209,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1205 RBIOS32(tmds_info + i * 10 + 0x08); 1209 RBIOS32(tmds_info + i * 10 + 0x08);
1206 tmds->tmds_pll[i].freq = 1210 tmds->tmds_pll[i].freq =
1207 RBIOS16(tmds_info + i * 10 + 0x10); 1211 RBIOS16(tmds_info + i * 10 + 0x10);
1208 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1212 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1209 tmds->tmds_pll[i].freq, 1213 tmds->tmds_pll[i].freq,
1210 tmds->tmds_pll[i].value); 1214 tmds->tmds_pll[i].value);
1211 } 1215 }
@@ -1223,7 +1227,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1223 stride += 10; 1227 stride += 10;
1224 else 1228 else
1225 stride += 6; 1229 stride += 6;
1226 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", 1230 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1227 tmds->tmds_pll[i].freq, 1231 tmds->tmds_pll[i].freq,
1228 tmds->tmds_pll[i].value); 1232 tmds->tmds_pll[i].value);
1229 } 1233 }
@@ -2208,7 +2212,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2208 uint16_t tmds_info = 2212 uint16_t tmds_info =
2209 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2213 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2210 if (tmds_info) { 2214 if (tmds_info) {
2211 DRM_DEBUG("Found DFP table, assuming DVI connector\n"); 2215 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2212 2216
2213 radeon_add_legacy_encoder(dev, 2217 radeon_add_legacy_encoder(dev,
2214 radeon_get_encoder_id(dev, 2218 radeon_get_encoder_id(dev,
@@ -2234,7 +2238,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2234 } else { 2238 } else {
2235 uint16_t crt_info = 2239 uint16_t crt_info =
2236 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2240 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2237 DRM_DEBUG("Found CRT table, assuming VGA connector\n"); 2241 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2238 if (crt_info) { 2242 if (crt_info) {
2239 radeon_add_legacy_encoder(dev, 2243 radeon_add_legacy_encoder(dev,
2240 radeon_get_encoder_id(dev, 2244 radeon_get_encoder_id(dev,
@@ -2251,7 +2255,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2251 CONNECTOR_OBJECT_ID_VGA, 2255 CONNECTOR_OBJECT_ID_VGA,
2252 &hpd); 2256 &hpd);
2253 } else { 2257 } else {
2254 DRM_DEBUG("No connector info found\n"); 2258 DRM_DEBUG_KMS("No connector info found\n");
2255 return false; 2259 return false;
2256 } 2260 }
2257 } 2261 }
@@ -2340,7 +2344,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2340 ddc_i2c.valid = false; 2344 ddc_i2c.valid = false;
2341 break; 2345 break;
2342 } 2346 }
2343 DRM_DEBUG("LCD DDC Info Table found!\n"); 2347 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2344 } else 2348 } else
2345 ddc_i2c.valid = false; 2349 ddc_i2c.valid = false;
2346 2350
@@ -2941,9 +2945,8 @@ static void combios_write_ram_size(struct drm_device *dev)
2941 if (rev < 3) { 2945 if (rev < 3) {
2942 mem_cntl = RBIOS32(offset + 1); 2946 mem_cntl = RBIOS32(offset + 1);
2943 mem_size = RBIOS16(offset + 5); 2947 mem_size = RBIOS16(offset + 5);
2944 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && 2948 if ((rdev->family < CHIP_R200) &&
2945 ((dev->pdev->device != 0x515e) 2949 !ASIC_IS_RN50(rdev))
2946 && (dev->pdev->device != 0x5969)))
2947 WREG32(RADEON_MEM_CNTL, mem_cntl); 2950 WREG32(RADEON_MEM_CNTL, mem_cntl);
2948 } 2951 }
2949 } 2952 }
@@ -2954,10 +2957,8 @@ static void combios_write_ram_size(struct drm_device *dev)
2954 if (offset) { 2957 if (offset) {
2955 rev = RBIOS8(offset - 1); 2958 rev = RBIOS8(offset - 1);
2956 if (rev < 1) { 2959 if (rev < 1) {
2957 if (((rdev->flags & RADEON_FAMILY_MASK) < 2960 if ((rdev->family < CHIP_R200)
2958 CHIP_R200) 2961 && !ASIC_IS_RN50(rdev)) {
2959 && ((dev->pdev->device != 0x515e)
2960 && (dev->pdev->device != 0x5969))) {
2961 int ram = 0; 2962 int ram = 0;
2962 int mem_addr_mapping = 0; 2963 int mem_addr_mapping = 0;
2963 2964
@@ -3121,14 +3122,14 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3121 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3122 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3122 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3123 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3123 if (connected) { 3124 if (connected) {
3124 DRM_DEBUG("TV1 connected\n"); 3125 DRM_DEBUG_KMS("TV1 connected\n");
3125 /* fix me */ 3126 /* fix me */
3126 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3127 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3127 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3128 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3128 bios_5_scratch |= RADEON_TV1_ON; 3129 bios_5_scratch |= RADEON_TV1_ON;
3129 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3130 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3130 } else { 3131 } else {
3131 DRM_DEBUG("TV1 disconnected\n"); 3132 DRM_DEBUG_KMS("TV1 disconnected\n");
3132 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3133 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3133 bios_5_scratch &= ~RADEON_TV1_ON; 3134 bios_5_scratch &= ~RADEON_TV1_ON;
3134 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3135 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
@@ -3137,12 +3138,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3137 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3138 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3138 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3139 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3139 if (connected) { 3140 if (connected) {
3140 DRM_DEBUG("LCD1 connected\n"); 3141 DRM_DEBUG_KMS("LCD1 connected\n");
3141 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3142 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3142 bios_5_scratch |= RADEON_LCD1_ON; 3143 bios_5_scratch |= RADEON_LCD1_ON;
3143 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3144 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3144 } else { 3145 } else {
3145 DRM_DEBUG("LCD1 disconnected\n"); 3146 DRM_DEBUG_KMS("LCD1 disconnected\n");
3146 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3147 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3147 bios_5_scratch &= ~RADEON_LCD1_ON; 3148 bios_5_scratch &= ~RADEON_LCD1_ON;
3148 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3149 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
@@ -3151,12 +3152,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3151 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3152 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3152 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3153 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3153 if (connected) { 3154 if (connected) {
3154 DRM_DEBUG("CRT1 connected\n"); 3155 DRM_DEBUG_KMS("CRT1 connected\n");
3155 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3156 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3156 bios_5_scratch |= RADEON_CRT1_ON; 3157 bios_5_scratch |= RADEON_CRT1_ON;
3157 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3158 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3158 } else { 3159 } else {
3159 DRM_DEBUG("CRT1 disconnected\n"); 3160 DRM_DEBUG_KMS("CRT1 disconnected\n");
3160 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3161 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3161 bios_5_scratch &= ~RADEON_CRT1_ON; 3162 bios_5_scratch &= ~RADEON_CRT1_ON;
3162 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3163 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
@@ -3165,12 +3166,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3165 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3166 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3166 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3167 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3167 if (connected) { 3168 if (connected) {
3168 DRM_DEBUG("CRT2 connected\n"); 3169 DRM_DEBUG_KMS("CRT2 connected\n");
3169 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3170 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3170 bios_5_scratch |= RADEON_CRT2_ON; 3171 bios_5_scratch |= RADEON_CRT2_ON;
3171 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3172 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3172 } else { 3173 } else {
3173 DRM_DEBUG("CRT2 disconnected\n"); 3174 DRM_DEBUG_KMS("CRT2 disconnected\n");
3174 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3175 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3175 bios_5_scratch &= ~RADEON_CRT2_ON; 3176 bios_5_scratch &= ~RADEON_CRT2_ON;
3176 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3177 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
@@ -3179,12 +3180,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3179 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3180 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3180 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3181 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3181 if (connected) { 3182 if (connected) {
3182 DRM_DEBUG("DFP1 connected\n"); 3183 DRM_DEBUG_KMS("DFP1 connected\n");
3183 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3184 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3184 bios_5_scratch |= RADEON_DFP1_ON; 3185 bios_5_scratch |= RADEON_DFP1_ON;
3185 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3186 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3186 } else { 3187 } else {
3187 DRM_DEBUG("DFP1 disconnected\n"); 3188 DRM_DEBUG_KMS("DFP1 disconnected\n");
3188 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3189 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3189 bios_5_scratch &= ~RADEON_DFP1_ON; 3190 bios_5_scratch &= ~RADEON_DFP1_ON;
3190 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3191 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
@@ -3193,12 +3194,12 @@ radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3193 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3194 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3194 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3195 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3195 if (connected) { 3196 if (connected) {
3196 DRM_DEBUG("DFP2 connected\n"); 3197 DRM_DEBUG_KMS("DFP2 connected\n");
3197 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3198 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3198 bios_5_scratch |= RADEON_DFP2_ON; 3199 bios_5_scratch |= RADEON_DFP2_ON;
3199 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3200 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3200 } else { 3201 } else {
3201 DRM_DEBUG("DFP2 disconnected\n"); 3202 DRM_DEBUG_KMS("DFP2 disconnected\n");
3202 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3203 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3203 bios_5_scratch &= ~RADEON_DFP2_ON; 3204 bios_5_scratch &= ~RADEON_DFP2_ON;
3204 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3205 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index adccbc2c202c..2395c8600cf4 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -214,7 +214,7 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
214 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 214 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
215 drm_mode_set_name(mode); 215 drm_mode_set_name(mode);
216 216
217 DRM_DEBUG("Adding native panel mode %s\n", mode->name); 217 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
218 } else if (native_mode->hdisplay != 0 && 218 } else if (native_mode->hdisplay != 0 &&
219 native_mode->vdisplay != 0) { 219 native_mode->vdisplay != 0) {
220 /* mac laptops without an edid */ 220 /* mac laptops without an edid */
@@ -226,7 +226,7 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
226 */ 226 */
227 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 227 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
228 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 228 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
229 DRM_DEBUG("Adding cvt approximation of native panel mode %s\n", mode->name); 229 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
230 } 230 }
231 return mode; 231 return mode;
232} 232}
@@ -312,6 +312,20 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
312 } 312 }
313 } 313 }
314 314
315 if (property == rdev->mode_info.underscan_property) {
316 /* need to find digital encoder on connector */
317 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
318 if (!encoder)
319 return 0;
320
321 radeon_encoder = to_radeon_encoder(encoder);
322
323 if (radeon_encoder->underscan_type != val) {
324 radeon_encoder->underscan_type = val;
325 radeon_property_change_mode(&radeon_encoder->base);
326 }
327 }
328
315 if (property == rdev->mode_info.tv_std_property) { 329 if (property == rdev->mode_info.tv_std_property) {
316 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC); 330 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
317 if (!encoder) { 331 if (!encoder) {
@@ -522,7 +536,7 @@ static int radeon_lvds_set_property(struct drm_connector *connector,
522 struct radeon_encoder *radeon_encoder; 536 struct radeon_encoder *radeon_encoder;
523 enum radeon_rmx_type rmx_type; 537 enum radeon_rmx_type rmx_type;
524 538
525 DRM_DEBUG("\n"); 539 DRM_DEBUG_KMS("\n");
526 if (property != dev->mode_config.scaling_mode_property) 540 if (property != dev->mode_config.scaling_mode_property)
527 return 0; 541 return 0;
528 542
@@ -1082,6 +1096,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1082 drm_connector_attach_property(&radeon_connector->base, 1096 drm_connector_attach_property(&radeon_connector->base,
1083 rdev->mode_info.load_detect_property, 1097 rdev->mode_info.load_detect_property,
1084 1); 1098 1);
1099 /* no HPD on analog connectors */
1100 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1085 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1101 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1086 break; 1102 break;
1087 case DRM_MODE_CONNECTOR_DVIA: 1103 case DRM_MODE_CONNECTOR_DVIA:
@@ -1096,6 +1112,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1096 drm_connector_attach_property(&radeon_connector->base, 1112 drm_connector_attach_property(&radeon_connector->base,
1097 rdev->mode_info.load_detect_property, 1113 rdev->mode_info.load_detect_property,
1098 1); 1114 1);
1115 /* no HPD on analog connectors */
1116 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1099 break; 1117 break;
1100 case DRM_MODE_CONNECTOR_DVII: 1118 case DRM_MODE_CONNECTOR_DVII:
1101 case DRM_MODE_CONNECTOR_DVID: 1119 case DRM_MODE_CONNECTOR_DVID:
@@ -1116,6 +1134,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1116 drm_connector_attach_property(&radeon_connector->base, 1134 drm_connector_attach_property(&radeon_connector->base,
1117 rdev->mode_info.coherent_mode_property, 1135 rdev->mode_info.coherent_mode_property,
1118 1); 1136 1);
1137 if (ASIC_IS_AVIVO(rdev))
1138 drm_connector_attach_property(&radeon_connector->base,
1139 rdev->mode_info.underscan_property,
1140 UNDERSCAN_AUTO);
1119 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1141 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1120 radeon_connector->dac_load_detect = true; 1142 radeon_connector->dac_load_detect = true;
1121 drm_connector_attach_property(&radeon_connector->base, 1143 drm_connector_attach_property(&radeon_connector->base,
@@ -1141,6 +1163,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1141 drm_connector_attach_property(&radeon_connector->base, 1163 drm_connector_attach_property(&radeon_connector->base,
1142 rdev->mode_info.coherent_mode_property, 1164 rdev->mode_info.coherent_mode_property,
1143 1); 1165 1);
1166 if (ASIC_IS_AVIVO(rdev))
1167 drm_connector_attach_property(&radeon_connector->base,
1168 rdev->mode_info.underscan_property,
1169 UNDERSCAN_AUTO);
1144 subpixel_order = SubPixelHorizontalRGB; 1170 subpixel_order = SubPixelHorizontalRGB;
1145 break; 1171 break;
1146 case DRM_MODE_CONNECTOR_DisplayPort: 1172 case DRM_MODE_CONNECTOR_DisplayPort:
@@ -1172,6 +1198,10 @@ radeon_add_atom_connector(struct drm_device *dev,
1172 drm_connector_attach_property(&radeon_connector->base, 1198 drm_connector_attach_property(&radeon_connector->base,
1173 rdev->mode_info.coherent_mode_property, 1199 rdev->mode_info.coherent_mode_property,
1174 1); 1200 1);
1201 if (ASIC_IS_AVIVO(rdev))
1202 drm_connector_attach_property(&radeon_connector->base,
1203 rdev->mode_info.underscan_property,
1204 UNDERSCAN_AUTO);
1175 break; 1205 break;
1176 case DRM_MODE_CONNECTOR_SVIDEO: 1206 case DRM_MODE_CONNECTOR_SVIDEO:
1177 case DRM_MODE_CONNECTOR_Composite: 1207 case DRM_MODE_CONNECTOR_Composite:
@@ -1186,6 +1216,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1186 drm_connector_attach_property(&radeon_connector->base, 1216 drm_connector_attach_property(&radeon_connector->base,
1187 rdev->mode_info.tv_std_property, 1217 rdev->mode_info.tv_std_property,
1188 radeon_atombios_get_tv_info(rdev)); 1218 radeon_atombios_get_tv_info(rdev));
1219 /* no HPD on analog connectors */
1220 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1189 } 1221 }
1190 break; 1222 break;
1191 case DRM_MODE_CONNECTOR_LVDS: 1223 case DRM_MODE_CONNECTOR_LVDS:
@@ -1209,7 +1241,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1209 break; 1241 break;
1210 } 1242 }
1211 1243
1212 if (hpd->hpd == RADEON_HPD_NONE) { 1244 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
1213 if (i2c_bus->valid) 1245 if (i2c_bus->valid)
1214 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1246 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1215 } else 1247 } else
@@ -1276,6 +1308,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1276 drm_connector_attach_property(&radeon_connector->base, 1308 drm_connector_attach_property(&radeon_connector->base,
1277 rdev->mode_info.load_detect_property, 1309 rdev->mode_info.load_detect_property,
1278 1); 1310 1);
1311 /* no HPD on analog connectors */
1312 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1279 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1313 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1280 break; 1314 break;
1281 case DRM_MODE_CONNECTOR_DVIA: 1315 case DRM_MODE_CONNECTOR_DVIA:
@@ -1290,6 +1324,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1290 drm_connector_attach_property(&radeon_connector->base, 1324 drm_connector_attach_property(&radeon_connector->base,
1291 rdev->mode_info.load_detect_property, 1325 rdev->mode_info.load_detect_property,
1292 1); 1326 1);
1327 /* no HPD on analog connectors */
1328 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1293 break; 1329 break;
1294 case DRM_MODE_CONNECTOR_DVII: 1330 case DRM_MODE_CONNECTOR_DVII:
1295 case DRM_MODE_CONNECTOR_DVID: 1331 case DRM_MODE_CONNECTOR_DVID:
@@ -1328,6 +1364,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1328 drm_connector_attach_property(&radeon_connector->base, 1364 drm_connector_attach_property(&radeon_connector->base,
1329 rdev->mode_info.tv_std_property, 1365 rdev->mode_info.tv_std_property,
1330 radeon_combios_get_tv_info(rdev)); 1366 radeon_combios_get_tv_info(rdev));
1367 /* no HPD on analog connectors */
1368 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
1331 } 1369 }
1332 break; 1370 break;
1333 case DRM_MODE_CONNECTOR_LVDS: 1371 case DRM_MODE_CONNECTOR_LVDS:
@@ -1345,7 +1383,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1345 break; 1383 break;
1346 } 1384 }
1347 1385
1348 if (hpd->hpd == RADEON_HPD_NONE) { 1386 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
1349 if (i2c_bus->valid) 1387 if (i2c_bus->valid)
1350 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1388 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1351 } else 1389 } else
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 2f042a3c0e62..eb6b9eed7349 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -2120,8 +2120,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2120 else 2120 else
2121 dev_priv->flags |= RADEON_IS_PCI; 2121 dev_priv->flags |= RADEON_IS_PCI;
2122 2122
2123 ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 2123 ret = drm_addmap(dev, pci_resource_start(dev->pdev, 2),
2124 drm_get_resource_len(dev, 2), _DRM_REGISTERS, 2124 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2125 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); 2125 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2126 if (ret != 0) 2126 if (ret != 0)
2127 return ret; 2127 return ret;
@@ -2194,9 +2194,9 @@ int radeon_driver_firstopen(struct drm_device *dev)
2194 2194
2195 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 2195 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2196 2196
2197 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 2197 dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2198 ret = drm_addmap(dev, dev_priv->fb_aper_offset, 2198 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2199 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 2199 pci_resource_len(dev->pdev, 0), _DRM_FRAME_BUFFER,
2200 _DRM_WRITE_COMBINING, &map); 2200 _DRM_WRITE_COMBINING, &map);
2201 if (ret != 0) 2201 if (ret != 0)
2202 return ret; 2202 return ret;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index dd279da90546..a64811a94519 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -415,6 +415,22 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
415 return r; 415 return r;
416} 416}
417 417
418static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
419{
420 struct radeon_device *rdev = info->dev->dev_private;
421
422 WREG32_IO(reg*4, val);
423}
424
425static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
426{
427 struct radeon_device *rdev = info->dev->dev_private;
428 uint32_t r;
429
430 r = RREG32_IO(reg*4);
431 return r;
432}
433
418int radeon_atombios_init(struct radeon_device *rdev) 434int radeon_atombios_init(struct radeon_device *rdev)
419{ 435{
420 struct card_info *atom_card_info = 436 struct card_info *atom_card_info =
@@ -427,6 +443,15 @@ int radeon_atombios_init(struct radeon_device *rdev)
427 atom_card_info->dev = rdev->ddev; 443 atom_card_info->dev = rdev->ddev;
428 atom_card_info->reg_read = cail_reg_read; 444 atom_card_info->reg_read = cail_reg_read;
429 atom_card_info->reg_write = cail_reg_write; 445 atom_card_info->reg_write = cail_reg_write;
446 /* needed for iio ops */
447 if (rdev->rio_mem) {
448 atom_card_info->ioreg_read = cail_ioreg_read;
449 atom_card_info->ioreg_write = cail_ioreg_write;
450 } else {
451 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
452 atom_card_info->ioreg_read = cail_reg_read;
453 atom_card_info->ioreg_write = cail_reg_write;
454 }
430 atom_card_info->mc_read = cail_mc_read; 455 atom_card_info->mc_read = cail_mc_read;
431 atom_card_info->mc_write = cail_mc_write; 456 atom_card_info->mc_write = cail_mc_write;
432 atom_card_info->pll_read = cail_pll_read; 457 atom_card_info->pll_read = cail_pll_read;
@@ -573,7 +598,7 @@ int radeon_device_init(struct radeon_device *rdev,
573 struct pci_dev *pdev, 598 struct pci_dev *pdev,
574 uint32_t flags) 599 uint32_t flags)
575{ 600{
576 int r; 601 int r, i;
577 int dma_bits; 602 int dma_bits;
578 603
579 rdev->shutdown = false; 604 rdev->shutdown = false;
@@ -650,8 +675,8 @@ int radeon_device_init(struct radeon_device *rdev,
650 675
651 /* Registers mapping */ 676 /* Registers mapping */
652 /* TODO: block userspace mapping of io register */ 677 /* TODO: block userspace mapping of io register */
653 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2); 678 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
654 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2); 679 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
655 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 680 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
656 if (rdev->rmmio == NULL) { 681 if (rdev->rmmio == NULL) {
657 return -ENOMEM; 682 return -ENOMEM;
@@ -659,6 +684,17 @@ int radeon_device_init(struct radeon_device *rdev,
659 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 684 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
660 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 685 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
661 686
687 /* io port mapping */
688 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
689 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
690 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
691 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
692 break;
693 }
694 }
695 if (rdev->rio_mem == NULL)
696 DRM_ERROR("Unable to find PCI I/O BAR\n");
697
662 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 698 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
663 /* this will fail for cards that aren't VGA class devices, just 699 /* this will fail for cards that aren't VGA class devices, just
664 * ignore it */ 700 * ignore it */
@@ -701,6 +737,9 @@ void radeon_device_fini(struct radeon_device *rdev)
701 destroy_workqueue(rdev->wq); 737 destroy_workqueue(rdev->wq);
702 vga_switcheroo_unregister_client(rdev->pdev); 738 vga_switcheroo_unregister_client(rdev->pdev);
703 vga_client_register(rdev->pdev, NULL, NULL, NULL); 739 vga_client_register(rdev->pdev, NULL, NULL, NULL);
740 if (rdev->rio_mem)
741 pci_iounmap(rdev->pdev, rdev->rio_mem);
742 rdev->rio_mem = NULL;
704 iounmap(rdev->rmmio); 743 iounmap(rdev->rmmio);
705 rdev->rmmio = NULL; 744 rdev->rmmio = NULL;
706} 745}
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 8154cdf796e4..74dac9635d70 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -42,7 +42,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
42 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_device *rdev = dev->dev_private;
43 int i; 43 int i;
44 44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id); 45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47 47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
@@ -75,7 +75,7 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
75 struct radeon_device *rdev = dev->dev_private; 75 struct radeon_device *rdev = dev->dev_private;
76 int i; 76 int i;
77 77
78 DRM_DEBUG("%d\n", radeon_crtc->crtc_id); 78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80 80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
@@ -469,7 +469,7 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
469 uint32_t post_div; 469 uint32_t post_div;
470 u32 pll_out_min, pll_out_max; 470 u32 pll_out_min, pll_out_max;
471 471
472 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 472 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
473 freq = freq * 1000; 473 freq = freq * 1000;
474 474
475 if (pll->flags & RADEON_PLL_IS_LCD) { 475 if (pll->flags & RADEON_PLL_IS_LCD) {
@@ -558,15 +558,17 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
558 current_freq = radeon_div(tmp, ref_div * post_div); 558 current_freq = radeon_div(tmp, ref_div * post_div);
559 559
560 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 560 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
561 error = freq - current_freq; 561 if (freq < current_freq)
562 error = error < 0 ? 0xffffffff : error; 562 error = 0xffffffff;
563 else
564 error = freq - current_freq;
563 } else 565 } else
564 error = abs(current_freq - freq); 566 error = abs(current_freq - freq);
565 vco_diff = abs(vco - best_vco); 567 vco_diff = abs(vco - best_vco);
566 568
567 if ((best_vco == 0 && error < best_error) || 569 if ((best_vco == 0 && error < best_error) ||
568 (best_vco != 0 && 570 (best_vco != 0 &&
569 (error < best_error - 100 || 571 ((best_error > 100 && error < best_error - 100) ||
570 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 572 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
571 best_post_div = post_div; 573 best_post_div = post_div;
572 best_ref_div = ref_div; 574 best_ref_div = ref_div;
@@ -803,7 +805,7 @@ done:
803 *ref_div_p = ref_div; 805 *ref_div_p = ref_div;
804 *post_div_p = post_div; 806 *post_div_p = post_div;
805 807
806 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); 808 DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
807} 809}
808 810
809void radeon_compute_pll(struct radeon_pll *pll, 811void radeon_compute_pll(struct radeon_pll *pll,
@@ -919,6 +921,12 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
919 { TV_STD_SECAM, "secam" }, 921 { TV_STD_SECAM, "secam" },
920}; 922};
921 923
924static struct drm_prop_enum_list radeon_underscan_enum_list[] =
925{ { UNDERSCAN_OFF, "off" },
926 { UNDERSCAN_ON, "on" },
927 { UNDERSCAN_AUTO, "auto" },
928};
929
922static int radeon_modeset_create_props(struct radeon_device *rdev) 930static int radeon_modeset_create_props(struct radeon_device *rdev)
923{ 931{
924 int i, sz; 932 int i, sz;
@@ -972,6 +980,18 @@ static int radeon_modeset_create_props(struct radeon_device *rdev)
972 radeon_tv_std_enum_list[i].name); 980 radeon_tv_std_enum_list[i].name);
973 } 981 }
974 982
983 sz = ARRAY_SIZE(radeon_underscan_enum_list);
984 rdev->mode_info.underscan_property =
985 drm_property_create(rdev->ddev,
986 DRM_MODE_PROP_ENUM,
987 "underscan", sz);
988 for (i = 0; i < sz; i++) {
989 drm_property_add_enum(rdev->mode_info.underscan_property,
990 i,
991 radeon_underscan_enum_list[i].type,
992 radeon_underscan_enum_list[i].name);
993 }
994
975 return 0; 995 return 0;
976} 996}
977 997
@@ -1067,15 +1087,26 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1067 struct drm_display_mode *adjusted_mode) 1087 struct drm_display_mode *adjusted_mode)
1068{ 1088{
1069 struct drm_device *dev = crtc->dev; 1089 struct drm_device *dev = crtc->dev;
1090 struct radeon_device *rdev = dev->dev_private;
1070 struct drm_encoder *encoder; 1091 struct drm_encoder *encoder;
1071 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1092 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1072 struct radeon_encoder *radeon_encoder; 1093 struct radeon_encoder *radeon_encoder;
1094 struct drm_connector *connector;
1095 struct radeon_connector *radeon_connector;
1073 bool first = true; 1096 bool first = true;
1097 u32 src_v = 1, dst_v = 1;
1098 u32 src_h = 1, dst_h = 1;
1099
1100 radeon_crtc->h_border = 0;
1101 radeon_crtc->v_border = 0;
1074 1102
1075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1103 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1076 radeon_encoder = to_radeon_encoder(encoder);
1077 if (encoder->crtc != crtc) 1104 if (encoder->crtc != crtc)
1078 continue; 1105 continue;
1106 radeon_encoder = to_radeon_encoder(encoder);
1107 connector = radeon_get_connector_for_encoder(encoder);
1108 radeon_connector = to_radeon_connector(connector);
1109
1079 if (first) { 1110 if (first) {
1080 /* set scaling */ 1111 /* set scaling */
1081 if (radeon_encoder->rmx_type == RMX_OFF) 1112 if (radeon_encoder->rmx_type == RMX_OFF)
@@ -1085,31 +1116,49 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1085 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1116 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1086 else 1117 else
1087 radeon_crtc->rmx_type = RMX_OFF; 1118 radeon_crtc->rmx_type = RMX_OFF;
1119 src_v = crtc->mode.vdisplay;
1120 dst_v = radeon_crtc->native_mode.vdisplay;
1121 src_h = crtc->mode.hdisplay;
1122 dst_h = radeon_crtc->native_mode.vdisplay;
1088 /* copy native mode */ 1123 /* copy native mode */
1089 memcpy(&radeon_crtc->native_mode, 1124 memcpy(&radeon_crtc->native_mode,
1090 &radeon_encoder->native_mode, 1125 &radeon_encoder->native_mode,
1091 sizeof(struct drm_display_mode)); 1126 sizeof(struct drm_display_mode));
1127
1128 /* fix up for overscan on hdmi */
1129 if (ASIC_IS_AVIVO(rdev) &&
1130 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1131 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1132 drm_detect_hdmi_monitor(radeon_connector->edid)))) {
1133 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1134 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1135 radeon_crtc->rmx_type = RMX_FULL;
1136 src_v = crtc->mode.vdisplay;
1137 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1138 src_h = crtc->mode.hdisplay;
1139 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1140 }
1092 first = false; 1141 first = false;
1093 } else { 1142 } else {
1094 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1143 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1095 /* WARNING: Right now this can't happen but 1144 /* WARNING: Right now this can't happen but
1096 * in the future we need to check that scaling 1145 * in the future we need to check that scaling
1097 * are consistent accross different encoder 1146 * are consistent across different encoder
1098 * (ie all encoder can work with the same 1147 * (ie all encoder can work with the same
1099 * scaling). 1148 * scaling).
1100 */ 1149 */
1101 DRM_ERROR("Scaling not consistent accross encoder.\n"); 1150 DRM_ERROR("Scaling not consistent across encoder.\n");
1102 return false; 1151 return false;
1103 } 1152 }
1104 } 1153 }
1105 } 1154 }
1106 if (radeon_crtc->rmx_type != RMX_OFF) { 1155 if (radeon_crtc->rmx_type != RMX_OFF) {
1107 fixed20_12 a, b; 1156 fixed20_12 a, b;
1108 a.full = dfixed_const(crtc->mode.vdisplay); 1157 a.full = dfixed_const(src_v);
1109 b.full = dfixed_const(radeon_crtc->native_mode.hdisplay); 1158 b.full = dfixed_const(dst_v);
1110 radeon_crtc->vsc.full = dfixed_div(a, b); 1159 radeon_crtc->vsc.full = dfixed_div(a, b);
1111 a.full = dfixed_const(crtc->mode.hdisplay); 1160 a.full = dfixed_const(src_h);
1112 b.full = dfixed_const(radeon_crtc->native_mode.vdisplay); 1161 b.full = dfixed_const(dst_h);
1113 radeon_crtc->hsc.full = dfixed_div(a, b); 1162 radeon_crtc->hsc.full = dfixed_div(a, b);
1114 } else { 1163 } else {
1115 radeon_crtc->vsc.full = dfixed_const(1); 1164 radeon_crtc->vsc.full = dfixed_const(1);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index e166fe4d7c30..795403b0e2cd 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -46,9 +46,10 @@
46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
47 * - 2.4.0 - add crtc id query 47 * - 2.4.0 - add crtc id query
48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
49 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
49 */ 50 */
50#define KMS_DRIVER_MAJOR 2 51#define KMS_DRIVER_MAJOR 2
51#define KMS_DRIVER_MINOR 5 52#define KMS_DRIVER_MINOR 6
52#define KMS_DRIVER_PATCHLEVEL 0 53#define KMS_DRIVER_PATCHLEVEL 0
53int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 54int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
54int radeon_driver_unload_kms(struct drm_device *dev); 55int radeon_driver_unload_kms(struct drm_device *dev);
@@ -238,7 +239,7 @@ static struct drm_driver kms_driver;
238static int __devinit 239static int __devinit
239radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 240radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
240{ 241{
241 return drm_get_dev(pdev, ent, &kms_driver); 242 return drm_get_pci_dev(pdev, ent, &kms_driver);
242} 243}
243 244
244static void 245static void
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index e0b30b264c28..263c8098d7dd 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -205,14 +205,14 @@ void radeon_encoder_set_active_device(struct drm_encoder *encoder)
205 if (connector->encoder == encoder) { 205 if (connector->encoder == encoder) {
206 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; 207 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", 208 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder->active_device, radeon_encoder->devices, 209 radeon_encoder->active_device, radeon_encoder->devices,
210 radeon_connector->devices, encoder->encoder_type); 210 radeon_connector->devices, encoder->encoder_type);
211 } 211 }
212 } 212 }
213} 213}
214 214
215static struct drm_connector * 215struct drm_connector *
216radeon_get_connector_for_encoder(struct drm_encoder *encoder) 216radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217{ 217{
218 struct drm_device *dev = encoder->dev; 218 struct drm_device *dev = encoder->dev;
@@ -1021,7 +1021,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1021 1021
1022 memset(&args, 0, sizeof(args)); 1022 memset(&args, 0, sizeof(args));
1023 1023
1024 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1024 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1025 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1025 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1026 radeon_encoder->active_device); 1026 radeon_encoder->active_device);
1027 switch (radeon_encoder->encoder_id) { 1027 switch (radeon_encoder->encoder_id) {
@@ -1484,7 +1484,7 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
1484 uint32_t bios_0_scratch; 1484 uint32_t bios_0_scratch;
1485 1485
1486 if (!atombios_dac_load_detect(encoder, connector)) { 1486 if (!atombios_dac_load_detect(encoder, connector)) {
1487 DRM_DEBUG("detect returned false \n"); 1487 DRM_DEBUG_KMS("detect returned false \n");
1488 return connector_status_unknown; 1488 return connector_status_unknown;
1489 } 1489 }
1490 1490
@@ -1493,7 +1493,7 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
1493 else 1493 else
1494 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1494 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1495 1495
1496 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1496 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1497 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1497 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1498 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1498 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1499 return connector_status_connected; 1499 return connector_status_connected;
@@ -1694,6 +1694,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1694 radeon_encoder->encoder_id = encoder_id; 1694 radeon_encoder->encoder_id = encoder_id;
1695 radeon_encoder->devices = supported_device; 1695 radeon_encoder->devices = supported_device;
1696 radeon_encoder->rmx_type = RMX_OFF; 1696 radeon_encoder->rmx_type = RMX_OFF;
1697 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1697 1698
1698 switch (radeon_encoder->encoder_id) { 1699 switch (radeon_encoder->encoder_id) {
1699 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1700 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
@@ -1707,6 +1708,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1707 } else { 1708 } else {
1708 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1709 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1709 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1710 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1711 if (ASIC_IS_AVIVO(rdev))
1712 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1710 } 1713 }
1711 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1714 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1712 break; 1715 break;
@@ -1736,6 +1739,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1736 } else { 1739 } else {
1737 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1740 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1738 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1741 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1742 if (ASIC_IS_AVIVO(rdev))
1743 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1739 } 1744 }
1740 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1745 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1741 break; 1746 break;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index ab389f89fa8d..ddcd3b13f151 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -49,7 +49,7 @@ int radeon_driver_unload_kms(struct drm_device *dev)
49int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 49int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50{ 50{
51 struct radeon_device *rdev; 51 struct radeon_device *rdev;
52 int r; 52 int r, acpi_status;
53 53
54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55 if (rdev == NULL) { 55 if (rdev == NULL) {
@@ -77,6 +77,12 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
77 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 77 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
78 goto out; 78 goto out;
79 } 79 }
80
81 /* Call ACPI methods */
82 acpi_status = radeon_acpi_init(rdev);
83 if (acpi_status)
84 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
85
80 /* Again modeset_init should fail only on fatal error 86 /* Again modeset_init should fail only on fatal error
81 * otherwise it should provide enough functionalities 87 * otherwise it should provide enough functionalities
82 * for shadowfb to run 88 * for shadowfb to run
@@ -135,15 +141,36 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
135 } 141 }
136 } 142 }
137 if (!found) { 143 if (!found) {
138 DRM_DEBUG("unknown crtc id %d\n", value); 144 DRM_DEBUG_KMS("unknown crtc id %d\n", value);
139 return -EINVAL; 145 return -EINVAL;
140 } 146 }
141 break; 147 break;
142 case RADEON_INFO_ACCEL_WORKING2: 148 case RADEON_INFO_ACCEL_WORKING2:
143 value = rdev->accel_working; 149 value = rdev->accel_working;
144 break; 150 break;
151 case RADEON_INFO_TILING_CONFIG:
152 if (rdev->family >= CHIP_CEDAR)
153 value = rdev->config.evergreen.tile_config;
154 else if (rdev->family >= CHIP_RV770)
155 value = rdev->config.rv770.tile_config;
156 else if (rdev->family >= CHIP_R600)
157 value = rdev->config.r600.tile_config;
158 else {
159 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
160 return -EINVAL;
161 }
162 case RADEON_INFO_WANT_HYPERZ:
163 mutex_lock(&dev->struct_mutex);
164 if (rdev->hyperz_filp)
165 value = 0;
166 else {
167 rdev->hyperz_filp = filp;
168 value = 1;
169 }
170 mutex_unlock(&dev->struct_mutex);
171 break;
145 default: 172 default:
146 DRM_DEBUG("Invalid request %d\n", info->request); 173 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
147 return -EINVAL; 174 return -EINVAL;
148 } 175 }
149 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { 176 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
@@ -181,9 +208,11 @@ void radeon_driver_postclose_kms(struct drm_device *dev,
181void radeon_driver_preclose_kms(struct drm_device *dev, 208void radeon_driver_preclose_kms(struct drm_device *dev,
182 struct drm_file *file_priv) 209 struct drm_file *file_priv)
183{ 210{
211 struct radeon_device *rdev = dev->dev_private;
212 if (rdev->hyperz_filp == file_priv)
213 rdev->hyperz_filp = NULL;
184} 214}
185 215
186
187/* 216/*
188 * VBlank related functions. 217 * VBlank related functions.
189 */ 218 */
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index e1e5255396ac..989df519a1e4 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -362,10 +362,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
362 uint32_t gen_cntl_reg, gen_cntl_val; 362 uint32_t gen_cntl_reg, gen_cntl_val;
363 int r; 363 int r;
364 364
365 DRM_DEBUG("\n"); 365 DRM_DEBUG_KMS("\n");
366 /* no fb bound */ 366 /* no fb bound */
367 if (!crtc->fb) { 367 if (!crtc->fb) {
368 DRM_DEBUG("No FB bound\n"); 368 DRM_DEBUG_KMS("No FB bound\n");
369 return 0; 369 return 0;
370 } 370 }
371 371
@@ -528,7 +528,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
528 uint32_t crtc_v_sync_strt_wid; 528 uint32_t crtc_v_sync_strt_wid;
529 bool is_tv = false; 529 bool is_tv = false;
530 530
531 DRM_DEBUG("\n"); 531 DRM_DEBUG_KMS("\n");
532 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 532 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
533 if (encoder->crtc == crtc) { 533 if (encoder->crtc == crtc) {
534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -757,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
757 } 757 }
758 } 758 }
759 759
760 DRM_DEBUG("\n"); 760 DRM_DEBUG_KMS("\n");
761 761
762 if (!use_bios_divs) { 762 if (!use_bios_divs) {
763 radeon_compute_pll(pll, mode->clock, 763 radeon_compute_pll(pll, mode->clock,
@@ -772,7 +772,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
772 if (!post_div->divider) 772 if (!post_div->divider)
773 post_div = &post_divs[0]; 773 post_div = &post_divs[0];
774 774
775 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", 775 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
776 (unsigned)freq, 776 (unsigned)freq,
777 feedback_div, 777 feedback_div,
778 reference_div, 778 reference_div,
@@ -841,12 +841,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
841 | RADEON_P2PLL_SLEEP 841 | RADEON_P2PLL_SLEEP
842 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 842 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
843 843
844 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 844 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
845 (unsigned)pll_ref_div, 845 (unsigned)pll_ref_div,
846 (unsigned)pll_fb_post_div, 846 (unsigned)pll_fb_post_div,
847 (unsigned)htotal_cntl, 847 (unsigned)htotal_cntl,
848 RREG32_PLL(RADEON_P2PLL_CNTL)); 848 RREG32_PLL(RADEON_P2PLL_CNTL));
849 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", 849 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
850 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 850 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
851 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 851 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
852 (unsigned)((pll_fb_post_div & 852 (unsigned)((pll_fb_post_div &
@@ -947,12 +947,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
947 | RADEON_PPLL_ATOMIC_UPDATE_EN 947 | RADEON_PPLL_ATOMIC_UPDATE_EN
948 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 948 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
949 949
950 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 950 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
951 pll_ref_div, 951 pll_ref_div,
952 pll_fb_post_div, 952 pll_fb_post_div,
953 (unsigned)htotal_cntl, 953 (unsigned)htotal_cntl,
954 RREG32_PLL(RADEON_PPLL_CNTL)); 954 RREG32_PLL(RADEON_PPLL_CNTL));
955 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", 955 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
956 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 956 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
957 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 957 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
958 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 958 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 5688a0cf6bbe..b8149cbc0c70 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -47,7 +47,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 int panel_pwr_delay = 2000; 48 int panel_pwr_delay = 2000;
49 bool is_mac = false; 49 bool is_mac = false;
50 DRM_DEBUG("\n"); 50 DRM_DEBUG_KMS("\n");
51 51
52 if (radeon_encoder->enc_priv) { 52 if (radeon_encoder->enc_priv) {
53 if (rdev->is_atom_bios) { 53 if (rdev->is_atom_bios) {
@@ -151,7 +151,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
151 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 151 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
152 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; 152 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
153 153
154 DRM_DEBUG("\n"); 154 DRM_DEBUG_KMS("\n");
155 155
156 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 156 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
157 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; 157 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
@@ -167,7 +167,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
167 } else { 167 } else {
168 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 168 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
169 if (lvds) { 169 if (lvds) {
170 DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); 170 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
171 lvds_gen_cntl = lvds->lvds_gen_cntl; 171 lvds_gen_cntl = lvds->lvds_gen_cntl;
172 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 172 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
173 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 173 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
@@ -250,7 +250,7 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode
250 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); 250 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
251 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 251 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
252 252
253 DRM_DEBUG("\n"); 253 DRM_DEBUG_KMS("\n");
254 254
255 switch (mode) { 255 switch (mode) {
256 case DRM_MODE_DPMS_ON: 256 case DRM_MODE_DPMS_ON:
@@ -315,7 +315,7 @@ static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
315 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 315 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
316 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; 316 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
317 317
318 DRM_DEBUG("\n"); 318 DRM_DEBUG_KMS("\n");
319 319
320 if (radeon_crtc->crtc_id == 0) { 320 if (radeon_crtc->crtc_id == 0) {
321 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 321 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
@@ -446,7 +446,7 @@ static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
446 struct drm_device *dev = encoder->dev; 446 struct drm_device *dev = encoder->dev;
447 struct radeon_device *rdev = dev->dev_private; 447 struct radeon_device *rdev = dev->dev_private;
448 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); 448 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
449 DRM_DEBUG("\n"); 449 DRM_DEBUG_KMS("\n");
450 450
451 switch (mode) { 451 switch (mode) {
452 case DRM_MODE_DPMS_ON: 452 case DRM_MODE_DPMS_ON:
@@ -502,7 +502,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
502 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; 502 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
503 int i; 503 int i;
504 504
505 DRM_DEBUG("\n"); 505 DRM_DEBUG_KMS("\n");
506 506
507 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); 507 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
508 tmp &= 0xfffff; 508 tmp &= 0xfffff;
@@ -610,7 +610,7 @@ static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
610 struct drm_device *dev = encoder->dev; 610 struct drm_device *dev = encoder->dev;
611 struct radeon_device *rdev = dev->dev_private; 611 struct radeon_device *rdev = dev->dev_private;
612 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 612 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
613 DRM_DEBUG("\n"); 613 DRM_DEBUG_KMS("\n");
614 614
615 switch (mode) { 615 switch (mode) {
616 case DRM_MODE_DPMS_ON: 616 case DRM_MODE_DPMS_ON:
@@ -666,7 +666,7 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
666 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 666 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
667 uint32_t fp2_gen_cntl; 667 uint32_t fp2_gen_cntl;
668 668
669 DRM_DEBUG("\n"); 669 DRM_DEBUG_KMS("\n");
670 670
671 if (rdev->is_atom_bios) { 671 if (rdev->is_atom_bios) {
672 radeon_encoder->pixel_clock = adjusted_mode->clock; 672 radeon_encoder->pixel_clock = adjusted_mode->clock;
@@ -760,7 +760,7 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
760 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 760 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
761 uint32_t tv_master_cntl = 0; 761 uint32_t tv_master_cntl = 0;
762 bool is_tv; 762 bool is_tv;
763 DRM_DEBUG("\n"); 763 DRM_DEBUG_KMS("\n");
764 764
765 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 765 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
766 766
@@ -878,7 +878,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
878 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; 878 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
879 bool is_tv = false; 879 bool is_tv = false;
880 880
881 DRM_DEBUG("\n"); 881 DRM_DEBUG_KMS("\n");
882 882
883 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 883 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
884 884
@@ -1075,10 +1075,10 @@ static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1075 tmp = RREG32(RADEON_TV_DAC_CNTL); 1075 tmp = RREG32(RADEON_TV_DAC_CNTL);
1076 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { 1076 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1077 found = true; 1077 found = true;
1078 DRM_DEBUG("S-video TV connection detected\n"); 1078 DRM_DEBUG_KMS("S-video TV connection detected\n");
1079 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1079 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1080 found = true; 1080 found = true;
1081 DRM_DEBUG("Composite TV connection detected\n"); 1081 DRM_DEBUG_KMS("Composite TV connection detected\n");
1082 } 1082 }
1083 1083
1084 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1084 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
@@ -1141,10 +1141,10 @@ static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1141 tmp = RREG32(RADEON_TV_DAC_CNTL); 1141 tmp = RREG32(RADEON_TV_DAC_CNTL);
1142 if (tmp & RADEON_TV_DAC_GDACDET) { 1142 if (tmp & RADEON_TV_DAC_GDACDET) {
1143 found = true; 1143 found = true;
1144 DRM_DEBUG("S-video TV connection detected\n"); 1144 DRM_DEBUG_KMS("S-video TV connection detected\n");
1145 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1145 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1146 found = true; 1146 found = true;
1147 DRM_DEBUG("Composite TV connection detected\n"); 1147 DRM_DEBUG_KMS("Composite TV connection detected\n");
1148 } 1148 }
1149 1149
1150 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 1150 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 032040397743..c7b6cb428d09 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -496,7 +496,7 @@ static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
496 496
497 restart -= v_offset + h_offset; 497 restart -= v_offset + h_offset;
498 498
499 DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 499 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
500 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 500 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
501 501
502 tv_dac->tv.hrestart = restart % h_total; 502 tv_dac->tv.hrestart = restart % h_total;
@@ -505,7 +505,7 @@ static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
505 restart /= v_total; 505 restart /= v_total;
506 tv_dac->tv.frestart = restart % f_total; 506 tv_dac->tv.frestart = restart % f_total;
507 507
508 DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n", 508 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n",
509 (unsigned)tv_dac->tv.frestart, 509 (unsigned)tv_dac->tv.frestart,
510 (unsigned)tv_dac->tv.vrestart, 510 (unsigned)tv_dac->tv.vrestart,
511 (unsigned)tv_dac->tv.hrestart); 511 (unsigned)tv_dac->tv.hrestart);
@@ -523,7 +523,7 @@ static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
523 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 523 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
524 ((u32)h_inc << RADEON_H_INC_SHIFT); 524 ((u32)h_inc << RADEON_H_INC_SHIFT);
525 525
526 DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 526 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
527 527
528 return h_changed; 528 return h_changed;
529} 529}
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 95696aa57ac8..71aea4037e90 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -66,6 +66,12 @@ enum radeon_tv_std {
66 TV_STD_PAL_N, 66 TV_STD_PAL_N,
67}; 67};
68 68
69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
69enum radeon_hpd_id { 75enum radeon_hpd_id {
70 RADEON_HPD_1 = 0, 76 RADEON_HPD_1 = 0,
71 RADEON_HPD_2, 77 RADEON_HPD_2,
@@ -226,10 +232,12 @@ struct radeon_mode_info {
226 struct drm_property *coherent_mode_property; 232 struct drm_property *coherent_mode_property;
227 /* DAC enable load detect */ 233 /* DAC enable load detect */
228 struct drm_property *load_detect_property; 234 struct drm_property *load_detect_property;
229 /* TV standard load detect */ 235 /* TV standard */
230 struct drm_property *tv_std_property; 236 struct drm_property *tv_std_property;
231 /* legacy TMDS PLL detect */ 237 /* legacy TMDS PLL detect */
232 struct drm_property *tmds_pll_property; 238 struct drm_property *tmds_pll_property;
239 /* underscan */
240 struct drm_property *underscan_property;
233 /* hardcoded DFP edid from BIOS */ 241 /* hardcoded DFP edid from BIOS */
234 struct edid *bios_hardcoded_edid; 242 struct edid *bios_hardcoded_edid;
235 243
@@ -266,6 +274,8 @@ struct radeon_crtc {
266 uint32_t legacy_display_base_addr; 274 uint32_t legacy_display_base_addr;
267 uint32_t legacy_cursor_offset; 275 uint32_t legacy_cursor_offset;
268 enum radeon_rmx_type rmx_type; 276 enum radeon_rmx_type rmx_type;
277 u8 h_border;
278 u8 v_border;
269 fixed20_12 vsc; 279 fixed20_12 vsc;
270 fixed20_12 hsc; 280 fixed20_12 hsc;
271 struct drm_display_mode native_mode; 281 struct drm_display_mode native_mode;
@@ -354,6 +364,7 @@ struct radeon_encoder {
354 uint32_t flags; 364 uint32_t flags;
355 uint32_t pixel_clock; 365 uint32_t pixel_clock;
356 enum radeon_rmx_type rmx_type; 366 enum radeon_rmx_type rmx_type;
367 enum radeon_underscan_type underscan_type;
357 struct drm_display_mode native_mode; 368 struct drm_display_mode native_mode;
358 void *enc_priv; 369 void *enc_priv;
359 int audio_polling_active; 370 int audio_polling_active;
@@ -392,7 +403,7 @@ struct radeon_connector {
392 uint32_t connector_id; 403 uint32_t connector_id;
393 uint32_t devices; 404 uint32_t devices;
394 struct radeon_i2c_chan *ddc_bus; 405 struct radeon_i2c_chan *ddc_bus;
395 /* some systems have a an hdmi and vga port with a shared ddc line */ 406 /* some systems have an hdmi and vga port with a shared ddc line */
396 bool shared_ddc; 407 bool shared_ddc;
397 bool use_digital; 408 bool use_digital;
398 /* we need to mind the EDID between detect 409 /* we need to mind the EDID between detect
@@ -414,6 +425,9 @@ radeon_combios_get_tv_info(struct radeon_device *rdev);
414extern enum radeon_tv_std 425extern enum radeon_tv_std
415radeon_atombios_get_tv_info(struct radeon_device *rdev); 426radeon_atombios_get_tv_info(struct radeon_device *rdev);
416 427
428extern struct drm_connector *
429radeon_get_connector_for_encoder(struct drm_encoder *encoder);
430
417extern void radeon_connector_hotplug(struct drm_connector *connector); 431extern void radeon_connector_hotplug(struct drm_connector *connector);
418extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 432extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
419extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 433extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d5b9373ce06c..0afd1e62347d 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -110,6 +110,7 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
110 bo->surface_reg = -1; 110 bo->surface_reg = -1;
111 INIT_LIST_HEAD(&bo->list); 111 INIT_LIST_HEAD(&bo->list);
112 112
113retry:
113 radeon_ttm_placement_from_domain(bo, domain); 114 radeon_ttm_placement_from_domain(bo, domain);
114 /* Kernel allocation are uninterruptible */ 115 /* Kernel allocation are uninterruptible */
115 mutex_lock(&rdev->vram_mutex); 116 mutex_lock(&rdev->vram_mutex);
@@ -118,10 +119,15 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
118 &radeon_ttm_bo_destroy); 119 &radeon_ttm_bo_destroy);
119 mutex_unlock(&rdev->vram_mutex); 120 mutex_unlock(&rdev->vram_mutex);
120 if (unlikely(r != 0)) { 121 if (unlikely(r != 0)) {
121 if (r != -ERESTARTSYS) 122 if (r != -ERESTARTSYS) {
123 if (domain == RADEON_GEM_DOMAIN_VRAM) {
124 domain |= RADEON_GEM_DOMAIN_GTT;
125 goto retry;
126 }
122 dev_err(rdev->dev, 127 dev_err(rdev->dev,
123 "object_init failed for (%lu, 0x%08X)\n", 128 "object_init failed for (%lu, 0x%08X)\n",
124 size, domain); 129 size, domain);
130 }
125 return r; 131 return r;
126 } 132 }
127 *bo_ptr = bo; 133 *bo_ptr = bo;
@@ -321,6 +327,7 @@ int radeon_bo_list_validate(struct list_head *head)
321{ 327{
322 struct radeon_bo_list *lobj; 328 struct radeon_bo_list *lobj;
323 struct radeon_bo *bo; 329 struct radeon_bo *bo;
330 u32 domain;
324 int r; 331 int r;
325 332
326 list_for_each_entry(lobj, head, list) { 333 list_for_each_entry(lobj, head, list) {
@@ -333,17 +340,19 @@ int radeon_bo_list_validate(struct list_head *head)
333 list_for_each_entry(lobj, head, list) { 340 list_for_each_entry(lobj, head, list) {
334 bo = lobj->bo; 341 bo = lobj->bo;
335 if (!bo->pin_count) { 342 if (!bo->pin_count) {
336 if (lobj->wdomain) { 343 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
337 radeon_ttm_placement_from_domain(bo, 344
338 lobj->wdomain); 345 retry:
339 } else { 346 radeon_ttm_placement_from_domain(bo, domain);
340 radeon_ttm_placement_from_domain(bo,
341 lobj->rdomain);
342 }
343 r = ttm_bo_validate(&bo->tbo, &bo->placement, 347 r = ttm_bo_validate(&bo->tbo, &bo->placement,
344 true, false, false); 348 true, false, false);
345 if (unlikely(r)) 349 if (unlikely(r)) {
350 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
351 domain |= RADEON_GEM_DOMAIN_GTT;
352 goto retry;
353 }
346 return r; 354 return r;
355 }
347 } 356 }
348 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 357 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
349 lobj->tiling_flags = bo->tiling_flags; 358 lobj->tiling_flags = bo->tiling_flags;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 3fa6984d9896..95f8b3a3c43d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -27,6 +27,8 @@
27#include <linux/acpi.h> 27#include <linux/acpi.h>
28#endif 28#endif
29#include <linux/power_supply.h> 29#include <linux/power_supply.h>
30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
30 32
31#define RADEON_IDLE_LOOP_MS 100 33#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200 34#define RADEON_RECLOCK_DELAY_MS 200
@@ -60,9 +62,9 @@ static int radeon_acpi_event(struct notifier_block *nb,
60 62
61 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) { 63 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
62 if (power_supply_is_system_supplied() > 0) 64 if (power_supply_is_system_supplied() > 0)
63 DRM_DEBUG("pm: AC\n"); 65 DRM_DEBUG_DRIVER("pm: AC\n");
64 else 66 else
65 DRM_DEBUG("pm: DC\n"); 67 DRM_DEBUG_DRIVER("pm: DC\n");
66 68
67 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 69 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
68 if (rdev->pm.profile == PM_PROFILE_AUTO) { 70 if (rdev->pm.profile == PM_PROFILE_AUTO) {
@@ -196,7 +198,7 @@ static void radeon_set_power_state(struct radeon_device *rdev)
196 radeon_set_engine_clock(rdev, sclk); 198 radeon_set_engine_clock(rdev, sclk);
197 radeon_pm_debug_check_in_vbl(rdev, true); 199 radeon_pm_debug_check_in_vbl(rdev, true);
198 rdev->pm.current_sclk = sclk; 200 rdev->pm.current_sclk = sclk;
199 DRM_DEBUG("Setting: e: %d\n", sclk); 201 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
200 } 202 }
201 203
202 /* set memory clock */ 204 /* set memory clock */
@@ -205,7 +207,7 @@ static void radeon_set_power_state(struct radeon_device *rdev)
205 radeon_set_memory_clock(rdev, mclk); 207 radeon_set_memory_clock(rdev, mclk);
206 radeon_pm_debug_check_in_vbl(rdev, true); 208 radeon_pm_debug_check_in_vbl(rdev, true);
207 rdev->pm.current_mclk = mclk; 209 rdev->pm.current_mclk = mclk;
208 DRM_DEBUG("Setting: m: %d\n", mclk); 210 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
209 } 211 }
210 212
211 if (misc_after) 213 if (misc_after)
@@ -217,7 +219,7 @@ static void radeon_set_power_state(struct radeon_device *rdev)
217 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 219 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
218 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 220 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
219 } else 221 } else
220 DRM_DEBUG("pm: GUI not idle!!!\n"); 222 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
221} 223}
222 224
223static void radeon_pm_set_clocks(struct radeon_device *rdev) 225static void radeon_pm_set_clocks(struct radeon_device *rdev)
@@ -292,27 +294,27 @@ static void radeon_pm_print_states(struct radeon_device *rdev)
292 struct radeon_power_state *power_state; 294 struct radeon_power_state *power_state;
293 struct radeon_pm_clock_info *clock_info; 295 struct radeon_pm_clock_info *clock_info;
294 296
295 DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states); 297 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
296 for (i = 0; i < rdev->pm.num_power_states; i++) { 298 for (i = 0; i < rdev->pm.num_power_states; i++) {
297 power_state = &rdev->pm.power_state[i]; 299 power_state = &rdev->pm.power_state[i];
298 DRM_DEBUG("State %d: %s\n", i, 300 DRM_DEBUG_DRIVER("State %d: %s\n", i,
299 radeon_pm_state_type_name[power_state->type]); 301 radeon_pm_state_type_name[power_state->type]);
300 if (i == rdev->pm.default_power_state_index) 302 if (i == rdev->pm.default_power_state_index)
301 DRM_DEBUG("\tDefault"); 303 DRM_DEBUG_DRIVER("\tDefault");
302 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 304 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
303 DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes); 305 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
304 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 306 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
305 DRM_DEBUG("\tSingle display only\n"); 307 DRM_DEBUG_DRIVER("\tSingle display only\n");
306 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 308 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
307 for (j = 0; j < power_state->num_clock_modes; j++) { 309 for (j = 0; j < power_state->num_clock_modes; j++) {
308 clock_info = &(power_state->clock_info[j]); 310 clock_info = &(power_state->clock_info[j]);
309 if (rdev->flags & RADEON_IS_IGP) 311 if (rdev->flags & RADEON_IS_IGP)
310 DRM_DEBUG("\t\t%d e: %d%s\n", 312 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
311 j, 313 j,
312 clock_info->sclk * 10, 314 clock_info->sclk * 10,
313 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : ""); 315 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
314 else 316 else
315 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n", 317 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
316 j, 318 j,
317 clock_info->sclk * 10, 319 clock_info->sclk * 10,
318 clock_info->mclk * 10, 320 clock_info->mclk * 10,
@@ -424,6 +426,82 @@ fail:
424static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 426static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
425static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 427static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
426 428
429static ssize_t radeon_hwmon_show_temp(struct device *dev,
430 struct device_attribute *attr,
431 char *buf)
432{
433 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
434 struct radeon_device *rdev = ddev->dev_private;
435 u32 temp;
436
437 switch (rdev->pm.int_thermal_type) {
438 case THERMAL_TYPE_RV6XX:
439 temp = rv6xx_get_temp(rdev);
440 break;
441 case THERMAL_TYPE_RV770:
442 temp = rv770_get_temp(rdev);
443 break;
444 case THERMAL_TYPE_EVERGREEN:
445 temp = evergreen_get_temp(rdev);
446 break;
447 default:
448 temp = 0;
449 break;
450 }
451
452 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
453}
454
455static ssize_t radeon_hwmon_show_name(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458{
459 return sprintf(buf, "radeon\n");
460}
461
462static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
463static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
464
465static struct attribute *hwmon_attributes[] = {
466 &sensor_dev_attr_temp1_input.dev_attr.attr,
467 &sensor_dev_attr_name.dev_attr.attr,
468 NULL
469};
470
471static const struct attribute_group hwmon_attrgroup = {
472 .attrs = hwmon_attributes,
473};
474
475static void radeon_hwmon_init(struct radeon_device *rdev)
476{
477 int err;
478
479 rdev->pm.int_hwmon_dev = NULL;
480
481 switch (rdev->pm.int_thermal_type) {
482 case THERMAL_TYPE_RV6XX:
483 case THERMAL_TYPE_RV770:
484 case THERMAL_TYPE_EVERGREEN:
485 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
486 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
487 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
488 &hwmon_attrgroup);
489 if (err)
490 DRM_ERROR("Unable to create hwmon sysfs file: %d\n", err);
491 break;
492 default:
493 break;
494 }
495}
496
497static void radeon_hwmon_fini(struct radeon_device *rdev)
498{
499 if (rdev->pm.int_hwmon_dev) {
500 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
501 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
502 }
503}
504
427void radeon_pm_suspend(struct radeon_device *rdev) 505void radeon_pm_suspend(struct radeon_device *rdev)
428{ 506{
429 bool flush_wq = false; 507 bool flush_wq = false;
@@ -471,6 +549,7 @@ int radeon_pm_init(struct radeon_device *rdev)
471 rdev->pm.dynpm_can_downclock = true; 549 rdev->pm.dynpm_can_downclock = true;
472 rdev->pm.current_sclk = rdev->clock.default_sclk; 550 rdev->pm.current_sclk = rdev->clock.default_sclk;
473 rdev->pm.current_mclk = rdev->clock.default_mclk; 551 rdev->pm.current_mclk = rdev->clock.default_mclk;
552 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
474 553
475 if (rdev->bios) { 554 if (rdev->bios) {
476 if (rdev->is_atom_bios) 555 if (rdev->is_atom_bios)
@@ -481,6 +560,8 @@ int radeon_pm_init(struct radeon_device *rdev)
481 radeon_pm_init_profile(rdev); 560 radeon_pm_init_profile(rdev);
482 } 561 }
483 562
563 /* set up the internal thermal sensor if applicable */
564 radeon_hwmon_init(rdev);
484 if (rdev->pm.num_power_states > 1) { 565 if (rdev->pm.num_power_states > 1) {
485 /* where's the best place to put these? */ 566 /* where's the best place to put these? */
486 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 567 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
@@ -536,6 +617,7 @@ void radeon_pm_fini(struct radeon_device *rdev)
536#endif 617#endif
537 } 618 }
538 619
620 radeon_hwmon_fini(rdev);
539 if (rdev->pm.i2c_bus) 621 if (rdev->pm.i2c_bus)
540 radeon_i2c_destroy(rdev->pm.i2c_bus); 622 radeon_i2c_destroy(rdev->pm.i2c_bus);
541} 623}
@@ -576,7 +658,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
576 radeon_pm_get_dynpm_state(rdev); 658 radeon_pm_get_dynpm_state(rdev);
577 radeon_pm_set_clocks(rdev); 659 radeon_pm_set_clocks(rdev);
578 660
579 DRM_DEBUG("radeon: dynamic power management deactivated\n"); 661 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
580 } 662 }
581 } else if (rdev->pm.active_crtc_count == 1) { 663 } else if (rdev->pm.active_crtc_count == 1) {
582 /* TODO: Increase clocks if needed for current mode */ 664 /* TODO: Increase clocks if needed for current mode */
@@ -593,7 +675,7 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
593 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 675 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
594 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work, 676 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
595 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 677 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
596 DRM_DEBUG("radeon: dynamic power management activated\n"); 678 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
597 } 679 }
598 } else { /* count == 0 */ 680 } else { /* count == 0 */
599 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 681 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
@@ -689,7 +771,7 @@ static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish
689 bool in_vbl = radeon_pm_in_vbl(rdev); 771 bool in_vbl = radeon_pm_in_vbl(rdev);
690 772
691 if (in_vbl == false) 773 if (in_vbl == false)
692 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc, 774 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
693 finish ? "exit" : "entry"); 775 finish ? "exit" : "entry");
694 return in_vbl; 776 return in_vbl;
695} 777}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index e9918d88f5b0..84c53e41a88f 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -59,28 +59,28 @@ static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
59/* 59/*
60 * Global memory. 60 * Global memory.
61 */ 61 */
62static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref) 62static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
63{ 63{
64 return ttm_mem_global_init(ref->object); 64 return ttm_mem_global_init(ref->object);
65} 65}
66 66
67static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref) 67static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
68{ 68{
69 ttm_mem_global_release(ref->object); 69 ttm_mem_global_release(ref->object);
70} 70}
71 71
72static int radeon_ttm_global_init(struct radeon_device *rdev) 72static int radeon_ttm_global_init(struct radeon_device *rdev)
73{ 73{
74 struct ttm_global_reference *global_ref; 74 struct drm_global_reference *global_ref;
75 int r; 75 int r;
76 76
77 rdev->mman.mem_global_referenced = false; 77 rdev->mman.mem_global_referenced = false;
78 global_ref = &rdev->mman.mem_global_ref; 78 global_ref = &rdev->mman.mem_global_ref;
79 global_ref->global_type = TTM_GLOBAL_TTM_MEM; 79 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
80 global_ref->size = sizeof(struct ttm_mem_global); 80 global_ref->size = sizeof(struct ttm_mem_global);
81 global_ref->init = &radeon_ttm_mem_global_init; 81 global_ref->init = &radeon_ttm_mem_global_init;
82 global_ref->release = &radeon_ttm_mem_global_release; 82 global_ref->release = &radeon_ttm_mem_global_release;
83 r = ttm_global_item_ref(global_ref); 83 r = drm_global_item_ref(global_ref);
84 if (r != 0) { 84 if (r != 0) {
85 DRM_ERROR("Failed setting up TTM memory accounting " 85 DRM_ERROR("Failed setting up TTM memory accounting "
86 "subsystem.\n"); 86 "subsystem.\n");
@@ -90,14 +90,14 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
90 rdev->mman.bo_global_ref.mem_glob = 90 rdev->mman.bo_global_ref.mem_glob =
91 rdev->mman.mem_global_ref.object; 91 rdev->mman.mem_global_ref.object;
92 global_ref = &rdev->mman.bo_global_ref.ref; 92 global_ref = &rdev->mman.bo_global_ref.ref;
93 global_ref->global_type = TTM_GLOBAL_TTM_BO; 93 global_ref->global_type = DRM_GLOBAL_TTM_BO;
94 global_ref->size = sizeof(struct ttm_bo_global); 94 global_ref->size = sizeof(struct ttm_bo_global);
95 global_ref->init = &ttm_bo_global_init; 95 global_ref->init = &ttm_bo_global_init;
96 global_ref->release = &ttm_bo_global_release; 96 global_ref->release = &ttm_bo_global_release;
97 r = ttm_global_item_ref(global_ref); 97 r = drm_global_item_ref(global_ref);
98 if (r != 0) { 98 if (r != 0) {
99 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 99 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
100 ttm_global_item_unref(&rdev->mman.mem_global_ref); 100 drm_global_item_unref(&rdev->mman.mem_global_ref);
101 return r; 101 return r;
102 } 102 }
103 103
@@ -108,8 +108,8 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
108static void radeon_ttm_global_fini(struct radeon_device *rdev) 108static void radeon_ttm_global_fini(struct radeon_device *rdev)
109{ 109{
110 if (rdev->mman.mem_global_referenced) { 110 if (rdev->mman.mem_global_referenced) {
111 ttm_global_item_unref(&rdev->mman.bo_global_ref.ref); 111 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
112 ttm_global_item_unref(&rdev->mman.mem_global_ref); 112 drm_global_item_unref(&rdev->mman.mem_global_ref);
113 rdev->mman.mem_global_referenced = false; 113 rdev->mman.mem_global_referenced = false;
114 } 114 }
115} 115}
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index 1e97b2d129fd..b506ec1cab4b 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -187,7 +187,6 @@ r300 0x4f60
1870x4364 RS_INST_13 1870x4364 RS_INST_13
1880x4368 RS_INST_14 1880x4368 RS_INST_14
1890x436C RS_INST_15 1890x436C RS_INST_15
1900x43A4 SC_HYPERZ_EN
1910x43A8 SC_EDGERULE 1900x43A8 SC_EDGERULE
1920x43B0 SC_CLIP_0_A 1910x43B0 SC_CLIP_0_A
1930x43B4 SC_CLIP_0_B 1920x43B4 SC_CLIP_0_B
@@ -716,16 +715,4 @@ r300 0x4f60
7160x4F08 ZB_STENCILREFMASK 7150x4F08 ZB_STENCILREFMASK
7170x4F14 ZB_ZTOP 7160x4F14 ZB_ZTOP
7180x4F18 ZB_ZCACHE_CTLSTAT 7170x4F18 ZB_ZCACHE_CTLSTAT
7190x4F1C ZB_BW_CNTL
7200x4F28 ZB_DEPTHCLEARVALUE
7210x4F30 ZB_ZMASK_OFFSET
7220x4F34 ZB_ZMASK_PITCH
7230x4F38 ZB_ZMASK_WRINDEX
7240x4F3C ZB_ZMASK_DWORD
7250x4F40 ZB_ZMASK_RDINDEX
7260x4F44 ZB_HIZ_OFFSET
7270x4F48 ZB_HIZ_WRINDEX
7280x4F4C ZB_HIZ_DWORD
7290x4F50 ZB_HIZ_RDINDEX
7300x4F54 ZB_HIZ_PITCH
7310x4F58 ZB_ZPASS_DATA 7180x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
index e958980d00f1..8c1214c2390f 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r420
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -130,6 +130,7 @@ r420 0x4f60
1300x401C GB_SELECT 1300x401C GB_SELECT
1310x4020 GB_AA_CONFIG 1310x4020 GB_AA_CONFIG
1320x4024 GB_FIFO_SIZE 1320x4024 GB_FIFO_SIZE
1330x4028 GB_Z_PEQ_CONFIG
1330x4100 TX_INVALTAGS 1340x4100 TX_INVALTAGS
1340x4200 GA_POINT_S0 1350x4200 GA_POINT_S0
1350x4204 GA_POINT_T0 1360x4204 GA_POINT_T0
@@ -187,7 +188,6 @@ r420 0x4f60
1870x4364 RS_INST_13 1880x4364 RS_INST_13
1880x4368 RS_INST_14 1890x4368 RS_INST_14
1890x436C RS_INST_15 1900x436C RS_INST_15
1900x43A4 SC_HYPERZ_EN
1910x43A8 SC_EDGERULE 1910x43A8 SC_EDGERULE
1920x43B0 SC_CLIP_0_A 1920x43B0 SC_CLIP_0_A
1930x43B4 SC_CLIP_0_B 1930x43B4 SC_CLIP_0_B
@@ -782,16 +782,4 @@ r420 0x4f60
7820x4F08 ZB_STENCILREFMASK 7820x4F08 ZB_STENCILREFMASK
7830x4F14 ZB_ZTOP 7830x4F14 ZB_ZTOP
7840x4F18 ZB_ZCACHE_CTLSTAT 7840x4F18 ZB_ZCACHE_CTLSTAT
7850x4F1C ZB_BW_CNTL
7860x4F28 ZB_DEPTHCLEARVALUE
7870x4F30 ZB_ZMASK_OFFSET
7880x4F34 ZB_ZMASK_PITCH
7890x4F38 ZB_ZMASK_WRINDEX
7900x4F3C ZB_ZMASK_DWORD
7910x4F40 ZB_ZMASK_RDINDEX
7920x4F44 ZB_HIZ_OFFSET
7930x4F48 ZB_HIZ_WRINDEX
7940x4F4C ZB_HIZ_DWORD
7950x4F50 ZB_HIZ_RDINDEX
7960x4F54 ZB_HIZ_PITCH
7970x4F58 ZB_ZPASS_DATA 7850x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 83e8bc0c2bb2..0828d80396f2 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -187,7 +187,6 @@ rs600 0x6d40
1870x4364 RS_INST_13 1870x4364 RS_INST_13
1880x4368 RS_INST_14 1880x4368 RS_INST_14
1890x436C RS_INST_15 1890x436C RS_INST_15
1900x43A4 SC_HYPERZ_EN
1910x43A8 SC_EDGERULE 1900x43A8 SC_EDGERULE
1920x43B0 SC_CLIP_0_A 1910x43B0 SC_CLIP_0_A
1930x43B4 SC_CLIP_0_B 1920x43B4 SC_CLIP_0_B
@@ -782,16 +781,4 @@ rs600 0x6d40
7820x4F08 ZB_STENCILREFMASK 7810x4F08 ZB_STENCILREFMASK
7830x4F14 ZB_ZTOP 7820x4F14 ZB_ZTOP
7840x4F18 ZB_ZCACHE_CTLSTAT 7830x4F18 ZB_ZCACHE_CTLSTAT
7850x4F1C ZB_BW_CNTL
7860x4F28 ZB_DEPTHCLEARVALUE
7870x4F30 ZB_ZMASK_OFFSET
7880x4F34 ZB_ZMASK_PITCH
7890x4F38 ZB_ZMASK_WRINDEX
7900x4F3C ZB_ZMASK_DWORD
7910x4F40 ZB_ZMASK_RDINDEX
7920x4F44 ZB_HIZ_OFFSET
7930x4F48 ZB_HIZ_WRINDEX
7940x4F4C ZB_HIZ_DWORD
7950x4F50 ZB_HIZ_RDINDEX
7960x4F54 ZB_HIZ_PITCH
7970x4F58 ZB_ZPASS_DATA 7840x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 1e46233985eb..8293855f5f0d 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -235,7 +235,6 @@ rv515 0x6d40
2350x4354 RS_INST_13 2350x4354 RS_INST_13
2360x4358 RS_INST_14 2360x4358 RS_INST_14
2370x435C RS_INST_15 2370x435C RS_INST_15
2380x43A4 SC_HYPERZ_EN
2390x43A8 SC_EDGERULE 2380x43A8 SC_EDGERULE
2400x43B0 SC_CLIP_0_A 2390x43B0 SC_CLIP_0_A
2410x43B4 SC_CLIP_0_B 2400x43B4 SC_CLIP_0_B
@@ -479,17 +478,5 @@ rv515 0x6d40
4790x4F08 ZB_STENCILREFMASK 4780x4F08 ZB_STENCILREFMASK
4800x4F14 ZB_ZTOP 4790x4F14 ZB_ZTOP
4810x4F18 ZB_ZCACHE_CTLSTAT 4800x4F18 ZB_ZCACHE_CTLSTAT
4820x4F1C ZB_BW_CNTL
4830x4F28 ZB_DEPTHCLEARVALUE
4840x4F30 ZB_ZMASK_OFFSET
4850x4F34 ZB_ZMASK_PITCH
4860x4F38 ZB_ZMASK_WRINDEX
4870x4F3C ZB_ZMASK_DWORD
4880x4F40 ZB_ZMASK_RDINDEX
4890x4F44 ZB_HIZ_OFFSET
4900x4F48 ZB_HIZ_WRINDEX
4910x4F4C ZB_HIZ_DWORD
4920x4F50 ZB_HIZ_RDINDEX
4930x4F54 ZB_HIZ_PITCH
4940x4F58 ZB_ZPASS_DATA 4810x4F58 ZB_ZPASS_DATA
4950x4FD4 ZB_STENCILREFMASK_BF 4820x4FD4 ZB_STENCILREFMASK_BF
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index f454c9a5e7f2..ae2b76b9a388 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -55,14 +55,6 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
55 rdev->mc.gtt_size = 32 * 1024 * 1024; 55 rdev->mc.gtt_size = 32 * 1024 * 1024;
56 return; 56 return;
57 } 57 }
58 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
59 /* FIXME: RS400 & RS480 seems to have issue with GART size
60 * if 4G of system memory (needs more testing)
61 */
62 /* XXX is this still an issue with proper alignment? */
63 rdev->mc.gtt_size = 32 * 1024 * 1024;
64 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
65 }
66} 58}
67 59
68void rs400_gart_tlb_flush(struct radeon_device *rdev) 60void rs400_gart_tlb_flush(struct radeon_device *rdev)
@@ -483,6 +475,8 @@ int rs400_init(struct radeon_device *rdev)
483 /* Initialize surface registers */ 475 /* Initialize surface registers */
484 radeon_surface_init(rdev); 476 radeon_surface_init(rdev);
485 /* TODO: disable VGA need to use VGA request */ 477 /* TODO: disable VGA need to use VGA request */
478 /* restore some register to sane defaults */
479 r100_restore_sanity(rdev);
486 /* BIOS*/ 480 /* BIOS*/
487 if (!radeon_get_bios(rdev)) { 481 if (!radeon_get_bios(rdev)) {
488 if (ASIC_IS_AVIVO(rdev)) 482 if (ASIC_IS_AVIVO(rdev))
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 6dc15ea8ba33..cc05b230d7ef 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -686,8 +686,8 @@ void rs600_mc_init(struct radeon_device *rdev)
686{ 686{
687 u64 base; 687 u64 base;
688 688
689 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 689 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
690 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 690 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
691 rdev->mc.vram_is_ddr = true; 691 rdev->mc.vram_is_ddr = true;
692 rdev->mc.vram_width = 128; 692 rdev->mc.vram_width = 128;
693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
@@ -696,7 +696,6 @@ void rs600_mc_init(struct radeon_device *rdev)
696 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 696 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
697 base = RREG32_MC(R_000004_MC_FB_LOCATION); 697 base = RREG32_MC(R_000004_MC_FB_LOCATION);
698 base = G_000004_MC_FB_START(base) << 16; 698 base = G_000004_MC_FB_START(base) << 16;
699 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
700 radeon_vram_location(rdev, &rdev->mc, base); 699 radeon_vram_location(rdev, &rdev->mc, base);
701 rdev->mc.gtt_base_align = 0; 700 rdev->mc.gtt_base_align = 0;
702 radeon_gtt_location(rdev, &rdev->mc); 701 radeon_gtt_location(rdev, &rdev->mc);
@@ -813,6 +812,13 @@ static int rs600_startup(struct radeon_device *rdev)
813 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 812 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
814 return r; 813 return r;
815 } 814 }
815
816 r = r600_audio_init(rdev);
817 if (r) {
818 dev_err(rdev->dev, "failed initializing audio\n");
819 return r;
820 }
821
816 return 0; 822 return 0;
817} 823}
818 824
@@ -839,6 +845,7 @@ int rs600_resume(struct radeon_device *rdev)
839 845
840int rs600_suspend(struct radeon_device *rdev) 846int rs600_suspend(struct radeon_device *rdev)
841{ 847{
848 r600_audio_fini(rdev);
842 r100_cp_disable(rdev); 849 r100_cp_disable(rdev);
843 r100_wb_disable(rdev); 850 r100_wb_disable(rdev);
844 rs600_irq_disable(rdev); 851 rs600_irq_disable(rdev);
@@ -848,6 +855,7 @@ int rs600_suspend(struct radeon_device *rdev)
848 855
849void rs600_fini(struct radeon_device *rdev) 856void rs600_fini(struct radeon_device *rdev)
850{ 857{
858 r600_audio_fini(rdev);
851 r100_cp_fini(rdev); 859 r100_cp_fini(rdev);
852 r100_wb_fini(rdev); 860 r100_wb_fini(rdev);
853 r100_ib_fini(rdev); 861 r100_ib_fini(rdev);
@@ -871,6 +879,8 @@ int rs600_init(struct radeon_device *rdev)
871 radeon_scratch_init(rdev); 879 radeon_scratch_init(rdev);
872 /* Initialize surface registers */ 880 /* Initialize surface registers */
873 radeon_surface_init(rdev); 881 radeon_surface_init(rdev);
882 /* restore some register to sane defaults */
883 r100_restore_sanity(rdev);
874 /* BIOS */ 884 /* BIOS */
875 if (!radeon_get_bios(rdev)) { 885 if (!radeon_get_bios(rdev)) {
876 if (ASIC_IS_AVIVO(rdev)) 886 if (ASIC_IS_AVIVO(rdev))
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index ce4ecbe10816..3e3f75718be3 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -154,13 +154,13 @@ void rs690_mc_init(struct radeon_device *rdev)
154 rdev->mc.vram_width = 128; 154 rdev->mc.vram_width = 128;
155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
157 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
158 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 161 base = G_000100_MC_FB_START(base) << 16;
162 rs690_pm_info(rdev);
163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
163 rs690_pm_info(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base); 164 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
166 radeon_gtt_location(rdev, &rdev->mc); 166 radeon_gtt_location(rdev, &rdev->mc);
@@ -398,7 +398,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
398 struct drm_display_mode *mode1 = NULL; 398 struct drm_display_mode *mode1 = NULL;
399 struct rs690_watermark wm0; 399 struct rs690_watermark wm0;
400 struct rs690_watermark wm1; 400 struct rs690_watermark wm1;
401 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; 401 u32 tmp;
402 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
403 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
402 fixed20_12 priority_mark02, priority_mark12, fill_rate; 404 fixed20_12 priority_mark02, priority_mark12, fill_rate;
403 fixed20_12 a, b; 405 fixed20_12 a, b;
404 406
@@ -495,10 +497,6 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
495 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 497 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
496 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 498 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
497 } 499 }
498 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
499 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
500 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
501 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
502 } else if (mode0) { 500 } else if (mode0) {
503 if (dfixed_trunc(wm0.dbpp) > 64) 501 if (dfixed_trunc(wm0.dbpp) > 64)
504 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 502 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
@@ -528,13 +526,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
528 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 526 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
529 if (rdev->disp_priority == 2) 527 if (rdev->disp_priority == 2)
530 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 528 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
531 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 529 } else if (mode1) {
532 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
533 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
534 S_006D48_D2MODE_PRIORITY_A_OFF(1));
535 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
536 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
537 } else {
538 if (dfixed_trunc(wm1.dbpp) > 64) 530 if (dfixed_trunc(wm1.dbpp) > 64)
539 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 531 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
540 else 532 else
@@ -563,13 +555,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
563 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 555 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
564 if (rdev->disp_priority == 2) 556 if (rdev->disp_priority == 2)
565 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 557 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
567 S_006548_D1MODE_PRIORITY_A_OFF(1));
568 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
569 S_00654C_D1MODE_PRIORITY_B_OFF(1));
570 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
571 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
572 } 558 }
559
560 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
561 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
562 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
563 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
573} 564}
574 565
575uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 566uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -641,6 +632,13 @@ static int rs690_startup(struct radeon_device *rdev)
641 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 632 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
642 return r; 633 return r;
643 } 634 }
635
636 r = r600_audio_init(rdev);
637 if (r) {
638 dev_err(rdev->dev, "failed initializing audio\n");
639 return r;
640 }
641
644 return 0; 642 return 0;
645} 643}
646 644
@@ -667,6 +665,7 @@ int rs690_resume(struct radeon_device *rdev)
667 665
668int rs690_suspend(struct radeon_device *rdev) 666int rs690_suspend(struct radeon_device *rdev)
669{ 667{
668 r600_audio_fini(rdev);
670 r100_cp_disable(rdev); 669 r100_cp_disable(rdev);
671 r100_wb_disable(rdev); 670 r100_wb_disable(rdev);
672 rs600_irq_disable(rdev); 671 rs600_irq_disable(rdev);
@@ -676,6 +675,7 @@ int rs690_suspend(struct radeon_device *rdev)
676 675
677void rs690_fini(struct radeon_device *rdev) 676void rs690_fini(struct radeon_device *rdev)
678{ 677{
678 r600_audio_fini(rdev);
679 r100_cp_fini(rdev); 679 r100_cp_fini(rdev);
680 r100_wb_fini(rdev); 680 r100_wb_fini(rdev);
681 r100_ib_fini(rdev); 681 r100_ib_fini(rdev);
@@ -699,6 +699,8 @@ int rs690_init(struct radeon_device *rdev)
699 radeon_scratch_init(rdev); 699 radeon_scratch_init(rdev);
700 /* Initialize surface registers */ 700 /* Initialize surface registers */
701 radeon_surface_init(rdev); 701 radeon_surface_init(rdev);
702 /* restore some register to sane defaults */
703 r100_restore_sanity(rdev);
702 /* TODO: disable VGA need to use VGA request */ 704 /* TODO: disable VGA need to use VGA request */
703 /* BIOS*/ 705 /* BIOS*/
704 if (!radeon_get_bios(rdev)) { 706 if (!radeon_get_bios(rdev)) {
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 0c9c169a6852..4d6e86041a9f 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -469,6 +469,8 @@ int rv515_init(struct radeon_device *rdev)
469 /* Initialize surface registers */ 469 /* Initialize surface registers */
470 radeon_surface_init(rdev); 470 radeon_surface_init(rdev);
471 /* TODO: disable VGA need to use VGA request */ 471 /* TODO: disable VGA need to use VGA request */
472 /* restore some register to sane defaults */
473 r100_restore_sanity(rdev);
472 /* BIOS*/ 474 /* BIOS*/
473 if (!radeon_get_bios(rdev)) { 475 if (!radeon_get_bios(rdev)) {
474 if (ASIC_IS_AVIVO(rdev)) 476 if (ASIC_IS_AVIVO(rdev))
@@ -925,7 +927,9 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
925 struct drm_display_mode *mode1 = NULL; 927 struct drm_display_mode *mode1 = NULL;
926 struct rv515_watermark wm0; 928 struct rv515_watermark wm0;
927 struct rv515_watermark wm1; 929 struct rv515_watermark wm1;
928 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; 930 u32 tmp;
931 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
932 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
929 fixed20_12 priority_mark02, priority_mark12, fill_rate; 933 fixed20_12 priority_mark02, priority_mark12, fill_rate;
930 fixed20_12 a, b; 934 fixed20_12 a, b;
931 935
@@ -999,10 +1003,6 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
999 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1003 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1000 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1004 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1001 } 1005 }
1002 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1003 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1004 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1005 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1006 } else if (mode0) { 1006 } else if (mode0) {
1007 if (dfixed_trunc(wm0.dbpp) > 64) 1007 if (dfixed_trunc(wm0.dbpp) > 64)
1008 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1008 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
@@ -1032,11 +1032,7 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1032 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1032 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1033 if (rdev->disp_priority == 2) 1033 if (rdev->disp_priority == 2)
1034 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1034 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1035 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1035 } else if (mode1) {
1036 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1037 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1038 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1039 } else {
1040 if (dfixed_trunc(wm1.dbpp) > 64) 1036 if (dfixed_trunc(wm1.dbpp) > 64)
1041 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1037 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1042 else 1038 else
@@ -1065,11 +1061,12 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1065 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1061 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1066 if (rdev->disp_priority == 2) 1062 if (rdev->disp_priority == 2)
1067 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1063 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1068 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1069 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1070 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1071 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1072 } 1064 }
1065
1066 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1067 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1068 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1069 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1073} 1070}
1074 1071
1075void rv515_bandwidth_update(struct radeon_device *rdev) 1072void rv515_bandwidth_update(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index b7fd82064922..f1c796810117 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -42,6 +42,21 @@
42static void rv770_gpu_init(struct radeon_device *rdev); 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev); 43void rv770_fini(struct radeon_device *rdev);
44 44
45/* get temperature in millidegrees */
46u32 rv770_get_temp(struct radeon_device *rdev)
47{
48 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
49 ASIC_T_SHIFT;
50 u32 actual_temp = 0;
51
52 if ((temp >> 9) & 1)
53 actual_temp = 0;
54 else
55 actual_temp = (temp >> 1) & 0xff;
56
57 return actual_temp * 1000;
58}
59
45void rv770_pm_misc(struct radeon_device *rdev) 60void rv770_pm_misc(struct radeon_device *rdev)
46{ 61{
47 int req_ps_idx = rdev->pm.requested_power_state_index; 62 int req_ps_idx = rdev->pm.requested_power_state_index;
@@ -189,7 +204,10 @@ static void rv770_mc_program(struct radeon_device *rdev)
189 WREG32((0x2c20 + j), 0x00000000); 204 WREG32((0x2c20 + j), 0x00000000);
190 WREG32((0x2c24 + j), 0x00000000); 205 WREG32((0x2c24 + j), 0x00000000);
191 } 206 }
192 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 207 /* r7xx hw bug. Read from HDP_DEBUG1 rather
208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
209 */
210 tmp = RREG32(HDP_DEBUG1);
193 211
194 rv515_mc_stop(rdev, &save); 212 rv515_mc_stop(rdev, &save);
195 if (r600_mc_wait_for_idle(rdev)) { 213 if (r600_mc_wait_for_idle(rdev)) {
@@ -659,8 +677,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
659 r600_count_pipe_bits((cc_rb_backend_disable & 677 r600_count_pipe_bits((cc_rb_backend_disable &
660 R7XX_MAX_BACKENDS_MASK) >> 16)), 678 R7XX_MAX_BACKENDS_MASK) >> 16)),
661 (cc_rb_backend_disable >> 16)); 679 (cc_rb_backend_disable >> 16));
662 gb_tiling_config |= BACKEND_MAP(backend_map);
663 680
681 rdev->config.rv770.tile_config = gb_tiling_config;
682 gb_tiling_config |= BACKEND_MAP(backend_map);
664 683
665 WREG32(GB_TILING_CONFIG, gb_tiling_config); 684 WREG32(GB_TILING_CONFIG, gb_tiling_config);
666 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 685 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
@@ -919,8 +938,8 @@ int rv770_mc_init(struct radeon_device *rdev)
919 } 938 }
920 rdev->mc.vram_width = numchan * chansize; 939 rdev->mc.vram_width = numchan * chansize;
921 /* Could aper size report 0 ? */ 940 /* Could aper size report 0 ? */
922 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 941 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
923 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 942 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
924 /* Setup GPU memory space */ 943 /* Setup GPU memory space */
925 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 944 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
926 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 945 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 9506f8cb99e0..b7a5a20e81dc 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -122,12 +122,18 @@
122#define GUI_ACTIVE (1<<31) 122#define GUI_ACTIVE (1<<31)
123#define GRBM_STATUS2 0x8014 123#define GRBM_STATUS2 0x8014
124 124
125#define CG_MULT_THERMAL_STATUS 0x740
126#define ASIC_T(x) ((x) << 16)
127#define ASIC_T_MASK 0x3FF0000
128#define ASIC_T_SHIFT 16
129
125#define HDP_HOST_PATH_CNTL 0x2C00 130#define HDP_HOST_PATH_CNTL 0x2C00
126#define HDP_NONSURFACE_BASE 0x2C04 131#define HDP_NONSURFACE_BASE 0x2C04
127#define HDP_NONSURFACE_INFO 0x2C08 132#define HDP_NONSURFACE_INFO 0x2C08
128#define HDP_NONSURFACE_SIZE 0x2C0C 133#define HDP_NONSURFACE_SIZE 0x2C0C
129#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 134#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
130#define HDP_TILING_CONFIG 0x2F3C 135#define HDP_TILING_CONFIG 0x2F3C
136#define HDP_DEBUG1 0x2F34
131 137
132#define MC_SHARED_CHMAP 0x2004 138#define MC_SHARED_CHMAP 0x2004
133#define NOOFCHAN_SHIFT 12 139#define NOOFCHAN_SHIFT 12
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 15:07:48 -0500