diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 312 |
1 files changed, 297 insertions, 15 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 1390073c3960..299d657d0168 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
| @@ -48,12 +48,76 @@ | |||
| 48 | #define SI_MAX_TCC 16 | 48 | #define SI_MAX_TCC 16 |
| 49 | #define SI_MAX_TCC_MASK 0xFFFF | 49 | #define SI_MAX_TCC_MASK 0xFFFF |
| 50 | 50 | ||
| 51 | /* SMC IND accessor regs */ | ||
| 52 | #define SMC_IND_INDEX_0 0x200 | ||
| 53 | #define SMC_IND_DATA_0 0x204 | ||
| 54 | |||
| 55 | #define SMC_IND_ACCESS_CNTL 0x228 | ||
| 56 | # define AUTO_INCREMENT_IND_0 (1 << 0) | ||
| 57 | #define SMC_MESSAGE_0 0x22c | ||
| 58 | #define SMC_RESP_0 0x230 | ||
| 59 | |||
| 51 | /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ | 60 | /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ |
| 52 | #define SMC_CG_IND_START 0xc0030000 | 61 | #define SMC_CG_IND_START 0xc0030000 |
| 62 | #define SMC_CG_IND_END 0xc0040000 | ||
| 53 | 63 | ||
| 54 | #define CG_CGTT_LOCAL_0 0x400 | 64 | #define CG_CGTT_LOCAL_0 0x400 |
| 55 | #define CG_CGTT_LOCAL_1 0x401 | 65 | #define CG_CGTT_LOCAL_1 0x401 |
| 56 | 66 | ||
| 67 | /* SMC IND registers */ | ||
| 68 | #define SMC_SYSCON_RESET_CNTL 0x80000000 | ||
| 69 | # define RST_REG (1 << 0) | ||
| 70 | #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 | ||
| 71 | # define CK_DISABLE (1 << 0) | ||
| 72 | # define CKEN (1 << 24) | ||
| 73 | |||
| 74 | #define VGA_HDP_CONTROL 0x328 | ||
| 75 | #define VGA_MEMORY_DISABLE (1 << 4) | ||
| 76 | |||
| 77 | #define DCCG_DISP_SLOW_SELECT_REG 0x4fc | ||
| 78 | #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) | ||
| 79 | #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) | ||
| 80 | #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 | ||
| 81 | #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) | ||
| 82 | #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) | ||
| 83 | #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 | ||
| 84 | |||
| 85 | #define CG_SPLL_FUNC_CNTL 0x600 | ||
| 86 | #define SPLL_RESET (1 << 0) | ||
| 87 | #define SPLL_SLEEP (1 << 1) | ||
| 88 | #define SPLL_BYPASS_EN (1 << 3) | ||
| 89 | #define SPLL_REF_DIV(x) ((x) << 4) | ||
| 90 | #define SPLL_REF_DIV_MASK (0x3f << 4) | ||
| 91 | #define SPLL_PDIV_A(x) ((x) << 20) | ||
| 92 | #define SPLL_PDIV_A_MASK (0x7f << 20) | ||
| 93 | #define SPLL_PDIV_A_SHIFT 20 | ||
| 94 | #define CG_SPLL_FUNC_CNTL_2 0x604 | ||
| 95 | #define SCLK_MUX_SEL(x) ((x) << 0) | ||
| 96 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | ||
| 97 | #define CG_SPLL_FUNC_CNTL_3 0x608 | ||
| 98 | #define SPLL_FB_DIV(x) ((x) << 0) | ||
| 99 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | ||
| 100 | #define SPLL_FB_DIV_SHIFT 0 | ||
| 101 | #define SPLL_DITHEN (1 << 28) | ||
| 102 | #define CG_SPLL_FUNC_CNTL_4 0x60c | ||
| 103 | |||
| 104 | #define SPLL_CNTL_MODE 0x618 | ||
| 105 | # define SPLL_REFCLK_SEL(x) ((x) << 8) | ||
| 106 | # define SPLL_REFCLK_SEL_MASK 0xFF00 | ||
| 107 | |||
| 108 | #define CG_SPLL_SPREAD_SPECTRUM 0x620 | ||
| 109 | #define SSEN (1 << 0) | ||
| 110 | #define CLK_S(x) ((x) << 4) | ||
| 111 | #define CLK_S_MASK (0xfff << 4) | ||
| 112 | #define CLK_S_SHIFT 4 | ||
| 113 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x624 | ||
| 114 | #define CLK_V(x) ((x) << 0) | ||
| 115 | #define CLK_V_MASK (0x3ffffff << 0) | ||
| 116 | #define CLK_V_SHIFT 0 | ||
| 117 | |||
| 118 | #define CG_SPLL_AUTOSCALE_CNTL 0x62c | ||
| 119 | # define AUTOSCALE_ON_SS_CLEAR (1 << 9) | ||
| 120 | |||
| 57 | /* discrete uvd clocks */ | 121 | /* discrete uvd clocks */ |
| 58 | #define CG_UPLL_FUNC_CNTL 0x634 | 122 | #define CG_UPLL_FUNC_CNTL 0x634 |
| 59 | # define UPLL_RESET_MASK 0x00000001 | 123 | # define UPLL_RESET_MASK 0x00000001 |
| @@ -83,21 +147,6 @@ | |||
| 83 | #define CG_UPLL_SPREAD_SPECTRUM 0x650 | 147 | #define CG_UPLL_SPREAD_SPECTRUM 0x650 |
| 84 | # define SSEN_MASK 0x00000001 | 148 | # define SSEN_MASK 0x00000001 |
| 85 | 149 | ||
| 86 | #define CG_MULT_THERMAL_STATUS 0x714 | ||
| 87 | #define ASIC_MAX_TEMP(x) ((x) << 0) | ||
| 88 | #define ASIC_MAX_TEMP_MASK 0x000001ff | ||
| 89 | #define ASIC_MAX_TEMP_SHIFT 0 | ||
| 90 | #define CTF_TEMP(x) ((x) << 9) | ||
| 91 | #define CTF_TEMP_MASK 0x0003fe00 | ||
| 92 | #define CTF_TEMP_SHIFT 9 | ||
| 93 | |||
| 94 | #define VGA_HDP_CONTROL 0x328 | ||
| 95 | #define VGA_MEMORY_DISABLE (1 << 4) | ||
| 96 | |||
| 97 | #define SPLL_CNTL_MODE 0x618 | ||
| 98 | # define SPLL_REFCLK_SEL(x) ((x) << 8) | ||
| 99 | # define SPLL_REFCLK_SEL_MASK 0xFF00 | ||
| 100 | |||
| 101 | #define MPLL_BYPASSCLK_SEL 0x65c | 150 | #define MPLL_BYPASSCLK_SEL 0x65c |
| 102 | # define MPLL_CLKOUT_SEL(x) ((x) << 8) | 151 | # define MPLL_CLKOUT_SEL(x) ((x) << 8) |
| 103 | # define MPLL_CLKOUT_SEL_MASK 0xFF00 | 152 | # define MPLL_CLKOUT_SEL_MASK 0xFF00 |
| @@ -120,6 +169,111 @@ | |||
| 120 | # define ZCLK_SEL(x) ((x) << 8) | 169 | # define ZCLK_SEL(x) ((x) << 8) |
| 121 | # define ZCLK_SEL_MASK 0xFF00 | 170 | # define ZCLK_SEL_MASK 0xFF00 |
| 122 | 171 | ||
| 172 | #define CG_THERMAL_CTRL 0x700 | ||
| 173 | #define DPM_EVENT_SRC(x) ((x) << 0) | ||
| 174 | #define DPM_EVENT_SRC_MASK (7 << 0) | ||
| 175 | #define DIG_THERM_DPM(x) ((x) << 14) | ||
| 176 | #define DIG_THERM_DPM_MASK 0x003FC000 | ||
| 177 | #define DIG_THERM_DPM_SHIFT 14 | ||
| 178 | |||
| 179 | #define CG_THERMAL_INT 0x708 | ||
| 180 | #define DIG_THERM_INTH(x) ((x) << 8) | ||
| 181 | #define DIG_THERM_INTH_MASK 0x0000FF00 | ||
| 182 | #define DIG_THERM_INTH_SHIFT 8 | ||
| 183 | #define DIG_THERM_INTL(x) ((x) << 16) | ||
| 184 | #define DIG_THERM_INTL_MASK 0x00FF0000 | ||
| 185 | #define DIG_THERM_INTL_SHIFT 16 | ||
| 186 | #define THERM_INT_MASK_HIGH (1 << 24) | ||
| 187 | #define THERM_INT_MASK_LOW (1 << 25) | ||
| 188 | |||
| 189 | #define CG_MULT_THERMAL_STATUS 0x714 | ||
| 190 | #define ASIC_MAX_TEMP(x) ((x) << 0) | ||
| 191 | #define ASIC_MAX_TEMP_MASK 0x000001ff | ||
| 192 | #define ASIC_MAX_TEMP_SHIFT 0 | ||
| 193 | #define CTF_TEMP(x) ((x) << 9) | ||
| 194 | #define CTF_TEMP_MASK 0x0003fe00 | ||
| 195 | #define CTF_TEMP_SHIFT 9 | ||
| 196 | |||
| 197 | #define GENERAL_PWRMGT 0x780 | ||
| 198 | # define GLOBAL_PWRMGT_EN (1 << 0) | ||
| 199 | # define STATIC_PM_EN (1 << 1) | ||
| 200 | # define THERMAL_PROTECTION_DIS (1 << 2) | ||
| 201 | # define THERMAL_PROTECTION_TYPE (1 << 3) | ||
| 202 | # define SW_SMIO_INDEX(x) ((x) << 6) | ||
| 203 | # define SW_SMIO_INDEX_MASK (1 << 6) | ||
| 204 | # define SW_SMIO_INDEX_SHIFT 6 | ||
| 205 | # define VOLT_PWRMGT_EN (1 << 10) | ||
| 206 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | ||
| 207 | #define CG_TPC 0x784 | ||
| 208 | #define SCLK_PWRMGT_CNTL 0x788 | ||
| 209 | # define SCLK_PWRMGT_OFF (1 << 0) | ||
| 210 | # define SCLK_LOW_D1 (1 << 1) | ||
| 211 | # define FIR_RESET (1 << 4) | ||
| 212 | # define FIR_FORCE_TREND_SEL (1 << 5) | ||
| 213 | # define FIR_TREND_MODE (1 << 6) | ||
| 214 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | ||
| 215 | # define GFX_CLK_FORCE_ON (1 << 8) | ||
| 216 | # define GFX_CLK_REQUEST_OFF (1 << 9) | ||
| 217 | # define GFX_CLK_FORCE_OFF (1 << 10) | ||
| 218 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) | ||
| 219 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) | ||
| 220 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) | ||
| 221 | # define DYN_LIGHT_SLEEP_EN (1 << 14) | ||
| 222 | |||
| 223 | #define CG_FTV 0x7bc | ||
| 224 | |||
| 225 | #define CG_FFCT_0 0x7c0 | ||
| 226 | # define UTC_0(x) ((x) << 0) | ||
| 227 | # define UTC_0_MASK (0x3ff << 0) | ||
| 228 | # define DTC_0(x) ((x) << 10) | ||
| 229 | # define DTC_0_MASK (0x3ff << 10) | ||
| 230 | |||
| 231 | #define CG_BSP 0x7fc | ||
| 232 | # define BSP(x) ((x) << 0) | ||
| 233 | # define BSP_MASK (0xffff << 0) | ||
| 234 | # define BSU(x) ((x) << 16) | ||
| 235 | # define BSU_MASK (0xf << 16) | ||
| 236 | #define CG_AT 0x800 | ||
| 237 | # define CG_R(x) ((x) << 0) | ||
| 238 | # define CG_R_MASK (0xffff << 0) | ||
| 239 | # define CG_L(x) ((x) << 16) | ||
| 240 | # define CG_L_MASK (0xffff << 16) | ||
| 241 | |||
| 242 | #define CG_GIT 0x804 | ||
| 243 | # define CG_GICST(x) ((x) << 0) | ||
| 244 | # define CG_GICST_MASK (0xffff << 0) | ||
| 245 | # define CG_GIPOT(x) ((x) << 16) | ||
| 246 | # define CG_GIPOT_MASK (0xffff << 16) | ||
| 247 | |||
| 248 | #define CG_SSP 0x80c | ||
| 249 | # define SST(x) ((x) << 0) | ||
| 250 | # define SST_MASK (0xffff << 0) | ||
| 251 | # define SSTU(x) ((x) << 16) | ||
| 252 | # define SSTU_MASK (0xf << 16) | ||
| 253 | |||
| 254 | #define CG_DISPLAY_GAP_CNTL 0x828 | ||
| 255 | # define DISP1_GAP(x) ((x) << 0) | ||
| 256 | # define DISP1_GAP_MASK (3 << 0) | ||
| 257 | # define DISP2_GAP(x) ((x) << 2) | ||
| 258 | # define DISP2_GAP_MASK (3 << 2) | ||
| 259 | # define VBI_TIMER_COUNT(x) ((x) << 4) | ||
| 260 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) | ||
| 261 | # define VBI_TIMER_UNIT(x) ((x) << 20) | ||
| 262 | # define VBI_TIMER_UNIT_MASK (7 << 20) | ||
| 263 | # define DISP1_GAP_MCHG(x) ((x) << 24) | ||
| 264 | # define DISP1_GAP_MCHG_MASK (3 << 24) | ||
| 265 | # define DISP2_GAP_MCHG(x) ((x) << 26) | ||
| 266 | # define DISP2_GAP_MCHG_MASK (3 << 26) | ||
| 267 | |||
| 268 | #define CG_ULV_CONTROL 0x878 | ||
| 269 | #define CG_ULV_PARAMETER 0x87c | ||
| 270 | |||
| 271 | #define SMC_SCRATCH0 0x884 | ||
| 272 | |||
| 273 | #define CG_CAC_CTRL 0x8b8 | ||
| 274 | # define CAC_WINDOW(x) ((x) << 0) | ||
| 275 | # define CAC_WINDOW_MASK 0x00ffffff | ||
| 276 | |||
| 123 | #define DMIF_ADDR_CONFIG 0xBD4 | 277 | #define DMIF_ADDR_CONFIG 0xBD4 |
| 124 | 278 | ||
| 125 | #define DMIF_ADDR_CALC 0xC00 | 279 | #define DMIF_ADDR_CALC 0xC00 |
| @@ -285,6 +439,23 @@ | |||
| 285 | #define NOOFGROUPS_SHIFT 12 | 439 | #define NOOFGROUPS_SHIFT 12 |
| 286 | #define NOOFGROUPS_MASK 0x00001000 | 440 | #define NOOFGROUPS_MASK 0x00001000 |
| 287 | 441 | ||
| 442 | #define MC_ARB_DRAM_TIMING 0x2774 | ||
| 443 | #define MC_ARB_DRAM_TIMING2 0x2778 | ||
| 444 | |||
| 445 | #define MC_ARB_BURST_TIME 0x2808 | ||
| 446 | #define STATE0(x) ((x) << 0) | ||
| 447 | #define STATE0_MASK (0x1f << 0) | ||
| 448 | #define STATE0_SHIFT 0 | ||
| 449 | #define STATE1(x) ((x) << 5) | ||
| 450 | #define STATE1_MASK (0x1f << 5) | ||
| 451 | #define STATE1_SHIFT 5 | ||
| 452 | #define STATE2(x) ((x) << 10) | ||
| 453 | #define STATE2_MASK (0x1f << 10) | ||
| 454 | #define STATE2_SHIFT 10 | ||
| 455 | #define STATE3(x) ((x) << 15) | ||
| 456 | #define STATE3_MASK (0x1f << 15) | ||
| 457 | #define STATE3_SHIFT 15 | ||
| 458 | |||
| 288 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 | 459 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 |
| 289 | #define TRAIN_DONE_D0 (1 << 30) | 460 | #define TRAIN_DONE_D0 (1 << 30) |
| 290 | #define TRAIN_DONE_D1 (1 << 31) | 461 | #define TRAIN_DONE_D1 (1 << 31) |
| @@ -292,15 +463,105 @@ | |||
| 292 | #define MC_SEQ_SUP_CNTL 0x28c8 | 463 | #define MC_SEQ_SUP_CNTL 0x28c8 |
| 293 | #define RUN_MASK (1 << 0) | 464 | #define RUN_MASK (1 << 0) |
| 294 | #define MC_SEQ_SUP_PGM 0x28cc | 465 | #define MC_SEQ_SUP_PGM 0x28cc |
| 466 | #define MC_PMG_AUTO_CMD 0x28d0 | ||
| 295 | 467 | ||
| 296 | #define MC_IO_PAD_CNTL_D0 0x29d0 | 468 | #define MC_IO_PAD_CNTL_D0 0x29d0 |
| 297 | #define MEM_FALL_OUT_CMD (1 << 8) | 469 | #define MEM_FALL_OUT_CMD (1 << 8) |
| 298 | 470 | ||
| 471 | #define MC_SEQ_RAS_TIMING 0x28a0 | ||
| 472 | #define MC_SEQ_CAS_TIMING 0x28a4 | ||
| 473 | #define MC_SEQ_MISC_TIMING 0x28a8 | ||
| 474 | #define MC_SEQ_MISC_TIMING2 0x28ac | ||
| 475 | #define MC_SEQ_PMG_TIMING 0x28b0 | ||
| 476 | #define MC_SEQ_RD_CTL_D0 0x28b4 | ||
| 477 | #define MC_SEQ_RD_CTL_D1 0x28b8 | ||
| 478 | #define MC_SEQ_WR_CTL_D0 0x28bc | ||
| 479 | #define MC_SEQ_WR_CTL_D1 0x28c0 | ||
| 480 | |||
| 299 | #define MC_SEQ_MISC0 0x2a00 | 481 | #define MC_SEQ_MISC0 0x2a00 |
| 482 | #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 | ||
| 483 | #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 | ||
| 484 | #define MC_SEQ_MISC0_VEN_ID_VALUE 3 | ||
| 485 | #define MC_SEQ_MISC0_REV_ID_SHIFT 12 | ||
| 486 | #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 | ||
| 487 | #define MC_SEQ_MISC0_REV_ID_VALUE 1 | ||
| 488 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | ||
| 489 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | ||
| 490 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | ||
| 491 | #define MC_SEQ_MISC1 0x2a04 | ||
| 492 | #define MC_SEQ_RESERVE_M 0x2a08 | ||
| 493 | #define MC_PMG_CMD_EMRS 0x2a0c | ||
| 300 | 494 | ||
| 301 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 | 495 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 |
| 302 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 | 496 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 |
| 303 | 497 | ||
| 498 | #define MC_SEQ_MISC5 0x2a54 | ||
| 499 | #define MC_SEQ_MISC6 0x2a58 | ||
| 500 | |||
| 501 | #define MC_SEQ_MISC7 0x2a64 | ||
| 502 | |||
| 503 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c | ||
| 504 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 | ||
| 505 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 | ||
| 506 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 | ||
| 507 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c | ||
| 508 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 | ||
| 509 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 | ||
| 510 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 | ||
| 511 | |||
| 512 | #define MC_PMG_CMD_MRS 0x2aac | ||
| 513 | |||
| 514 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c | ||
| 515 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 | ||
| 516 | |||
| 517 | #define MC_PMG_CMD_MRS1 0x2b44 | ||
| 518 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 | ||
| 519 | #define MC_SEQ_PMG_TIMING_LP 0x2b4c | ||
| 520 | |||
| 521 | #define MC_SEQ_WR_CTL_2 0x2b54 | ||
| 522 | #define MC_SEQ_WR_CTL_2_LP 0x2b58 | ||
| 523 | #define MC_PMG_CMD_MRS2 0x2b5c | ||
| 524 | #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 | ||
| 525 | |||
| 526 | #define MCLK_PWRMGT_CNTL 0x2ba0 | ||
| 527 | # define DLL_SPEED(x) ((x) << 0) | ||
| 528 | # define DLL_SPEED_MASK (0x1f << 0) | ||
| 529 | # define DLL_READY (1 << 6) | ||
| 530 | # define MC_INT_CNTL (1 << 7) | ||
| 531 | # define MRDCK0_PDNB (1 << 8) | ||
| 532 | # define MRDCK1_PDNB (1 << 9) | ||
| 533 | # define MRDCK0_RESET (1 << 16) | ||
| 534 | # define MRDCK1_RESET (1 << 17) | ||
| 535 | # define DLL_READY_READ (1 << 24) | ||
| 536 | #define DLL_CNTL 0x2ba4 | ||
| 537 | # define MRDCK0_BYPASS (1 << 24) | ||
| 538 | # define MRDCK1_BYPASS (1 << 25) | ||
| 539 | |||
| 540 | #define MPLL_FUNC_CNTL 0x2bb4 | ||
| 541 | #define BWCTRL(x) ((x) << 20) | ||
| 542 | #define BWCTRL_MASK (0xff << 20) | ||
| 543 | #define MPLL_FUNC_CNTL_1 0x2bb8 | ||
| 544 | #define VCO_MODE(x) ((x) << 0) | ||
| 545 | #define VCO_MODE_MASK (3 << 0) | ||
| 546 | #define CLKFRAC(x) ((x) << 4) | ||
| 547 | #define CLKFRAC_MASK (0xfff << 4) | ||
| 548 | #define CLKF(x) ((x) << 16) | ||
| 549 | #define CLKF_MASK (0xfff << 16) | ||
| 550 | #define MPLL_FUNC_CNTL_2 0x2bbc | ||
| 551 | #define MPLL_AD_FUNC_CNTL 0x2bc0 | ||
| 552 | #define YCLK_POST_DIV(x) ((x) << 0) | ||
| 553 | #define YCLK_POST_DIV_MASK (7 << 0) | ||
| 554 | #define MPLL_DQ_FUNC_CNTL 0x2bc4 | ||
| 555 | #define YCLK_SEL(x) ((x) << 4) | ||
| 556 | #define YCLK_SEL_MASK (1 << 4) | ||
| 557 | |||
| 558 | #define MPLL_SS1 0x2bcc | ||
| 559 | #define CLKV(x) ((x) << 0) | ||
| 560 | #define CLKV_MASK (0x3ffffff << 0) | ||
| 561 | #define MPLL_SS2 0x2bd0 | ||
| 562 | #define CLKS(x) ((x) << 0) | ||
| 563 | #define CLKS_MASK (0xfff << 0) | ||
| 564 | |||
| 304 | #define HDP_HOST_PATH_CNTL 0x2C00 | 565 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 305 | #define HDP_NONSURFACE_BASE 0x2C04 | 566 | #define HDP_NONSURFACE_BASE 0x2C04 |
| 306 | #define HDP_NONSURFACE_INFO 0x2C08 | 567 | #define HDP_NONSURFACE_INFO 0x2C08 |
| @@ -470,6 +731,9 @@ | |||
| 470 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | 731 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
| 471 | # define DC_HPDx_EN (1 << 28) | 732 | # define DC_HPDx_EN (1 << 28) |
| 472 | 733 | ||
| 734 | #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 | ||
| 735 | # define STUTTER_ENABLE (1 << 0) | ||
| 736 | |||
| 473 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ | 737 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ |
| 474 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 | 738 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 |
| 475 | 739 | ||
| @@ -645,6 +909,24 @@ | |||
| 645 | 909 | ||
| 646 | #define SQC_CACHES 0x8C08 | 910 | #define SQC_CACHES 0x8C08 |
| 647 | 911 | ||
| 912 | #define SQ_POWER_THROTTLE 0x8e58 | ||
| 913 | #define MIN_POWER(x) ((x) << 0) | ||
| 914 | #define MIN_POWER_MASK (0x3fff << 0) | ||
| 915 | #define MIN_POWER_SHIFT 0 | ||
| 916 | #define MAX_POWER(x) ((x) << 16) | ||
| 917 | #define MAX_POWER_MASK (0x3fff << 16) | ||
| 918 | #define MAX_POWER_SHIFT 0 | ||
| 919 | #define SQ_POWER_THROTTLE2 0x8e5c | ||
| 920 | #define MAX_POWER_DELTA(x) ((x) << 0) | ||
| 921 | #define MAX_POWER_DELTA_MASK (0x3fff << 0) | ||
| 922 | #define MAX_POWER_DELTA_SHIFT 0 | ||
| 923 | #define STI_SIZE(x) ((x) << 16) | ||
| 924 | #define STI_SIZE_MASK (0x3ff << 16) | ||
| 925 | #define STI_SIZE_SHIFT 16 | ||
| 926 | #define LTI_RATIO(x) ((x) << 27) | ||
| 927 | #define LTI_RATIO_MASK (0xf << 27) | ||
| 928 | #define LTI_RATIO_SHIFT 27 | ||
| 929 | |||
| 648 | #define SX_DEBUG_1 0x9060 | 930 | #define SX_DEBUG_1 0x9060 |
| 649 | 931 | ||
| 650 | #define SPI_STATIC_THREAD_MGMT_1 0x90E0 | 932 | #define SPI_STATIC_THREAD_MGMT_1 0x90E0 |