1 files changed, 67 insertions, 13 deletions

diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 88699e3cd868..5be9b4e72350 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -1753,6 +1753,9 @@ static int si_calculate_sclk_params(struct radeon_device *rdev,
                                     u32 engine_clock,
                                     SISLANDS_SMC_SCLK_VALUE *sclk);
 
+extern void si_update_cg(struct radeon_device *rdev,
+                         u32 block, bool enable);
+
 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
 {
         struct si_power_info *pi = rdev->pm.dpm.priv;
@@ -3663,7 +3666,7 @@ static void si_clear_vc(struct radeon_device *rdev)
         WREG32(CG_FTV, 0);
 }
 
-static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
+u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
 {
         u8 mc_para_index;
 
@@ -3676,7 +3679,7 @@ static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
         return mc_para_index;
 }
 
-static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
+u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
 {
         u8 mc_para_index;
 
@@ -3758,20 +3761,21 @@ static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
         return true;
 }
 
-static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
-                                                     struct atom_voltage_table *voltage_table)
+void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
+                                              u32 max_voltage_steps,
+                                              struct atom_voltage_table *voltage_table)
 {
         unsigned int i, diff;
 
-        if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS)
+        if (voltage_table->count <= max_voltage_steps)
                 return;
 
-        diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS;
+        diff = voltage_table->count - max_voltage_steps;
 
-        for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++)
+        for (i= 0; i < max_voltage_steps; i++)
                 voltage_table->entries[i] = voltage_table->entries[i + diff];
 
-        voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS;
+        voltage_table->count = max_voltage_steps;
 }
 
 static int si_construct_voltage_tables(struct radeon_device *rdev)
@@ -3787,7 +3791,9 @@ static int si_construct_voltage_tables(struct radeon_device *rdev)
                 return ret;
 
         if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
-                si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table);
+                si_trim_voltage_table_to_fit_state_table(rdev,
+                                                         SISLANDS_MAX_NO_VREG_STEPS,
+                                                         &eg_pi->vddc_voltage_table);
 
         if (eg_pi->vddci_control) {
                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
@@ -3796,7 +3802,9 @@ static int si_construct_voltage_tables(struct radeon_device *rdev)
                         return ret;
 
                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
-                        si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table);
+                        si_trim_voltage_table_to_fit_state_table(rdev,
+                                                                 SISLANDS_MAX_NO_VREG_STEPS,
+                                                                 &eg_pi->vddci_voltage_table);
         }
 
         if (pi->mvdd_control) {
@@ -3814,7 +3822,9 @@ static int si_construct_voltage_tables(struct radeon_device *rdev)
                 }
 
                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
-                        si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table);
+                        si_trim_voltage_table_to_fit_state_table(rdev,
+                                                                 SISLANDS_MAX_NO_VREG_STEPS,
+                                                                 &si_pi->mvdd_voltage_table);
         }
 
         if (si_pi->vddc_phase_shed_control) {
@@ -5752,6 +5762,13 @@ int si_dpm_enable(struct radeon_device *rdev)
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
         int ret;
 
+        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
+                            RADEON_CG_BLOCK_MC |
+                            RADEON_CG_BLOCK_SDMA |
+                            RADEON_CG_BLOCK_BIF |
+                            RADEON_CG_BLOCK_UVD |
+                            RADEON_CG_BLOCK_HDP), false);
+
         if (si_is_smc_running(rdev))
                 return -EINVAL;
         if (pi->voltage_control)
@@ -5871,6 +5888,13 @@ int si_dpm_enable(struct radeon_device *rdev)
 
         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
 
+        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
+                            RADEON_CG_BLOCK_MC |
+                            RADEON_CG_BLOCK_SDMA |
+                            RADEON_CG_BLOCK_BIF |
+                            RADEON_CG_BLOCK_UVD |
+                            RADEON_CG_BLOCK_HDP), true);
+
         ni_update_current_ps(rdev, boot_ps);
 
         return 0;
@@ -5881,6 +5905,13 @@ void si_dpm_disable(struct radeon_device *rdev)
         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
 
+        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
+                            RADEON_CG_BLOCK_MC |
+                            RADEON_CG_BLOCK_SDMA |
+                            RADEON_CG_BLOCK_BIF |
+                            RADEON_CG_BLOCK_UVD |
+                            RADEON_CG_BLOCK_HDP), false);
+
         if (!si_is_smc_running(rdev))
                 return;
         si_disable_ulv(rdev);
@@ -5945,6 +5976,13 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
         struct radeon_ps *old_ps = &eg_pi->current_rps;
         int ret;
 
+        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
+                            RADEON_CG_BLOCK_MC |
+                            RADEON_CG_BLOCK_SDMA |
+                            RADEON_CG_BLOCK_BIF |
+                            RADEON_CG_BLOCK_UVD |
+                            RADEON_CG_BLOCK_HDP), false);
+
         ret = si_disable_ulv(rdev);
         if (ret) {
                 DRM_ERROR("si_disable_ulv failed\n");
@@ -6043,6 +6081,13 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
                 return ret;
         }
 
+        si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
+                            RADEON_CG_BLOCK_MC |
+                            RADEON_CG_BLOCK_SDMA |
+                            RADEON_CG_BLOCK_BIF |
+                            RADEON_CG_BLOCK_UVD |
+                            RADEON_CG_BLOCK_HDP), true);
+
         return 0;
 }
 
@@ -6232,6 +6277,7 @@ static int si_parse_power_table(struct radeon_device *rdev)
         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
         for (i = 0; i < state_array->ucNumEntries; i++) {
+                u8 *idx;
                 power_state = (union pplib_power_state *)power_state_offset;
                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
@@ -6248,14 +6294,16 @@ static int si_parse_power_table(struct radeon_device *rdev)
                                               non_clock_info,
                                               non_clock_info_array->ucEntrySize);
                 k = 0;
+                idx = (u8 *)&power_state->v2.clockInfoIndex[0];
                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
-                        clock_array_index = power_state->v2.clockInfoIndex[j];
+                        clock_array_index = idx[j];
                         if (clock_array_index >= clock_info_array->ucNumEntries)
                                 continue;
                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
                                 break;
                         clock_info = (union pplib_clock_info *)
-                                &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
+                                ((u8 *)&clock_info_array->clockInfo[0] +
+                                 (clock_array_index * clock_info_array->ucEntrySize));
                         si_parse_pplib_clock_info(rdev,
                                                   &rdev->pm.dpm.ps[i], k,
                                                   clock_info);
@@ -6401,6 +6449,12 @@ int si_dpm_init(struct radeon_device *rdev)
 
         si_initialize_powertune_defaults(rdev);
 
+        /* make sure dc limits are valid */
+        if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
+            (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
+                rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
+                        rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
+
         return 0;
 }