diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/si.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 5c1c0c795e98..d64ef9115b69 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
| @@ -5784,7 +5784,6 @@ int si_irq_set(struct radeon_device *rdev) | |||
| 5784 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | 5784 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
| 5785 | u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; | 5785 | u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
| 5786 | u32 grbm_int_cntl = 0; | 5786 | u32 grbm_int_cntl = 0; |
| 5787 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | ||
| 5788 | u32 dma_cntl, dma_cntl1; | 5787 | u32 dma_cntl, dma_cntl1; |
| 5789 | u32 thermal_int = 0; | 5788 | u32 thermal_int = 0; |
| 5790 | 5789 | ||
| @@ -5923,16 +5922,22 @@ int si_irq_set(struct radeon_device *rdev) | |||
| 5923 | } | 5922 | } |
| 5924 | 5923 | ||
| 5925 | if (rdev->num_crtc >= 2) { | 5924 | if (rdev->num_crtc >= 2) { |
| 5926 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); | 5925 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, |
| 5927 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | 5926 | GRPH_PFLIP_INT_MASK); |
| 5927 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, | ||
| 5928 | GRPH_PFLIP_INT_MASK); | ||
| 5928 | } | 5929 | } |
| 5929 | if (rdev->num_crtc >= 4) { | 5930 | if (rdev->num_crtc >= 4) { |
| 5930 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | 5931 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, |
| 5931 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | 5932 | GRPH_PFLIP_INT_MASK); |
| 5933 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, | ||
| 5934 | GRPH_PFLIP_INT_MASK); | ||
| 5932 | } | 5935 | } |
| 5933 | if (rdev->num_crtc >= 6) { | 5936 | if (rdev->num_crtc >= 6) { |
| 5934 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | 5937 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, |
| 5935 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | 5938 | GRPH_PFLIP_INT_MASK); |
| 5939 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, | ||
| 5940 | GRPH_PFLIP_INT_MASK); | ||
| 5936 | } | 5941 | } |
| 5937 | 5942 | ||
| 5938 | if (!ASIC_IS_NODCE(rdev)) { | 5943 | if (!ASIC_IS_NODCE(rdev)) { |
| @@ -6296,6 +6301,15 @@ restart_ih: | |||
| 6296 | break; | 6301 | break; |
| 6297 | } | 6302 | } |
| 6298 | break; | 6303 | break; |
| 6304 | case 8: /* D1 page flip */ | ||
| 6305 | case 10: /* D2 page flip */ | ||
| 6306 | case 12: /* D3 page flip */ | ||
| 6307 | case 14: /* D4 page flip */ | ||
| 6308 | case 16: /* D5 page flip */ | ||
| 6309 | case 18: /* D6 page flip */ | ||
| 6310 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); | ||
| 6311 | radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); | ||
| 6312 | break; | ||
| 6299 | case 42: /* HPD hotplug */ | 6313 | case 42: /* HPD hotplug */ |
| 6300 | switch (src_data) { | 6314 | switch (src_data) { |
| 6301 | case 0: | 6315 | case 0: |