diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index d325280e2f9f..d71037f4f68f 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -3383,8 +3383,8 @@ static int si_cp_resume(struct radeon_device *rdev) | |||
3383 | /* ring 0 - compute and gfx */ | 3383 | /* ring 0 - compute and gfx */ |
3384 | /* Set ring buffer size */ | 3384 | /* Set ring buffer size */ |
3385 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | 3385 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3386 | rb_bufsz = drm_order(ring->ring_size / 8); | 3386 | rb_bufsz = order_base_2(ring->ring_size / 8); |
3387 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | 3387 | tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3388 | #ifdef __BIG_ENDIAN | 3388 | #ifdef __BIG_ENDIAN |
3389 | tmp |= BUF_SWAP_32BIT; | 3389 | tmp |= BUF_SWAP_32BIT; |
3390 | #endif | 3390 | #endif |
@@ -3416,8 +3416,8 @@ static int si_cp_resume(struct radeon_device *rdev) | |||
3416 | /* ring1 - compute only */ | 3416 | /* ring1 - compute only */ |
3417 | /* Set ring buffer size */ | 3417 | /* Set ring buffer size */ |
3418 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; | 3418 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; |
3419 | rb_bufsz = drm_order(ring->ring_size / 8); | 3419 | rb_bufsz = order_base_2(ring->ring_size / 8); |
3420 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | 3420 | tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3421 | #ifdef __BIG_ENDIAN | 3421 | #ifdef __BIG_ENDIAN |
3422 | tmp |= BUF_SWAP_32BIT; | 3422 | tmp |= BUF_SWAP_32BIT; |
3423 | #endif | 3423 | #endif |
@@ -3442,8 +3442,8 @@ static int si_cp_resume(struct radeon_device *rdev) | |||
3442 | /* ring2 - compute only */ | 3442 | /* ring2 - compute only */ |
3443 | /* Set ring buffer size */ | 3443 | /* Set ring buffer size */ |
3444 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; | 3444 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; |
3445 | rb_bufsz = drm_order(ring->ring_size / 8); | 3445 | rb_bufsz = order_base_2(ring->ring_size / 8); |
3446 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | 3446 | tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3447 | #ifdef __BIG_ENDIAN | 3447 | #ifdef __BIG_ENDIAN |
3448 | tmp |= BUF_SWAP_32BIT; | 3448 | tmp |= BUF_SWAP_32BIT; |
3449 | #endif | 3449 | #endif |
@@ -5651,7 +5651,7 @@ static int si_irq_init(struct radeon_device *rdev) | |||
5651 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | 5651 | WREG32(INTERRUPT_CNTL, interrupt_cntl); |
5652 | 5652 | ||
5653 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | 5653 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); |
5654 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | 5654 | rb_bufsz = order_base_2(rdev->ih.ring_size / 4); |
5655 | 5655 | ||
5656 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | 5656 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | |
5657 | IH_WPTR_OVERFLOW_CLEAR | | 5657 | IH_WPTR_OVERFLOW_CLEAR | |