1 files changed, 45 insertions, 20 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index d589475fe9e6..22a63c98ba14 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -39,30 +39,35 @@ MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
+MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
 MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
+MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
 MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
 MODULE_FIRMWARE("radeon/VERDE_me.bin");
 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
+MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
 MODULE_FIRMWARE("radeon/VERDE_smc.bin");
 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
 MODULE_FIRMWARE("radeon/OLAND_me.bin");
 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
+MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
 MODULE_FIRMWARE("radeon/OLAND_smc.bin");
 MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
 MODULE_FIRMWARE("radeon/HAINAN_me.bin");
 MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
 MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
+MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
 MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
 MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
 
@@ -1467,36 +1472,33 @@ int si_mc_load_microcode(struct radeon_device *rdev)
         const __be32 *fw_data;
         u32 running, blackout = 0;
         u32 *io_mc_regs;
-        int i, ucode_size, regs_size;
+        int i, regs_size, ucode_size;
 
         if (!rdev->mc_fw)
                 return -EINVAL;
 
+        ucode_size = rdev->mc_fw->size / 4;
+
         switch (rdev->family) {
         case CHIP_TAHITI:
                 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
-                ucode_size = SI_MC_UCODE_SIZE;
                 regs_size = TAHITI_IO_MC_REGS_SIZE;
                 break;
         case CHIP_PITCAIRN:
                 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
-                ucode_size = SI_MC_UCODE_SIZE;
                 regs_size = TAHITI_IO_MC_REGS_SIZE;
                 break;
         case CHIP_VERDE:
         default:
                 io_mc_regs = (u32 *)&verde_io_mc_regs;
-                ucode_size = SI_MC_UCODE_SIZE;
                 regs_size = TAHITI_IO_MC_REGS_SIZE;
                 break;
         case CHIP_OLAND:
                 io_mc_regs = (u32 *)&oland_io_mc_regs;
-                ucode_size = OLAND_MC_UCODE_SIZE;
                 regs_size = TAHITI_IO_MC_REGS_SIZE;
                 break;
         case CHIP_HAINAN:
                 io_mc_regs = (u32 *)&hainan_io_mc_regs;
-                ucode_size = OLAND_MC_UCODE_SIZE;
                 regs_size = TAHITI_IO_MC_REGS_SIZE;
                 break;
         }
@@ -1552,7 +1554,7 @@ static int si_init_microcode(struct radeon_device *rdev)
         const char *chip_name;
         const char *rlc_chip_name;
         size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
-        size_t smc_req_size;
+        size_t smc_req_size, mc2_req_size;
         char fw_name[30];
         int err;
 
@@ -1567,6 +1569,7 @@ static int si_init_microcode(struct radeon_device *rdev)
                 ce_req_size = SI_CE_UCODE_SIZE * 4;
                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
                 mc_req_size = SI_MC_UCODE_SIZE * 4;
+                mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
                 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
                 break;
         case CHIP_PITCAIRN:
@@ -1577,6 +1580,7 @@ static int si_init_microcode(struct radeon_device *rdev)
                 ce_req_size = SI_CE_UCODE_SIZE * 4;
                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
                 mc_req_size = SI_MC_UCODE_SIZE * 4;
+                mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
                 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
                 break;
         case CHIP_VERDE:
@@ -1587,6 +1591,7 @@ static int si_init_microcode(struct radeon_device *rdev)
                 ce_req_size = SI_CE_UCODE_SIZE * 4;
                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
                 mc_req_size = SI_MC_UCODE_SIZE * 4;
+                mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
                 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
                 break;
         case CHIP_OLAND:
@@ -1596,7 +1601,7 @@ static int si_init_microcode(struct radeon_device *rdev)
                 me_req_size = SI_PM4_UCODE_SIZE * 4;
                 ce_req_size = SI_CE_UCODE_SIZE * 4;
                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
-                mc_req_size = OLAND_MC_UCODE_SIZE * 4;
+                mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
                 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
                 break;
         case CHIP_HAINAN:
@@ -1606,7 +1611,7 @@ static int si_init_microcode(struct radeon_device *rdev)
                 me_req_size = SI_PM4_UCODE_SIZE * 4;
                 ce_req_size = SI_CE_UCODE_SIZE * 4;
                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
-                mc_req_size = OLAND_MC_UCODE_SIZE * 4;
+                mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
                 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
                 break;
         default: BUG();
@@ -1659,16 +1664,22 @@ static int si_init_microcode(struct radeon_device *rdev)
                 err = -EINVAL;
         }
 
-        snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
+        snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
         err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
-        if (err)
-                goto out;
-        if (rdev->mc_fw->size != mc_req_size) {
+        if (err) {
+                snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
+                err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
+                if (err)
+                        goto out;
+        }
+        if ((rdev->mc_fw->size != mc_req_size) &&
+            (rdev->mc_fw->size != mc2_req_size)) {
                 printk(KERN_ERR
                        "si_mc: Bogus length %zu in firmware \"%s\"\n",
                        rdev->mc_fw->size, fw_name);
                 err = -EINVAL;
         }
+        DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
 
         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
         err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
@@ -5769,7 +5780,6 @@ int si_irq_set(struct radeon_device *rdev)
         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
         u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
         u32 grbm_int_cntl = 0;
-        u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
         u32 dma_cntl, dma_cntl1;
         u32 thermal_int = 0;
 
@@ -5908,16 +5918,22 @@ int si_irq_set(struct radeon_device *rdev)
         }
 
         if (rdev->num_crtc >= 2) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
         }
         if (rdev->num_crtc >= 4) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
         }
         if (rdev->num_crtc >= 6) {
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
-                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
+                WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
+                       GRPH_PFLIP_INT_MASK);
         }
 
         if (!ASIC_IS_NODCE(rdev)) {
@@ -6281,6 +6297,15 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 8: /* D1 page flip */
+                case 10: /* D2 page flip */
+                case 12: /* D3 page flip */
+                case 14: /* D4 page flip */
+                case 16: /* D5 page flip */
+                case 18: /* D6 page flip */
+                        DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
+                        radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+                        break;
                 case 42: /* HPD hotplug */
                         switch (src_data) {
                         case 0: