1 files changed, 145 insertions, 23 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 85e1edfaa3be..9a124d0608b3 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -80,6 +80,8 @@ extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
                                          bool enable);
+static void si_init_pg(struct radeon_device *rdev);
+static void si_init_cg(struct radeon_device *rdev);
 static void si_fini_pg(struct radeon_device *rdev);
 static void si_fini_cg(struct radeon_device *rdev);
 static void si_rlc_stop(struct radeon_device *rdev);
@@ -1460,7 +1462,7 @@ static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 };
 
 /* ucode loading */
-static int si_mc_load_microcode(struct radeon_device *rdev)
+int si_mc_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
         u32 running, blackout = 0;
@@ -3247,7 +3249,8 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
         if (enable)
                 WREG32(CP_ME_CNTL, 0);
         else {
-                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+                if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
                 WREG32(SCRATCH_UMSK, 0);
                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -3508,6 +3511,9 @@ static int si_cp_resume(struct radeon_device *rdev)
 
         si_enable_gui_idle_interrupt(rdev, true);
 
+        if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+
         return 0;
 }
 
@@ -3724,6 +3730,106 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
         evergreen_print_gpu_status_regs(rdev);
 }
 
+static void si_set_clk_bypass_mode(struct radeon_device *rdev)
+{
+        u32 tmp, i;
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL);
+        tmp |= SPLL_BYPASS_EN;
+        WREG32(CG_SPLL_FUNC_CNTL, tmp);
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
+        tmp |= SPLL_CTLREQ_CHG;
+        WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
+                        break;
+                udelay(1);
+        }
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
+        tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
+        WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
+
+        tmp = RREG32(MPLL_CNTL_MODE);
+        tmp &= ~MPLL_MCLK_SEL;
+        WREG32(MPLL_CNTL_MODE, tmp);
+}
+
+static void si_spll_powerdown(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        tmp = RREG32(SPLL_CNTL_MODE);
+        tmp |= SPLL_SW_DIR_CONTROL;
+        WREG32(SPLL_CNTL_MODE, tmp);
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL);
+        tmp |= SPLL_RESET;
+        WREG32(CG_SPLL_FUNC_CNTL, tmp);
+
+        tmp = RREG32(CG_SPLL_FUNC_CNTL);
+        tmp |= SPLL_SLEEP;
+        WREG32(CG_SPLL_FUNC_CNTL, tmp);
+
+        tmp = RREG32(SPLL_CNTL_MODE);
+        tmp &= ~SPLL_SW_DIR_CONTROL;
+        WREG32(SPLL_CNTL_MODE, tmp);
+}
+
+static void si_gpu_pci_config_reset(struct radeon_device *rdev)
+{
+        struct evergreen_mc_save save;
+        u32 tmp, i;
+
+        dev_info(rdev->dev, "GPU pci config reset\n");
+
+        /* disable dpm? */
+
+        /* disable cg/pg */
+        si_fini_pg(rdev);
+        si_fini_cg(rdev);
+
+        /* Disable CP parsing/prefetching */
+        WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+        /* dma0 */
+        tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
+        /* dma1 */
+        tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
+        /* XXX other engines? */
+
+        /* halt the rlc, disable cp internal ints */
+        si_rlc_stop(rdev);
+
+        udelay(50);
+
+        /* disable mem access */
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
+        }
+
+        /* set mclk/sclk to bypass */
+        si_set_clk_bypass_mode(rdev);
+        /* powerdown spll */
+        si_spll_powerdown(rdev);
+        /* disable BM */
+        pci_clear_master(rdev->pdev);
+        /* reset */
+        radeon_pci_config_reset(rdev);
+        /* wait for asic to come out of reset */
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
+                        break;
+                udelay(1);
+        }
+}
+
 int si_asic_reset(struct radeon_device *rdev)
 {
         u32 reset_mask;
@@ -3733,10 +3839,17 @@ int si_asic_reset(struct radeon_device *rdev)
         if (reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, true);
 
+        /* try soft reset */
         si_gpu_soft_reset(rdev, reset_mask);
 
         reset_mask = si_gpu_check_soft_reset(rdev);
 
+        /* try pci config reset */
+        if (reset_mask && radeon_hard_reset)
+                si_gpu_pci_config_reset(rdev);
+
+        reset_mask = si_gpu_check_soft_reset(rdev);
+
         if (!reset_mask)
                 r600_set_bios_scratch_engine_hung(rdev, false);
 
@@ -5212,8 +5325,8 @@ static void si_enable_hdp_ls(struct radeon_device *rdev,
                 WREG32(HDP_MEM_POWER_LS, data);
 }
 
-void si_update_cg(struct radeon_device *rdev,
-                  u32 block, bool enable)
+static void si_update_cg(struct radeon_device *rdev,
+                         u32 block, bool enable)
 {
         if (block & RADEON_CG_BLOCK_GFX) {
                 si_enable_gui_idle_interrupt(rdev, false);
@@ -5379,6 +5492,9 @@ static void si_init_pg(struct radeon_device *rdev)
                 si_init_ao_cu_mask(rdev);
                 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
                         si_init_gfx_cgpg(rdev);
+                } else {
+                        WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
+                        WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
                 }
                 si_enable_dma_pg(rdev, true);
                 si_enable_gfx_cgpg(rdev, true);
@@ -5566,7 +5682,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
         }
 
         if (!ASIC_IS_NODCE(rdev)) {
-                WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+                WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
 
                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
                 WREG32(DC_HPD1_INT_CONTROL, tmp);
@@ -6222,6 +6338,10 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 124: /* UVD */
+                        DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
+                        radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
+                        break;
                 case 146:
                 case 147:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
@@ -6324,21 +6444,14 @@ static int si_startup(struct radeon_device *rdev)
 
         si_mc_program(rdev);
 
-        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
-            !rdev->rlc_fw || !rdev->mc_fw) {
-                r = si_init_microcode(rdev);
+        if (!rdev->pm.dpm_enabled) {
+                r = si_mc_load_microcode(rdev);
                 if (r) {
-                        DRM_ERROR("Failed to load firmware!\n");
+                        DRM_ERROR("Failed to load MC firmware!\n");
                         return r;
                 }
         }
 
-        r = si_mc_load_microcode(rdev);
-        if (r) {
-                DRM_ERROR("Failed to load MC firmware!\n");
-                return r;
-        }
-
         r = si_pcie_gart_enable(rdev);
         if (r)
                 return r;
@@ -6421,37 +6534,30 @@ static int si_startup(struct radeon_device *rdev)
 
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
-                             CP_RB0_RPTR, CP_RB0_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
-                             CP_RB1_RPTR, CP_RB1_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
-                             CP_RB2_RPTR, CP_RB2_WPTR,
                              RADEON_CP_PACKET2);
         if (r)
                 return r;
 
         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
-                             DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
-                             DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
         if (r)
                 return r;
 
         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
-                             DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
-                             DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
         if (r)
                 return r;
@@ -6471,7 +6577,6 @@ static int si_startup(struct radeon_device *rdev)
                 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
                 if (ring->ring_size) {
                         r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
-                                             UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
                                              RADEON_CP_PACKET2);
                         if (!r)
                                 r = uvd_v1_0_init(rdev);
@@ -6513,6 +6618,9 @@ int si_resume(struct radeon_device *rdev)
         /* init golden registers */
         si_init_golden_registers(rdev);
 
+        if (rdev->pm.pm_method == PM_METHOD_DPM)
+                radeon_pm_resume(rdev);
+
         rdev->accel_working = true;
         r = si_startup(rdev);
         if (r) {
@@ -6527,6 +6635,7 @@ int si_resume(struct radeon_device *rdev)
 
 int si_suspend(struct radeon_device *rdev)
 {
+        radeon_pm_suspend(rdev);
         dce6_audio_fini(rdev);
         radeon_vm_manager_fini(rdev);
         si_cp_enable(rdev, false);
@@ -6600,6 +6709,18 @@ int si_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+            !rdev->rlc_fw || !rdev->mc_fw) {
+                r = si_init_microcode(rdev);
+                if (r) {
+                        DRM_ERROR("Failed to load firmware!\n");
+                        return r;
+                }
+        }
+
+        /* Initialize power management */
+        radeon_pm_init(rdev);
+
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
@@ -6666,6 +6787,7 @@ int si_init(struct radeon_device *rdev)
 
 void si_fini(struct radeon_device *rdev)
 {
+        radeon_pm_fini(rdev);
         si_cp_fini(rdev);
         cayman_dma_fini(rdev);
         si_fini_pg(rdev);