diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/si.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index ac708e006180..22a63c98ba14 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
| @@ -5780,7 +5780,6 @@ int si_irq_set(struct radeon_device *rdev) | |||
| 5780 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | 5780 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
| 5781 | u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; | 5781 | u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
| 5782 | u32 grbm_int_cntl = 0; | 5782 | u32 grbm_int_cntl = 0; |
| 5783 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | ||
| 5784 | u32 dma_cntl, dma_cntl1; | 5783 | u32 dma_cntl, dma_cntl1; |
| 5785 | u32 thermal_int = 0; | 5784 | u32 thermal_int = 0; |
| 5786 | 5785 | ||
| @@ -5919,16 +5918,22 @@ int si_irq_set(struct radeon_device *rdev) | |||
| 5919 | } | 5918 | } |
| 5920 | 5919 | ||
| 5921 | if (rdev->num_crtc >= 2) { | 5920 | if (rdev->num_crtc >= 2) { |
| 5922 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); | 5921 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, |
| 5923 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | 5922 | GRPH_PFLIP_INT_MASK); |
| 5923 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, | ||
| 5924 | GRPH_PFLIP_INT_MASK); | ||
| 5924 | } | 5925 | } |
| 5925 | if (rdev->num_crtc >= 4) { | 5926 | if (rdev->num_crtc >= 4) { |
| 5926 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | 5927 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, |
| 5927 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | 5928 | GRPH_PFLIP_INT_MASK); |
| 5929 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, | ||
| 5930 | GRPH_PFLIP_INT_MASK); | ||
| 5928 | } | 5931 | } |
| 5929 | if (rdev->num_crtc >= 6) { | 5932 | if (rdev->num_crtc >= 6) { |
| 5930 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | 5933 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, |
| 5931 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | 5934 | GRPH_PFLIP_INT_MASK); |
| 5935 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, | ||
| 5936 | GRPH_PFLIP_INT_MASK); | ||
| 5932 | } | 5937 | } |
| 5933 | 5938 | ||
| 5934 | if (!ASIC_IS_NODCE(rdev)) { | 5939 | if (!ASIC_IS_NODCE(rdev)) { |
| @@ -6292,6 +6297,15 @@ restart_ih: | |||
| 6292 | break; | 6297 | break; |
| 6293 | } | 6298 | } |
| 6294 | break; | 6299 | break; |
| 6300 | case 8: /* D1 page flip */ | ||
| 6301 | case 10: /* D2 page flip */ | ||
| 6302 | case 12: /* D3 page flip */ | ||
| 6303 | case 14: /* D4 page flip */ | ||
| 6304 | case 16: /* D5 page flip */ | ||
| 6305 | case 18: /* D6 page flip */ | ||
| 6306 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); | ||
| 6307 | radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); | ||
| 6308 | break; | ||
| 6295 | case 42: /* HPD hotplug */ | 6309 | case 42: /* HPD hotplug */ |
| 6296 | switch (src_data) { | 6310 | switch (src_data) { |
| 6297 | case 0: | 6311 | case 0: |