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path: root/drivers/gpu/drm/radeon/rv770d.h
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-rw-r--r--drivers/gpu/drm/radeon/rv770d.h279
1 files changed, 273 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 85b16266f748..784eeaf315c3 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -62,6 +62,242 @@
62# define UPLL_FB_DIV(x) ((x) << 0) 62# define UPLL_FB_DIV(x) ((x) << 0)
63# define UPLL_FB_DIV_MASK 0x01FFFFFF 63# define UPLL_FB_DIV_MASK 0x01FFFFFF
64 64
65/* pm registers */
66#define SMC_SRAM_ADDR 0x200
67#define SMC_SRAM_AUTO_INC_DIS (1 << 16)
68#define SMC_SRAM_DATA 0x204
69#define SMC_IO 0x208
70#define SMC_RST_N (1 << 0)
71#define SMC_STOP_MODE (1 << 2)
72#define SMC_CLK_EN (1 << 11)
73#define SMC_MSG 0x20c
74#define HOST_SMC_MSG(x) ((x) << 0)
75#define HOST_SMC_MSG_MASK (0xff << 0)
76#define HOST_SMC_MSG_SHIFT 0
77#define HOST_SMC_RESP(x) ((x) << 8)
78#define HOST_SMC_RESP_MASK (0xff << 8)
79#define HOST_SMC_RESP_SHIFT 8
80#define SMC_HOST_MSG(x) ((x) << 16)
81#define SMC_HOST_MSG_MASK (0xff << 16)
82#define SMC_HOST_MSG_SHIFT 16
83#define SMC_HOST_RESP(x) ((x) << 24)
84#define SMC_HOST_RESP_MASK (0xff << 24)
85#define SMC_HOST_RESP_SHIFT 24
86
87#define SMC_ISR_FFD8_FFDB 0x218
88
89#define CG_SPLL_FUNC_CNTL 0x600
90#define SPLL_RESET (1 << 0)
91#define SPLL_SLEEP (1 << 1)
92#define SPLL_DIVEN (1 << 2)
93#define SPLL_BYPASS_EN (1 << 3)
94#define SPLL_REF_DIV(x) ((x) << 4)
95#define SPLL_REF_DIV_MASK (0x3f << 4)
96#define SPLL_HILEN(x) ((x) << 12)
97#define SPLL_HILEN_MASK (0xf << 12)
98#define SPLL_LOLEN(x) ((x) << 16)
99#define SPLL_LOLEN_MASK (0xf << 16)
100#define CG_SPLL_FUNC_CNTL_2 0x604
101#define SCLK_MUX_SEL(x) ((x) << 0)
102#define SCLK_MUX_SEL_MASK (0x1ff << 0)
103#define CG_SPLL_FUNC_CNTL_3 0x608
104#define SPLL_FB_DIV(x) ((x) << 0)
105#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
106#define SPLL_DITHEN (1 << 28)
107
108#define SPLL_CNTL_MODE 0x610
109#define SPLL_DIV_SYNC (1 << 5)
110
111#define MPLL_AD_FUNC_CNTL 0x624
112#define CLKF(x) ((x) << 0)
113#define CLKF_MASK (0x7f << 0)
114#define CLKR(x) ((x) << 7)
115#define CLKR_MASK (0x1f << 7)
116#define CLKFRAC(x) ((x) << 12)
117#define CLKFRAC_MASK (0x1f << 12)
118#define YCLK_POST_DIV(x) ((x) << 17)
119#define YCLK_POST_DIV_MASK (3 << 17)
120#define IBIAS(x) ((x) << 20)
121#define IBIAS_MASK (0x3ff << 20)
122#define RESET (1 << 30)
123#define PDNB (1 << 31)
124#define MPLL_AD_FUNC_CNTL_2 0x628
125#define BYPASS (1 << 19)
126#define BIAS_GEN_PDNB (1 << 24)
127#define RESET_EN (1 << 25)
128#define VCO_MODE (1 << 29)
129#define MPLL_DQ_FUNC_CNTL 0x62c
130#define MPLL_DQ_FUNC_CNTL_2 0x630
131
132#define GENERAL_PWRMGT 0x63c
133# define GLOBAL_PWRMGT_EN (1 << 0)
134# define STATIC_PM_EN (1 << 1)
135# define THERMAL_PROTECTION_DIS (1 << 2)
136# define THERMAL_PROTECTION_TYPE (1 << 3)
137# define ENABLE_GEN2PCIE (1 << 4)
138# define ENABLE_GEN2XSP (1 << 5)
139# define SW_SMIO_INDEX(x) ((x) << 6)
140# define SW_SMIO_INDEX_MASK (3 << 6)
141# define SW_SMIO_INDEX_SHIFT 6
142# define LOW_VOLT_D2_ACPI (1 << 8)
143# define LOW_VOLT_D3_ACPI (1 << 9)
144# define VOLT_PWRMGT_EN (1 << 10)
145# define BACKBIAS_PAD_EN (1 << 18)
146# define BACKBIAS_VALUE (1 << 19)
147# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
148# define AC_DC_SW (1 << 24)
149
150#define CG_TPC 0x640
151#define SCLK_PWRMGT_CNTL 0x644
152# define SCLK_PWRMGT_OFF (1 << 0)
153# define SCLK_LOW_D1 (1 << 1)
154# define FIR_RESET (1 << 4)
155# define FIR_FORCE_TREND_SEL (1 << 5)
156# define FIR_TREND_MODE (1 << 6)
157# define DYN_GFX_CLK_OFF_EN (1 << 7)
158# define GFX_CLK_FORCE_ON (1 << 8)
159# define GFX_CLK_REQUEST_OFF (1 << 9)
160# define GFX_CLK_FORCE_OFF (1 << 10)
161# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
162# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
163# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
164#define MCLK_PWRMGT_CNTL 0x648
165# define DLL_SPEED(x) ((x) << 0)
166# define DLL_SPEED_MASK (0x1f << 0)
167# define MPLL_PWRMGT_OFF (1 << 5)
168# define DLL_READY (1 << 6)
169# define MC_INT_CNTL (1 << 7)
170# define MRDCKA0_SLEEP (1 << 8)
171# define MRDCKA1_SLEEP (1 << 9)
172# define MRDCKB0_SLEEP (1 << 10)
173# define MRDCKB1_SLEEP (1 << 11)
174# define MRDCKC0_SLEEP (1 << 12)
175# define MRDCKC1_SLEEP (1 << 13)
176# define MRDCKD0_SLEEP (1 << 14)
177# define MRDCKD1_SLEEP (1 << 15)
178# define MRDCKA0_RESET (1 << 16)
179# define MRDCKA1_RESET (1 << 17)
180# define MRDCKB0_RESET (1 << 18)
181# define MRDCKB1_RESET (1 << 19)
182# define MRDCKC0_RESET (1 << 20)
183# define MRDCKC1_RESET (1 << 21)
184# define MRDCKD0_RESET (1 << 22)
185# define MRDCKD1_RESET (1 << 23)
186# define DLL_READY_READ (1 << 24)
187# define USE_DISPLAY_GAP (1 << 25)
188# define USE_DISPLAY_URGENT_NORMAL (1 << 26)
189# define MPLL_TURNOFF_D2 (1 << 28)
190#define DLL_CNTL 0x64c
191# define MRDCKA0_BYPASS (1 << 24)
192# define MRDCKA1_BYPASS (1 << 25)
193# define MRDCKB0_BYPASS (1 << 26)
194# define MRDCKB1_BYPASS (1 << 27)
195# define MRDCKC0_BYPASS (1 << 28)
196# define MRDCKC1_BYPASS (1 << 29)
197# define MRDCKD0_BYPASS (1 << 30)
198# define MRDCKD1_BYPASS (1 << 31)
199
200#define MPLL_TIME 0x654
201# define MPLL_LOCK_TIME(x) ((x) << 0)
202# define MPLL_LOCK_TIME_MASK (0xffff << 0)
203# define MPLL_RESET_TIME(x) ((x) << 16)
204# define MPLL_RESET_TIME_MASK (0xffff << 16)
205
206#define CG_CLKPIN_CNTL 0x660
207# define MUX_TCLK_TO_XCLK (1 << 8)
208# define XTALIN_DIVIDE (1 << 9)
209
210#define S0_VID_LOWER_SMIO_CNTL 0x678
211#define S1_VID_LOWER_SMIO_CNTL 0x67c
212#define S2_VID_LOWER_SMIO_CNTL 0x680
213#define S3_VID_LOWER_SMIO_CNTL 0x684
214
215#define CG_FTV 0x690
216#define CG_FFCT_0 0x694
217# define UTC_0(x) ((x) << 0)
218# define UTC_0_MASK (0x3ff << 0)
219# define DTC_0(x) ((x) << 10)
220# define DTC_0_MASK (0x3ff << 10)
221
222#define CG_BSP 0x6d0
223# define BSP(x) ((x) << 0)
224# define BSP_MASK (0xffff << 0)
225# define BSU(x) ((x) << 16)
226# define BSU_MASK (0xf << 16)
227#define CG_AT 0x6d4
228# define CG_R(x) ((x) << 0)
229# define CG_R_MASK (0xffff << 0)
230# define CG_L(x) ((x) << 16)
231# define CG_L_MASK (0xffff << 16)
232#define CG_GIT 0x6d8
233# define CG_GICST(x) ((x) << 0)
234# define CG_GICST_MASK (0xffff << 0)
235# define CG_GIPOT(x) ((x) << 16)
236# define CG_GIPOT_MASK (0xffff << 16)
237
238#define CG_SSP 0x6e8
239# define SST(x) ((x) << 0)
240# define SST_MASK (0xffff << 0)
241# define SSTU(x) ((x) << 16)
242# define SSTU_MASK (0xf << 16)
243
244#define CG_DISPLAY_GAP_CNTL 0x714
245# define DISP1_GAP(x) ((x) << 0)
246# define DISP1_GAP_MASK (3 << 0)
247# define DISP2_GAP(x) ((x) << 2)
248# define DISP2_GAP_MASK (3 << 2)
249# define VBI_TIMER_COUNT(x) ((x) << 4)
250# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
251# define VBI_TIMER_UNIT(x) ((x) << 20)
252# define VBI_TIMER_UNIT_MASK (7 << 20)
253# define DISP1_GAP_MCHG(x) ((x) << 24)
254# define DISP1_GAP_MCHG_MASK (3 << 24)
255# define DISP2_GAP_MCHG(x) ((x) << 26)
256# define DISP2_GAP_MCHG_MASK (3 << 26)
257
258#define CG_SPLL_SPREAD_SPECTRUM 0x790
259#define SSEN (1 << 0)
260#define CLKS(x) ((x) << 4)
261#define CLKS_MASK (0xfff << 4)
262#define CG_SPLL_SPREAD_SPECTRUM_2 0x794
263#define CLKV(x) ((x) << 0)
264#define CLKV_MASK (0x3ffffff << 0)
265#define CG_MPLL_SPREAD_SPECTRUM 0x798
266#define CG_UPLL_SPREAD_SPECTRUM 0x79c
267# define SSEN_MASK 0x00000001
268
269#define CG_CGTT_LOCAL_0 0x7d0
270#define CG_CGTT_LOCAL_1 0x7d4
271
272#define BIOS_SCRATCH_4 0x1734
273
274#define MC_SEQ_MISC0 0x2a00
275#define MC_SEQ_MISC0_GDDR5_SHIFT 28
276#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
277#define MC_SEQ_MISC0_GDDR5_VALUE 5
278
279#define MC_ARB_SQM_RATIO 0x2770
280#define STATE0(x) ((x) << 0)
281#define STATE0_MASK (0xff << 0)
282#define STATE1(x) ((x) << 8)
283#define STATE1_MASK (0xff << 8)
284#define STATE2(x) ((x) << 16)
285#define STATE2_MASK (0xff << 16)
286#define STATE3(x) ((x) << 24)
287#define STATE3_MASK (0xff << 24)
288
289#define MC_ARB_RFSH_RATE 0x27b0
290#define POWERMODE0(x) ((x) << 0)
291#define POWERMODE0_MASK (0xff << 0)
292#define POWERMODE1(x) ((x) << 8)
293#define POWERMODE1_MASK (0xff << 8)
294#define POWERMODE2(x) ((x) << 16)
295#define POWERMODE2_MASK (0xff << 16)
296#define POWERMODE3(x) ((x) << 24)
297#define POWERMODE3_MASK (0xff << 24)
298
299#define CGTS_SM_CTRL_REG 0x9150
300
65/* Registers */ 301/* Registers */
66#define CB_COLOR0_BASE 0x28040 302#define CB_COLOR0_BASE 0x28040
67#define CB_COLOR1_BASE 0x28044 303#define CB_COLOR1_BASE 0x28044
@@ -86,8 +322,8 @@
86#define CONFIG_MEMSIZE 0x5428 322#define CONFIG_MEMSIZE 0x5428
87 323
88#define CP_ME_CNTL 0x86D8 324#define CP_ME_CNTL 0x86D8
89#define CP_ME_HALT (1<<28) 325#define CP_ME_HALT (1 << 28)
90#define CP_PFP_HALT (1<<26) 326#define CP_PFP_HALT (1 << 26)
91#define CP_ME_RAM_DATA 0xC160 327#define CP_ME_RAM_DATA 0xC160
92#define CP_ME_RAM_RADDR 0xC158 328#define CP_ME_RAM_RADDR 0xC158
93#define CP_ME_RAM_WADDR 0xC15C 329#define CP_ME_RAM_WADDR 0xC15C
@@ -157,9 +393,22 @@
157#define GUI_ACTIVE (1<<31) 393#define GUI_ACTIVE (1<<31)
158#define GRBM_STATUS2 0x8014 394#define GRBM_STATUS2 0x8014
159 395
160#define CG_CLKPIN_CNTL 0x660 396#define CG_THERMAL_CTRL 0x72C
161# define MUX_TCLK_TO_XCLK (1 << 8) 397#define DPM_EVENT_SRC(x) ((x) << 0)
162# define XTALIN_DIVIDE (1 << 9) 398#define DPM_EVENT_SRC_MASK (7 << 0)
399#define DIG_THERM_DPM(x) ((x) << 14)
400#define DIG_THERM_DPM_MASK 0x003FC000
401#define DIG_THERM_DPM_SHIFT 14
402
403#define CG_THERMAL_INT 0x734
404#define DIG_THERM_INTH(x) ((x) << 8)
405#define DIG_THERM_INTH_MASK 0x0000FF00
406#define DIG_THERM_INTH_SHIFT 8
407#define DIG_THERM_INTL(x) ((x) << 16)
408#define DIG_THERM_INTL_MASK 0x00FF0000
409#define DIG_THERM_INTL_SHIFT 16
410#define THERM_INT_MASK_HIGH (1 << 24)
411#define THERM_INT_MASK_LOW (1 << 25)
163 412
164#define CG_MULT_THERMAL_STATUS 0x740 413#define CG_MULT_THERMAL_STATUS 0x740
165#define ASIC_T(x) ((x) << 16) 414#define ASIC_T(x) ((x) << 16)
@@ -662,7 +911,22 @@
662#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 911#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
663#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 912#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
664 913
665/* PCIE link stuff */ 914/* PCIE indirect regs */
915#define PCIE_P_CNTL 0x40
916# define P_PLL_PWRDN_IN_L1L23 (1 << 3)
917# define P_PLL_BUF_PDNB (1 << 4)
918# define P_PLL_PDNB (1 << 9)
919# define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12)
920/* PCIE PORT regs */
921#define PCIE_LC_CNTL 0xa0
922# define LC_L0S_INACTIVITY(x) ((x) << 8)
923# define LC_L0S_INACTIVITY_MASK (0xf << 8)
924# define LC_L0S_INACTIVITY_SHIFT 8
925# define LC_L1_INACTIVITY(x) ((x) << 12)
926# define LC_L1_INACTIVITY_MASK (0xf << 12)
927# define LC_L1_INACTIVITY_SHIFT 12
928# define LC_PMI_TO_L1_DIS (1 << 16)
929# define LC_ASPM_TO_L1_DIS (1 << 24)
666#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 930#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
667#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 931#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
668# define LC_LINK_WIDTH_SHIFT 0 932# define LC_LINK_WIDTH_SHIFT 0
@@ -690,6 +954,9 @@
690# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 954# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
691# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 955# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
692# define LC_CURRENT_DATA_RATE (1 << 11) 956# define LC_CURRENT_DATA_RATE (1 << 11)
957# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
958# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
959# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
693# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 960# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
694# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 961# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
695# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 962# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)