1 files changed, 341 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
new file mode 100644
index 000000000000..4b9c3d6396ff
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef RV770_H
+#define RV770_H
+#define R7XX_MAX_SH_GPRS           256
+#define R7XX_MAX_TEMP_GPRS         16
+#define R7XX_MAX_SH_THREADS        256
+#define R7XX_MAX_SH_STACK_ENTRIES  4096
+#define R7XX_MAX_BACKENDS          8
+#define R7XX_MAX_BACKENDS_MASK     0xff
+#define R7XX_MAX_SIMDS             16
+#define R7XX_MAX_SIMDS_MASK        0xffff
+#define R7XX_MAX_PIPES             8
+#define R7XX_MAX_PIPES_MASK        0xff
+/* Registers */
+#define CB_COLOR0_BASE                                  0x28040
+#define CB_COLOR1_BASE                                  0x28044
+#define CB_COLOR2_BASE                                  0x28048
+#define CB_COLOR3_BASE                                  0x2804C
+#define CB_COLOR4_BASE                                  0x28050
+#define CB_COLOR5_BASE                                  0x28054
+#define CB_COLOR6_BASE                                  0x28058
+#define CB_COLOR7_BASE                                  0x2805C
+#define CB_COLOR7_FRAG                                  0x280FC
+#define CC_GC_SHADER_PIPE_CONFIG                        0x8950
+#define CC_RB_BACKEND_DISABLE                           0x98F4
+#define         BACKEND_DISABLE(x)                              ((x) << 16)
+#define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
+#define CGTS_SYS_TCC_DISABLE                            0x3F90
+#define CGTS_TCC_DISABLE                                0x9148
+#define CGTS_USER_SYS_TCC_DISABLE                       0x3F94
+#define CGTS_USER_TCC_DISABLE                           0x914C
+#define CONFIG_MEMSIZE                                  0x5428
+#define CP_ME_CNTL                                      0x86D8
+#define         CP_ME_HALT                                      (1<<28)
+#define         CP_PFP_HALT                                     (1<<26)
+#define CP_ME_RAM_DATA                                  0xC160
+#define CP_ME_RAM_RADDR                                 0xC158
+#define CP_ME_RAM_WADDR                                 0xC15C
+#define CP_MEQ_THRESHOLDS                               0x8764
+#define         STQ_SPLIT(x)                                    ((x) << 0)
+#define CP_PERFMON_CNTL                                 0x87FC
+#define CP_PFP_UCODE_ADDR                               0xC150
+#define CP_PFP_UCODE_DATA                               0xC154
+#define CP_QUEUE_THRESHOLDS                             0x8760
+#define         ROQ_IB1_START(x)                                ((x) << 0)
+#define         ROQ_IB2_START(x)                                ((x) << 8)
+#define CP_RB_CNTL                                      0xC104
+#define         RB_BUFSZ(x)                                     ((x)<<0)
+#define         RB_BLKSZ(x)                                     ((x)<<8)
+#define         RB_NO_UPDATE                                    (1<<27)
+#define         RB_RPTR_WR_ENA                                  (1<<31)
+#define         BUF_SWAP_32BIT                                  (2 << 16)
+#define CP_RB_RPTR                                      0x8700
+#define CP_RB_RPTR_ADDR                                 0xC10C
+#define CP_RB_RPTR_ADDR_HI                              0xC110
+#define CP_RB_RPTR_WR                                   0xC108
+#define CP_RB_WPTR                                      0xC114
+#define CP_RB_WPTR_ADDR                                 0xC118
+#define CP_RB_WPTR_ADDR_HI                              0xC11C
+#define CP_RB_WPTR_DELAY                                0x8704
+#define CP_SEM_WAIT_TIMER                               0x85BC
+#define DB_DEBUG3                                       0x98B0
+#define         DB_CLK_OFF_DELAY(x)                             ((x) << 11)
+#define DB_DEBUG4                                       0x9B8C
+#define         DISABLE_TILE_COVERED_FOR_PS_ITER                (1 << 6)
+#define DCP_TILING_CONFIG                               0x6CA0
+#define         PIPE_TILING(x)                                  ((x) << 1)
+#define         BANK_TILING(x)                                  ((x) << 4)
+#define         GROUP_SIZE(x)                                   ((x) << 6)
+#define         ROW_TILING(x)                                   ((x) << 8)
+#define         BANK_SWAPS(x)                                   ((x) << 11)
+#define         SAMPLE_SPLIT(x)                                 ((x) << 14)
+#define         BACKEND_MAP(x)                                  ((x) << 16)
+#define GB_TILING_CONFIG                                0x98F0
+#define GC_USER_SHADER_PIPE_CONFIG                      0x8954
+#define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
+#define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
+#define         INACTIVE_SIMDS(x)                               ((x) << 16)
+#define         INACTIVE_SIMDS_MASK                             0x00FF0000
+#define GRBM_CNTL                                       0x8000
+#define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
+#define GRBM_SOFT_RESET                                 0x8020
+#define         SOFT_RESET_CP                                   (1<<0)
+#define GRBM_STATUS                                     0x8010
+#define         CMDFIFO_AVAIL_MASK                              0x0000000F
+#define         GUI_ACTIVE                                      (1<<31)
+#define GRBM_STATUS2                                    0x8014
+#define HDP_HOST_PATH_CNTL                              0x2C00
+#define HDP_NONSURFACE_BASE                             0x2C04
+#define HDP_NONSURFACE_INFO                             0x2C08
+#define HDP_NONSURFACE_SIZE                             0x2C0C
+#define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
+#define HDP_TILING_CONFIG                               0x2F3C
+#define MC_ARB_RAMCFG                                   0x2760
+#define         NOOFBANK_SHIFT                                  0
+#define         NOOFBANK_MASK                                   0x00000003
+#define         NOOFRANK_SHIFT                                  2
+#define         NOOFRANK_MASK                                   0x00000004
+#define         NOOFROWS_SHIFT                                  3
+#define         NOOFROWS_MASK                                   0x00000038
+#define         NOOFCOLS_SHIFT                                  6
+#define         NOOFCOLS_MASK                                   0x000000C0
+#define         CHANSIZE_SHIFT                                  8
+#define         CHANSIZE_MASK                                   0x00000100
+#define         BURSTLENGTH_SHIFT                               9
+#define         BURSTLENGTH_MASK                                0x00000200
+#define MC_VM_AGP_TOP                                   0x2028
+#define MC_VM_AGP_BOT                                   0x202C
+#define MC_VM_AGP_BASE                                  0x2030
+#define MC_VM_FB_LOCATION                               0x2024
+#define MC_VM_MB_L1_TLB0_CNTL                           0x2234
+#define MC_VM_MB_L1_TLB1_CNTL                           0x2238
+#define MC_VM_MB_L1_TLB2_CNTL                           0x223C
+#define MC_VM_MB_L1_TLB3_CNTL                           0x2240
+#define         ENABLE_L1_TLB                                   (1 << 0)
+#define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
+#define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
+#define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
+#define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
+#define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
+#define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
+#define         EFFECTIVE_L1_TLB_SIZE(x)                        ((x)<<15)
+#define         EFFECTIVE_L1_QUEUE_SIZE(x)                      ((x)<<18)
+#define MC_VM_MD_L1_TLB0_CNTL                           0x2654
+#define MC_VM_MD_L1_TLB1_CNTL                           0x2658
+#define MC_VM_MD_L1_TLB2_CNTL                           0x265C
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
+#define PA_CL_ENHANCE                                   0x8A14
+#define         CLIP_VTX_REORDER_ENA                            (1 << 0)
+#define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
+#define PA_SC_AA_CONFIG                                 0x28C04
+#define PA_SC_CLIPRECT_RULE                             0x2820C
+#define PA_SC_EDGERULE                                  0x28230
+#define PA_SC_FIFO_SIZE                                 0x8BCC
+#define         SC_PRIM_FIFO_SIZE(x)                            ((x) << 0)
+#define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 12)
+#define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
+#define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x)<<0)
+#define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x)<<16)
+#define PA_SC_LINE_STIPPLE                              0x28A0C
+#define PA_SC_LINE_STIPPLE_STATE                        0x8B10
+#define PA_SC_MODE_CNTL                                 0x28A4C
+#define PA_SC_MULTI_CHIP_CNTL                           0x8B20
+#define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 20)
+#define SCRATCH_REG0                                    0x8500
+#define SCRATCH_REG1                                    0x8504
+#define SCRATCH_REG2                                    0x8508
+#define SCRATCH_REG3                                    0x850C
+#define SCRATCH_REG4                                    0x8510
+#define SCRATCH_REG5                                    0x8514
+#define SCRATCH_REG6                                    0x8518
+#define SCRATCH_REG7                                    0x851C
+#define SCRATCH_UMSK                                    0x8540
+#define SCRATCH_ADDR                                    0x8544
+#define SMX_DC_CTL0                                     0xA020
+#define         USE_HASH_FUNCTION                               (1 << 0)
+#define         CACHE_DEPTH(x)                                  ((x) << 1)
+#define         FLUSH_ALL_ON_EVENT                              (1 << 10)
+#define         STALL_ON_EVENT                                  (1 << 11)
+#define SMX_EVENT_CTL                                   0xA02C
+#define         ES_FLUSH_CTL(x)                                 ((x) << 0)
+#define         GS_FLUSH_CTL(x)                                 ((x) << 3)
+#define         ACK_FLUSH_CTL(x)                                ((x) << 6)
+#define         SYNC_FLUSH_CTL                                  (1 << 8)
+#define SPI_CONFIG_CNTL                                 0x9100
+#define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
+#define         DISABLE_INTERP_1                                (1 << 5)
+#define SPI_CONFIG_CNTL_1                               0x913C
+#define         VTX_DONE_DELAY(x)                               ((x) << 0)
+#define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
+#define SPI_INPUT_Z                                     0x286D8
+#define SPI_PS_IN_CONTROL_0                             0x286CC
+#define         NUM_INTERP(x)                                   ((x)<<0)
+#define         POSITION_ENA                                    (1<<8)
+#define         POSITION_CENTROID                               (1<<9)
+#define         POSITION_ADDR(x)                                ((x)<<10)
+#define         PARAM_GEN(x)                                    ((x)<<15)
+#define         PARAM_GEN_ADDR(x)                               ((x)<<19)
+#define         BARYC_SAMPLE_CNTL(x)                            ((x)<<26)
+#define         PERSP_GRADIENT_ENA                              (1<<28)
+#define         LINEAR_GRADIENT_ENA                             (1<<29)
+#define         POSITION_SAMPLE                                 (1<<30)
+#define         BARYC_AT_SAMPLE_ENA                             (1<<31)
+#define SQ_CONFIG                                       0x8C00
+#define         VC_ENABLE                                       (1 << 0)
+#define         EXPORT_SRC_C                                    (1 << 1)
+#define         DX9_CONSTS                                      (1 << 2)
+#define         ALU_INST_PREFER_VECTOR                          (1 << 3)
+#define         DX10_CLAMP                                      (1 << 4)
+#define         CLAUSE_SEQ_PRIO(x)                              ((x) << 8)
+#define         PS_PRIO(x)                                      ((x) << 24)
+#define         VS_PRIO(x)                                      ((x) << 26)
+#define         GS_PRIO(x)                                      ((x) << 28)
+#define SQ_DYN_GPR_SIZE_SIMD_AB_0                       0x8DB0
+#define         SIMDA_RING0(x)                                  ((x)<<0)
+#define         SIMDA_RING1(x)                                  ((x)<<8)
+#define         SIMDB_RING0(x)                                  ((x)<<16)
+#define         SIMDB_RING1(x)                                  ((x)<<24)
+#define SQ_DYN_GPR_SIZE_SIMD_AB_1                       0x8DB4
+#define SQ_DYN_GPR_SIZE_SIMD_AB_2                       0x8DB8
+#define SQ_DYN_GPR_SIZE_SIMD_AB_3                       0x8DBC
+#define SQ_DYN_GPR_SIZE_SIMD_AB_4                       0x8DC0
+#define SQ_DYN_GPR_SIZE_SIMD_AB_5                       0x8DC4
+#define SQ_DYN_GPR_SIZE_SIMD_AB_6                       0x8DC8
+#define SQ_DYN_GPR_SIZE_SIMD_AB_7                       0x8DCC
+#define         ES_PRIO(x)                                      ((x) << 30)
+#define SQ_GPR_RESOURCE_MGMT_1                          0x8C04
+#define         NUM_PS_GPRS(x)                                  ((x) << 0)
+#define         NUM_VS_GPRS(x)                                  ((x) << 16)
+#define         DYN_GPR_ENABLE                                  (1 << 27)
+#define         NUM_CLAUSE_TEMP_GPRS(x)                         ((x) << 28)
+#define SQ_GPR_RESOURCE_MGMT_2                          0x8C08
+#define         NUM_GS_GPRS(x)                                  ((x) << 0)
+#define         NUM_ES_GPRS(x)                                  ((x) << 16)
+#define SQ_MS_FIFO_SIZES                                0x8CF0
+#define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
+#define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
+#define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
+#define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)
+#define SQ_STACK_RESOURCE_MGMT_1                        0x8C10
+#define         NUM_PS_STACK_ENTRIES(x)                         ((x) << 0)
+#define         NUM_VS_STACK_ENTRIES(x)                         ((x) << 16)
+#define SQ_STACK_RESOURCE_MGMT_2                        0x8C14
+#define         NUM_GS_STACK_ENTRIES(x)                         ((x) << 0)
+#define         NUM_ES_STACK_ENTRIES(x)                         ((x) << 16)
+#define SQ_THREAD_RESOURCE_MGMT                         0x8C0C
+#define         NUM_PS_THREADS(x)                               ((x) << 0)
+#define         NUM_VS_THREADS(x)                               ((x) << 8)
+#define         NUM_GS_THREADS(x)                               ((x) << 16)
+#define         NUM_ES_THREADS(x)                               ((x) << 24)
+#define SX_DEBUG_1                                      0x9058
+#define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
+#define SX_EXPORT_BUFFER_SIZES                          0x900C
+#define         COLOR_BUFFER_SIZE(x)                            ((x) << 0)
+#define         POSITION_BUFFER_SIZE(x)                         ((x) << 8)
+#define         SMX_BUFFER_SIZE(x)                              ((x) << 16)
+#define SX_MISC                                         0x28350
+#define TA_CNTL_AUX                                     0x9508
+#define         DISABLE_CUBE_WRAP                               (1 << 0)
+#define         DISABLE_CUBE_ANISO                              (1 << 1)
+#define         SYNC_GRADIENT                                   (1 << 24)
+#define         SYNC_WALKER                                     (1 << 25)
+#define         SYNC_ALIGNER                                    (1 << 26)
+#define         BILINEAR_PRECISION_6_BIT                        (0 << 31)
+#define         BILINEAR_PRECISION_8_BIT                        (1 << 31)
+#define TCP_CNTL                                        0x9610
+#define VGT_CACHE_INVALIDATION                          0x88C4
+#define         CACHE_INVALIDATION(x)                           ((x)<<0)
+#define                 VC_ONLY                                         0
+#define                 TC_ONLY                                         1
+#define                 VC_AND_TC                                       2
+#define         AUTO_INVLD_EN(x)                                ((x) << 6)
+#define                 NO_AUTO                                         0
+#define                 ES_AUTO                                         1
+#define                 GS_AUTO                                         2
+#define                 ES_AND_GS_AUTO                                  3
+#define VGT_ES_PER_GS                                   0x88CC
+#define VGT_GS_PER_ES                                   0x88C8
+#define VGT_GS_PER_VS                                   0x88E8
+#define VGT_GS_VERTEX_REUSE                             0x88D4
+#define VGT_NUM_INSTANCES                               0x8974
+#define VGT_OUT_DEALLOC_CNTL                            0x28C5C
+#define         DEALLOC_DIST_MASK                               0x0000007F
+#define VGT_STRMOUT_EN                                  0x28AB0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL                     0x28C58
+#define         VTX_REUSE_DEPTH_MASK                            0x000000FF
+#define VM_CONTEXT0_CNTL                                0x1410
+#define         ENABLE_CONTEXT                                  (1 << 0)
+#define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
+#define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
+#define VM_L2_CNTL                                      0x1400
+#define         ENABLE_L2_CACHE                                 (1 << 0)
+#define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
+#define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
+#define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
+#define VM_L2_CNTL2                                     0x1404
+#define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
+#define         INVALIDATE_L2_CACHE                             (1 << 1)
+#define VM_L2_CNTL3                                     0x1408
+#define         BANK_SELECT(x)                                  ((x) << 0)
+#define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
+#define VM_L2_STATUS                                    0x140C
+#define         L2_BUSY                                         (1 << 0)
+#define WAIT_UNTIL                                      0x8040
+#endif

diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h new file mode 100644 index 000000000000..4b9c3d6396ff --- /dev/null +++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -0,0 +1,341 @@
	1	/*
	2	* Copyright 2009 Advanced Micro Devices, Inc.
	3	* Copyright 2009 Red Hat Inc.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors: Dave Airlie
	24	* Alex Deucher
	25	* Jerome Glisse
	26	*/
	27	#ifndef RV770_H
	28	#define RV770_H
	29
	30	#define R7XX_MAX_SH_GPRS 256
	31	#define R7XX_MAX_TEMP_GPRS 16
	32	#define R7XX_MAX_SH_THREADS 256
	33	#define R7XX_MAX_SH_STACK_ENTRIES 4096
	34	#define R7XX_MAX_BACKENDS 8
	35	#define R7XX_MAX_BACKENDS_MASK 0xff
	36	#define R7XX_MAX_SIMDS 16
	37	#define R7XX_MAX_SIMDS_MASK 0xffff
	38	#define R7XX_MAX_PIPES 8
	39	#define R7XX_MAX_PIPES_MASK 0xff
	40
	41	/* Registers */
	42	#define CB_COLOR0_BASE 0x28040
	43	#define CB_COLOR1_BASE 0x28044
	44	#define CB_COLOR2_BASE 0x28048
	45	#define CB_COLOR3_BASE 0x2804C
	46	#define CB_COLOR4_BASE 0x28050
	47	#define CB_COLOR5_BASE 0x28054
	48	#define CB_COLOR6_BASE 0x28058
	49	#define CB_COLOR7_BASE 0x2805C
	50	#define CB_COLOR7_FRAG 0x280FC
	51
	52	#define CC_GC_SHADER_PIPE_CONFIG 0x8950
	53	#define CC_RB_BACKEND_DISABLE 0x98F4
	54	#define BACKEND_DISABLE(x) ((x) << 16)
	55	#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
	56
	57	#define CGTS_SYS_TCC_DISABLE 0x3F90
	58	#define CGTS_TCC_DISABLE 0x9148
	59	#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
	60	#define CGTS_USER_TCC_DISABLE 0x914C
	61
	62	#define CONFIG_MEMSIZE 0x5428
	63
	64	#define CP_ME_CNTL 0x86D8
	65	#define CP_ME_HALT (1<<28)
	66	#define CP_PFP_HALT (1<<26)
	67	#define CP_ME_RAM_DATA 0xC160
	68	#define CP_ME_RAM_RADDR 0xC158
	69	#define CP_ME_RAM_WADDR 0xC15C
	70	#define CP_MEQ_THRESHOLDS 0x8764
	71	#define STQ_SPLIT(x) ((x) << 0)
	72	#define CP_PERFMON_CNTL 0x87FC
	73	#define CP_PFP_UCODE_ADDR 0xC150
	74	#define CP_PFP_UCODE_DATA 0xC154
	75	#define CP_QUEUE_THRESHOLDS 0x8760
	76	#define ROQ_IB1_START(x) ((x) << 0)
	77	#define ROQ_IB2_START(x) ((x) << 8)
	78	#define CP_RB_CNTL 0xC104
	79	#define RB_BUFSZ(x) ((x)<<0)
	80	#define RB_BLKSZ(x) ((x)<<8)
	81	#define RB_NO_UPDATE (1<<27)
	82	#define RB_RPTR_WR_ENA (1<<31)
	83	#define BUF_SWAP_32BIT (2 << 16)
	84	#define CP_RB_RPTR 0x8700
	85	#define CP_RB_RPTR_ADDR 0xC10C
	86	#define CP_RB_RPTR_ADDR_HI 0xC110
	87	#define CP_RB_RPTR_WR 0xC108
	88	#define CP_RB_WPTR 0xC114
	89	#define CP_RB_WPTR_ADDR 0xC118
	90	#define CP_RB_WPTR_ADDR_HI 0xC11C
	91	#define CP_RB_WPTR_DELAY 0x8704
	92	#define CP_SEM_WAIT_TIMER 0x85BC
	93
	94	#define DB_DEBUG3 0x98B0
	95	#define DB_CLK_OFF_DELAY(x) ((x) << 11)
	96	#define DB_DEBUG4 0x9B8C
	97	#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
	98
	99	#define DCP_TILING_CONFIG 0x6CA0
	100	#define PIPE_TILING(x) ((x) << 1)
	101	#define BANK_TILING(x) ((x) << 4)
	102	#define GROUP_SIZE(x) ((x) << 6)
	103	#define ROW_TILING(x) ((x) << 8)
	104	#define BANK_SWAPS(x) ((x) << 11)
	105	#define SAMPLE_SPLIT(x) ((x) << 14)
	106	#define BACKEND_MAP(x) ((x) << 16)
	107
	108	#define GB_TILING_CONFIG 0x98F0
	109
	110	#define GC_USER_SHADER_PIPE_CONFIG 0x8954
	111	#define INACTIVE_QD_PIPES(x) ((x) << 8)
	112	#define INACTIVE_QD_PIPES_MASK 0x0000FF00
	113	#define INACTIVE_SIMDS(x) ((x) << 16)
	114	#define INACTIVE_SIMDS_MASK 0x00FF0000
	115
	116	#define GRBM_CNTL 0x8000
	117	#define GRBM_READ_TIMEOUT(x) ((x) << 0)
	118	#define GRBM_SOFT_RESET 0x8020
	119	#define SOFT_RESET_CP (1<<0)
	120	#define GRBM_STATUS 0x8010
	121	#define CMDFIFO_AVAIL_MASK 0x0000000F
	122	#define GUI_ACTIVE (1<<31)
	123	#define GRBM_STATUS2 0x8014
	124
	125	#define HDP_HOST_PATH_CNTL 0x2C00
	126	#define HDP_NONSURFACE_BASE 0x2C04
	127	#define HDP_NONSURFACE_INFO 0x2C08
	128	#define HDP_NONSURFACE_SIZE 0x2C0C
	129	#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
	130	#define HDP_TILING_CONFIG 0x2F3C
	131
	132	#define MC_ARB_RAMCFG 0x2760
	133	#define NOOFBANK_SHIFT 0
	134	#define NOOFBANK_MASK 0x00000003
	135	#define NOOFRANK_SHIFT 2
	136	#define NOOFRANK_MASK 0x00000004
	137	#define NOOFROWS_SHIFT 3
	138	#define NOOFROWS_MASK 0x00000038
	139	#define NOOFCOLS_SHIFT 6
	140	#define NOOFCOLS_MASK 0x000000C0
	141	#define CHANSIZE_SHIFT 8
	142	#define CHANSIZE_MASK 0x00000100
	143	#define BURSTLENGTH_SHIFT 9
	144	#define BURSTLENGTH_MASK 0x00000200
	145	#define MC_VM_AGP_TOP 0x2028
	146	#define MC_VM_AGP_BOT 0x202C
	147	#define MC_VM_AGP_BASE 0x2030
	148	#define MC_VM_FB_LOCATION 0x2024
	149	#define MC_VM_MB_L1_TLB0_CNTL 0x2234
	150	#define MC_VM_MB_L1_TLB1_CNTL 0x2238
	151	#define MC_VM_MB_L1_TLB2_CNTL 0x223C
	152	#define MC_VM_MB_L1_TLB3_CNTL 0x2240
	153	#define ENABLE_L1_TLB (1 << 0)
	154	#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
	155	#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
	156	#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
	157	#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
	158	#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
	159	#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
	160	#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
	161	#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
	162	#define MC_VM_MD_L1_TLB0_CNTL 0x2654
	163	#define MC_VM_MD_L1_TLB1_CNTL 0x2658
	164	#define MC_VM_MD_L1_TLB2_CNTL 0x265C
	165	#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
	166	#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
	167	#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
	168
	169	#define PA_CL_ENHANCE 0x8A14
	170	#define CLIP_VTX_REORDER_ENA (1 << 0)
	171	#define NUM_CLIP_SEQ(x) ((x) << 1)
	172	#define PA_SC_AA_CONFIG 0x28C04
	173	#define PA_SC_CLIPRECT_RULE 0x2820C
	174	#define PA_SC_EDGERULE 0x28230
	175	#define PA_SC_FIFO_SIZE 0x8BCC
	176	#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
	177	#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
	178	#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
	179	#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
	180	#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
	181	#define PA_SC_LINE_STIPPLE 0x28A0C
	182	#define PA_SC_LINE_STIPPLE_STATE 0x8B10
	183	#define PA_SC_MODE_CNTL 0x28A4C
	184	#define PA_SC_MULTI_CHIP_CNTL 0x8B20
	185	#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
	186
	187	#define SCRATCH_REG0 0x8500
	188	#define SCRATCH_REG1 0x8504
	189	#define SCRATCH_REG2 0x8508
	190	#define SCRATCH_REG3 0x850C
	191	#define SCRATCH_REG4 0x8510
	192	#define SCRATCH_REG5 0x8514
	193	#define SCRATCH_REG6 0x8518
	194	#define SCRATCH_REG7 0x851C
	195	#define SCRATCH_UMSK 0x8540
	196	#define SCRATCH_ADDR 0x8544
	197
	198	#define SMX_DC_CTL0 0xA020
	199	#define USE_HASH_FUNCTION (1 << 0)
	200	#define CACHE_DEPTH(x) ((x) << 1)
	201	#define FLUSH_ALL_ON_EVENT (1 << 10)
	202	#define STALL_ON_EVENT (1 << 11)
	203	#define SMX_EVENT_CTL 0xA02C
	204	#define ES_FLUSH_CTL(x) ((x) << 0)
	205	#define GS_FLUSH_CTL(x) ((x) << 3)
	206	#define ACK_FLUSH_CTL(x) ((x) << 6)
	207	#define SYNC_FLUSH_CTL (1 << 8)
	208
	209	#define SPI_CONFIG_CNTL 0x9100
	210	#define GPR_WRITE_PRIORITY(x) ((x) << 0)
	211	#define DISABLE_INTERP_1 (1 << 5)
	212	#define SPI_CONFIG_CNTL_1 0x913C
	213	#define VTX_DONE_DELAY(x) ((x) << 0)
	214	#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
	215	#define SPI_INPUT_Z 0x286D8
	216	#define SPI_PS_IN_CONTROL_0 0x286CC
	217	#define NUM_INTERP(x) ((x)<<0)
	218	#define POSITION_ENA (1<<8)
	219	#define POSITION_CENTROID (1<<9)
	220	#define POSITION_ADDR(x) ((x)<<10)
	221	#define PARAM_GEN(x) ((x)<<15)
	222	#define PARAM_GEN_ADDR(x) ((x)<<19)
	223	#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
	224	#define PERSP_GRADIENT_ENA (1<<28)
	225	#define LINEAR_GRADIENT_ENA (1<<29)
	226	#define POSITION_SAMPLE (1<<30)
	227	#define BARYC_AT_SAMPLE_ENA (1<<31)
	228
	229	#define SQ_CONFIG 0x8C00
	230	#define VC_ENABLE (1 << 0)
	231	#define EXPORT_SRC_C (1 << 1)
	232	#define DX9_CONSTS (1 << 2)
	233	#define ALU_INST_PREFER_VECTOR (1 << 3)
	234	#define DX10_CLAMP (1 << 4)
	235	#define CLAUSE_SEQ_PRIO(x) ((x) << 8)
	236	#define PS_PRIO(x) ((x) << 24)
	237	#define VS_PRIO(x) ((x) << 26)
	238	#define GS_PRIO(x) ((x) << 28)
	239	#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
	240	#define SIMDA_RING0(x) ((x)<<0)
	241	#define SIMDA_RING1(x) ((x)<<8)
	242	#define SIMDB_RING0(x) ((x)<<16)
	243	#define SIMDB_RING1(x) ((x)<<24)
	244	#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
	245	#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
	246	#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
	247	#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
	248	#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
	249	#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
	250	#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
	251	#define ES_PRIO(x) ((x) << 30)
	252	#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
	253	#define NUM_PS_GPRS(x) ((x) << 0)
	254	#define NUM_VS_GPRS(x) ((x) << 16)
	255	#define DYN_GPR_ENABLE (1 << 27)
	256	#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
	257	#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
	258	#define NUM_GS_GPRS(x) ((x) << 0)
	259	#define NUM_ES_GPRS(x) ((x) << 16)
	260	#define SQ_MS_FIFO_SIZES 0x8CF0
	261	#define CACHE_FIFO_SIZE(x) ((x) << 0)
	262	#define FETCH_FIFO_HIWATER(x) ((x) << 8)
	263	#define DONE_FIFO_HIWATER(x) ((x) << 16)
	264	#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
	265	#define SQ_STACK_RESOURCE_MGMT_1 0x8C10
	266	#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
	267	#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
	268	#define SQ_STACK_RESOURCE_MGMT_2 0x8C14
	269	#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
	270	#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
	271	#define SQ_THREAD_RESOURCE_MGMT 0x8C0C
	272	#define NUM_PS_THREADS(x) ((x) << 0)
	273	#define NUM_VS_THREADS(x) ((x) << 8)
	274	#define NUM_GS_THREADS(x) ((x) << 16)
	275	#define NUM_ES_THREADS(x) ((x) << 24)
	276
	277	#define SX_DEBUG_1 0x9058
	278	#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
	279	#define SX_EXPORT_BUFFER_SIZES 0x900C
	280	#define COLOR_BUFFER_SIZE(x) ((x) << 0)
	281	#define POSITION_BUFFER_SIZE(x) ((x) << 8)
	282	#define SMX_BUFFER_SIZE(x) ((x) << 16)
	283	#define SX_MISC 0x28350
	284
	285	#define TA_CNTL_AUX 0x9508
	286	#define DISABLE_CUBE_WRAP (1 << 0)
	287	#define DISABLE_CUBE_ANISO (1 << 1)
	288	#define SYNC_GRADIENT (1 << 24)
	289	#define SYNC_WALKER (1 << 25)
	290	#define SYNC_ALIGNER (1 << 26)
	291	#define BILINEAR_PRECISION_6_BIT (0 << 31)
	292	#define BILINEAR_PRECISION_8_BIT (1 << 31)
	293
	294	#define TCP_CNTL 0x9610
	295
	296	#define VGT_CACHE_INVALIDATION 0x88C4
	297	#define CACHE_INVALIDATION(x) ((x)<<0)
	298	#define VC_ONLY 0
	299	#define TC_ONLY 1
	300	#define VC_AND_TC 2
	301	#define AUTO_INVLD_EN(x) ((x) << 6)
	302	#define NO_AUTO 0
	303	#define ES_AUTO 1
	304	#define GS_AUTO 2
	305	#define ES_AND_GS_AUTO 3
	306	#define VGT_ES_PER_GS 0x88CC
	307	#define VGT_GS_PER_ES 0x88C8
	308	#define VGT_GS_PER_VS 0x88E8
	309	#define VGT_GS_VERTEX_REUSE 0x88D4
	310	#define VGT_NUM_INSTANCES 0x8974
	311	#define VGT_OUT_DEALLOC_CNTL 0x28C5C
	312	#define DEALLOC_DIST_MASK 0x0000007F
	313	#define VGT_STRMOUT_EN 0x28AB0
	314	#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
	315	#define VTX_REUSE_DEPTH_MASK 0x000000FF
	316
	317	#define VM_CONTEXT0_CNTL 0x1410
	318	#define ENABLE_CONTEXT (1 << 0)
	319	#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
	320	#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
	321	#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
	322	#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
	323	#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
	324	#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
	325	#define VM_L2_CNTL 0x1400
	326	#define ENABLE_L2_CACHE (1 << 0)
	327	#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
	328	#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
	329	#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
	330	#define VM_L2_CNTL2 0x1404
	331	#define INVALIDATE_ALL_L1_TLBS (1 << 0)
	332	#define INVALIDATE_L2_CACHE (1 << 1)
	333	#define VM_L2_CNTL3 0x1408
	334	#define BANK_SELECT(x) ((x) << 0)
	335	#define CACHE_UPDATE_MODE(x) ((x) << 6)
	336	#define VM_L2_STATUS 0x140C
	337	#define L2_BUSY (1 << 0)
	338
	339	#define WAIT_UNTIL 0x8040
	340
	341	#endif