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path: root/drivers/gpu/drm/radeon/rv515.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/rv515.c')
-rw-r--r--drivers/gpu/drm/radeon/rv515.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 41a34c23e6d8..ba68c9fe90a1 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -380,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
381 381
382 /* Stop all video */ 382 /* Stop all video */
383 WREG32(R_000330_D1VGA_CONTROL, 0);
384 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 383 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
385 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 384 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
386 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 385 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -389,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
389 WREG32(R_006880_D2CRTC_CONTROL, 0); 388 WREG32(R_006880_D2CRTC_CONTROL, 0);
390 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 389 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
391 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 390 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
391 WREG32(R_000330_D1VGA_CONTROL, 0);
392 WREG32(R_000338_D2VGA_CONTROL, 0);
392} 393}
393 394
394void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 395void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -402,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
402 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 403 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
403 mdelay(1); 404 mdelay(1);
404 /* Restore video state */ 405 /* Restore video state */
406 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
407 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
405 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 408 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
406 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 409 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
407 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 410 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
408 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 411 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
409 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 412 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
410 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 413 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
411 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
412 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
413 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 414 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
414} 415}
415 416
@@ -585,6 +586,8 @@ int rv515_init(struct radeon_device *rdev)
585 } 586 }
586 /* Initialize clocks */ 587 /* Initialize clocks */
587 radeon_get_clock_info(rdev->ddev); 588 radeon_get_clock_info(rdev->ddev);
589 /* Initialize power management */
590 radeon_pm_init(rdev);
588 /* Get vram informations */ 591 /* Get vram informations */
589 rv515_vram_info(rdev); 592 rv515_vram_info(rdev);
590 /* Initialize memory controller (also test AGP) */ 593 /* Initialize memory controller (also test AGP) */