diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/rs600d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/rs600d.h | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h index e52d2695510b..a27c13ac47c3 100644 --- a/drivers/gpu/drm/radeon/rs600d.h +++ b/drivers/gpu/drm/radeon/rs600d.h | |||
| @@ -178,6 +178,52 @@ | |||
| 178 | #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) | 178 | #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) |
| 179 | #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) | 179 | #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) |
| 180 | #define C_000074_MC_IND_DATA 0x00000000 | 180 | #define C_000074_MC_IND_DATA 0x00000000 |
| 181 | #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 | ||
| 182 | #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) | ||
| 183 | #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) | ||
| 184 | #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE | ||
| 185 | #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) | ||
| 186 | #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) | ||
| 187 | #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD | ||
| 188 | #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) | ||
| 189 | #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) | ||
| 190 | #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB | ||
| 191 | #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) | ||
| 192 | #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) | ||
| 193 | #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 | ||
| 194 | #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) | ||
| 195 | #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) | ||
| 196 | #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF | ||
| 197 | #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) | ||
| 198 | #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) | ||
| 199 | #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF | ||
| 200 | #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) | ||
| 201 | #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) | ||
| 202 | #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF | ||
| 203 | #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) | ||
| 204 | #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) | ||
| 205 | #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F | ||
| 206 | #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) | ||
| 207 | #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) | ||
| 208 | #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF | ||
| 209 | #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) | ||
| 210 | #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) | ||
| 211 | #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF | ||
| 212 | #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) | ||
| 213 | #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) | ||
| 214 | #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF | ||
| 215 | #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) | ||
| 216 | #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) | ||
| 217 | #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF | ||
| 218 | #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) | ||
| 219 | #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) | ||
| 220 | #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF | ||
| 221 | #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) | ||
| 222 | #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) | ||
| 223 | #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF | ||
| 224 | #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) | ||
| 225 | #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) | ||
| 226 | #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF | ||
| 181 | #define R_000134_HDP_FB_LOCATION 0x000134 | 227 | #define R_000134_HDP_FB_LOCATION 0x000134 |
| 182 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) | 228 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) |
| 183 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) | 229 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) |
| @@ -588,4 +634,38 @@ | |||
| 588 | #define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) | 634 | #define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) |
| 589 | #define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF | 635 | #define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF |
| 590 | 636 | ||
| 637 | /* PLL regs */ | ||
| 638 | #define GENERAL_PWRMGT 0x8 | ||
| 639 | #define GLOBAL_PWRMGT_EN (1 << 0) | ||
| 640 | #define MOBILE_SU (1 << 2) | ||
| 641 | #define DYN_PWRMGT_SCLK_LENGTH 0xc | ||
| 642 | #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) | ||
| 643 | #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) | ||
| 644 | #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) | ||
| 645 | #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) | ||
| 646 | #define POWER_D1_SCLK_HILEN(x) ((x) << 16) | ||
| 647 | #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) | ||
| 648 | #define STATIC_SCREEN_HILEN(x) ((x) << 24) | ||
| 649 | #define STATIC_SCREEN_LOLEN(x) ((x) << 28) | ||
| 650 | #define DYN_SCLK_VOL_CNTL 0xe | ||
| 651 | #define IO_CG_VOLTAGE_DROP (1 << 0) | ||
| 652 | #define VOLTAGE_DROP_SYNC (1 << 2) | ||
| 653 | #define VOLTAGE_DELAY_SEL(x) ((x) << 3) | ||
| 654 | #define HDP_DYN_CNTL 0x10 | ||
| 655 | #define HDP_FORCEON (1 << 0) | ||
| 656 | #define MC_HOST_DYN_CNTL 0x1e | ||
| 657 | #define MC_HOST_FORCEON (1 << 0) | ||
| 658 | #define DYN_BACKBIAS_CNTL 0x29 | ||
| 659 | #define IO_CG_BACKBIAS_EN (1 << 0) | ||
| 660 | |||
| 661 | /* mmreg */ | ||
| 662 | #define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0 | ||
| 663 | #define PWRDN_WAIT_BUSY_OFF (1 << 0) | ||
| 664 | #define PWRDN_WAIT_PWRSEQ_OFF (1 << 4) | ||
| 665 | #define PWRDN_WAIT_PPLL_OFF (1 << 8) | ||
| 666 | #define PWRUP_WAIT_PPLL_ON (1 << 12) | ||
| 667 | #define PWRUP_WAIT_MEM_INIT_DONE (1 << 16) | ||
| 668 | #define PM_ASSERT_RESET (1 << 20) | ||
| 669 | #define PM_PWRDN_PPLL (1 << 24) | ||
| 670 | |||
| 591 | #endif | 671 | #endif |