diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/rs600d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/rs600d.h | 406 |
1 files changed, 406 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h new file mode 100644 index 000000000000..6dac524f6757 --- /dev/null +++ b/drivers/gpu/drm/radeon/rs600d.h | |||
| @@ -0,0 +1,406 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | ||
| 3 | * Copyright 2008 Red Hat Inc. | ||
| 4 | * Copyright 2009 Jerome Glisse. | ||
| 5 | * | ||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 7 | * copy of this software and associated documentation files (the "Software"), | ||
| 8 | * to deal in the Software without restriction, including without limitation | ||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 11 | * Software is furnished to do so, subject to the following conditions: | ||
| 12 | * | ||
| 13 | * The above copyright notice and this permission notice shall be included in | ||
| 14 | * all copies or substantial portions of the Software. | ||
| 15 | * | ||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 23 | * | ||
| 24 | * Authors: Dave Airlie | ||
| 25 | * Alex Deucher | ||
| 26 | * Jerome Glisse | ||
| 27 | */ | ||
| 28 | #ifndef __RS600D_H__ | ||
| 29 | #define __RS600D_H__ | ||
| 30 | |||
| 31 | /* Registers */ | ||
| 32 | #define R_000040_GEN_INT_CNTL 0x000040 | ||
| 33 | #define S_000040_DISPLAY_INT_STATUS(x) (((x) & 0x1) << 0) | ||
| 34 | #define G_000040_DISPLAY_INT_STATUS(x) (((x) >> 0) & 0x1) | ||
| 35 | #define C_000040_DISPLAY_INT_STATUS 0xFFFFFFFE | ||
| 36 | #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) | ||
| 37 | #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) | ||
| 38 | #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF | ||
| 39 | #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) | ||
| 40 | #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) | ||
| 41 | #define C_000040_CRTC2_VSYNC 0xFFFFFFBF | ||
| 42 | #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) | ||
| 43 | #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) | ||
| 44 | #define C_000040_SNAPSHOT2 0xFFFFFF7F | ||
| 45 | #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) | ||
| 46 | #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) | ||
| 47 | #define C_000040_CRTC2_VBLANK 0xFFFFFDFF | ||
| 48 | #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) | ||
| 49 | #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) | ||
| 50 | #define C_000040_FP2_DETECT 0xFFFFFBFF | ||
| 51 | #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) | ||
| 52 | #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) | ||
| 53 | #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF | ||
| 54 | #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) | ||
| 55 | #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) | ||
| 56 | #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF | ||
| 57 | #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) | ||
| 58 | #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) | ||
| 59 | #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF | ||
| 60 | #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) | ||
| 61 | #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) | ||
| 62 | #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF | ||
| 63 | #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) | ||
| 64 | #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) | ||
| 65 | #define C_000040_I2C_INT_EN 0xFFFDFFFF | ||
| 66 | #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) | ||
| 67 | #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) | ||
| 68 | #define C_000040_GUI_IDLE 0xFFF7FFFF | ||
| 69 | #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) | ||
| 70 | #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) | ||
| 71 | #define C_000040_VIPH_INT_EN 0xFEFFFFFF | ||
| 72 | #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) | ||
| 73 | #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) | ||
| 74 | #define C_000040_SW_INT_EN 0xFDFFFFFF | ||
| 75 | #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) | ||
| 76 | #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) | ||
| 77 | #define C_000040_GEYSERVILLE 0xF7FFFFFF | ||
| 78 | #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) | ||
| 79 | #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) | ||
| 80 | #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF | ||
| 81 | #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) | ||
| 82 | #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) | ||
| 83 | #define C_000040_DVI_I2C_INT 0xDFFFFFFF | ||
| 84 | #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) | ||
| 85 | #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) | ||
| 86 | #define C_000040_GUIDMA 0xBFFFFFFF | ||
| 87 | #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) | ||
| 88 | #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) | ||
| 89 | #define C_000040_VIDDMA 0x7FFFFFFF | ||
| 90 | #define R_00004C_BUS_CNTL 0x00004C | ||
| 91 | #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14) | ||
| 92 | #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1) | ||
| 93 | #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF | ||
| 94 | #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20) | ||
| 95 | #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1) | ||
| 96 | #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF | ||
| 97 | #define R_000070_MC_IND_INDEX 0x000070 | ||
| 98 | #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0) | ||
| 99 | #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF) | ||
| 100 | #define C_000070_MC_IND_ADDR 0xFFFF0000 | ||
| 101 | #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16) | ||
| 102 | #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1) | ||
| 103 | #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF | ||
| 104 | #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17) | ||
| 105 | #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1) | ||
| 106 | #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF | ||
| 107 | #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18) | ||
| 108 | #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1) | ||
| 109 | #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF | ||
| 110 | #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19) | ||
| 111 | #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1) | ||
| 112 | #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF | ||
| 113 | #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20) | ||
| 114 | #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1) | ||
| 115 | #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF | ||
| 116 | #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21) | ||
| 117 | #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1) | ||
| 118 | #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF | ||
| 119 | #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22) | ||
| 120 | #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1) | ||
| 121 | #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF | ||
| 122 | #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23) | ||
| 123 | #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1) | ||
| 124 | #define C_000070_MC_IND_WR_EN 0xFF7FFFFF | ||
| 125 | #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24) | ||
| 126 | #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1) | ||
| 127 | #define C_000070_MC_IND_RD_INV 0xFEFFFFFF | ||
| 128 | #define R_000074_MC_IND_DATA 0x000074 | ||
| 129 | #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 130 | #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 131 | #define C_000074_MC_IND_DATA 0x00000000 | ||
| 132 | #define R_000134_HDP_FB_LOCATION 0x000134 | ||
| 133 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) | ||
| 134 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
| 135 | #define C_000134_HDP_FB_START 0xFFFF0000 | ||
| 136 | #define R_0007C0_CP_STAT 0x0007C0 | ||
| 137 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) | ||
| 138 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) | ||
| 139 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE | ||
| 140 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) | ||
| 141 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) | ||
| 142 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD | ||
| 143 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) | ||
| 144 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) | ||
| 145 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB | ||
| 146 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) | ||
| 147 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) | ||
| 148 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 | ||
| 149 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) | ||
| 150 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) | ||
| 151 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF | ||
| 152 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) | ||
| 153 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) | ||
| 154 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF | ||
| 155 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) | ||
| 156 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) | ||
| 157 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF | ||
| 158 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) | ||
| 159 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) | ||
| 160 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF | ||
| 161 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) | ||
| 162 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) | ||
| 163 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF | ||
| 164 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) | ||
| 165 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) | ||
| 166 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF | ||
| 167 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) | ||
| 168 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) | ||
| 169 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF | ||
| 170 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) | ||
| 171 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) | ||
| 172 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF | ||
| 173 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) | ||
| 174 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) | ||
| 175 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF | ||
| 176 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) | ||
| 177 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) | ||
| 178 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF | ||
| 179 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) | ||
| 180 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) | ||
| 181 | #define C_0007C0_CP_BUSY 0x7FFFFFFF | ||
| 182 | #define R_000E40_RBBM_STATUS 0x000E40 | ||
| 183 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) | ||
| 184 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) | ||
| 185 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 | ||
| 186 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) | ||
| 187 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) | ||
| 188 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF | ||
| 189 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) | ||
| 190 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) | ||
| 191 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF | ||
| 192 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) | ||
| 193 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) | ||
| 194 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF | ||
| 195 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) | ||
| 196 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) | ||
| 197 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF | ||
| 198 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) | ||
| 199 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) | ||
| 200 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF | ||
| 201 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) | ||
| 202 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) | ||
| 203 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF | ||
| 204 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) | ||
| 205 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) | ||
| 206 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF | ||
| 207 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) | ||
| 208 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) | ||
| 209 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF | ||
| 210 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) | ||
| 211 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) | ||
| 212 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF | ||
| 213 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) | ||
| 214 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) | ||
| 215 | #define C_000E40_E2_BUSY 0xFFFDFFFF | ||
| 216 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) | ||
| 217 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) | ||
| 218 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF | ||
| 219 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) | ||
| 220 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) | ||
| 221 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF | ||
| 222 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) | ||
| 223 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) | ||
| 224 | #define C_000E40_VAP_BUSY 0xFFEFFFFF | ||
| 225 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) | ||
| 226 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) | ||
| 227 | #define C_000E40_RE_BUSY 0xFFDFFFFF | ||
| 228 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) | ||
| 229 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) | ||
| 230 | #define C_000E40_TAM_BUSY 0xFFBFFFFF | ||
| 231 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) | ||
| 232 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) | ||
| 233 | #define C_000E40_TDM_BUSY 0xFF7FFFFF | ||
| 234 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) | ||
| 235 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) | ||
| 236 | #define C_000E40_PB_BUSY 0xFEFFFFFF | ||
| 237 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) | ||
| 238 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) | ||
| 239 | #define C_000E40_TIM_BUSY 0xFDFFFFFF | ||
| 240 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) | ||
| 241 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) | ||
| 242 | #define C_000E40_GA_BUSY 0xFBFFFFFF | ||
| 243 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) | ||
| 244 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) | ||
| 245 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF | ||
| 246 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) | ||
| 247 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) | ||
| 248 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF | ||
| 249 | #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4 | ||
| 250 | #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) | ||
| 251 | #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) | ||
| 252 | #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000 | ||
| 253 | #define R_006534_D1MODE_VBLANK_STATUS 0x006534 | ||
| 254 | #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) | ||
| 255 | #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) | ||
| 256 | #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE | ||
| 257 | #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) | ||
| 258 | #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) | ||
| 259 | #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF | ||
| 260 | #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) | ||
| 261 | #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) | ||
| 262 | #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF | ||
| 263 | #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) | ||
| 264 | #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) | ||
| 265 | #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF | ||
| 266 | #define R_006540_DxMODE_INT_MASK 0x006540 | ||
| 267 | #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0) | ||
| 268 | #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1) | ||
| 269 | #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE | ||
| 270 | #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4) | ||
| 271 | #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1) | ||
| 272 | #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF | ||
| 273 | #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8) | ||
| 274 | #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1) | ||
| 275 | #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF | ||
| 276 | #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12) | ||
| 277 | #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1) | ||
| 278 | #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF | ||
| 279 | #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30) | ||
| 280 | #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1) | ||
| 281 | #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF | ||
| 282 | #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31) | ||
| 283 | #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1) | ||
| 284 | #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF | ||
| 285 | #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4 | ||
| 286 | #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) | ||
| 287 | #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) | ||
| 288 | #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000 | ||
| 289 | #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34 | ||
| 290 | #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) | ||
| 291 | #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) | ||
| 292 | #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE | ||
| 293 | #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) | ||
| 294 | #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) | ||
| 295 | #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF | ||
| 296 | #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) | ||
| 297 | #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) | ||
| 298 | #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF | ||
| 299 | #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) | ||
| 300 | #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) | ||
| 301 | #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF | ||
| 302 | #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC | ||
| 303 | #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4) | ||
| 304 | #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1) | ||
| 305 | #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF | ||
| 306 | #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) | ||
| 307 | #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) | ||
| 308 | #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF | ||
| 309 | |||
| 310 | |||
| 311 | /* MC registers */ | ||
| 312 | #define R_000000_MC_STATUS 0x000000 | ||
| 313 | #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0) | ||
| 314 | #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1) | ||
| 315 | #define C_000000_MC_IDLE 0xFFFFFFFE | ||
| 316 | #define R_000004_MC_FB_LOCATION 0x000004 | ||
| 317 | #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) | ||
| 318 | #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
| 319 | #define C_000004_MC_FB_START 0xFFFF0000 | ||
| 320 | #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) | ||
| 321 | #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) | ||
| 322 | #define C_000004_MC_FB_TOP 0x0000FFFF | ||
| 323 | #define R_000005_MC_AGP_LOCATION 0x000005 | ||
| 324 | #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) | ||
| 325 | #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) | ||
| 326 | #define C_000005_MC_AGP_START 0xFFFF0000 | ||
| 327 | #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) | ||
| 328 | #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) | ||
| 329 | #define C_000005_MC_AGP_TOP 0x0000FFFF | ||
| 330 | #define R_000006_AGP_BASE 0x000006 | ||
| 331 | #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) | ||
| 332 | #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) | ||
| 333 | #define C_000006_AGP_BASE_ADDR 0x00000000 | ||
| 334 | #define R_000007_AGP_BASE_2 0x000007 | ||
| 335 | #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) | ||
| 336 | #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) | ||
| 337 | #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 | ||
| 338 | #define R_000009_MC_CNTL1 0x000009 | ||
| 339 | #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26) | ||
| 340 | #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1) | ||
| 341 | #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF | ||
| 342 | /* FIXME don't know the various field size need feedback from AMD */ | ||
| 343 | #define R_000100_MC_PT0_CNTL 0x000100 | ||
| 344 | #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0) | ||
| 345 | #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1) | ||
| 346 | #define C_000100_ENABLE_PT 0xFFFFFFFE | ||
| 347 | #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15) | ||
| 348 | #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7) | ||
| 349 | #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF | ||
| 350 | #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21) | ||
| 351 | #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7) | ||
| 352 | #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF | ||
| 353 | #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28) | ||
| 354 | #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1) | ||
| 355 | #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF | ||
| 356 | #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29) | ||
| 357 | #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1) | ||
| 358 | #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF | ||
| 359 | #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102 | ||
| 360 | #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0) | ||
| 361 | #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1) | ||
| 362 | #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE | ||
| 363 | #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1) | ||
| 364 | #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3) | ||
| 365 | #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9 | ||
| 366 | #define V_000102_PAGE_TABLE_FLAT 0 | ||
| 367 | /* R600 documentation suggest that this should be a number of pages */ | ||
| 368 | #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112 | ||
| 369 | #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114 | ||
| 370 | #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C | ||
| 371 | #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C | ||
| 372 | #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C | ||
| 373 | #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C | ||
| 374 | #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C | ||
| 375 | #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0) | ||
| 376 | #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1) | ||
| 377 | #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE | ||
| 378 | #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1) | ||
| 379 | #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1) | ||
| 380 | #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD | ||
| 381 | #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8) | ||
| 382 | #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3) | ||
| 383 | #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF | ||
| 384 | #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0 | ||
| 385 | #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1 | ||
| 386 | #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2 | ||
| 387 | #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3 | ||
| 388 | #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10) | ||
| 389 | #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1) | ||
| 390 | #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF | ||
| 391 | #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0 | ||
| 392 | #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1 | ||
| 393 | #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11) | ||
| 394 | #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7) | ||
| 395 | #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF | ||
| 396 | #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14) | ||
| 397 | #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1) | ||
| 398 | #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF | ||
| 399 | #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15) | ||
| 400 | #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7) | ||
| 401 | #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF | ||
| 402 | #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20) | ||
| 403 | #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) | ||
| 404 | #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF | ||
| 405 | |||
| 406 | #endif | ||