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-rw-r--r--drivers/gpu/drm/radeon/rs400d.h160
1 files changed, 160 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rs400d.h b/drivers/gpu/drm/radeon/rs400d.h
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index 000000000000..6d8bac58ced9
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+++ b/drivers/gpu/drm/radeon/rs400d.h
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RS400D_H__
29#define __RS400D_H__
30
31/* Registers */
32#define R_000148_MC_FB_LOCATION 0x000148
33#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
34#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
35#define C_000148_MC_FB_START 0xFFFF0000
36#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
37#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
38#define C_000148_MC_FB_TOP 0x0000FFFF
39#define R_00015C_NB_TOM 0x00015C
40#define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0)
41#define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
42#define C_00015C_MC_FB_START 0xFFFF0000
43#define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
44#define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
45#define C_00015C_MC_FB_TOP 0x0000FFFF
46#define R_0007C0_CP_STAT 0x0007C0
47#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
48#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
49#define C_0007C0_MRU_BUSY 0xFFFFFFFE
50#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
51#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
52#define C_0007C0_MWU_BUSY 0xFFFFFFFD
53#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
54#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
55#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
56#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
57#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
58#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
59#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
60#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
61#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
62#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
63#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
64#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
65#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
66#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
67#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
68#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
69#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
70#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
71#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
72#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
73#define C_0007C0_CSI_BUSY 0xFFFFDFFF
74#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
75#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
76#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
77#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
78#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
79#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
80#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
81#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
82#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
83#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
84#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
85#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
86#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
87#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
88#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
89#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
90#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
91#define C_0007C0_CP_BUSY 0x7FFFFFFF
92#define R_000E40_RBBM_STATUS 0x000E40
93#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
94#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
95#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
96#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
97#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
98#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
99#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
100#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
101#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
102#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
103#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
104#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
105#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
106#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
107#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
108#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
109#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
110#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
111#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
112#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
113#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
114#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
115#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
116#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
117#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
118#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
119#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
120#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
121#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
122#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
123#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
124#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
125#define C_000E40_E2_BUSY 0xFFFDFFFF
126#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
127#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
128#define C_000E40_RB2D_BUSY 0xFFFBFFFF
129#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
130#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
131#define C_000E40_RB3D_BUSY 0xFFF7FFFF
132#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
133#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
134#define C_000E40_VAP_BUSY 0xFFEFFFFF
135#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
136#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
137#define C_000E40_RE_BUSY 0xFFDFFFFF
138#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
139#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
140#define C_000E40_TAM_BUSY 0xFFBFFFFF
141#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
142#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
143#define C_000E40_TDM_BUSY 0xFF7FFFFF
144#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
145#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
146#define C_000E40_PB_BUSY 0xFEFFFFFF
147#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
148#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
149#define C_000E40_TIM_BUSY 0xFDFFFFFF
150#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
151#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
152#define C_000E40_GA_BUSY 0xFBFFFFFF
153#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
154#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
155#define C_000E40_CBA2D_BUSY 0xF7FFFFFF
156#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
157#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
158#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
159
160#endif