aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/rs400.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/radeon/rs400.c')
-rw-r--r--drivers/gpu/drm/radeon/rs400.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index ca037160a582..c1fcdddb6be6 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -352,7 +352,7 @@ static int rs400_mc_init(struct radeon_device *rdev)
352 u32 tmp; 352 u32 tmp;
353 353
354 /* Setup GPU memory space */ 354 /* Setup GPU memory space */
355 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); 355 tmp = RREG32(R_00015C_NB_TOM);
356 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; 356 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
357 rdev->mc.gtt_location = 0xFFFFFFFFUL; 357 rdev->mc.gtt_location = 0xFFFFFFFFUL;
358 r = radeon_mc_setup(rdev); 358 r = radeon_mc_setup(rdev);
@@ -387,13 +387,13 @@ static int rs400_startup(struct radeon_device *rdev)
387 r300_clock_startup(rdev); 387 r300_clock_startup(rdev);
388 /* Initialize GPU configuration (# pipes, ...) */ 388 /* Initialize GPU configuration (# pipes, ...) */
389 rs400_gpu_init(rdev); 389 rs400_gpu_init(rdev);
390 r100_enable_bm(rdev);
390 /* Initialize GART (initialize after TTM so we can allocate 391 /* Initialize GART (initialize after TTM so we can allocate
391 * memory through TTM but finalize after TTM) */ 392 * memory through TTM but finalize after TTM) */
392 r = rs400_gart_enable(rdev); 393 r = rs400_gart_enable(rdev);
393 if (r) 394 if (r)
394 return r; 395 return r;
395 /* Enable IRQ */ 396 /* Enable IRQ */
396 rdev->irq.sw_int = true;
397 r100_irq_set(rdev); 397 r100_irq_set(rdev);
398 /* 1M ring buffer */ 398 /* 1M ring buffer */
399 r = r100_cp_init(rdev, 1024 * 1024); 399 r = r100_cp_init(rdev, 1024 * 1024);
@@ -430,6 +430,8 @@ int rs400_resume(struct radeon_device *rdev)
430 radeon_combios_asic_init(rdev->ddev); 430 radeon_combios_asic_init(rdev->ddev);
431 /* Resume clock after posting */ 431 /* Resume clock after posting */
432 r300_clock_startup(rdev); 432 r300_clock_startup(rdev);
433 /* Initialize surface registers */
434 radeon_surface_init(rdev);
433 return rs400_startup(rdev); 435 return rs400_startup(rdev);
434} 436}
435 437
@@ -452,7 +454,7 @@ void rs400_fini(struct radeon_device *rdev)
452 rs400_gart_fini(rdev); 454 rs400_gart_fini(rdev);
453 radeon_irq_kms_fini(rdev); 455 radeon_irq_kms_fini(rdev);
454 radeon_fence_driver_fini(rdev); 456 radeon_fence_driver_fini(rdev);
455 radeon_object_fini(rdev); 457 radeon_bo_fini(rdev);
456 radeon_atombios_fini(rdev); 458 radeon_atombios_fini(rdev);
457 kfree(rdev->bios); 459 kfree(rdev->bios);
458 rdev->bios = NULL; 460 rdev->bios = NULL;
@@ -490,10 +492,9 @@ int rs400_init(struct radeon_device *rdev)
490 RREG32(R_0007C0_CP_STAT)); 492 RREG32(R_0007C0_CP_STAT));
491 } 493 }
492 /* check if cards are posted or not */ 494 /* check if cards are posted or not */
493 if (!radeon_card_posted(rdev) && rdev->bios) { 495 if (radeon_boot_test_post_card(rdev) == false)
494 DRM_INFO("GPU not posted. posting now...\n"); 496 return -EINVAL;
495 radeon_combios_asic_init(rdev->ddev); 497
496 }
497 /* Initialize clocks */ 498 /* Initialize clocks */
498 radeon_get_clock_info(rdev->ddev); 499 radeon_get_clock_info(rdev->ddev);
499 /* Get vram informations */ 500 /* Get vram informations */
@@ -510,7 +511,7 @@ int rs400_init(struct radeon_device *rdev)
510 if (r) 511 if (r)
511 return r; 512 return r;
512 /* Memory manager */ 513 /* Memory manager */
513 r = radeon_object_init(rdev); 514 r = radeon_bo_init(rdev);
514 if (r) 515 if (r)
515 return r; 516 return r;
516 r = rs400_gart_init(rdev); 517 r = rs400_gart_init(rdev);