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path: root/drivers/gpu/drm/radeon/radeon_ucode.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_ucode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_ucode.h71
1 files changed, 71 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
index 4e7c3269b183..dc4576e4d8ad 100644
--- a/drivers/gpu/drm/radeon/radeon_ucode.h
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -153,4 +153,75 @@
153#define HAWAII_SMC_UCODE_START 0x20000 153#define HAWAII_SMC_UCODE_START 0x20000
154#define HAWAII_SMC_UCODE_SIZE 0x1FDEC 154#define HAWAII_SMC_UCODE_SIZE 0x1FDEC
155 155
156struct common_firmware_header {
157 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
158 uint32_t header_size_bytes; /* size of just the header in bytes */
159 uint16_t header_version_major; /* header version */
160 uint16_t header_version_minor; /* header version */
161 uint16_t ip_version_major; /* IP version */
162 uint16_t ip_version_minor; /* IP version */
163 uint32_t ucode_version;
164 uint32_t ucode_size_bytes; /* size of ucode in bytes */
165 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
166 uint32_t crc32; /* crc32 checksum of the payload */
167};
168
169/* version_major=1, version_minor=0 */
170struct mc_firmware_header_v1_0 {
171 struct common_firmware_header header;
172 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
173 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
174};
175
176/* version_major=1, version_minor=0 */
177struct smc_firmware_header_v1_0 {
178 struct common_firmware_header header;
179 uint32_t ucode_start_addr;
180};
181
182/* version_major=1, version_minor=0 */
183struct gfx_firmware_header_v1_0 {
184 struct common_firmware_header header;
185 uint32_t ucode_feature_version;
186 uint32_t jt_offset; /* jt location */
187 uint32_t jt_size; /* size of jt */
188};
189
190/* version_major=1, version_minor=0 */
191struct rlc_firmware_header_v1_0 {
192 struct common_firmware_header header;
193 uint32_t ucode_feature_version;
194 uint32_t save_and_restore_offset;
195 uint32_t clear_state_descriptor_offset;
196 uint32_t avail_scratch_ram_locations;
197 uint32_t master_pkt_description_offset;
198};
199
200/* version_major=1, version_minor=0 */
201struct sdma_firmware_header_v1_0 {
202 struct common_firmware_header header;
203 uint32_t ucode_feature_version;
204 uint32_t ucode_change_version;
205 uint32_t jt_offset; /* jt location */
206 uint32_t jt_size; /* size of jt */
207};
208
209/* header is fixed size */
210union radeon_firmware_header {
211 struct common_firmware_header common;
212 struct mc_firmware_header_v1_0 mc;
213 struct smc_firmware_header_v1_0 smc;
214 struct gfx_firmware_header_v1_0 gfx;
215 struct rlc_firmware_header_v1_0 rlc;
216 struct sdma_firmware_header_v1_0 sdma;
217 uint8_t raw[0x100];
218};
219
220void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
221void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
222void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
223void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
224void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
225int radeon_ucode_validate(const struct firmware *fw);
226
156#endif 227#endif