diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_reg.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_reg.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index e1b618574461..4df43f62c678 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h | |||
@@ -982,12 +982,15 @@ | |||
982 | # define RS400_TMDS2_PLLRST (1 << 1) | 982 | # define RS400_TMDS2_PLLRST (1 << 1) |
983 | 983 | ||
984 | #define RADEON_GEN_INT_CNTL 0x0040 | 984 | #define RADEON_GEN_INT_CNTL 0x0040 |
985 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) | ||
986 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) | ||
985 | # define RADEON_SW_INT_ENABLE (1 << 25) | 987 | # define RADEON_SW_INT_ENABLE (1 << 25) |
986 | #define RADEON_GEN_INT_STATUS 0x0044 | 988 | #define RADEON_GEN_INT_STATUS 0x0044 |
987 | # define RADEON_VSYNC_INT_AK (1 << 2) | 989 | # define AVIVO_DISPLAY_INT_STATUS (1 << 0) |
988 | # define RADEON_VSYNC_INT (1 << 2) | 990 | # define RADEON_CRTC_VBLANK_STAT (1 << 0) |
989 | # define RADEON_VSYNC2_INT_AK (1 << 6) | 991 | # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) |
990 | # define RADEON_VSYNC2_INT (1 << 6) | 992 | # define RADEON_CRTC2_VBLANK_STAT (1 << 9) |
993 | # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) | ||
991 | # define RADEON_SW_INT_FIRE (1 << 26) | 994 | # define RADEON_SW_INT_FIRE (1 << 26) |
992 | # define RADEON_SW_INT_TEST (1 << 25) | 995 | # define RADEON_SW_INT_TEST (1 << 25) |
993 | # define RADEON_SW_INT_TEST_ACK (1 << 25) | 996 | # define RADEON_SW_INT_TEST_ACK (1 << 25) |
@@ -2334,6 +2337,9 @@ | |||
2334 | # define RADEON_RE_WIDTH_SHIFT 0 | 2337 | # define RADEON_RE_WIDTH_SHIFT 0 |
2335 | # define RADEON_RE_HEIGHT_SHIFT 16 | 2338 | # define RADEON_RE_HEIGHT_SHIFT 16 |
2336 | 2339 | ||
2340 | #define RADEON_RB3D_ZPASS_DATA 0x3290 | ||
2341 | #define RADEON_RB3D_ZPASS_ADDR 0x3294 | ||
2342 | |||
2337 | #define RADEON_SE_CNTL 0x1c4c | 2343 | #define RADEON_SE_CNTL 0x1c4c |
2338 | # define RADEON_FFACE_CULL_CW (0 << 0) | 2344 | # define RADEON_FFACE_CULL_CW (0 << 0) |
2339 | # define RADEON_FFACE_CULL_CCW (1 << 0) | 2345 | # define RADEON_FFACE_CULL_CCW (1 << 0) |
@@ -3568,4 +3574,6 @@ | |||
3568 | #define RADEON_SCRATCH_REG4 0x15f0 | 3574 | #define RADEON_SCRATCH_REG4 0x15f0 |
3569 | #define RADEON_SCRATCH_REG5 0x15f4 | 3575 | #define RADEON_SCRATCH_REG5 0x15f4 |
3570 | 3576 | ||
3577 | #define RV530_GB_PIPE_SELECT2 0x4124 | ||
3578 | |||
3571 | #endif | 3579 | #endif |