diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 223 |
1 files changed, 116 insertions, 107 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 263c8098d7dd..2c293e8304d6 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
| @@ -81,7 +81,7 @@ void radeon_setup_encoder_clones(struct drm_device *dev) | |||
| 81 | } | 81 | } |
| 82 | 82 | ||
| 83 | uint32_t | 83 | uint32_t |
| 84 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) | 84 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
| 85 | { | 85 | { |
| 86 | struct radeon_device *rdev = dev->dev_private; | 86 | struct radeon_device *rdev = dev->dev_private; |
| 87 | uint32_t ret = 0; | 87 | uint32_t ret = 0; |
| @@ -97,59 +97,59 @@ radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t | |||
| 97 | if ((rdev->family == CHIP_RS300) || | 97 | if ((rdev->family == CHIP_RS300) || |
| 98 | (rdev->family == CHIP_RS400) || | 98 | (rdev->family == CHIP_RS400) || |
| 99 | (rdev->family == CHIP_RS480)) | 99 | (rdev->family == CHIP_RS480)) |
| 100 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; | 100 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
| 101 | else if (ASIC_IS_AVIVO(rdev)) | 101 | else if (ASIC_IS_AVIVO(rdev)) |
| 102 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; | 102 | ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; |
| 103 | else | 103 | else |
| 104 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; | 104 | ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; |
| 105 | break; | 105 | break; |
| 106 | case 2: /* dac b */ | 106 | case 2: /* dac b */ |
| 107 | if (ASIC_IS_AVIVO(rdev)) | 107 | if (ASIC_IS_AVIVO(rdev)) |
| 108 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; | 108 | ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; |
| 109 | else { | 109 | else { |
| 110 | /*if (rdev->family == CHIP_R200) | 110 | /*if (rdev->family == CHIP_R200) |
| 111 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | 111 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
| 112 | else*/ | 112 | else*/ |
| 113 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; | 113 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
| 114 | } | 114 | } |
| 115 | break; | 115 | break; |
| 116 | case 3: /* external dac */ | 116 | case 3: /* external dac */ |
| 117 | if (ASIC_IS_AVIVO(rdev)) | 117 | if (ASIC_IS_AVIVO(rdev)) |
| 118 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; | 118 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
| 119 | else | 119 | else |
| 120 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | 120 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
| 121 | break; | 121 | break; |
| 122 | } | 122 | } |
| 123 | break; | 123 | break; |
| 124 | case ATOM_DEVICE_LCD1_SUPPORT: | 124 | case ATOM_DEVICE_LCD1_SUPPORT: |
| 125 | if (ASIC_IS_AVIVO(rdev)) | 125 | if (ASIC_IS_AVIVO(rdev)) |
| 126 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; | 126 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
| 127 | else | 127 | else |
| 128 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; | 128 | ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; |
| 129 | break; | 129 | break; |
| 130 | case ATOM_DEVICE_DFP1_SUPPORT: | 130 | case ATOM_DEVICE_DFP1_SUPPORT: |
| 131 | if ((rdev->family == CHIP_RS300) || | 131 | if ((rdev->family == CHIP_RS300) || |
| 132 | (rdev->family == CHIP_RS400) || | 132 | (rdev->family == CHIP_RS400) || |
| 133 | (rdev->family == CHIP_RS480)) | 133 | (rdev->family == CHIP_RS480)) |
| 134 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | 134 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
| 135 | else if (ASIC_IS_AVIVO(rdev)) | 135 | else if (ASIC_IS_AVIVO(rdev)) |
| 136 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; | 136 | ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; |
| 137 | else | 137 | else |
| 138 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; | 138 | ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; |
| 139 | break; | 139 | break; |
| 140 | case ATOM_DEVICE_LCD2_SUPPORT: | 140 | case ATOM_DEVICE_LCD2_SUPPORT: |
| 141 | case ATOM_DEVICE_DFP2_SUPPORT: | 141 | case ATOM_DEVICE_DFP2_SUPPORT: |
| 142 | if ((rdev->family == CHIP_RS600) || | 142 | if ((rdev->family == CHIP_RS600) || |
| 143 | (rdev->family == CHIP_RS690) || | 143 | (rdev->family == CHIP_RS690) || |
| 144 | (rdev->family == CHIP_RS740)) | 144 | (rdev->family == CHIP_RS740)) |
| 145 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; | 145 | ret = ENCODER_INTERNAL_DDI_ENUM_ID1; |
| 146 | else if (ASIC_IS_AVIVO(rdev)) | 146 | else if (ASIC_IS_AVIVO(rdev)) |
| 147 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; | 147 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
| 148 | else | 148 | else |
| 149 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; | 149 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
| 150 | break; | 150 | break; |
| 151 | case ATOM_DEVICE_DFP3_SUPPORT: | 151 | case ATOM_DEVICE_DFP3_SUPPORT: |
| 152 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; | 152 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
| 153 | break; | 153 | break; |
| 154 | } | 154 | } |
| 155 | 155 | ||
| @@ -228,32 +228,6 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder) | |||
| 228 | return NULL; | 228 | return NULL; |
| 229 | } | 229 | } |
| 230 | 230 | ||
| 231 | static struct radeon_connector_atom_dig * | ||
| 232 | radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder) | ||
| 233 | { | ||
| 234 | struct drm_device *dev = encoder->dev; | ||
| 235 | struct radeon_device *rdev = dev->dev_private; | ||
| 236 | struct drm_connector *connector; | ||
| 237 | struct radeon_connector *radeon_connector; | ||
| 238 | struct radeon_connector_atom_dig *dig_connector; | ||
| 239 | |||
| 240 | if (!rdev->is_atom_bios) | ||
| 241 | return NULL; | ||
| 242 | |||
| 243 | connector = radeon_get_connector_for_encoder(encoder); | ||
| 244 | if (!connector) | ||
| 245 | return NULL; | ||
| 246 | |||
| 247 | radeon_connector = to_radeon_connector(connector); | ||
| 248 | |||
| 249 | if (!radeon_connector->con_priv) | ||
| 250 | return NULL; | ||
| 251 | |||
| 252 | dig_connector = radeon_connector->con_priv; | ||
| 253 | |||
| 254 | return dig_connector; | ||
| 255 | } | ||
| 256 | |||
| 257 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, | 231 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
| 258 | struct drm_display_mode *adjusted_mode) | 232 | struct drm_display_mode *adjusted_mode) |
| 259 | { | 233 | { |
| @@ -512,14 +486,12 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
| 512 | struct radeon_device *rdev = dev->dev_private; | 486 | struct radeon_device *rdev = dev->dev_private; |
| 513 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 487 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 514 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 488 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 515 | struct radeon_connector_atom_dig *dig_connector = | ||
| 516 | radeon_get_atom_connector_priv_from_encoder(encoder); | ||
| 517 | union lvds_encoder_control args; | 489 | union lvds_encoder_control args; |
| 518 | int index = 0; | 490 | int index = 0; |
| 519 | int hdmi_detected = 0; | 491 | int hdmi_detected = 0; |
| 520 | uint8_t frev, crev; | 492 | uint8_t frev, crev; |
| 521 | 493 | ||
| 522 | if (!dig || !dig_connector) | 494 | if (!dig) |
| 523 | return; | 495 | return; |
| 524 | 496 | ||
| 525 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) | 497 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
| @@ -562,7 +534,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
| 562 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) | 534 | if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) |
| 563 | args.v1.ucMisc |= (1 << 1); | 535 | args.v1.ucMisc |= (1 << 1); |
| 564 | } else { | 536 | } else { |
| 565 | if (dig_connector->linkb) | 537 | if (dig->linkb) |
| 566 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | 538 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
| 567 | if (radeon_encoder->pixel_clock > 165000) | 539 | if (radeon_encoder->pixel_clock > 165000) |
| 568 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | 540 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| @@ -601,7 +573,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
| 601 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; | 573 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
| 602 | } | 574 | } |
| 603 | } else { | 575 | } else { |
| 604 | if (dig_connector->linkb) | 576 | if (dig->linkb) |
| 605 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; | 577 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
| 606 | if (radeon_encoder->pixel_clock > 165000) | 578 | if (radeon_encoder->pixel_clock > 165000) |
| 607 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | 579 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| @@ -623,6 +595,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
| 623 | int | 595 | int |
| 624 | atombios_get_encoder_mode(struct drm_encoder *encoder) | 596 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
| 625 | { | 597 | { |
| 598 | struct drm_device *dev = encoder->dev; | ||
| 599 | struct radeon_device *rdev = dev->dev_private; | ||
| 626 | struct drm_connector *connector; | 600 | struct drm_connector *connector; |
| 627 | struct radeon_connector *radeon_connector; | 601 | struct radeon_connector *radeon_connector; |
| 628 | struct radeon_connector_atom_dig *dig_connector; | 602 | struct radeon_connector_atom_dig *dig_connector; |
| @@ -636,9 +610,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
| 636 | switch (connector->connector_type) { | 610 | switch (connector->connector_type) { |
| 637 | case DRM_MODE_CONNECTOR_DVII: | 611 | case DRM_MODE_CONNECTOR_DVII: |
| 638 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ | 612 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
| 639 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) | 613 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) { |
| 640 | return ATOM_ENCODER_MODE_HDMI; | 614 | /* fix me */ |
| 641 | else if (radeon_connector->use_digital) | 615 | if (ASIC_IS_DCE4(rdev)) |
| 616 | return ATOM_ENCODER_MODE_DVI; | ||
| 617 | else | ||
| 618 | return ATOM_ENCODER_MODE_HDMI; | ||
| 619 | } else if (radeon_connector->use_digital) | ||
| 642 | return ATOM_ENCODER_MODE_DVI; | 620 | return ATOM_ENCODER_MODE_DVI; |
| 643 | else | 621 | else |
| 644 | return ATOM_ENCODER_MODE_CRT; | 622 | return ATOM_ENCODER_MODE_CRT; |
| @@ -646,9 +624,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
| 646 | case DRM_MODE_CONNECTOR_DVID: | 624 | case DRM_MODE_CONNECTOR_DVID: |
| 647 | case DRM_MODE_CONNECTOR_HDMIA: | 625 | case DRM_MODE_CONNECTOR_HDMIA: |
| 648 | default: | 626 | default: |
| 649 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) | 627 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) { |
| 650 | return ATOM_ENCODER_MODE_HDMI; | 628 | /* fix me */ |
| 651 | else | 629 | if (ASIC_IS_DCE4(rdev)) |
| 630 | return ATOM_ENCODER_MODE_DVI; | ||
| 631 | else | ||
| 632 | return ATOM_ENCODER_MODE_HDMI; | ||
| 633 | } else | ||
| 652 | return ATOM_ENCODER_MODE_DVI; | 634 | return ATOM_ENCODER_MODE_DVI; |
| 653 | break; | 635 | break; |
| 654 | case DRM_MODE_CONNECTOR_LVDS: | 636 | case DRM_MODE_CONNECTOR_LVDS: |
| @@ -660,9 +642,13 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
| 660 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | 642 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
| 661 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | 643 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
| 662 | return ATOM_ENCODER_MODE_DP; | 644 | return ATOM_ENCODER_MODE_DP; |
| 663 | else if (drm_detect_hdmi_monitor(radeon_connector->edid)) | 645 | else if (drm_detect_hdmi_monitor(radeon_connector->edid)) { |
| 664 | return ATOM_ENCODER_MODE_HDMI; | 646 | /* fix me */ |
| 665 | else | 647 | if (ASIC_IS_DCE4(rdev)) |
| 648 | return ATOM_ENCODER_MODE_DVI; | ||
| 649 | else | ||
| 650 | return ATOM_ENCODER_MODE_HDMI; | ||
| 651 | } else | ||
| 666 | return ATOM_ENCODER_MODE_DVI; | 652 | return ATOM_ENCODER_MODE_DVI; |
| 667 | break; | 653 | break; |
| 668 | case DRM_MODE_CONNECTOR_DVIA: | 654 | case DRM_MODE_CONNECTOR_DVIA: |
| @@ -729,13 +715,24 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
| 729 | struct radeon_device *rdev = dev->dev_private; | 715 | struct radeon_device *rdev = dev->dev_private; |
| 730 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 716 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 731 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 717 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 732 | struct radeon_connector_atom_dig *dig_connector = | 718 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 733 | radeon_get_atom_connector_priv_from_encoder(encoder); | ||
| 734 | union dig_encoder_control args; | 719 | union dig_encoder_control args; |
| 735 | int index = 0; | 720 | int index = 0; |
| 736 | uint8_t frev, crev; | 721 | uint8_t frev, crev; |
| 722 | int dp_clock = 0; | ||
| 723 | int dp_lane_count = 0; | ||
| 724 | |||
| 725 | if (connector) { | ||
| 726 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | ||
| 727 | struct radeon_connector_atom_dig *dig_connector = | ||
| 728 | radeon_connector->con_priv; | ||
| 737 | 729 | ||
| 738 | if (!dig || !dig_connector) | 730 | dp_clock = dig_connector->dp_clock; |
| 731 | dp_lane_count = dig_connector->dp_lane_count; | ||
| 732 | } | ||
| 733 | |||
| 734 | /* no dig encoder assigned */ | ||
| 735 | if (dig->dig_encoder == -1) | ||
| 739 | return; | 736 | return; |
| 740 | 737 | ||
| 741 | memset(&args, 0, sizeof(args)); | 738 | memset(&args, 0, sizeof(args)); |
| @@ -757,9 +754,9 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
| 757 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | 754 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 758 | 755 | ||
| 759 | if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { | 756 | if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { |
| 760 | if (dig_connector->dp_clock == 270000) | 757 | if (dp_clock == 270000) |
| 761 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | 758 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
| 762 | args.v1.ucLaneNum = dig_connector->dp_lane_count; | 759 | args.v1.ucLaneNum = dp_lane_count; |
| 763 | } else if (radeon_encoder->pixel_clock > 165000) | 760 | } else if (radeon_encoder->pixel_clock > 165000) |
| 764 | args.v1.ucLaneNum = 8; | 761 | args.v1.ucLaneNum = 8; |
| 765 | else | 762 | else |
| @@ -781,7 +778,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
| 781 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; | 778 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
| 782 | break; | 779 | break; |
| 783 | } | 780 | } |
| 784 | if (dig_connector->linkb) | 781 | if (dig->linkb) |
| 785 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; | 782 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
| 786 | else | 783 | else |
| 787 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | 784 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
| @@ -804,38 +801,47 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
| 804 | struct radeon_device *rdev = dev->dev_private; | 801 | struct radeon_device *rdev = dev->dev_private; |
| 805 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 802 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 806 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 803 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 807 | struct radeon_connector_atom_dig *dig_connector = | 804 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 808 | radeon_get_atom_connector_priv_from_encoder(encoder); | ||
| 809 | struct drm_connector *connector; | ||
| 810 | struct radeon_connector *radeon_connector; | ||
| 811 | union dig_transmitter_control args; | 805 | union dig_transmitter_control args; |
| 812 | int index = 0; | 806 | int index = 0; |
| 813 | uint8_t frev, crev; | 807 | uint8_t frev, crev; |
| 814 | bool is_dp = false; | 808 | bool is_dp = false; |
| 815 | int pll_id = 0; | 809 | int pll_id = 0; |
| 810 | int dp_clock = 0; | ||
| 811 | int dp_lane_count = 0; | ||
| 812 | int connector_object_id = 0; | ||
| 813 | int igp_lane_info = 0; | ||
| 816 | 814 | ||
| 817 | if (!dig || !dig_connector) | 815 | if (connector) { |
| 818 | return; | 816 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 817 | struct radeon_connector_atom_dig *dig_connector = | ||
| 818 | radeon_connector->con_priv; | ||
| 819 | 819 | ||
| 820 | connector = radeon_get_connector_for_encoder(encoder); | 820 | dp_clock = dig_connector->dp_clock; |
| 821 | radeon_connector = to_radeon_connector(connector); | 821 | dp_lane_count = dig_connector->dp_lane_count; |
| 822 | connector_object_id = | ||
| 823 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | ||
| 824 | igp_lane_info = dig_connector->igp_lane_info; | ||
| 825 | } | ||
| 826 | |||
| 827 | /* no dig encoder assigned */ | ||
| 828 | if (dig->dig_encoder == -1) | ||
| 829 | return; | ||
| 822 | 830 | ||
| 823 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) | 831 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
| 824 | is_dp = true; | 832 | is_dp = true; |
| 825 | 833 | ||
| 826 | memset(&args, 0, sizeof(args)); | 834 | memset(&args, 0, sizeof(args)); |
| 827 | 835 | ||
| 828 | if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) | 836 | switch (radeon_encoder->encoder_id) { |
| 837 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | ||
| 838 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | ||
| 839 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | ||
| 829 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); | 840 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
| 830 | else { | 841 | break; |
| 831 | switch (radeon_encoder->encoder_id) { | 842 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 832 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | 843 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); |
| 833 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); | 844 | break; |
| 834 | break; | ||
| 835 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | ||
| 836 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); | ||
| 837 | break; | ||
| 838 | } | ||
| 839 | } | 845 | } |
| 840 | 846 | ||
| 841 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | 847 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| @@ -843,14 +849,14 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
| 843 | 849 | ||
| 844 | args.v1.ucAction = action; | 850 | args.v1.ucAction = action; |
| 845 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | 851 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 846 | args.v1.usInitInfo = radeon_connector->connector_object_id; | 852 | args.v1.usInitInfo = connector_object_id; |
| 847 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { | 853 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
| 848 | args.v1.asMode.ucLaneSel = lane_num; | 854 | args.v1.asMode.ucLaneSel = lane_num; |
| 849 | args.v1.asMode.ucLaneSet = lane_set; | 855 | args.v1.asMode.ucLaneSet = lane_set; |
| 850 | } else { | 856 | } else { |
| 851 | if (is_dp) | 857 | if (is_dp) |
| 852 | args.v1.usPixelClock = | 858 | args.v1.usPixelClock = |
| 853 | cpu_to_le16(dig_connector->dp_clock / 10); | 859 | cpu_to_le16(dp_clock / 10); |
| 854 | else if (radeon_encoder->pixel_clock > 165000) | 860 | else if (radeon_encoder->pixel_clock > 165000) |
| 855 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); | 861 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 856 | else | 862 | else |
| @@ -858,13 +864,13 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
| 858 | } | 864 | } |
| 859 | if (ASIC_IS_DCE4(rdev)) { | 865 | if (ASIC_IS_DCE4(rdev)) { |
| 860 | if (is_dp) | 866 | if (is_dp) |
| 861 | args.v3.ucLaneNum = dig_connector->dp_lane_count; | 867 | args.v3.ucLaneNum = dp_lane_count; |
| 862 | else if (radeon_encoder->pixel_clock > 165000) | 868 | else if (radeon_encoder->pixel_clock > 165000) |
| 863 | args.v3.ucLaneNum = 8; | 869 | args.v3.ucLaneNum = 8; |
| 864 | else | 870 | else |
| 865 | args.v3.ucLaneNum = 4; | 871 | args.v3.ucLaneNum = 4; |
| 866 | 872 | ||
| 867 | if (dig_connector->linkb) { | 873 | if (dig->linkb) { |
| 868 | args.v3.acConfig.ucLinkSel = 1; | 874 | args.v3.acConfig.ucLinkSel = 1; |
| 869 | args.v3.acConfig.ucEncoderSel = 1; | 875 | args.v3.acConfig.ucEncoderSel = 1; |
| 870 | } | 876 | } |
| @@ -904,7 +910,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
| 904 | } | 910 | } |
| 905 | } else if (ASIC_IS_DCE32(rdev)) { | 911 | } else if (ASIC_IS_DCE32(rdev)) { |
| 906 | args.v2.acConfig.ucEncoderSel = dig->dig_encoder; | 912 | args.v2.acConfig.ucEncoderSel = dig->dig_encoder; |
| 907 | if (dig_connector->linkb) | 913 | if (dig->linkb) |
| 908 | args.v2.acConfig.ucLinkSel = 1; | 914 | args.v2.acConfig.ucLinkSel = 1; |
| 909 | 915 | ||
| 910 | switch (radeon_encoder->encoder_id) { | 916 | switch (radeon_encoder->encoder_id) { |
| @@ -938,23 +944,23 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
| 938 | if ((rdev->flags & RADEON_IS_IGP) && | 944 | if ((rdev->flags & RADEON_IS_IGP) && |
| 939 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | 945 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { |
| 940 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { | 946 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { |
| 941 | if (dig_connector->igp_lane_info & 0x1) | 947 | if (igp_lane_info & 0x1) |
| 942 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; | 948 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 943 | else if (dig_connector->igp_lane_info & 0x2) | 949 | else if (igp_lane_info & 0x2) |
| 944 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; | 950 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
| 945 | else if (dig_connector->igp_lane_info & 0x4) | 951 | else if (igp_lane_info & 0x4) |
| 946 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; | 952 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
| 947 | else if (dig_connector->igp_lane_info & 0x8) | 953 | else if (igp_lane_info & 0x8) |
| 948 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; | 954 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
| 949 | } else { | 955 | } else { |
| 950 | if (dig_connector->igp_lane_info & 0x3) | 956 | if (igp_lane_info & 0x3) |
| 951 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; | 957 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
| 952 | else if (dig_connector->igp_lane_info & 0xc) | 958 | else if (igp_lane_info & 0xc) |
| 953 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; | 959 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
| 954 | } | 960 | } |
| 955 | } | 961 | } |
| 956 | 962 | ||
| 957 | if (dig_connector->linkb) | 963 | if (dig->linkb) |
| 958 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; | 964 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
| 959 | else | 965 | else |
| 960 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | 966 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
| @@ -1072,8 +1078,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
| 1072 | if (is_dig) { | 1078 | if (is_dig) { |
| 1073 | switch (mode) { | 1079 | switch (mode) { |
| 1074 | case DRM_MODE_DPMS_ON: | 1080 | case DRM_MODE_DPMS_ON: |
| 1075 | if (!ASIC_IS_DCE4(rdev)) | 1081 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
| 1076 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); | ||
| 1077 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { | 1082 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
| 1078 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | 1083 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 1079 | 1084 | ||
| @@ -1085,8 +1090,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
| 1085 | case DRM_MODE_DPMS_STANDBY: | 1090 | case DRM_MODE_DPMS_STANDBY: |
| 1086 | case DRM_MODE_DPMS_SUSPEND: | 1091 | case DRM_MODE_DPMS_SUSPEND: |
| 1087 | case DRM_MODE_DPMS_OFF: | 1092 | case DRM_MODE_DPMS_OFF: |
| 1088 | if (!ASIC_IS_DCE4(rdev)) | 1093 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
| 1089 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); | ||
| 1090 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { | 1094 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
| 1091 | if (ASIC_IS_DCE4(rdev)) | 1095 | if (ASIC_IS_DCE4(rdev)) |
| 1092 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); | 1096 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); |
| @@ -1290,24 +1294,22 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) | |||
| 1290 | uint32_t dig_enc_in_use = 0; | 1294 | uint32_t dig_enc_in_use = 0; |
| 1291 | 1295 | ||
| 1292 | if (ASIC_IS_DCE4(rdev)) { | 1296 | if (ASIC_IS_DCE4(rdev)) { |
| 1293 | struct radeon_connector_atom_dig *dig_connector = | 1297 | dig = radeon_encoder->enc_priv; |
| 1294 | radeon_get_atom_connector_priv_from_encoder(encoder); | ||
| 1295 | |||
| 1296 | switch (radeon_encoder->encoder_id) { | 1298 | switch (radeon_encoder->encoder_id) { |
| 1297 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | 1299 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1298 | if (dig_connector->linkb) | 1300 | if (dig->linkb) |
| 1299 | return 1; | 1301 | return 1; |
| 1300 | else | 1302 | else |
| 1301 | return 0; | 1303 | return 0; |
| 1302 | break; | 1304 | break; |
| 1303 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | 1305 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1304 | if (dig_connector->linkb) | 1306 | if (dig->linkb) |
| 1305 | return 3; | 1307 | return 3; |
| 1306 | else | 1308 | else |
| 1307 | return 2; | 1309 | return 2; |
| 1308 | break; | 1310 | break; |
| 1309 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | 1311 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1310 | if (dig_connector->linkb) | 1312 | if (dig->linkb) |
| 1311 | return 5; | 1313 | return 5; |
| 1312 | else | 1314 | else |
| 1313 | return 4; | 1315 | return 4; |
| @@ -1641,6 +1643,7 @@ radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) | |||
| 1641 | struct radeon_encoder_atom_dig * | 1643 | struct radeon_encoder_atom_dig * |
| 1642 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | 1644 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
| 1643 | { | 1645 | { |
| 1646 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; | ||
| 1644 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | 1647 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| 1645 | 1648 | ||
| 1646 | if (!dig) | 1649 | if (!dig) |
| @@ -1650,11 +1653,16 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | |||
| 1650 | dig->coherent_mode = true; | 1653 | dig->coherent_mode = true; |
| 1651 | dig->dig_encoder = -1; | 1654 | dig->dig_encoder = -1; |
| 1652 | 1655 | ||
| 1656 | if (encoder_enum == 2) | ||
| 1657 | dig->linkb = true; | ||
| 1658 | else | ||
| 1659 | dig->linkb = false; | ||
| 1660 | |||
| 1653 | return dig; | 1661 | return dig; |
| 1654 | } | 1662 | } |
| 1655 | 1663 | ||
| 1656 | void | 1664 | void |
| 1657 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) | 1665 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) |
| 1658 | { | 1666 | { |
| 1659 | struct radeon_device *rdev = dev->dev_private; | 1667 | struct radeon_device *rdev = dev->dev_private; |
| 1660 | struct drm_encoder *encoder; | 1668 | struct drm_encoder *encoder; |
| @@ -1663,7 +1671,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su | |||
| 1663 | /* see if we already added it */ | 1671 | /* see if we already added it */ |
| 1664 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 1672 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1665 | radeon_encoder = to_radeon_encoder(encoder); | 1673 | radeon_encoder = to_radeon_encoder(encoder); |
| 1666 | if (radeon_encoder->encoder_id == encoder_id) { | 1674 | if (radeon_encoder->encoder_enum == encoder_enum) { |
| 1667 | radeon_encoder->devices |= supported_device; | 1675 | radeon_encoder->devices |= supported_device; |
| 1668 | return; | 1676 | return; |
| 1669 | } | 1677 | } |
| @@ -1691,7 +1699,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su | |||
| 1691 | 1699 | ||
| 1692 | radeon_encoder->enc_priv = NULL; | 1700 | radeon_encoder->enc_priv = NULL; |
| 1693 | 1701 | ||
| 1694 | radeon_encoder->encoder_id = encoder_id; | 1702 | radeon_encoder->encoder_enum = encoder_enum; |
| 1703 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | ||
| 1695 | radeon_encoder->devices = supported_device; | 1704 | radeon_encoder->devices = supported_device; |
| 1696 | radeon_encoder->rmx_type = RMX_OFF; | 1705 | radeon_encoder->rmx_type = RMX_OFF; |
| 1697 | radeon_encoder->underscan_type = UNDERSCAN_OFF; | 1706 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
