diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 125 |
1 files changed, 55 insertions, 70 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index a65ab1a0dad2..d42bc512d75a 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
| @@ -31,6 +31,10 @@ | |||
| 31 | 31 | ||
| 32 | extern int atom_debug; | 32 | extern int atom_debug; |
| 33 | 33 | ||
| 34 | /* evil but including atombios.h is much worse */ | ||
| 35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | ||
| 36 | struct drm_display_mode *mode); | ||
| 37 | |||
| 34 | uint32_t | 38 | uint32_t |
| 35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) | 39 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
| 36 | { | 40 | { |
| @@ -167,49 +171,17 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder, | |||
| 167 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 171 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 168 | struct drm_device *dev = encoder->dev; | 172 | struct drm_device *dev = encoder->dev; |
| 169 | struct radeon_device *rdev = dev->dev_private; | 173 | struct radeon_device *rdev = dev->dev_private; |
| 170 | struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; | 174 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
| 171 | 175 | ||
| 172 | if (mode->hdisplay < native_mode->panel_xres || | 176 | if (mode->hdisplay < native_mode->hdisplay || |
| 173 | mode->vdisplay < native_mode->panel_yres) { | 177 | mode->vdisplay < native_mode->vdisplay) { |
| 174 | if (ASIC_IS_AVIVO(rdev)) { | 178 | int mode_id = adjusted_mode->base.id; |
| 175 | adjusted_mode->hdisplay = native_mode->panel_xres; | 179 | *adjusted_mode = *native_mode; |
| 176 | adjusted_mode->vdisplay = native_mode->panel_yres; | 180 | if (!ASIC_IS_AVIVO(rdev)) { |
| 177 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; | 181 | adjusted_mode->hdisplay = mode->hdisplay; |
| 178 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; | 182 | adjusted_mode->vdisplay = mode->vdisplay; |
| 179 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; | ||
| 180 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; | ||
| 181 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; | ||
| 182 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; | ||
| 183 | /* update crtc values */ | ||
| 184 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | ||
| 185 | /* adjust crtc values */ | ||
| 186 | adjusted_mode->crtc_hdisplay = native_mode->panel_xres; | ||
| 187 | adjusted_mode->crtc_vdisplay = native_mode->panel_yres; | ||
| 188 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; | ||
| 189 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; | ||
| 190 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; | ||
| 191 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; | ||
| 192 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; | ||
| 193 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; | ||
| 194 | } else { | ||
| 195 | adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; | ||
| 196 | adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; | ||
| 197 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width; | ||
| 198 | adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank; | ||
| 199 | adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus; | ||
| 200 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width; | ||
| 201 | /* update crtc values */ | ||
| 202 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | ||
| 203 | /* adjust crtc values */ | ||
| 204 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank; | ||
| 205 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus; | ||
| 206 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width; | ||
| 207 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank; | ||
| 208 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus; | ||
| 209 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width; | ||
| 210 | } | 183 | } |
| 211 | adjusted_mode->flags = native_mode->flags; | 184 | adjusted_mode->base.id = mode_id; |
| 212 | adjusted_mode->clock = native_mode->dotclock; | ||
| 213 | } | 185 | } |
| 214 | } | 186 | } |
| 215 | 187 | ||
| @@ -219,7 +191,11 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, | |||
| 219 | struct drm_display_mode *adjusted_mode) | 191 | struct drm_display_mode *adjusted_mode) |
| 220 | { | 192 | { |
| 221 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 193 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 194 | struct drm_device *dev = encoder->dev; | ||
| 195 | struct radeon_device *rdev = dev->dev_private; | ||
| 222 | 196 | ||
| 197 | /* set the active encoder to connector routing */ | ||
| 198 | radeon_encoder_set_active_device(encoder); | ||
| 223 | drm_mode_set_crtcinfo(adjusted_mode, 0); | 199 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 224 | 200 | ||
| 225 | if (radeon_encoder->rmx_type != RMX_OFF) | 201 | if (radeon_encoder->rmx_type != RMX_OFF) |
| @@ -230,6 +206,18 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, | |||
| 230 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | 206 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
| 231 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | 207 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
| 232 | 208 | ||
| 209 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { | ||
| 210 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; | ||
| 211 | if (tv_dac) { | ||
| 212 | if (tv_dac->tv_std == TV_STD_NTSC || | ||
| 213 | tv_dac->tv_std == TV_STD_NTSC_J || | ||
| 214 | tv_dac->tv_std == TV_STD_PAL_M) | ||
| 215 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | ||
| 216 | else | ||
| 217 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | ||
| 218 | } | ||
| 219 | } | ||
| 220 | |||
| 233 | return true; | 221 | return true; |
| 234 | } | 222 | } |
| 235 | 223 | ||
| @@ -461,7 +449,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
| 461 | case 1: | 449 | case 1: |
| 462 | args.v1.ucMisc = 0; | 450 | args.v1.ucMisc = 0; |
| 463 | args.v1.ucAction = action; | 451 | args.v1.ucAction = action; |
| 464 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) | 452 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
| 465 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; | 453 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
| 466 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 454 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 467 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | 455 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| @@ -486,7 +474,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) | |||
| 486 | if (dig->coherent_mode) | 474 | if (dig->coherent_mode) |
| 487 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | 475 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
| 488 | } | 476 | } |
| 489 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) | 477 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
| 490 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; | 478 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
| 491 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 479 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 492 | args.v2.ucTruncate = 0; | 480 | args.v2.ucTruncate = 0; |
| @@ -544,7 +532,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
| 544 | switch (connector->connector_type) { | 532 | switch (connector->connector_type) { |
| 545 | case DRM_MODE_CONNECTOR_DVII: | 533 | case DRM_MODE_CONNECTOR_DVII: |
| 546 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ | 534 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
| 547 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) | 535 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
| 548 | return ATOM_ENCODER_MODE_HDMI; | 536 | return ATOM_ENCODER_MODE_HDMI; |
| 549 | else if (radeon_connector->use_digital) | 537 | else if (radeon_connector->use_digital) |
| 550 | return ATOM_ENCODER_MODE_DVI; | 538 | return ATOM_ENCODER_MODE_DVI; |
| @@ -554,7 +542,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
| 554 | case DRM_MODE_CONNECTOR_DVID: | 542 | case DRM_MODE_CONNECTOR_DVID: |
| 555 | case DRM_MODE_CONNECTOR_HDMIA: | 543 | case DRM_MODE_CONNECTOR_HDMIA: |
| 556 | default: | 544 | default: |
| 557 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) | 545 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
| 558 | return ATOM_ENCODER_MODE_HDMI; | 546 | return ATOM_ENCODER_MODE_HDMI; |
| 559 | else | 547 | else |
| 560 | return ATOM_ENCODER_MODE_DVI; | 548 | return ATOM_ENCODER_MODE_DVI; |
| @@ -566,7 +554,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
| 566 | /*if (radeon_output->MonType == MT_DP) | 554 | /*if (radeon_output->MonType == MT_DP) |
| 567 | return ATOM_ENCODER_MODE_DP; | 555 | return ATOM_ENCODER_MODE_DP; |
| 568 | else*/ | 556 | else*/ |
| 569 | if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) | 557 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
| 570 | return ATOM_ENCODER_MODE_HDMI; | 558 | return ATOM_ENCODER_MODE_HDMI; |
| 571 | else | 559 | else |
| 572 | return ATOM_ENCODER_MODE_DVI; | 560 | return ATOM_ENCODER_MODE_DVI; |
| @@ -734,14 +722,17 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action) | |||
| 734 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); | 722 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
| 735 | 723 | ||
| 736 | args.v1.ucAction = action; | 724 | args.v1.ucAction = action; |
| 737 | 725 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { | |
| 726 | args.v1.usInitInfo = radeon_connector->connector_object_id; | ||
| 727 | } else { | ||
| 728 | if (radeon_encoder->pixel_clock > 165000) | ||
| 729 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); | ||
| 730 | else | ||
| 731 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | ||
| 732 | } | ||
| 738 | if (ASIC_IS_DCE32(rdev)) { | 733 | if (ASIC_IS_DCE32(rdev)) { |
| 739 | if (radeon_encoder->pixel_clock > 165000) { | 734 | if (radeon_encoder->pixel_clock > 165000) |
| 740 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100); | 735 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 741 | args.v2.acConfig.fDualLinkConnector = 1; | ||
| 742 | } else { | ||
| 743 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100); | ||
| 744 | } | ||
| 745 | if (dig->dig_block) | 736 | if (dig->dig_block) |
| 746 | args.v2.acConfig.ucEncoderSel = 1; | 737 | args.v2.acConfig.ucEncoderSel = 1; |
| 747 | 738 | ||
| @@ -766,7 +757,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action) | |||
| 766 | } | 757 | } |
| 767 | } else { | 758 | } else { |
| 768 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; | 759 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
| 769 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10); | ||
| 770 | 760 | ||
| 771 | switch (radeon_encoder->encoder_id) { | 761 | switch (radeon_encoder->encoder_id) { |
| 772 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | 762 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| @@ -874,16 +864,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
| 874 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; | 864 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
| 875 | int index = 0; | 865 | int index = 0; |
| 876 | bool is_dig = false; | 866 | bool is_dig = false; |
| 877 | int devices; | ||
| 878 | 867 | ||
| 879 | memset(&args, 0, sizeof(args)); | 868 | memset(&args, 0, sizeof(args)); |
| 880 | 869 | ||
| 881 | /* on DPMS off we have no idea if active device is meaningful */ | ||
| 882 | if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device) | ||
| 883 | devices = radeon_encoder->devices; | ||
| 884 | else | ||
| 885 | devices = radeon_encoder->active_device; | ||
| 886 | |||
| 887 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", | 870 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
| 888 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, | 871 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
| 889 | radeon_encoder->active_device); | 872 | radeon_encoder->active_device); |
| @@ -914,18 +897,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |||
| 914 | break; | 897 | break; |
| 915 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | 898 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 916 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | 899 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 917 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) | 900 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 918 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | 901 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
| 919 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) | 902 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 920 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | 903 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 921 | else | 904 | else |
| 922 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | 905 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
| 923 | break; | 906 | break; |
| 924 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | 907 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 925 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | 908 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 926 | if (devices & (ATOM_DEVICE_TV_SUPPORT)) | 909 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 927 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | 910 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
| 928 | else if (devices & (ATOM_DEVICE_CV_SUPPORT)) | 911 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
| 929 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | 912 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 930 | else | 913 | else |
| 931 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | 914 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
| @@ -1104,8 +1087,11 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |||
| 1104 | } | 1087 | } |
| 1105 | 1088 | ||
| 1106 | /* set scaler clears this on some chips */ | 1089 | /* set scaler clears this on some chips */ |
| 1107 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) | 1090 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
| 1108 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); | 1091 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
| 1092 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | ||
| 1093 | AVIVO_D1MODE_INTERLEAVE_EN); | ||
| 1094 | } | ||
| 1109 | } | 1095 | } |
| 1110 | 1096 | ||
| 1111 | static void | 1097 | static void |
| @@ -1153,6 +1139,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
| 1153 | 1139 | ||
| 1154 | /* setup and enable the encoder and transmitter */ | 1140 | /* setup and enable the encoder and transmitter */ |
| 1155 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); | 1141 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
| 1142 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT); | ||
| 1156 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); | 1143 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); |
| 1157 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); | 1144 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
| 1158 | break; | 1145 | break; |
| @@ -1268,8 +1255,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |||
| 1268 | { | 1255 | { |
| 1269 | radeon_atom_output_lock(encoder, true); | 1256 | radeon_atom_output_lock(encoder, true); |
| 1270 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | 1257 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 1271 | |||
| 1272 | radeon_encoder_set_active_device(encoder); | ||
| 1273 | } | 1258 | } |
| 1274 | 1259 | ||
| 1275 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | 1260 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
