1 files changed, 25 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 9278429af9ed..4dbb813910c3 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -122,6 +122,7 @@ enum radeon_family {
         CHIP_RV350,
         CHIP_RV380,
         CHIP_R420,
+        CHIP_R423,
         CHIP_RV410,
         CHIP_RS400,
         CHIP_RS480,
@@ -439,8 +440,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #       define RADEON_SCISSOR_1_ENABLE          (1 << 29)
 #       define RADEON_SCISSOR_2_ENABLE          (1 << 30)
 
+/*
+ * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
+ * don't have an explicit bus mastering disable bit.  It's handled
+ * by the PCI D-states.  PMI_BM_DIS disables D-state bus master
+ * handling, not bus mastering itself.
+ */
 #define RADEON_BUS_CNTL                 0x0030
+/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
 #       define RADEON_BUS_MASTER_DIS            (1 << 6)
+/* rs400, rs690/rs740 */
+#       define RS400_BUS_MASTER_DIS             (1 << 14)
+#       define RS400_MSI_REARM                  (1 << 20)
+/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
+
+#define RADEON_BUS_CNTL1                0x0034
+#       define RADEON_PMI_BM_DIS                (1 << 2)
+#       define RADEON_PMI_INT_DIS               (1 << 3)
+
+#define RV370_BUS_CNTL                  0x004c
+#       define RV370_PMI_BM_DIS                 (1 << 5)
+#       define RV370_PMI_INT_DIS                (1 << 6)
+
+#define RADEON_MSI_REARM_EN             0x0160
+/* rv370/rv380, rv410, r423/r430/r480, r5xx */
+#       define RV370_MSI_REARM_EN               (1 << 0)
 
 #define RADEON_CLOCK_CNTL_DATA          0x000c
 #       define RADEON_PLL_WR_EN                 (1 << 7)
@@ -913,6 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define RADEON_AIC_CNTL                 0x01d0
 #       define RADEON_PCIGART_TRANSLATE_EN      (1 << 0)
+#       define RS480_MSI_REARM                  (1 << 3)
 #define RADEON_AIC_STAT                 0x01d4
 #define RADEON_AIC_PT_BASE              0x01d8
 #define RADEON_AIC_LO_ADDR              0x01dc