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path: root/drivers/gpu/drm/radeon/radeon_display.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_display.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c45
1 files changed, 26 insertions, 19 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 0ec491ead2ff..6a92f994cc26 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -357,7 +357,8 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
357 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 357 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
358 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 358 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
359 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 359 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
360 if (dig->dp_i2c_bus) 360 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
361 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
361 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); 362 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
362 } 363 }
363 if (!radeon_connector->ddc_bus) 364 if (!radeon_connector->ddc_bus)
@@ -410,11 +411,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
410 uint32_t *fb_div_p, 411 uint32_t *fb_div_p,
411 uint32_t *frac_fb_div_p, 412 uint32_t *frac_fb_div_p,
412 uint32_t *ref_div_p, 413 uint32_t *ref_div_p,
413 uint32_t *post_div_p, 414 uint32_t *post_div_p)
414 int flags)
415{ 415{
416 uint32_t min_ref_div = pll->min_ref_div; 416 uint32_t min_ref_div = pll->min_ref_div;
417 uint32_t max_ref_div = pll->max_ref_div; 417 uint32_t max_ref_div = pll->max_ref_div;
418 uint32_t min_post_div = pll->min_post_div;
419 uint32_t max_post_div = pll->max_post_div;
418 uint32_t min_fractional_feed_div = 0; 420 uint32_t min_fractional_feed_div = 0;
419 uint32_t max_fractional_feed_div = 0; 421 uint32_t max_fractional_feed_div = 0;
420 uint32_t best_vco = pll->best_vco; 422 uint32_t best_vco = pll->best_vco;
@@ -430,7 +432,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
430 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 432 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
431 freq = freq * 1000; 433 freq = freq * 1000;
432 434
433 if (flags & RADEON_PLL_USE_REF_DIV) 435 if (pll->flags & RADEON_PLL_USE_REF_DIV)
434 min_ref_div = max_ref_div = pll->reference_div; 436 min_ref_div = max_ref_div = pll->reference_div;
435 else { 437 else {
436 while (min_ref_div < max_ref_div-1) { 438 while (min_ref_div < max_ref_div-1) {
@@ -445,19 +447,22 @@ void radeon_compute_pll(struct radeon_pll *pll,
445 } 447 }
446 } 448 }
447 449
448 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 450 if (pll->flags & RADEON_PLL_USE_POST_DIV)
451 min_post_div = max_post_div = pll->post_div;
452
453 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
449 min_fractional_feed_div = pll->min_frac_feedback_div; 454 min_fractional_feed_div = pll->min_frac_feedback_div;
450 max_fractional_feed_div = pll->max_frac_feedback_div; 455 max_fractional_feed_div = pll->max_frac_feedback_div;
451 } 456 }
452 457
453 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { 458 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
454 uint32_t ref_div; 459 uint32_t ref_div;
455 460
456 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 461 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
457 continue; 462 continue;
458 463
459 /* legacy radeons only have a few post_divs */ 464 /* legacy radeons only have a few post_divs */
460 if (flags & RADEON_PLL_LEGACY) { 465 if (pll->flags & RADEON_PLL_LEGACY) {
461 if ((post_div == 5) || 466 if ((post_div == 5) ||
462 (post_div == 7) || 467 (post_div == 7) ||
463 (post_div == 9) || 468 (post_div == 9) ||
@@ -504,7 +509,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
504 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 509 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
505 current_freq = radeon_div(tmp, ref_div * post_div); 510 current_freq = radeon_div(tmp, ref_div * post_div);
506 511
507 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 512 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
508 error = freq - current_freq; 513 error = freq - current_freq;
509 error = error < 0 ? 0xffffffff : error; 514 error = error < 0 ? 0xffffffff : error;
510 } else 515 } else
@@ -531,12 +536,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
531 best_freq = current_freq; 536 best_freq = current_freq;
532 best_error = error; 537 best_error = error;
533 best_vco_diff = vco_diff; 538 best_vco_diff = vco_diff;
534 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 539 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
535 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 540 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
536 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 541 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
537 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 542 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
538 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 543 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
539 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 544 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
540 best_post_div = post_div; 545 best_post_div = post_div;
541 best_ref_div = ref_div; 546 best_ref_div = ref_div;
542 best_feedback_div = feedback_div; 547 best_feedback_div = feedback_div;
@@ -572,8 +577,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
572 uint32_t *fb_div_p, 577 uint32_t *fb_div_p,
573 uint32_t *frac_fb_div_p, 578 uint32_t *frac_fb_div_p,
574 uint32_t *ref_div_p, 579 uint32_t *ref_div_p,
575 uint32_t *post_div_p, 580 uint32_t *post_div_p)
576 int flags)
577{ 581{
578 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; 582 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
579 fixed20_12 pll_out_max, pll_out_min; 583 fixed20_12 pll_out_max, pll_out_min;
@@ -667,7 +671,6 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
667 radeonfb_remove(dev, fb); 671 radeonfb_remove(dev, fb);
668 672
669 if (radeon_fb->obj) { 673 if (radeon_fb->obj) {
670 radeon_gem_object_unpin(radeon_fb->obj);
671 mutex_lock(&dev->struct_mutex); 674 mutex_lock(&dev->struct_mutex);
672 drm_gem_object_unreference(radeon_fb->obj); 675 drm_gem_object_unreference(radeon_fb->obj);
673 mutex_unlock(&dev->struct_mutex); 676 mutex_unlock(&dev->struct_mutex);
@@ -715,7 +718,11 @@ radeon_user_framebuffer_create(struct drm_device *dev,
715 struct drm_gem_object *obj; 718 struct drm_gem_object *obj;
716 719
717 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 720 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
718 721 if (obj == NULL) {
722 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
723 "can't create framebuffer\n", mode_cmd->handle);
724 return NULL;
725 }
719 return radeon_framebuffer_create(dev, mode_cmd, obj); 726 return radeon_framebuffer_create(dev, mode_cmd, obj);
720} 727}
721 728