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path: root/drivers/gpu/drm/radeon/radeon_device.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c27
1 files changed, 16 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index c2c59fb1ea01..189973836cff 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev)
467{ 467{
468 uint32_t reg; 468 uint32_t reg;
469 469
470 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
470 if (efi_enabled(EFI_BOOT) && 471 if (efi_enabled(EFI_BOOT) &&
471 rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) 472 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
473 (rdev->family < CHIP_R600))
472 return false; 474 return false;
473 475
476 if (ASIC_IS_NODCE(rdev))
477 goto check_memsize;
478
474 /* first check CRTCs */ 479 /* first check CRTCs */
475 if (ASIC_IS_DCE41(rdev)) { 480 if (ASIC_IS_DCE4(rdev)) {
476 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 481 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
477 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 482 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
478 if (reg & EVERGREEN_CRTC_MASTER_EN) 483 if (rdev->num_crtc >= 4) {
479 return true; 484 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
480 } else if (ASIC_IS_DCE4(rdev)) { 485 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
481 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 486 }
482 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 487 if (rdev->num_crtc >= 6) {
483 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 488 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
484 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 489 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
485 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 490 }
486 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
487 if (reg & EVERGREEN_CRTC_MASTER_EN) 491 if (reg & EVERGREEN_CRTC_MASTER_EN)
488 return true; 492 return true;
489 } else if (ASIC_IS_AVIVO(rdev)) { 493 } else if (ASIC_IS_AVIVO(rdev)) {
@@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev)
500 } 504 }
501 } 505 }
502 506
507check_memsize:
503 /* then check MEM_SIZE, in case the crtcs are off */ 508 /* then check MEM_SIZE, in case the crtcs are off */
504 if (rdev->family >= CHIP_R600) 509 if (rdev->family >= CHIP_R600)
505 reg = RREG32(R600_CONFIG_MEMSIZE); 510 reg = RREG32(R600_CONFIG_MEMSIZE);