diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 237 |
1 files changed, 38 insertions, 199 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 0cc337edf3a3..bddf17f97da8 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -34,7 +34,6 @@ | |||
34 | #include <linux/vga_switcheroo.h> | 34 | #include <linux/vga_switcheroo.h> |
35 | #include "radeon_reg.h" | 35 | #include "radeon_reg.h" |
36 | #include "radeon.h" | 36 | #include "radeon.h" |
37 | #include "radeon_asic.h" | ||
38 | #include "atom.h" | 37 | #include "atom.h" |
39 | 38 | ||
40 | /* | 39 | /* |
@@ -243,6 +242,36 @@ bool radeon_card_posted(struct radeon_device *rdev) | |||
243 | 242 | ||
244 | } | 243 | } |
245 | 244 | ||
245 | void radeon_update_bandwidth_info(struct radeon_device *rdev) | ||
246 | { | ||
247 | fixed20_12 a; | ||
248 | u32 sclk, mclk; | ||
249 | |||
250 | if (rdev->flags & RADEON_IS_IGP) { | ||
251 | sclk = radeon_get_engine_clock(rdev); | ||
252 | mclk = rdev->clock.default_mclk; | ||
253 | |||
254 | a.full = rfixed_const(100); | ||
255 | rdev->pm.sclk.full = rfixed_const(sclk); | ||
256 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | ||
257 | rdev->pm.mclk.full = rfixed_const(mclk); | ||
258 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); | ||
259 | |||
260 | a.full = rfixed_const(16); | ||
261 | /* core_bandwidth = sclk(Mhz) * 16 */ | ||
262 | rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); | ||
263 | } else { | ||
264 | sclk = radeon_get_engine_clock(rdev); | ||
265 | mclk = radeon_get_memory_clock(rdev); | ||
266 | |||
267 | a.full = rfixed_const(100); | ||
268 | rdev->pm.sclk.full = rfixed_const(sclk); | ||
269 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | ||
270 | rdev->pm.mclk.full = rfixed_const(mclk); | ||
271 | rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a); | ||
272 | } | ||
273 | } | ||
274 | |||
246 | bool radeon_boot_test_post_card(struct radeon_device *rdev) | 275 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
247 | { | 276 | { |
248 | if (radeon_card_posted(rdev)) | 277 | if (radeon_card_posted(rdev)) |
@@ -289,181 +318,6 @@ void radeon_dummy_page_fini(struct radeon_device *rdev) | |||
289 | } | 318 | } |
290 | 319 | ||
291 | 320 | ||
292 | /* | ||
293 | * Registers accessors functions. | ||
294 | */ | ||
295 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) | ||
296 | { | ||
297 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | ||
298 | BUG_ON(1); | ||
299 | return 0; | ||
300 | } | ||
301 | |||
302 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | ||
303 | { | ||
304 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | ||
305 | reg, v); | ||
306 | BUG_ON(1); | ||
307 | } | ||
308 | |||
309 | void radeon_register_accessor_init(struct radeon_device *rdev) | ||
310 | { | ||
311 | rdev->mc_rreg = &radeon_invalid_rreg; | ||
312 | rdev->mc_wreg = &radeon_invalid_wreg; | ||
313 | rdev->pll_rreg = &radeon_invalid_rreg; | ||
314 | rdev->pll_wreg = &radeon_invalid_wreg; | ||
315 | rdev->pciep_rreg = &radeon_invalid_rreg; | ||
316 | rdev->pciep_wreg = &radeon_invalid_wreg; | ||
317 | |||
318 | /* Don't change order as we are overridding accessor. */ | ||
319 | if (rdev->family < CHIP_RV515) { | ||
320 | rdev->pcie_reg_mask = 0xff; | ||
321 | } else { | ||
322 | rdev->pcie_reg_mask = 0x7ff; | ||
323 | } | ||
324 | /* FIXME: not sure here */ | ||
325 | if (rdev->family <= CHIP_R580) { | ||
326 | rdev->pll_rreg = &r100_pll_rreg; | ||
327 | rdev->pll_wreg = &r100_pll_wreg; | ||
328 | } | ||
329 | if (rdev->family >= CHIP_R420) { | ||
330 | rdev->mc_rreg = &r420_mc_rreg; | ||
331 | rdev->mc_wreg = &r420_mc_wreg; | ||
332 | } | ||
333 | if (rdev->family >= CHIP_RV515) { | ||
334 | rdev->mc_rreg = &rv515_mc_rreg; | ||
335 | rdev->mc_wreg = &rv515_mc_wreg; | ||
336 | } | ||
337 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | ||
338 | rdev->mc_rreg = &rs400_mc_rreg; | ||
339 | rdev->mc_wreg = &rs400_mc_wreg; | ||
340 | } | ||
341 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | ||
342 | rdev->mc_rreg = &rs690_mc_rreg; | ||
343 | rdev->mc_wreg = &rs690_mc_wreg; | ||
344 | } | ||
345 | if (rdev->family == CHIP_RS600) { | ||
346 | rdev->mc_rreg = &rs600_mc_rreg; | ||
347 | rdev->mc_wreg = &rs600_mc_wreg; | ||
348 | } | ||
349 | if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { | ||
350 | rdev->pciep_rreg = &r600_pciep_rreg; | ||
351 | rdev->pciep_wreg = &r600_pciep_wreg; | ||
352 | } | ||
353 | } | ||
354 | |||
355 | |||
356 | /* | ||
357 | * ASIC | ||
358 | */ | ||
359 | int radeon_asic_init(struct radeon_device *rdev) | ||
360 | { | ||
361 | radeon_register_accessor_init(rdev); | ||
362 | switch (rdev->family) { | ||
363 | case CHIP_R100: | ||
364 | case CHIP_RV100: | ||
365 | case CHIP_RS100: | ||
366 | case CHIP_RV200: | ||
367 | case CHIP_RS200: | ||
368 | rdev->asic = &r100_asic; | ||
369 | break; | ||
370 | case CHIP_R200: | ||
371 | case CHIP_RV250: | ||
372 | case CHIP_RS300: | ||
373 | case CHIP_RV280: | ||
374 | rdev->asic = &r200_asic; | ||
375 | break; | ||
376 | case CHIP_R300: | ||
377 | case CHIP_R350: | ||
378 | case CHIP_RV350: | ||
379 | case CHIP_RV380: | ||
380 | if (rdev->flags & RADEON_IS_PCIE) | ||
381 | rdev->asic = &r300_asic_pcie; | ||
382 | else | ||
383 | rdev->asic = &r300_asic; | ||
384 | break; | ||
385 | case CHIP_R420: | ||
386 | case CHIP_R423: | ||
387 | case CHIP_RV410: | ||
388 | rdev->asic = &r420_asic; | ||
389 | break; | ||
390 | case CHIP_RS400: | ||
391 | case CHIP_RS480: | ||
392 | rdev->asic = &rs400_asic; | ||
393 | break; | ||
394 | case CHIP_RS600: | ||
395 | rdev->asic = &rs600_asic; | ||
396 | break; | ||
397 | case CHIP_RS690: | ||
398 | case CHIP_RS740: | ||
399 | rdev->asic = &rs690_asic; | ||
400 | break; | ||
401 | case CHIP_RV515: | ||
402 | rdev->asic = &rv515_asic; | ||
403 | break; | ||
404 | case CHIP_R520: | ||
405 | case CHIP_RV530: | ||
406 | case CHIP_RV560: | ||
407 | case CHIP_RV570: | ||
408 | case CHIP_R580: | ||
409 | rdev->asic = &r520_asic; | ||
410 | break; | ||
411 | case CHIP_R600: | ||
412 | case CHIP_RV610: | ||
413 | case CHIP_RV630: | ||
414 | case CHIP_RV620: | ||
415 | case CHIP_RV635: | ||
416 | case CHIP_RV670: | ||
417 | case CHIP_RS780: | ||
418 | case CHIP_RS880: | ||
419 | rdev->asic = &r600_asic; | ||
420 | break; | ||
421 | case CHIP_RV770: | ||
422 | case CHIP_RV730: | ||
423 | case CHIP_RV710: | ||
424 | case CHIP_RV740: | ||
425 | rdev->asic = &rv770_asic; | ||
426 | break; | ||
427 | case CHIP_CEDAR: | ||
428 | case CHIP_REDWOOD: | ||
429 | case CHIP_JUNIPER: | ||
430 | case CHIP_CYPRESS: | ||
431 | case CHIP_HEMLOCK: | ||
432 | rdev->asic = &evergreen_asic; | ||
433 | break; | ||
434 | default: | ||
435 | /* FIXME: not supported yet */ | ||
436 | return -EINVAL; | ||
437 | } | ||
438 | |||
439 | if (rdev->flags & RADEON_IS_IGP) { | ||
440 | rdev->asic->get_memory_clock = NULL; | ||
441 | rdev->asic->set_memory_clock = NULL; | ||
442 | } | ||
443 | |||
444 | return 0; | ||
445 | } | ||
446 | |||
447 | |||
448 | /* | ||
449 | * Wrapper around modesetting bits. | ||
450 | */ | ||
451 | int radeon_clocks_init(struct radeon_device *rdev) | ||
452 | { | ||
453 | int r; | ||
454 | |||
455 | r = radeon_static_clocks_init(rdev->ddev); | ||
456 | if (r) { | ||
457 | return r; | ||
458 | } | ||
459 | DRM_INFO("Clocks initialized !\n"); | ||
460 | return 0; | ||
461 | } | ||
462 | |||
463 | void radeon_clocks_fini(struct radeon_device *rdev) | ||
464 | { | ||
465 | } | ||
466 | |||
467 | /* ATOM accessor methods */ | 321 | /* ATOM accessor methods */ |
468 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | 322 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
469 | { | 323 | { |
@@ -568,29 +422,6 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state) | |||
568 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | 422 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
569 | } | 423 | } |
570 | 424 | ||
571 | void radeon_agp_disable(struct radeon_device *rdev) | ||
572 | { | ||
573 | rdev->flags &= ~RADEON_IS_AGP; | ||
574 | if (rdev->family >= CHIP_R600) { | ||
575 | DRM_INFO("Forcing AGP to PCIE mode\n"); | ||
576 | rdev->flags |= RADEON_IS_PCIE; | ||
577 | } else if (rdev->family >= CHIP_RV515 || | ||
578 | rdev->family == CHIP_RV380 || | ||
579 | rdev->family == CHIP_RV410 || | ||
580 | rdev->family == CHIP_R423) { | ||
581 | DRM_INFO("Forcing AGP to PCIE mode\n"); | ||
582 | rdev->flags |= RADEON_IS_PCIE; | ||
583 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; | ||
584 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; | ||
585 | } else { | ||
586 | DRM_INFO("Forcing AGP to PCI mode\n"); | ||
587 | rdev->flags |= RADEON_IS_PCI; | ||
588 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; | ||
589 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; | ||
590 | } | ||
591 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | ||
592 | } | ||
593 | |||
594 | void radeon_check_arguments(struct radeon_device *rdev) | 425 | void radeon_check_arguments(struct radeon_device *rdev) |
595 | { | 426 | { |
596 | /* vramlimit must be a power of two */ | 427 | /* vramlimit must be a power of two */ |
@@ -732,6 +563,14 @@ int radeon_device_init(struct radeon_device *rdev, | |||
732 | return r; | 563 | return r; |
733 | radeon_check_arguments(rdev); | 564 | radeon_check_arguments(rdev); |
734 | 565 | ||
566 | /* all of the newer IGP chips have an internal gart | ||
567 | * However some rs4xx report as AGP, so remove that here. | ||
568 | */ | ||
569 | if ((rdev->family >= CHIP_RS400) && | ||
570 | (rdev->flags & RADEON_IS_IGP)) { | ||
571 | rdev->flags &= ~RADEON_IS_AGP; | ||
572 | } | ||
573 | |||
735 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { | 574 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
736 | radeon_agp_disable(rdev); | 575 | radeon_agp_disable(rdev); |
737 | } | 576 | } |